From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: linux-sunxi@lists.linux.dev, Dragan Simic <dsimic@manjaro.org>
Cc: wens@csie.org, samuel@sholland.org,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6
Date: Sun, 28 Apr 2024 18:21:28 +0200 [thread overview]
Message-ID: <5773383.DvuYhMxLoT@jernej-laptop> (raw)
In-Reply-To: <49abb93000078c692c48c0a65ff677893909361a.1714304071.git.dsimic@manjaro.org>
Dne nedelja, 28. april 2024 ob 13:40:36 GMT +2 je Dragan Simic napisal(a):
> Add missing cache information to the Allwinner H6 SoC dtsi, to allow
> the userspace, which includes lscpu(1) that uses the virtual files provided
> by the kernel under the /sys/devices/system/cpu directory, to display the
> proper H6 cache information.
>
> Adding the cache information to the H6 SoC dtsi also makes the following
> warning message in the kernel log go away:
>
> cacheinfo: Unable to detect cache hierarchy for CPU 0
>
> The cache parameters for the H6 dtsi were obtained and partially derived
> by hand from the cache size and layout specifications found in the following
> datasheets and technical reference manuals:
>
> - Allwinner H6 V200 datasheet, version 1.1
> - ARM Cortex-A53 revision r0p3 TRM, version E
>
> For future reference, here's a brief summary of the documentation:
>
> - All caches employ the 64-byte cache line length
> - Each Cortex-A53 core has 32 KB of L1 2-way, set-associative instruction
> cache and 32 KB of L1 4-way, set-associative data cache
> - The entire SoC has 512 KB of unified L2 16-way, set-associative cache
>
> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
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next prev parent reply other threads:[~2024-04-28 16:21 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-28 11:40 [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Dragan Simic
2024-04-28 11:40 ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for H6 Dragan Simic
2024-04-28 16:21 ` Jernej Škrabec [this message]
2024-04-29 23:10 ` Andre Przywara
2024-04-30 0:01 ` Dragan Simic
2024-04-30 10:46 ` Andre Przywara
2024-04-30 11:10 ` Dragan Simic
2024-05-01 9:30 ` Andre Przywara
2024-05-03 9:13 ` Dragan Simic
2024-05-28 15:46 ` Chen-Yu Tsai
2024-05-28 15:56 ` Chen-Yu Tsai
2024-05-28 16:02 ` Dragan Simic
2024-05-28 16:06 ` Chen-Yu Tsai
2024-05-28 16:17 ` Chen-Yu Tsai
2024-05-28 16:10 ` Chen-Yu Tsai
2024-04-28 16:19 ` [PATCH] arm64: dts: allwinner: Add cache information to the SoC dtsi for A64 Jernej Škrabec
2024-04-29 10:33 ` Andre Przywara
2024-04-29 13:51 ` Dragan Simic
2024-05-28 16:10 ` Chen-Yu Tsai
2024-05-28 16:16 ` Chen-Yu Tsai
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