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* [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support
@ 2021-12-20 11:06 Sascha Hauer
  2021-12-20 11:06 ` [PATCH 01/22] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer
                   ` (23 more replies)
  0 siblings, 24 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer


Third round of patches and last one for this year. I hopefully integrated
all review feedback. Additionally the driver is now fully converted to
regmap, so no struct vop_reg necessary anymore.

Sascha

Changes since v2:
- Add pin names to HDMI supply pin description
- Add hclk support to HDMI driver
- Dual license rockchip-vop2 binding, update binding
- Add HDMI connector to board dts files
- drop unnecessary gamma_lut registers from vop2
- Update dclk_vop[012] clock handling, no longer hacks needed
- Complete regmap conversion

Changes since v1:
- drop all unnecessary waiting for frames within atomic modeset and plane update
- Cluster subwin support removed
- gamma support removed
- unnecessary irq_lock removed
- interrupt handling simplified
- simplified zpos handling
- drop is_alpha_support(), use fb->format->has_alpha instead
- use devm_regulator_get() rather than devm_regulator_get_optional() for hdmi regulators
- Use fixed number of planes per video port
- Drop homegrown regmap code from vop2 driver (not complete yet)
- Add separate include file for vop2 driver to not pollute the vop include

Andy Yan (1):
  drm: rockchip: Add VOP2 driver

Benjamin Gaignard (1):
  dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568
    HDMI

Michael Riesch (1):
  arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a

Sascha Hauer (19):
  drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
  drm/rockchip: dw_hdmi: rename vpll clock to reference clock
  drm/rockchip: dw_hdmi: add rk3568 support
  drm/rockchip: dw_hdmi: add regulator support
  drm/rockchip: dw_hdmi: Add support for hclk
  dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional
  dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  dt-bindings: display: rockchip: dw-hdmi: Add regulator support
  dt-bindings: display: rockchip: dw-hdmi: Add additional clock
  dt-bindings: display: rockchip: Add binding for VOP2
  arm64: dts: rockchip: rk3399: reorder hmdi clocks
  arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref'
  arm64: dts: rockchip: rk356x: Add VOP2 nodes
  arm64: dts: rockchip: rk356x: Add HDMI nodes
  arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
  clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop*
  clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock
  drm/encoder: Add of_graph port to struct drm_encoder
  drm/rockchip: Make VOP driver optional

 .../display/rockchip/rockchip,dw-hdmi.yaml    |   28 +-
 .../display/rockchip/rockchip-vop2.yaml       |  146 +
 arch/arm64/boot/dts/rockchip/rk3399.dtsi      |    6 +-
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   |   48 +
 arch/arm64/boot/dts/rockchip/rk3566.dtsi      |    4 +
 .../boot/dts/rockchip/rk3568-evb1-v10.dts     |   48 +
 arch/arm64/boot/dts/rockchip/rk3568.dtsi      |    4 +
 arch/arm64/boot/dts/rockchip/rk356x.dtsi      |   85 +
 drivers/clk/rockchip/clk-rk3568.c             |    8 +-
 drivers/gpu/drm/rockchip/Kconfig              |   14 +
 drivers/gpu/drm/rockchip/Makefile             |    4 +-
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c   |  125 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c   |    3 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h   |    7 +-
 drivers/gpu/drm/rockchip/rockchip_drm_fb.c    |    2 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop.h   |   15 +
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c  | 2768 +++++++++++++++++
 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h  |  480 +++
 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c  |  285 ++
 include/drm/drm_encoder.h                     |    2 +
 include/dt-bindings/soc/rockchip,vop2.h       |   14 +
 21 files changed, 4063 insertions(+), 33 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
 create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
 create mode 100644 include/dt-bindings/soc/rockchip,vop2.h

-- 
2.30.2


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^ permalink raw reply	[flat|nested] 45+ messages in thread

* [PATCH 01/22] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 02/22] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
                   ` (22 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The driver returns an error when devm_phy_optional_get() fails leaving
the previously enabled clock turned on. Change order and enable the
clock only after the phy has been acquired.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 830bdd5e9b7ce..8677c82716784 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -529,13 +529,6 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
-	ret = clk_prepare_enable(hdmi->vpll_clk);
-	if (ret) {
-		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
-			      ret);
-		return ret;
-	}
-
 	hdmi->phy = devm_phy_optional_get(dev, "hdmi");
 	if (IS_ERR(hdmi->phy)) {
 		ret = PTR_ERR(hdmi->phy);
@@ -544,6 +537,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	ret = clk_prepare_enable(hdmi->vpll_clk);
+	if (ret) {
+		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+			      ret);
+		return ret;
+	}
+
 	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
 
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 02/22] drm/rockchip: dw_hdmi: rename vpll clock to reference clock
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
  2021-12-20 11:06 ` [PATCH 01/22] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 03/22] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
                   ` (21 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock. The clock
name "vpll" is left for compatibility to old device trees.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 29 ++++++++++++---------
 1 file changed, 16 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 8677c82716784..e352e0404f772 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -69,7 +69,7 @@ struct rockchip_hdmi {
 	struct regmap *regmap;
 	struct drm_encoder encoder;
 	const struct rockchip_hdmi_chip_data *chip_data;
-	struct clk *vpll_clk;
+	struct clk *ref_clk;
 	struct clk *grf_clk;
 	struct dw_hdmi *hdmi;
 	struct phy *phy;
@@ -196,14 +196,17 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 		return PTR_ERR(hdmi->regmap);
 	}
 
-	hdmi->vpll_clk = devm_clk_get(hdmi->dev, "vpll");
-	if (PTR_ERR(hdmi->vpll_clk) == -ENOENT) {
-		hdmi->vpll_clk = NULL;
-	} else if (PTR_ERR(hdmi->vpll_clk) == -EPROBE_DEFER) {
+	hdmi->ref_clk = devm_clk_get(hdmi->dev, "ref");
+	if (PTR_ERR(hdmi->ref_clk) == -ENOENT)
+		hdmi->ref_clk = devm_clk_get(hdmi->dev, "vpll");
+
+	if (PTR_ERR(hdmi->ref_clk) == -ENOENT) {
+		hdmi->ref_clk = NULL;
+	} else if (PTR_ERR(hdmi->ref_clk) == -EPROBE_DEFER) {
 		return -EPROBE_DEFER;
-	} else if (IS_ERR(hdmi->vpll_clk)) {
-		DRM_DEV_ERROR(hdmi->dev, "failed to get vpll clock\n");
-		return PTR_ERR(hdmi->vpll_clk);
+	} else if (IS_ERR(hdmi->ref_clk)) {
+		DRM_DEV_ERROR(hdmi->dev, "failed to get reference clock\n");
+		return PTR_ERR(hdmi->ref_clk);
 	}
 
 	hdmi->grf_clk = devm_clk_get(hdmi->dev, "grf");
@@ -257,7 +260,7 @@ static void dw_hdmi_rockchip_encoder_mode_set(struct drm_encoder *encoder,
 {
 	struct rockchip_hdmi *hdmi = to_rockchip_hdmi(encoder);
 
-	clk_set_rate(hdmi->vpll_clk, adj_mode->clock * 1000);
+	clk_set_rate(hdmi->ref_clk, adj_mode->clock * 1000);
 }
 
 static void dw_hdmi_rockchip_encoder_enable(struct drm_encoder *encoder)
@@ -537,9 +540,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
-	ret = clk_prepare_enable(hdmi->vpll_clk);
+	ret = clk_prepare_enable(hdmi->ref_clk);
 	if (ret) {
-		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI vpll: %d\n",
+		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
 			      ret);
 		return ret;
 	}
@@ -558,7 +561,7 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 	if (IS_ERR(hdmi->hdmi)) {
 		ret = PTR_ERR(hdmi->hdmi);
 		drm_encoder_cleanup(encoder);
-		clk_disable_unprepare(hdmi->vpll_clk);
+		clk_disable_unprepare(hdmi->ref_clk);
 	}
 
 	return ret;
@@ -570,7 +573,7 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 	struct rockchip_hdmi *hdmi = dev_get_drvdata(dev);
 
 	dw_hdmi_unbind(hdmi->hdmi);
-	clk_disable_unprepare(hdmi->vpll_clk);
+	clk_disable_unprepare(hdmi->ref_clk);
 }
 
 static const struct component_ops dw_hdmi_rockchip_ops = {
-- 
2.30.2


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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 03/22] drm/rockchip: dw_hdmi: add rk3568 support
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
  2021-12-20 11:06 ` [PATCH 01/22] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer
  2021-12-20 11:06 ` [PATCH 02/22] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 04/22] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
                   ` (20 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

Add a new dw_hdmi_plat_data struct and new compatible for rk3568.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 31 +++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index e352e0404f772..262eef614cb12 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -50,6 +50,10 @@
 #define RK3399_GRF_SOC_CON20		0x6250
 #define RK3399_HDMI_LCDC_SEL		BIT(6)
 
+#define RK3568_GRF_VO_CON1		0x0364
+#define RK3568_HDMI_SDAIN_MSK		BIT(15)
+#define RK3568_HDMI_SCLIN_MSK		BIT(14)
+
 #define HIWORD_UPDATE(val, mask)	(val | (mask) << 16)
 
 /**
@@ -470,6 +474,19 @@ static const struct dw_hdmi_plat_data rk3399_hdmi_drv_data = {
 	.use_drm_infoframe = true,
 };
 
+static struct rockchip_hdmi_chip_data rk3568_chip_data = {
+	.lcdsel_grf_reg = -1,
+};
+
+static const struct dw_hdmi_plat_data rk3568_hdmi_drv_data = {
+	.mode_valid = dw_hdmi_rockchip_mode_valid,
+	.mpll_cfg   = rockchip_mpll_cfg,
+	.cur_ctr    = rockchip_cur_ctr,
+	.phy_config = rockchip_phy_config,
+	.phy_data = &rk3568_chip_data,
+	.use_drm_infoframe = true,
+};
+
 static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 	{ .compatible = "rockchip,rk3228-dw-hdmi",
 	  .data = &rk3228_hdmi_drv_data
@@ -483,6 +500,9 @@ static const struct of_device_id dw_hdmi_rockchip_dt_ids[] = {
 	{ .compatible = "rockchip,rk3399-dw-hdmi",
 	  .data = &rk3399_hdmi_drv_data
 	},
+	{ .compatible = "rockchip,rk3568-dw-hdmi",
+	  .data = &rk3568_hdmi_drv_data
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, dw_hdmi_rockchip_dt_ids);
@@ -517,6 +537,9 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 	encoder = &hdmi->encoder;
 
 	encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+
+	encoder->port = of_graph_get_port_by_id(dev->of_node, 0);
+
 	/*
 	 * If we failed to find the CRTC(s) which this encoder is
 	 * supposed to be connected to, it's because the CRTC has
@@ -547,6 +570,14 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	if (hdmi->chip_data == &rk3568_chip_data) {
+		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
+			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
+					   RK3568_HDMI_SCLIN_MSK,
+					   RK3568_HDMI_SDAIN_MSK |
+					   RK3568_HDMI_SCLIN_MSK));
+	}
+
 	drm_encoder_helper_add(encoder, &dw_hdmi_rockchip_encoder_helper_funcs);
 	drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
 
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 04/22] drm/rockchip: dw_hdmi: add regulator support
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (2 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 03/22] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 05/22] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
                   ` (19 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The RK3568 has HDMI_TX_AVDD0V9 and HDMI_TX_AVDD_1V8 supply inputs needed
for the HDMI port. add support for these to the driver for boards which
have them supplied by switchable regulators.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 41 +++++++++++++++++++--
 1 file changed, 38 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 262eef614cb12..3d7c3f6fdf223 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -9,6 +9,7 @@
 #include <linux/platform_device.h>
 #include <linux/phy/phy.h>
 #include <linux/regmap.h>
+#include <linux/regulator/consumer.h>
 
 #include <drm/bridge/dw_hdmi.h>
 #include <drm/drm_edid.h>
@@ -76,6 +77,8 @@ struct rockchip_hdmi {
 	struct clk *ref_clk;
 	struct clk *grf_clk;
 	struct dw_hdmi *hdmi;
+	struct regulator *avdd_0v9;
+	struct regulator *avdd_1v8;
 	struct phy *phy;
 };
 
@@ -223,6 +226,14 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 		return PTR_ERR(hdmi->grf_clk);
 	}
 
+	hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
+	if (IS_ERR(hdmi->avdd_0v9))
+		return PTR_ERR(hdmi->avdd_0v9);
+
+	hdmi->avdd_1v8 = devm_regulator_get(hdmi->dev, "avdd-1v8");
+	if (IS_ERR(hdmi->avdd_1v8))
+		return PTR_ERR(hdmi->avdd_1v8);
+
 	return 0;
 }
 
@@ -563,11 +574,23 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 		return ret;
 	}
 
+	ret = regulator_enable(hdmi->avdd_0v9);
+	if (ret) {
+		DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd0v9: %d\n", ret);
+		goto err_avdd_0v9;
+	}
+
+	ret = regulator_enable(hdmi->avdd_1v8);
+	if (ret) {
+		DRM_DEV_ERROR(hdmi->dev, "failed to enable avdd1v8: %d\n", ret);
+		goto err_avdd_1v8;
+	}
+
 	ret = clk_prepare_enable(hdmi->ref_clk);
 	if (ret) {
 		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI reference clock: %d\n",
 			      ret);
-		return ret;
+		goto err_clk;
 	}
 
 	if (hdmi->chip_data == &rk3568_chip_data) {
@@ -591,10 +614,19 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 	 */
 	if (IS_ERR(hdmi->hdmi)) {
 		ret = PTR_ERR(hdmi->hdmi);
-		drm_encoder_cleanup(encoder);
-		clk_disable_unprepare(hdmi->ref_clk);
+		goto err_bind;
 	}
 
+	return 0;
+
+err_bind:
+	clk_disable_unprepare(hdmi->ref_clk);
+	drm_encoder_cleanup(encoder);
+err_clk:
+	regulator_disable(hdmi->avdd_1v8);
+err_avdd_1v8:
+	regulator_disable(hdmi->avdd_0v9);
+err_avdd_0v9:
 	return ret;
 }
 
@@ -605,6 +637,9 @@ static void dw_hdmi_rockchip_unbind(struct device *dev, struct device *master,
 
 	dw_hdmi_unbind(hdmi->hdmi);
 	clk_disable_unprepare(hdmi->ref_clk);
+
+	regulator_disable(hdmi->avdd_1v8);
+	regulator_disable(hdmi->avdd_0v9);
 }
 
 static const struct component_ops dw_hdmi_rockchip_ops = {
-- 
2.30.2


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 05/22] drm/rockchip: dw_hdmi: Add support for hclk
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (3 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 04/22] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 06/22] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
                   ` (18 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 3d7c3f6fdf223..b9928e622adf5 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -76,6 +76,7 @@ struct rockchip_hdmi {
 	const struct rockchip_hdmi_chip_data *chip_data;
 	struct clk *ref_clk;
 	struct clk *grf_clk;
+	struct clk *hclk_clk;
 	struct dw_hdmi *hdmi;
 	struct regulator *avdd_0v9;
 	struct regulator *avdd_1v8;
@@ -226,6 +227,16 @@ static int rockchip_hdmi_parse_dt(struct rockchip_hdmi *hdmi)
 		return PTR_ERR(hdmi->grf_clk);
 	}
 
+	hdmi->hclk_clk = devm_clk_get(hdmi->dev, "hclk");
+	if (PTR_ERR(hdmi->hclk_clk) == -ENOENT) {
+		hdmi->hclk_clk = NULL;
+	} else if (PTR_ERR(hdmi->hclk_clk) == -EPROBE_DEFER) {
+		return -EPROBE_DEFER;
+	} else if (IS_ERR(hdmi->hclk_clk)) {
+		DRM_DEV_ERROR(hdmi->dev, "failed to get hclk_clk clock\n");
+		return PTR_ERR(hdmi->hclk_clk);
+	}
+
 	hdmi->avdd_0v9 = devm_regulator_get(hdmi->dev, "avdd-0v9");
 	if (IS_ERR(hdmi->avdd_0v9))
 		return PTR_ERR(hdmi->avdd_0v9);
@@ -593,6 +604,13 @@ static int dw_hdmi_rockchip_bind(struct device *dev, struct device *master,
 		goto err_clk;
 	}
 
+	ret = clk_prepare_enable(hdmi->hclk_clk);
+	if (ret) {
+		DRM_DEV_ERROR(hdmi->dev, "Failed to enable HDMI hclk clock: %d\n",
+			      ret);
+		goto err_clk;
+	}
+
 	if (hdmi->chip_data == &rk3568_chip_data) {
 		regmap_write(hdmi->regmap, RK3568_GRF_VO_CON1,
 			     HIWORD_UPDATE(RK3568_HDMI_SDAIN_MSK |
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 06/22] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (4 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 05/22] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
                   ` (17 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Rob Herring, Sascha Hauer

From: Benjamin Gaignard <benjamin.gaignard@collabora.com>

Define a new compatible for rk3568 HDMI.
This version of HDMI hardware block needs two new clocks hclk_vio and hclk
to provide phy reference clocks.

Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20210707120323.401785-2-benjamin.gaignard@collabora.com
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index da3b889ad8fcd..45cae4f57a1c1 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -23,6 +23,7 @@ properties:
       - rockchip,rk3288-dw-hdmi
       - rockchip,rk3328-dw-hdmi
       - rockchip,rk3399-dw-hdmi
+      - rockchip,rk3568-dw-hdmi
 
   reg-io-width:
     const: 4
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (5 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 06/22] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 14:27   ` Rob Herring
  2021-12-20 11:06 ` [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
                   ` (16 subsequent siblings)
  23 siblings, 1 reply; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

None of the upstream device tree files has a "unwedge" pinctrl
specified. Make it optional.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 45cae4f57a1c1..6e09dd2ee05ac 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -73,6 +73,7 @@ properties:
       The unwedge pinctrl entry shall drive the DDC SDA line low. This is
       intended to work around a hardware errata that can cause the DDC I2C
       bus to be wedged.
+    minItems: 1
     items:
       - const: default
       - const: unwedge
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (6 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 14:27   ` Rob Herring
  2021-12-21 14:31   ` Rob Herring
  2021-12-20 11:06 ` [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer
                   ` (15 subsequent siblings)
  23 siblings, 2 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

"vpll" is a misnomer. A clock input to a device should be named after
the usage in the device, not after the clock that drives it. On the
rk3568 the same clock is driven by the HPLL.
To fix that, this patch renames the vpll clock to ref clock.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../bindings/display/rockchip/rockchip,dw-hdmi.yaml        | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 6e09dd2ee05ac..3b40219e3ea60 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -47,11 +47,12 @@ properties:
       - enum:
           - cec
           - grf
-          - vpll
+          - ref
       - enum:
           - grf
-          - vpll
-      - const: vpll
+          - ref
+      - const:
+          - ref
 
   ddc-i2c-bus:
     $ref: /schemas/types.yaml#/definitions/phandle
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (7 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 14:27   ` Rob Herring
  2021-12-20 11:06 ` [PATCH 10/22] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
                   ` (14 subsequent siblings)
  23 siblings, 1 reply; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../bindings/display/rockchip/rockchip,dw-hdmi.yaml   | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index 3b40219e3ea60..bf8618b26721a 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -28,6 +28,17 @@ properties:
   reg-io-width:
     const: 4
 
+  avdd-0v9-supply:
+    description:
+      A 0.9V supply that powers up the SoC internal circuitry. The actual pin name
+      varies between the different SoCs and is usually HDMI_TX_AVDD_0V9 or sometimes
+      HDMI_AVDD_1V0.
+
+  avdd-1v8-supply:
+    description:
+      A 1.8V supply that powers up the SoC internal circuitry. The pin name on the
+      SoC usually is HDMI_TX_AVDD_1V8.
+
   clocks:
     minItems: 2
     items:
-- 
2.30.2


_______________________________________________
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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 10/22] dt-bindings: display: rockchip: dw-hdmi: Add additional clock
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (8 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
                   ` (13 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The rk3568 HDMI has an additional clock that needs to be enabled for the
HDMI controller to work. The purpose of that clock is not clear. It is
named "hclk" in the downstream driver, so use the same name.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../bindings/display/rockchip/rockchip,dw-hdmi.yaml    | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
index bf8618b26721a..a50ebf24b7f93 100644
--- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
@@ -44,11 +44,12 @@ properties:
     items:
       - {}
       - {}
-      # The next three clocks are all optional, but shall be specified in this
+      # The next four clocks are all optional, but shall be specified in this
       # order when present.
       - description: The HDMI CEC controller main clock
       - description: Power for GRF IO
       - description: External clock for some HDMI PHY
+      - description: hclk
 
   clock-names:
     minItems: 2
@@ -59,11 +60,16 @@ properties:
           - cec
           - grf
           - ref
+          - hclk
       - enum:
           - grf
           - ref
-      - const:
+          - hclk
+      - enum:
           - ref
+          - hclk
+      - const:
+          - hclk
 
   ddc-i2c-bus:
     $ref: /schemas/types.yaml#/definitions/phandle
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (9 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 10/22] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 14:27   ` Rob Herring
  2021-12-21 14:33   ` Rob Herring
  2021-12-20 11:06 ` [PATCH 12/22] arm64: dts: rockchip: rk3399: reorder hmdi clocks Sascha Hauer
                   ` (12 subsequent siblings)
  23 siblings, 2 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
The binding differs slightly from the existing VOP binding, so add a new
binding file for it.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../display/rockchip/rockchip-vop2.yaml       | 146 ++++++++++++++++++
 1 file changed, 146 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml

diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
new file mode 100644
index 0000000000000..df14d5aa85c85
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip SoC display controller (VOP2)
+
+description:
+  VOP2 (Video Output Processor v2) is the display controller for the Rockchip
+  series of SoCs which transfers the image data from a video memory
+  buffer to an external LCD interface.
+
+maintainers:
+  - Sandy Huang <hjc@rock-chips.com>
+  - Heiko Stuebner <heiko@sntech.de>
+
+properties:
+  compatible:
+    enum:
+      - rockchip,rk3566-vop
+      - rockchip,rk3568-vop
+
+  reg:
+    minItems: 1
+    items:
+      - description:
+          Must contain one entry corresponding to the base address and length
+          of the register space.
+      - description:
+          Can optionally contain a second entry corresponding to
+          the CRTC gamma LUT address.
+
+  interrupts:
+    maxItems: 1
+    description:
+      The VOP interrupt is shared by several interrupt sources, such as
+      frame start (VSYNC), line flag and other status interrupts.
+
+  clocks:
+    items:
+      - description: Clock for ddr buffer transfer.
+      - description: Clock for the ahb bus to R/W the phy regs.
+      - description: Pixel clock for video port 0.
+      - description: Pixel clock for video port 1.
+      - description: Pixel clock for video port 2.
+
+  clock-names:
+    items:
+      - const: aclk_vop
+      - const: hclk_vop
+      - const: dclk_vp0
+      - const: dclk_vp1
+      - const: dclk_vp2
+
+  rockchip,grf:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to GRF regs used for misc control
+
+  ports:
+    $ref: /schemas/graph.yaml#/properties/port
+
+    properties:
+      port@0:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output endpoint of VP0
+
+      port@1:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output endpoint of VP1
+
+      port@:
+        $ref: /schemas/graph.yaml#/properties/port
+        description:
+          Output endpoint of VP2
+
+  assigned-clocks: true
+
+  assigned-clock-rates: true
+
+  assigned-clock-parents: true
+
+  iommus:
+    maxItems: 1
+
+  power-domains:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - clock-names
+  - ports
+
+additionalProperties: false
+
+examples:
+  - |
+        #include <dt-bindings/clock/rk3568-cru.h>
+        #include <dt-bindings/interrupt-controller/arm-gic.h>
+        #include <dt-bindings/power/rk3568-power.h>
+        bus {
+            #address-cells = <2>;
+            #size-cells = <2>;
+            vop: vop@fe040000 {
+                compatible = "rockchip,rk3568-vop";
+                reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+                clocks = <&cru ACLK_VOP>,
+                         <&cru HCLK_VOP>,
+                         <&cru DCLK_VOP0>,
+                         <&cru DCLK_VOP1>,
+                         <&cru DCLK_VOP2>;
+                clock-names = "aclk_vop",
+                              "hclk_vop",
+                              "dclk_vp0",
+                              "dclk_vp1",
+                              "dclk_vp2";
+                power-domains = <&power RK3568_PD_VO>;
+                iommus = <&vop_mmu>;
+                vop_out: ports {
+                    #address-cells = <1>;
+                    #size-cells = <0>;
+                    vp0: port@0 {
+                        reg = <0>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                    };
+                    vp1: port@1 {
+                        reg = <1>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                    };
+                    vp2: port@2 {
+                        reg = <2>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                    };
+                };
+            };
+        };
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 12/22] arm64: dts: rockchip: rk3399: reorder hmdi clocks
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (10 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 13/22] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
                   ` (11 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The binding specifies the clock order to "cec", "grf", "vpll". Reorder
the clocks accordingly.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index d3cdf6f42a303..080457a68e3c7 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1881,10 +1881,10 @@ hdmi: hdmi@ff940000 {
 		interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&cru PCLK_HDMI_CTRL>,
 			 <&cru SCLK_HDMI_SFR>,
-			 <&cru PLL_VPLL>,
+			 <&cru SCLK_HDMI_CEC>,
 			 <&cru PCLK_VIO_GRF>,
-			 <&cru SCLK_HDMI_CEC>;
-		clock-names = "iahb", "isfr", "vpll", "grf", "cec";
+			 <&cru PLL_VPLL>;
+		clock-names = "iahb", "isfr", "cec", "grf", "vpll";
 		power-domains = <&power RK3399_PD_HDCP>;
 		reg-io-width = <4>;
 		rockchip,grf = <&grf>;
-- 
2.30.2


_______________________________________________
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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 13/22] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref'
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (11 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 12/22] arm64: dts: rockchip: rk3399: reorder hmdi clocks Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 14/22] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
                   ` (10 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The reference clock for the HDMI controller has been renamed to 'ref',
the previous 'vpll' name is only left for compatibility in the driver.
Rename the clock to the new name.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 080457a68e3c7..d0add619b0d22 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -1884,7 +1884,7 @@ hdmi: hdmi@ff940000 {
 			 <&cru SCLK_HDMI_CEC>,
 			 <&cru PCLK_VIO_GRF>,
 			 <&cru PLL_VPLL>;
-		clock-names = "iahb", "isfr", "cec", "grf", "vpll";
+		clock-names = "iahb", "isfr", "cec", "grf", "ref";
 		power-domains = <&power RK3399_PD_HDCP>;
 		reg-io-width = <4>;
 		rockchip,grf = <&grf>;
-- 
2.30.2


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 14/22] arm64: dts: rockchip: rk356x: Add VOP2 nodes
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (12 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 13/22] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 15/22] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
                   ` (9 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The VOP2 is the display output controller on the RK3568. Add the node
for it to the dtsi file along with the required display-subsystem node
and the iommu node.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/rockchip/rk3566.dtsi |  4 ++
 arch/arm64/boot/dts/rockchip/rk3568.dtsi |  4 ++
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 50 ++++++++++++++++++++++++
 include/dt-bindings/soc/rockchip,vop2.h  | 14 +++++++
 4 files changed, 72 insertions(+)
 create mode 100644 include/dt-bindings/soc/rockchip,vop2.h

diff --git a/arch/arm64/boot/dts/rockchip/rk3566.dtsi b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
index 3839eef5e4f76..595fa2562cb8e 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3566.dtsi
@@ -18,3 +18,7 @@ power-domain@RK3568_PD_PIPE {
 		#power-domain-cells = <0>;
 	};
 };
+
+&vop {
+	compatible = "rockchip,rk3566-vop";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
index 2fd313a295f8a..1e55efb6fcfde 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
@@ -95,3 +95,7 @@ power-domain@RK3568_PD_PIPE {
 		#power-domain-cells = <0>;
 	};
 };
+
+&vop {
+	compatible = "rockchip,rk3568-vop";
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 46d9552f60284..7c62ad921cf7b 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/power/rk3568-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -125,6 +126,11 @@ opp-1800000000 {
 		};
 	};
 
+	display_subsystem: display-subsystem {
+		compatible = "rockchip,display-subsystem";
+		ports = <&vop_out>;
+	};
+
 	firmware {
 		scmi: scmi {
 			compatible = "arm,scmi-smc";
@@ -447,6 +453,50 @@ gmac1_mtl_tx_setup: tx-queues-config {
 		};
 	};
 
+	vop: vop@fe040000 {
+		reg = <0x0 0xfe040000 0x0 0x5000>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
+		clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
+		iommus = <&vop_mmu>;
+		power-domains = <&power RK3568_PD_VO>;
+		rockchip,grf = <&grf>;
+		status = "disabled";
+
+		vop_out: ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			vp0: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			vp1: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			vp2: port@2 {
+				reg = <2>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
+	vop_mmu: iommu@fe043e00 {
+		compatible = "rockchip,rk3568-iommu";
+		reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
+		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
+		clock-names = "aclk", "iface";
+		#iommu-cells = <0>;
+		status = "disabled";
+	};
+
 	qos_gpu: qos@fe128000 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe128000 0x0 0x20>;
diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h
new file mode 100644
index 0000000000000..0a87bc90564a7
--- /dev/null
+++ b/include/dt-bindings/soc/rockchip,vop2.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+
+#ifndef __DT_BINDINGS_ROCKCHIP_VOP2_H
+#define __DT_BINDINGS_ROCKCHIP_VOP2_H
+
+#define RK3568_VOP2_EP_RGB	0
+#define RK3568_VOP2_EP_HDMI	1
+#define RK3568_VOP2_EP_EDP	2
+#define RK3568_VOP2_EP_MIPI0	3
+#define RK3568_VOP2_EP_LVDS0	4
+#define RK3568_VOP2_EP_MIPI1	5
+#define RK3568_VOP2_EP_LVDS1	6
+
+#endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 15/22] arm64: dts: rockchip: rk356x: Add HDMI nodes
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (13 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 14/22] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 16/22] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
                   ` (8 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

Add support for the HDMI port found on RK3568.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 37 +++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 7c62ad921cf7b..6d93b8fcee179 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -10,7 +10,6 @@
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/power/rk3568-power.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
-#include <dt-bindings/soc/rockchip,vop2.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -497,6 +496,42 @@ vop_mmu: iommu@fe043e00 {
 		status = "disabled";
 	};
 
+	hdmi: hdmi@fe0a0000 {
+		compatible = "rockchip,rk3568-dw-hdmi";
+		reg = <0x0 0xfe0a0000 0x0 0x20000>;
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&cru PCLK_HDMI_HOST>,
+			 <&cru CLK_HDMI_SFR>,
+			 <&cru CLK_HDMI_CEC>,
+			 <&pmucru CLK_HDMI_REF>,
+			 <&cru HCLK_VOP>;
+		clock-names = "iahb", "isfr", "cec", "ref", "hclk";
+		pinctrl-names = "default";
+		pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
+		power-domains = <&power RK3568_PD_VO>;
+		reg-io-width = <4>;
+		rockchip,grf = <&grf>;
+		#sound-dai-cells = <0>;
+		status = "disabled";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			hdmi_in: port@0 {
+				reg = <0>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+
+			hdmi_out: port@1 {
+				reg = <1>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+			};
+		};
+	};
+
 	qos_gpu: qos@fe128000 {
 		compatible = "rockchip,rk3568-qos", "syscon";
 		reg = <0x0 0xfe128000 0x0 0x20>;
-- 
2.30.2


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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 16/22] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (14 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 15/22] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 17/22] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
                   ` (7 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

This enabled the VOP2 display controller along with hdmi and the
required port routes which is enough to get a picture out of the
hdmi port of the board.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../boot/dts/rockchip/rk3568-evb1-v10.dts     | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
index 184e2aa2416af..3fa0e654d7cf6 100644
--- a/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3568-evb1-v10.dts
@@ -7,6 +7,7 @@
 /dts-v1/;
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3568.dtsi"
 
 / {
@@ -33,6 +34,17 @@ dc_12v: dc-12v {
 		regulator-max-microvolt = <12000000>;
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "c";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	vcc3v3_sys: vcc3v3-sys {
 		compatible = "regulator-fixed";
 		regulator-name = "vcc3v3_sys";
@@ -106,6 +118,12 @@ &gmac1m1_rgmii_clk
 	status = "okay";
 };
 
+&hdmi {
+	avdd-0v9-supply = <&vdda0v9_image>;
+	avdd-1v8-supply = <&vcca1v8_image>;
+	status = "okay";
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -390,3 +408,33 @@ &sdmmc0 {
 &uart2 {
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint@0 {
+		reg = <0>;
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI {
+		reg = <RK3568_VOP2_EP_HDMI>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
-- 
2.30.2


_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 17/22] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (15 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 16/22] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 18/22] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* Sascha Hauer
                   ` (6 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

From: Michael Riesch <michael.riesch@wolfvision.net>

Enable the RK356x Video Output Processor (VOP) 2 on the Pine64
Quartz64 Model A.

Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 .../boot/dts/rockchip/rk3566-quartz64-a.dts   | 48 +++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 4d4b2a301b1a4..29748537cdbd0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -4,6 +4,7 @@
 
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
 #include "rk3566.dtsi"
 
 / {
@@ -35,6 +36,17 @@ fan: gpio_fan {
 		#cooling-cells = <2>;
 	};
 
+	hdmi-con {
+		compatible = "hdmi-connector";
+		type = "c";
+
+		port {
+			hdmi_con_in: endpoint {
+				remote-endpoint = <&hdmi_out_con>;
+			};
+		};
+	};
+
 	leds {
 		compatible = "gpio-leds";
 
@@ -205,6 +217,18 @@ &gmac1m0_clkinout
 	status = "okay";
 };
 
+&hdmi {
+	avdd-0v9-supply = <&vdda_0v9>;
+	avdd-1v8-supply = <&vcc_1v8>;
+	status = "okay";
+};
+
+&hdmi_out {
+	hdmi_out_con: endpoint {
+		remote-endpoint = <&hdmi_con_in>;
+	};
+};
+
 &i2c0 {
 	status = "okay";
 
@@ -546,3 +570,27 @@ bluetooth {
 &uart2 {
 	status = "okay";
 };
+
+&vop {
+	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+	status = "okay";
+};
+
+&vop_mmu {
+	status = "okay";
+};
+
+&hdmi_in {
+	hdmi_in_vp0: endpoint@0 {
+		reg = <0>;
+		remote-endpoint = <&vp0_out_hdmi>;
+	};
+};
+
+&vp0 {
+	vp0_out_hdmi: endpoint@RK3568_VOP2_EP_HDMI {
+		reg = <RK3568_VOP2_EP_HDMI>;
+		remote-endpoint = <&hdmi_in_vp0>;
+	};
+};
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 18/22] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop*
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (16 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 17/22] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 19/22] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Sascha Hauer
                   ` (5 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

The pixel clocks dclk_vop[012] can be clocked from hpll, vpll, gpll or
cpll. gpll and cpll also drive many other clocks, so changing the
dclk_vop[012] clocks could change these other clocks as well. Drop
CLK_SET_RATE_PARENT to fix that. With this change the VOP2 driver can
only adjust the pixel clocks with the divider between the PLL and the
dclk_vop[012] which means the user may have to adjust the PLL clock to a
suitable rate using the assigned-clock-rate device tree property.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/rockchip/clk-rk3568.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 69a9e8069a486..604a367bc498a 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1038,13 +1038,13 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
 			RK3568_CLKGATE_CON(20), 8, GFLAGS),
 	GATE(HCLK_VOP, "hclk_vop", "hclk_vo", 0,
 			RK3568_CLKGATE_CON(20), 9, GFLAGS),
-	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VOP0, "dclk_vop0", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
 			RK3568_CLKSEL_CON(39), 10, 2, MFLAGS, 0, 8, DFLAGS,
 			RK3568_CLKGATE_CON(20), 10, GFLAGS),
-	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
+	COMPOSITE(DCLK_VOP1, "dclk_vop1", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
 			RK3568_CLKSEL_CON(40), 10, 2, MFLAGS, 0, 8, DFLAGS,
 			RK3568_CLKGATE_CON(20), 11, GFLAGS),
-	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, 0,
+	COMPOSITE(DCLK_VOP2, "dclk_vop2", hpll_vpll_gpll_cpll_p, CLK_SET_RATE_NO_REPARENT,
 			RK3568_CLKSEL_CON(41), 10, 2, MFLAGS, 0, 8, DFLAGS,
 			RK3568_CLKGATE_CON(20), 12, GFLAGS),
 	GATE(CLK_VOP_PWM, "clk_vop_pwm", "xin24m", 0,
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 19/22] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (17 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 18/22] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:06 ` [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer
                   ` (4 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

On the rk3568 we have this (simplified) situation:

 .--------.     .-----.    .---------.
-| hpll   |--.--| /n  |----|dclk_vop0|-
 `--------´  |  `-----´    `---------´
             |  .-----.    .---------.
             `--| /m  |----|dclk_vop1|-
             |  `-----´    `---------´
             |             .---------.
             `-------------|hdmi_ref |-
                           `---------´

For the HDMI to work the HDMI reference clock needs to be the same as the
pixel clock which means the dividers have be set to one. The last patch removed
the CLK_SET_RATE_PARENT flag from the pixel clocks which means the hpll is not
changed on pixel clock changes. In order to allow the HDMI controller to
set a suitable PLL rate we now add the CLK_SET_RATE_PARENT flag to the
HDMI reference clock. With this the flow becomes:

1) HDMI controller driver sets the rate to its pixel clock which means
   hpll is set to the pixel clock
2) VOP2 driver sets dclk_vop[012] to the pixel clock. As this can't change
   the hpll clock anymore this means only the divider is adjusted to the
   desired value of dividing by one.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/clk/rockchip/clk-rk3568.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index 604a367bc498a..1fe78a58010ea 100644
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -1562,7 +1562,7 @@ static struct rockchip_clk_branch rk3568_clk_pmu_branches[] __initdata = {
 			RK3568_PMU_CLKGATE_CON(2), 14, GFLAGS),
 	GATE(XIN_OSC0_EDPPHY_G, "xin_osc0_edpphy_g", "xin24m", 0,
 			RK3568_PMU_CLKGATE_CON(2), 15, GFLAGS),
-	MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, 0,
+	MUX(CLK_HDMI_REF, "clk_hdmi_ref", clk_hdmi_ref_p, CLK_SET_RATE_PARENT,
 			RK3568_PMU_CLKSEL_CON(8), 7, 1, MFLAGS),
 };
 
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (18 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 19/22] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-21 17:31   ` Heiko Stübner
  2021-12-20 11:06 ` [PATCH 21/22] drm/rockchip: Make VOP driver optional Sascha Hauer
                   ` (3 subsequent siblings)
  23 siblings, 1 reply; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

Add a device node to drm_encoder which corresponds with the port node
in the DT description of the encoder. This allows drivers to find the
of_graph link between a crtc and an encoder.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 include/drm/drm_encoder.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h
index 6e91a0280f31b..3acd054b1eb3e 100644
--- a/include/drm/drm_encoder.h
+++ b/include/drm/drm_encoder.h
@@ -99,6 +99,8 @@ struct drm_encoder {
 	struct drm_device *dev;
 	struct list_head head;
 
+	struct device_node *port;
+
 	struct drm_mode_object base;
 	char *name;
 	/**
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* [PATCH 21/22] drm/rockchip: Make VOP driver optional
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (19 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer
@ 2021-12-20 11:06 ` Sascha Hauer
  2021-12-20 11:51 ` [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Nicolas Frattaroli
                   ` (2 subsequent siblings)
  23 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 11:06 UTC (permalink / raw)
  To: dri-devel
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

With upcoming VOP2 support VOP won't be the only choice anymore, so make
the VOP driver optional.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
 drivers/gpu/drm/rockchip/Kconfig            | 8 ++++++++
 drivers/gpu/drm/rockchip/Makefile           | 3 ++-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
 3 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 9f1ecefc39332..b9b156308460a 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -21,8 +21,16 @@ config DRM_ROCKCHIP
 
 if DRM_ROCKCHIP
 
+config ROCKCHIP_VOP
+	bool "Rockchip VOP driver"
+	default y
+	help
+	  This selects support for the VOP driver. You should enable it
+	  on all older SoCs up to RK3399.
+
 config ROCKCHIP_ANALOGIX_DP
 	bool "Rockchip specific extensions for Analogix DP driver"
+	depends on ROCKCHIP_VOP
 	help
 	  This selects support for Rockchip SoC specific extensions
 	  for the Analogix Core DP driver. If you want to enable DP
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index 17a9e7eb2130d..cd6e7bb5ce9c5 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -4,9 +4,10 @@
 # Direct Rendering Infrastructure (DRI) in XFree86 4.1.0 and higher.
 
 rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
-		rockchip_drm_gem.o rockchip_drm_vop.o rockchip_vop_reg.o
+		rockchip_drm_gem.o
 rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
 
+rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
 rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
 rockchipdrm-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index e4ebe60b3cc1a..64fa5fd62c01a 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -473,7 +473,7 @@ static int __init rockchip_drm_init(void)
 	int ret;
 
 	num_rockchip_sub_drivers = 0;
-	ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_DRM_ROCKCHIP);
+	ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP);
 	ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
 				CONFIG_ROCKCHIP_LVDS);
 	ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
-- 
2.30.2


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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (20 preceding siblings ...)
  2021-12-20 11:06 ` [PATCH 21/22] drm/rockchip: Make VOP driver optional Sascha Hauer
@ 2021-12-20 11:51 ` Nicolas Frattaroli
       [not found] ` <20211220110630.3521121-23-s.hauer@pengutronix.de>
  2022-01-19 11:29 ` [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Piotr Oniszczuk
  23 siblings, 0 replies; 45+ messages in thread
From: Nicolas Frattaroli @ 2021-12-20 11:51 UTC (permalink / raw)
  To: dri-devel, linux-rockchip
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer

On Montag, 20. Dezember 2021 12:06:08 CET Sascha Hauer wrote:
> 
> Third round of patches and last one for this year. I hopefully integrated
> all review feedback. Additionally the driver is now fully converted to
> regmap, so no struct vop_reg necessary anymore.
> 
> Sascha
> 
> Changes since v2:
> - Add pin names to HDMI supply pin description
> - Add hclk support to HDMI driver
> - Dual license rockchip-vop2 binding, update binding
> - Add HDMI connector to board dts files
> - drop unnecessary gamma_lut registers from vop2
> - Update dclk_vop[012] clock handling, no longer hacks needed
> - Complete regmap conversion

Hi Sascha,

for future reference, you can add `-v 3` to your git format-patch
command line to mark the whole patch series as PATCH v3 and not
just the cover letter.

Thanks for your continued work on this,
Nicolas Frattaroli



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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
       [not found] ` <20211220110630.3521121-23-s.hauer@pengutronix.de>
@ 2021-12-20 14:16   ` Nicolas Frattaroli
  2021-12-20 16:53     ` Nicolas Frattaroli
  2021-12-20 18:51     ` Sascha Hauer
  2021-12-21 13:44   ` Nicolas Frattaroli
       [not found]   ` <a0942adc-52c1-811e-0de6-d0616266ce2d@rock-chips.com>
  2 siblings, 2 replies; 45+ messages in thread
From: Nicolas Frattaroli @ 2021-12-20 14:16 UTC (permalink / raw)
  To: dri-devel, linux-rockchip
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer, Sascha Hauer

On Montag, 20. Dezember 2021 12:06:30 CET Sascha Hauer wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> It replaces the VOP unit found in the older Rockchip SoCs.
> 
> This driver has been derived from the downstream Rockchip Kernel and
> heavily modified:
> 
> - All nonstandard DRM properties have been removed
> - dropped struct vop2_plane_state and pass around less data between
>   functions
> - Dropped all DRM_FORMAT_* not known on upstream
> - rework register access to get rid of excessively used macros
> - Drop all waiting for framesyncs
> 
> The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> board. Overlay support is tested with the modetest utility. AFBC support
> on the cluster windows is tested with weston-simple-dmabuf-egl on
> weston using the (yet to be upstreamed) panfrost driver support.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---

Hi Sascha,

sadly I'm getting

[    1.668856] rockchip-drm display-subsystem: [drm] *ERROR* failed to get vop2 register byname
[    1.669621] rockchip-drm display-subsystem: failed to bind fe040000.vop (ops vop2_component_ops): -22
[    1.670584] rockchip-drm display-subsystem: master bind failed: -22
[    1.671164] dwhdmi-rockchip: probe of fe0a0000.hdmi failed with error -22

on a Quartz64 Model A.


> +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> +	if (!res) {
> +		drm_err(vop2->drm, "failed to get vop2 register byname\n");
> +		return -EINVAL;
> +	}

This seems to be the code that triggers it.

Any ideas as to what could be causing this?

Regards,
Nicolas Frattaroli




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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-20 11:06 ` [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
@ 2021-12-20 14:27   ` Rob Herring
  2021-12-21 14:31   ` Rob Herring
  1 sibling, 0 replies; 45+ messages in thread
From: Rob Herring @ 2021-12-20 14:27 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: Heiko Stübner, Peter Geis, linux-arm-kernel, dri-devel,
	linux-rockchip, Andy Yan, kernel, Benjamin Gaignard, devicetree,
	Michael Riesch, Sandy Huang

On Mon, 20 Dec 2021 12:06:16 +0100, Sascha Hauer wrote:
> "vpll" is a misnomer. A clock input to a device should be named after
> the usage in the device, not after the clock that drives it. On the
> rk3568 the same clock is driven by the HPLL.
> To fix that, this patch renames the vpll clock to ref clock.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  .../bindings/display/rockchip/rockchip,dw-hdmi.yaml        | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml: properties:clock-names:items: 'oneOf' conditional failed, one must be fixed:
	[{}, {}, {'enum': ['cec', 'grf', 'ref']}, {'enum': ['grf', 'ref']}, {'const': ['ref']}] is not of type 'object'
	['ref'] is not of type 'string'
	from schema $id: http://devicetree.org/meta-schemas/string-array.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml: ignoring, error in schema: properties: clock-names: items
warning: no schema found in file: ./Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.example.dt.yaml:0:0: /example-0/hdmi@ff980000: failed to match any schema with compatible: ['rockchip,rk3288-dw-hdmi']

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1570972

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support
  2021-12-20 11:06 ` [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer
@ 2021-12-20 14:27   ` Rob Herring
  0 siblings, 0 replies; 45+ messages in thread
From: Rob Herring @ 2021-12-20 14:27 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: Heiko Stübner, dri-devel, Sandy Huang, Peter Geis,
	Michael Riesch, Andy Yan, linux-arm-kernel, kernel,
	Benjamin Gaignard, linux-rockchip, devicetree

On Mon, 20 Dec 2021 12:06:17 +0100, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  .../bindings/display/rockchip/rockchip,dw-hdmi.yaml   | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1570969


hdmi@200a0000: clock-names:0: 'iahb' was expected
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: clock-names:1: 'isfr' was expected
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: pinctrl-names: ['default'] is too short
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: ports:port: 'endpoint@1' is a required property
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: Unevaluated properties are not allowed ('reg', 'interrupts', 'pinctrl-names', 'pinctrl-0', 'resets', 'reset-names', 'ports' were unexpected)
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@ff3c0000: interrupts: [[0, 35, 4], [0, 71, 4]] is too long
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: pinctrl-names: ['default'] is too short
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: ports:port: 'endpoint@0' is a required property
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: ports:port: 'endpoint@1' is a required property
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: Unevaluated properties are not allowed ('reg', 'interrupts', 'pinctrl-names', 'pinctrl-0', '#sound-dai-cells', 'ports' were unexpected)
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff940000: clock-names:4: 'vpll' was expected
	arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-ficus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-firefly.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-orangepi.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock960.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-sapphire.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dt.yaml

hdmi@ff940000: pinctrl-names: ['default'] is too short
	arch/arm64/boot/dts/rockchip/rk3399-ficus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-firefly.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock960.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dt.yaml

hdmi@ff980000: pinctrl-names: ['default'] is too short
	arch/arm/boot/dts/rk3288-firefly-reload.dt.yaml
	arch/arm/boot/dts/rk3288-rock-pi-n8.dt.yaml
	arch/arm/boot/dts/rk3288-tinker-s.dt.yaml


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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2
  2021-12-20 11:06 ` [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
@ 2021-12-20 14:27   ` Rob Herring
  2021-12-21 14:33   ` Rob Herring
  1 sibling, 0 replies; 45+ messages in thread
From: Rob Herring @ 2021-12-20 14:27 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: linux-arm-kernel, linux-rockchip, Michael Riesch, Sandy Huang,
	dri-devel, Andy Yan, devicetree, Heiko Stübner, Peter Geis,
	Benjamin Gaignard, kernel

On Mon, 20 Dec 2021 12:06:19 +0100, Sascha Hauer wrote:
> The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
> The binding differs slightly from the existing VOP binding, so add a new
> binding file for it.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  .../display/rockchip/rockchip-vop2.yaml       | 146 ++++++++++++++++++
>  1 file changed, 146 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.example.dt.yaml: vop@fe040000: ports: Unevaluated properties are not allowed ('port@0', 'port@1', 'port@2' were unexpected)
	From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1570971

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.


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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional
  2021-12-20 11:06 ` [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
@ 2021-12-20 14:27   ` Rob Herring
  0 siblings, 0 replies; 45+ messages in thread
From: Rob Herring @ 2021-12-20 14:27 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: kernel, Heiko Stübner, Michael Riesch, Peter Geis,
	linux-arm-kernel, Benjamin Gaignard, Sandy Huang, devicetree,
	Andy Yan, dri-devel, linux-rockchip

On Mon, 20 Dec 2021 12:06:15 +0100, Sascha Hauer wrote:
> None of the upstream device tree files has a "unwedge" pinctrl
> specified. Make it optional.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  .../devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/1570970


hdmi@200a0000: clock-names:0: 'iahb' was expected
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: clock-names:1: 'isfr' was expected
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: ports:port: 'endpoint@1' is a required property
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@200a0000: Unevaluated properties are not allowed ('reg', 'interrupts', 'pinctrl-0', 'resets', 'reset-names', 'ports' were unexpected)
	arch/arm/boot/dts/rk3228-evb.dt.yaml
	arch/arm/boot/dts/rk3229-evb.dt.yaml
	arch/arm/boot/dts/rk3229-xms6.dt.yaml

hdmi@ff3c0000: interrupts: [[0, 35, 4], [0, 71, 4]] is too long
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: ports:port: 'endpoint@0' is a required property
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: ports:port: 'endpoint@1' is a required property
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff3c0000: Unevaluated properties are not allowed ('reg', 'interrupts', 'pinctrl-0', '#sound-dai-cells', 'ports' were unexpected)
	arch/arm64/boot/dts/rockchip/rk3318-a95x-z2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-a1.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-rock-pi-e.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3328-roc-pc.dt.yaml

hdmi@ff940000: clock-names:4: 'vpll' was expected
	arch/arm64/boot/dts/rockchip/rk3399-evb.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-ficus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-firefly.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-kevin.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-dumo.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-inx.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet-kd.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-hugsun-x99.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-captain.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-khadas-edge-v.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-kobol-helios64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-leez-p710.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopc-t4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4b.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-m4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-neo4.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-orangepi.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399pro-rock-pi-n10.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-puma-haikou.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock960.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4a-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4c.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-rockpro64-v2.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc-mezzanine.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-roc-pc-plus.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-sapphire.dt.yaml
	arch/arm64/boot/dts/rockchip/rk3399-sapphire-excavator.dt.yaml


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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
  2021-12-20 14:16   ` [PATCH 22/22] drm: rockchip: Add VOP2 driver Nicolas Frattaroli
@ 2021-12-20 16:53     ` Nicolas Frattaroli
  2021-12-20 18:51     ` Sascha Hauer
  1 sibling, 0 replies; 45+ messages in thread
From: Nicolas Frattaroli @ 2021-12-20 16:53 UTC (permalink / raw)
  To: dri-devel, linux-rockchip
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer, Sascha Hauer,
	Nicolas Frattaroli

On Montag, 20. Dezember 2021 15:16:55 CET Nicolas Frattaroli wrote:
> On Montag, 20. Dezember 2021 12:06:30 CET Sascha Hauer wrote:
> > From: Andy Yan <andy.yan@rock-chips.com>
> > 
> > The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> > It replaces the VOP unit found in the older Rockchip SoCs.
> > 
> > This driver has been derived from the downstream Rockchip Kernel and
> > heavily modified:
> > 
> > - All nonstandard DRM properties have been removed
> > - dropped struct vop2_plane_state and pass around less data between
> >   functions
> > - Dropped all DRM_FORMAT_* not known on upstream
> > - rework register access to get rid of excessively used macros
> > - Drop all waiting for framesyncs
> > 
> > The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> > board. Overlay support is tested with the modetest utility. AFBC support
> > on the cluster windows is tested with weston-simple-dmabuf-egl on
> > weston using the (yet to be upstreamed) panfrost driver support.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> 
> Hi Sascha,
> 
> sadly I'm getting
> 
> [    1.668856] rockchip-drm display-subsystem: [drm] *ERROR* failed to get vop2 register byname
> [    1.669621] rockchip-drm display-subsystem: failed to bind fe040000.vop (ops vop2_component_ops): -22
> [    1.670584] rockchip-drm display-subsystem: master bind failed: -22
> [    1.671164] dwhdmi-rockchip: probe of fe0a0000.hdmi failed with error -22
> 
> on a Quartz64 Model A.
> 
> 
> > +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> > +	if (!res) {
> > +		drm_err(vop2->drm, "failed to get vop2 register byname\n");
> > +		return -EINVAL;
> > +	}
> 
> This seems to be the code that triggers it.
> 
> Any ideas as to what could be causing this?
> 
> Regards,
> Nicolas Frattaroli
> 

A small follow-up:

We're trying to get IORESOURCE_MEM by the name "regs", but nothing
has a reg-names property in the device tree changes you sent in.

How did you test this on your system?

Also, adding the reg-names = "regs"; to the vop node doesn't make
it probe, it just fails with

[    1.668560] rockchip-vop2 fe040000.vop: can't request region for resource [mem 0xfe040000-0xfe044fff]

then.

We're also trying to get gamma_lut the same way, but your cover letter states

> drop unnecessary gamma_lut registers from vop2

which makes me wonder: is this the correct series of patches you sent in?

Regards,
Nicolas Frattaroli



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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
  2021-12-20 14:16   ` [PATCH 22/22] drm: rockchip: Add VOP2 driver Nicolas Frattaroli
  2021-12-20 16:53     ` Nicolas Frattaroli
@ 2021-12-20 18:51     ` Sascha Hauer
  1 sibling, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2021-12-20 18:51 UTC (permalink / raw)
  To: Nicolas Frattaroli
  Cc: dri-devel, linux-rockchip, linux-arm-kernel, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis

On Mon, Dec 20, 2021 at 03:16:55PM +0100, Nicolas Frattaroli wrote:
> On Montag, 20. Dezember 2021 12:06:30 CET Sascha Hauer wrote:
> > From: Andy Yan <andy.yan@rock-chips.com>
> > 
> > The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> > It replaces the VOP unit found in the older Rockchip SoCs.
> > 
> > This driver has been derived from the downstream Rockchip Kernel and
> > heavily modified:
> > 
> > - All nonstandard DRM properties have been removed
> > - dropped struct vop2_plane_state and pass around less data between
> >   functions
> > - Dropped all DRM_FORMAT_* not known on upstream
> > - rework register access to get rid of excessively used macros
> > - Drop all waiting for framesyncs
> > 
> > The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> > board. Overlay support is tested with the modetest utility. AFBC support
> > on the cluster windows is tested with weston-simple-dmabuf-egl on
> > weston using the (yet to be upstreamed) panfrost driver support.
> > 
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
> 
> Hi Sascha,
> 
> sadly I'm getting
> 
> [    1.668856] rockchip-drm display-subsystem: [drm] *ERROR* failed to get vop2 register byname
> [    1.669621] rockchip-drm display-subsystem: failed to bind fe040000.vop (ops vop2_component_ops): -22
> [    1.670584] rockchip-drm display-subsystem: master bind failed: -22
> [    1.671164] dwhdmi-rockchip: probe of fe0a0000.hdmi failed with error -22
> 
> on a Quartz64 Model A.
> 
> 
> > +	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> > +	if (!res) {
> > +		drm_err(vop2->drm, "failed to get vop2 register byname\n");
> > +		return -EINVAL;
> > +	}
> 
> This seems to be the code that triggers it.
> 
> Any ideas as to what could be causing this?

Gnaa, this was a last minute change I did and thought it was too trivial
to fail :(

The binding previously had:

	reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
	reg-names = "regs", "gamma_lut";

I thought that I can merge these two regions into one bigger region.
Apart from the fact that I got it wrong (The driver still requests a
resource "regs" as you found out), it doesnt work, because the space
between those two regions is not unused, the iommu is in between them.

I'll have to revert that change for the next round. Please use the
attached fixup patch in the meantime.

Sascha

-------------------------------8<------------------------------

From 9b3dee3d8584f5a9cc24f21ff8c5895465c4b3ae Mon Sep 17 00:00:00 2001
From: Sascha Hauer <s.hauer@pengutronix.de>
Date: Mon, 20 Dec 2021 19:49:14 +0100
Subject: [PATCH] fixup! arm64: dts: rockchip: rk356x: Add VOP2 nodes

---
 arch/arm64/boot/dts/rockchip/rk356x.dtsi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index 6d93b8fcee179..cce4b789d6d58 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -453,7 +453,8 @@ gmac1_mtl_tx_setup: tx-queues-config {
 	};
 
 	vop: vop@fe040000 {
-		reg = <0x0 0xfe040000 0x0 0x5000>;
+		reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
+		reg-names = "regs", "gamma_lut";
 		interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>, <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
 		clock-names = "aclk_vop", "hclk_vop", "dclk_vp0", "dclk_vp1", "dclk_vp2";
-- 
2.30.2


-- 
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^ permalink raw reply related	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
       [not found] ` <20211220110630.3521121-23-s.hauer@pengutronix.de>
  2021-12-20 14:16   ` [PATCH 22/22] drm: rockchip: Add VOP2 driver Nicolas Frattaroli
@ 2021-12-21 13:44   ` Nicolas Frattaroli
  2021-12-22 17:07     ` Nicolas Frattaroli
  2022-01-03 14:55     ` Sascha Hauer
       [not found]   ` <a0942adc-52c1-811e-0de6-d0616266ce2d@rock-chips.com>
  2 siblings, 2 replies; 45+ messages in thread
From: Nicolas Frattaroli @ 2021-12-21 13:44 UTC (permalink / raw)
  To: dri-devel, linux-rockchip
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer, Sascha Hauer

On Montag, 20. Dezember 2021 12:06:30 CET Sascha Hauer wrote:
> From: Andy Yan <andy.yan@rock-chips.com>
> 
> The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> It replaces the VOP unit found in the older Rockchip SoCs.
> 
> This driver has been derived from the downstream Rockchip Kernel and
> heavily modified:
> 
> - All nonstandard DRM properties have been removed
> - dropped struct vop2_plane_state and pass around less data between
>   functions
> - Dropped all DRM_FORMAT_* not known on upstream
> - rework register access to get rid of excessively used macros
> - Drop all waiting for framesyncs
> 
> The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> board. Overlay support is tested with the modetest utility. AFBC support
> on the cluster windows is tested with weston-simple-dmabuf-egl on
> weston using the (yet to be upstreamed) panfrost driver support.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---

Hi Sascha,

quick partial review of the code in-line.

For reference, I debugged locking issues with the kernel lock
debug config options and assert_spin_locked in the reg write
functions, as well as some manual deduction.

>  drivers/gpu/drm/rockchip/Kconfig             |    6 +
>  drivers/gpu/drm/rockchip/Makefile            |    1 +
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.c  |    1 +
>  drivers/gpu/drm/rockchip/rockchip_drm_drv.h  |    7 +-
>  drivers/gpu/drm/rockchip/rockchip_drm_fb.c   |    2 +
>  drivers/gpu/drm/rockchip/rockchip_drm_vop.h  |   15 +
>  drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 2768 ++++++++++++++++++
>  drivers/gpu/drm/rockchip/rockchip_drm_vop2.h |  480 +++
>  drivers/gpu/drm/rockchip/rockchip_vop2_reg.c |  285 ++
>  9 files changed, 3564 insertions(+), 1 deletion(-)
>  create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
>  create mode 100644 drivers/gpu/drm/rockchip/rockchip_drm_vop2.h
>  create mode 100644 drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> 
> diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
> index b9b156308460a..4ff0043f0ee70 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -28,6 +28,12 @@ config ROCKCHIP_VOP
>  	  This selects support for the VOP driver. You should enable it
>  	  on all older SoCs up to RK3399.
>  
> +config ROCKCHIP_VOP2
> +	bool "Rockchip VOP2 driver"
> +	help
> +	  This selects support for the VOP2 driver. You should enable it
> +	  on all newer SoCs beginning form RK3568.
> +
>  config ROCKCHIP_ANALOGIX_DP
>  	bool "Rockchip specific extensions for Analogix DP driver"
>  	depends on ROCKCHIP_VOP
> diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
> index cd6e7bb5ce9c5..29848caef5c21 100644
> --- a/drivers/gpu/drm/rockchip/Makefile
> +++ b/drivers/gpu/drm/rockchip/Makefile
> @@ -7,6 +7,7 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o \
>  		rockchip_drm_gem.o
>  rockchipdrm-$(CONFIG_DRM_FBDEV_EMULATION) += rockchip_drm_fbdev.o
>  
> +rockchipdrm-$(CONFIG_ROCKCHIP_VOP2) += rockchip_drm_vop2.o rockchip_vop2_reg.o
>  rockchipdrm-$(CONFIG_ROCKCHIP_VOP) += rockchip_drm_vop.o rockchip_vop_reg.o
>  rockchipdrm-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
>  rockchipdrm-$(CONFIG_ROCKCHIP_CDN_DP) += cdn-dp-core.o cdn-dp-reg.o
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> index 64fa5fd62c01a..2bd9acb265e5a 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
> @@ -474,6 +474,7 @@ static int __init rockchip_drm_init(void)
>  
>  	num_rockchip_sub_drivers = 0;
>  	ADD_ROCKCHIP_SUB_DRIVER(vop_platform_driver, CONFIG_ROCKCHIP_VOP);
> +	ADD_ROCKCHIP_SUB_DRIVER(vop2_platform_driver, CONFIG_ROCKCHIP_VOP2);
>  	ADD_ROCKCHIP_SUB_DRIVER(rockchip_lvds_driver,
>  				CONFIG_ROCKCHIP_LVDS);
>  	ADD_ROCKCHIP_SUB_DRIVER(rockchip_dp_driver,
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> index aa0909e8edf93..fd6994f21817e 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
> @@ -18,7 +18,7 @@
>  
>  #define ROCKCHIP_MAX_FB_BUFFER	3
>  #define ROCKCHIP_MAX_CONNECTOR	2
> -#define ROCKCHIP_MAX_CRTC	2
> +#define ROCKCHIP_MAX_CRTC	4
>  
>  struct drm_device;
>  struct drm_connector;
> @@ -31,6 +31,9 @@ struct rockchip_crtc_state {
>  	int output_bpc;
>  	int output_flags;
>  	bool enable_afbc;
> +	uint32_t bus_format;
> +	u32 bus_flags;
> +	int color_space;
>  };
>  #define to_rockchip_crtc_state(s) \
>  		container_of(s, struct rockchip_crtc_state, base)
> @@ -65,4 +68,6 @@ extern struct platform_driver rockchip_dp_driver;
>  extern struct platform_driver rockchip_lvds_driver;
>  extern struct platform_driver vop_platform_driver;
>  extern struct platform_driver rk3066_hdmi_driver;
> +extern struct platform_driver vop2_platform_driver;
> +
>  #endif /* _ROCKCHIP_DRM_DRV_H_ */
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
> index 3aa37e177667e..0d2cb4f3922b8 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_fb.c
> @@ -134,4 +134,6 @@ void rockchip_drm_mode_config_init(struct drm_device *dev)
>  
>  	dev->mode_config.funcs = &rockchip_drm_mode_config_funcs;
>  	dev->mode_config.helper_private = &rockchip_mode_config_helpers;
> +
> +	dev->mode_config.normalize_zpos = true;
>  }
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> index 857d97cdc67c6..1e364d7b50e69 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
> @@ -54,9 +54,23 @@ struct vop_afbc {
>  	struct vop_reg enable;
>  	struct vop_reg win_sel;
>  	struct vop_reg format;
> +	struct vop_reg rb_swap;
> +	struct vop_reg uv_swap;
> +	struct vop_reg auto_gating_en;
> +	struct vop_reg block_split_en;
> +	struct vop_reg pic_vir_width;
> +	struct vop_reg tile_num;
>  	struct vop_reg hreg_block_split;
> +	struct vop_reg pic_offset;
>  	struct vop_reg pic_size;
> +	struct vop_reg dsp_offset;
> +	struct vop_reg transform_offset;
>  	struct vop_reg hdr_ptr;
> +	struct vop_reg half_block_en;
> +	struct vop_reg xmirror;
> +	struct vop_reg ymirror;
> +	struct vop_reg rotate_270;
> +	struct vop_reg rotate_90;
>  	struct vop_reg rstn;
>  };
>  
> @@ -410,4 +424,5 @@ static inline int scl_vop_cal_lb_mode(int width, bool is_yuv)
>  }
>  
>  extern const struct component_ops vop_component_ops;
> +
>  #endif /* _ROCKCHIP_DRM_VOP_H */
> diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> new file mode 100644
> index 0000000000000..7d39ba90061d1
> --- /dev/null
> +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c
> @@ -0,0 +1,2768 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
> + * Author: Andy Yan <andy.yan@rock-chips.com>
> + */
> +#include <drm/drm.h>
> +#include <drm/drm_atomic.h>
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_flip_work.h>
> +#include <drm/drm_plane_helper.h>
> +#include <drm/drm_writeback.h>
> +#include <drm/drm_probe_helper.h>
> +#include <drm/drm_atomic_uapi.h>
> +
> +#include <linux/iopoll.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/iopoll.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/component.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/delay.h>
> +#include <linux/swab.h>
> +#include <linux/bitfield.h>
> +#include <drm/drm_debugfs.h>
> +#include <uapi/linux/videodev2.h>
> +#include <drm/drm_vblank.h>
> +#include <dt-bindings/soc/rockchip,vop2.h>

Alphabetically sort these includes? Not sure on what the
convention is in the DRM subsystem.

> +
> +#include "rockchip_drm_drv.h"
> +#include "rockchip_drm_gem.h"
> +#include "rockchip_drm_fb.h"
> +#include "rockchip_drm_vop2.h"
> +
> +/*
> + * VOP2 architecture
> + *
> + +----------+   +-------------+                                                        +-----------+
> + |  Cluster |   | Sel 1 from 6|                                                        | 1 from 3  |
> + |  window0 |   |    Layer0   |                                                        |    RGB    |
> + +----------+   +-------------+              +---------------+    +-------------+      +-----------+
> + +----------+   +-------------+              |N from 6 layers|    |             |
> + |  Cluster |   | Sel 1 from 6|              |   Overlay0    +--->| Video Port0 |      +-----------+
> + |  window1 |   |    Layer1   |              |               |    |             |      | 1 from 3  |
> + +----------+   +-------------+              +---------------+    +-------------+      |   LVDS    |
> + +----------+   +-------------+                                                        +-----------+
> + |  Esmart  |   | Sel 1 from 6|
> + |  window0 |   |   Layer2    |              +---------------+    +-------------+      +-----------+
> + +----------+   +-------------+              |N from 6 Layers|    |             | +--> | 1 from 3  |
> + +----------+   +-------------+   -------->  |   Overlay1    +--->| Video Port1 |      |   MIPI    |
> + |  Esmart  |   | Sel 1 from 6|   -------->  |               |    |             |      +-----------+
> + |  Window1 |   |   Layer3    |              +---------------+    +-------------+
> + +----------+   +-------------+                                                        +-----------+
> + +----------+   +-------------+                                                        | 1 from 3  |
> + |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |   HDMI    |
> + |  Window0 |   |    Layer4   |              |N from 6 Layers|    |             |      +-----------+
> + +----------+   +-------------+              |   Overlay2    +--->| Video Port2 |
> + +----------+   +-------------+              |               |    |             |      +-----------+
> + |  Smart   |   | Sel 1 from 6|              +---------------+    +-------------+      |  1 from 3 |
> + |  Window1 |   |    Layer5   |                                                        |    eDP    |
> + +----------+   +-------------+                                                        +-----------+
> + *
> + */
> +
> +enum vop2_data_format {
> +	VOP2_FMT_ARGB8888 = 0,
> +	VOP2_FMT_RGB888,
> +	VOP2_FMT_RGB565,
> +	VOP2_FMT_XRGB101010,
> +	VOP2_FMT_YUV420SP,
> +	VOP2_FMT_YUV422SP,
> +	VOP2_FMT_YUV444SP,
> +	VOP2_FMT_YUYV422 = 8,
> +	VOP2_FMT_YUYV420,
> +	VOP2_FMT_VYUY422,
> +	VOP2_FMT_VYUY420,
> +	VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
> +	VOP2_FMT_YUV420SP_TILE_16x2,
> +	VOP2_FMT_YUV422SP_TILE_8x4,
> +	VOP2_FMT_YUV422SP_TILE_16x2,
> +	VOP2_FMT_YUV420SP_10,
> +	VOP2_FMT_YUV422SP_10,
> +	VOP2_FMT_YUV444SP_10,
> +};
> +
> +enum vop2_afbc_format {
> +	VOP2_AFBC_FMT_RGB565,
> +	VOP2_AFBC_FMT_ARGB2101010 = 2,
> +	VOP2_AFBC_FMT_YUV420_10BIT,
> +	VOP2_AFBC_FMT_RGB888,
> +	VOP2_AFBC_FMT_ARGB8888,
> +	VOP2_AFBC_FMT_YUV420 = 9,
> +	VOP2_AFBC_FMT_YUV422 = 0xb,
> +	VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
> +	VOP2_AFBC_FMT_INVALID = -1,
> +};
> +
> +union vop2_alpha_ctrl {
> +	uint32_t val;
> +	struct {
> +		/* [0:1] */
> +		uint32_t color_mode:1;
> +		uint32_t alpha_mode:1;
> +		/* [2:3] */
> +		uint32_t blend_mode:2;
> +		uint32_t alpha_cal_mode:1;
> +		/* [5:7] */
> +		uint32_t factor_mode:3;
> +		/* [8:9] */
> +		uint32_t alpha_en:1;
> +		uint32_t src_dst_swap:1;
> +		uint32_t reserved:6;
> +		/* [16:23] */
> +		uint32_t glb_alpha:8;
> +	} bits;
> +};
> +
> +struct vop2_alpha {
> +	union vop2_alpha_ctrl src_color_ctrl;
> +	union vop2_alpha_ctrl dst_color_ctrl;
> +	union vop2_alpha_ctrl src_alpha_ctrl;
> +	union vop2_alpha_ctrl dst_alpha_ctrl;
> +};
> +
> +struct vop2_alpha_config {
> +	bool src_premulti_en;
> +	bool dst_premulti_en;
> +	bool src_pixel_alpha_en;
> +	bool dst_pixel_alpha_en;
> +	uint16_t src_glb_alpha_value;
> +	uint16_t dst_glb_alpha_value;
> +};
> +
> +struct vop2_win {
> +	struct vop2 *vop2;
> +	struct drm_plane base;
> +	const struct vop2_win_data *data;
> +	struct regmap_field *reg[VOP2_WIN_MAX_REG];
> +
> +	/**
> +	 * @win_id: graphic window id, a cluster maybe split into two

maybe -> may be

> +	 * graphics windows.
> +	 */
> +	uint8_t win_id;
> +
> +	uint32_t offset;
> +
> +	uint8_t delay;
> +	enum drm_plane_type type;
> +};
> +
> +struct vop2_video_port {
> +	struct drm_crtc crtc;
> +	struct vop2 *vop2;
> +	struct clk *dclk;
> +	uint8_t id;
> +	const struct vop2_video_port_regs *regs;
> +	const struct vop2_video_port_data *data;
> +
> +	struct completion dsp_hold_completion;
> +
> +	/**
> +	 * @win_mask: Bitmask of wins attached to the video port;

wins -> windows

> +	 */
> +	uint32_t win_mask;
> +
> +	struct vop2_win *primary_plane;
> +	struct drm_pending_vblank_event *event;
> +
> +	int nlayers;
> +};
> +
> +struct vop2 {
> +	struct device *dev;
> +	struct drm_device *drm;
> +	struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
> +
> +	const struct vop2_data *data;
> +	/* Number of win that registered as plane,
> +	 * maybe less than the total number of hardware
> +	 * win.

Number of windows that are registered as planes, may be, windows again

> +	 */
> +	uint32_t registered_num_wins;
> +
> +	void __iomem *regs;
> +	struct regmap *map;
> +
> +	struct regmap *grf;
> +
> +	/* physical map length of vop2 register */
> +	uint32_t len;
> +
> +	void __iomem *lut_regs;
> +	/* one time only one process allowed to config the register */

only one thread at a time is allowed to configure the registers

> +	spinlock_t reg_lock;
> +
> +	/* protects crtc enable/disable */
> +	struct mutex vop2_lock;
> +
> +	int irq;
> +
> +	/*
> +	 * Some globle resource are shared between all
> +	 * the vidoe ports(crtcs), so we need a ref counter here.

Some global resources, video

> +	 */
> +	unsigned int enable_count;
> +	struct clk *hclk;
> +	struct clk *aclk;
> +
> +	/* must put at the end of the struct */

must be put

> +	struct vop2_win win[];
> +};
> +
> +static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
> +{
> +	return container_of(crtc, struct vop2_video_port, crtc);
> +}
> +
> +static struct vop2_win *to_vop2_win(struct drm_plane *p)
> +{
> +	return container_of(p, struct vop2_win, base);
> +}
> +
> +static void vop2_lock(struct vop2 *vop2)
> +{
> +	mutex_lock(&vop2->vop2_lock);
> +}
> +
> +static void vop2_unlock(struct vop2 *vop2)
> +{
> +	mutex_unlock(&vop2->vop2_lock);
> +}
> +
> +static void vop2_writel(struct vop2 *vop2, uint32_t offset, uint32_t v)
> +{
> +	regmap_write(vop2->map, offset, v);
> +}
> +
> +static void vop2_vp_write(struct vop2_video_port *vp, uint32_t offset,
> +			  uint32_t v)
> +{
> +	regmap_write(vp->vop2->map, vp->data->offset + offset, v);
> +}
> +
> +static uint32_t vop2_readl(struct vop2 *vop2, uint32_t offset)
> +{
> +	uint32_t val;
> +
> +	regmap_read(vop2->map, offset, &val);
> +
> +	return val;
> +}
> +
> +static void vop2_win_write(const struct vop2_win *win, unsigned int reg,
> +			   uint32_t v)
> +{
> +	regmap_field_write(win->reg[reg], v);
> +}
> +
> +static bool vop2_cluster_window(const struct vop2_win *win)
> +{
> +	return win->data->feature & WIN_FEATURE_CLUSTER;
> +}
> +
> +static void vop2_cfg_done(struct vop2_video_port *vp)
> +{
> +	struct vop2 *vop2 = vp->vop2;
> +	uint32_t val;
> +
> +	val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
> +
> +	val &= 0x7;

GENMASK(2, 0) instead of 0x7, should that be a constant somewhere?

> +
> +	vop2_writel(vop2, RK3568_REG_CFG_DONE,
> +		    val | BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
> +}
> +
> +static void vop2_win_disable(struct vop2_win *win)
> +{
> +	vop2_win_write(win, VOP2_WIN_ENABLE, 0);
> +
> +	if (vop2_cluster_window(win))
> +		vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
> +}
> +
> +static enum vop2_data_format vop2_convert_format(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_ARGB8888:
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_ABGR8888:
> +		return VOP2_FMT_ARGB8888;
> +	case DRM_FORMAT_RGB888:
> +	case DRM_FORMAT_BGR888:
> +		return VOP2_FMT_RGB888;
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_BGR565:
> +		return VOP2_FMT_RGB565;
> +	case DRM_FORMAT_NV12:
> +		return VOP2_FMT_YUV420SP;
> +	case DRM_FORMAT_NV16:
> +		return VOP2_FMT_YUV422SP;
> +	case DRM_FORMAT_NV24:
> +		return VOP2_FMT_YUV444SP;
> +	case DRM_FORMAT_YUYV:
> +	case DRM_FORMAT_YVYU:
> +		return VOP2_FMT_VYUY422;
> +	case DRM_FORMAT_VYUY:
> +	case DRM_FORMAT_UYVY:
> +		return VOP2_FMT_YUYV422;
> +	default:
> +		DRM_ERROR("unsupported format[%08x]\n", format);
> +		return -EINVAL;
> +	}
> +}
> +
> +static enum vop2_afbc_format vop2_convert_afbc_format(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_XRGB8888:
> +	case DRM_FORMAT_ARGB8888:
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_ABGR8888:
> +		return VOP2_AFBC_FMT_ARGB8888;
> +	case DRM_FORMAT_RGB888:
> +	case DRM_FORMAT_BGR888:
> +		return VOP2_AFBC_FMT_RGB888;
> +	case DRM_FORMAT_RGB565:
> +	case DRM_FORMAT_BGR565:
> +		return VOP2_AFBC_FMT_RGB565;
> +	case DRM_FORMAT_NV12:
> +		return VOP2_AFBC_FMT_YUV420;
> +	case DRM_FORMAT_NV16:
> +		return VOP2_AFBC_FMT_YUV422;
> +	default:
> +		return VOP2_AFBC_FMT_INVALID;
> +	}
> +
> +	return VOP2_AFBC_FMT_INVALID;
> +}
> +
> +static bool vop2_win_rb_swap(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_XBGR8888:
> +	case DRM_FORMAT_ABGR8888:
> +	case DRM_FORMAT_BGR888:
> +	case DRM_FORMAT_BGR565:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool vop2_afbc_rb_swap(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_NV24:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool vop2_afbc_uv_swap(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_NV16:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool vop2_win_uv_swap(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_NV12:
> +	case DRM_FORMAT_NV16:
> +	case DRM_FORMAT_NV24:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool vop2_win_dither_up(uint32_t format)
> +{
> +	switch (format) {
> +	case DRM_FORMAT_BGR565:
> +	case DRM_FORMAT_RGB565:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool vop2_output_uv_swap(uint32_t bus_format, uint32_t output_mode)
> +{
> +	/*
> +	 * FIXME:
> +	 *
> +	 * There is no media type for YUV444 output,
> +	 * so when out_mode is AAAA or P888, assume output is YUV444 on
> +	 * yuv format.
> +	 *
> +	 * From H/W testing, YUV444 mode need a rb swap.
> +	 */
> +	if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
> +	    bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
> +	    bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
> +	    bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
> +	    ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
> +	      bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
> +	     (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
> +	      output_mode == ROCKCHIP_OUT_MODE_P888)))
> +		return true;
> +	else
> +		return false;
> +}
> +
> +static bool is_yuv_output(uint32_t bus_format)
> +{
> +	switch (bus_format) {
> +	case MEDIA_BUS_FMT_YUV8_1X24:
> +	case MEDIA_BUS_FMT_YUV10_1X30:
> +	case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
> +	case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
> +	case MEDIA_BUS_FMT_YUYV8_2X8:
> +	case MEDIA_BUS_FMT_YVYU8_2X8:
> +	case MEDIA_BUS_FMT_UYVY8_2X8:
> +	case MEDIA_BUS_FMT_VYUY8_2X8:
> +	case MEDIA_BUS_FMT_YUYV8_1X16:
> +	case MEDIA_BUS_FMT_YVYU8_1X16:
> +	case MEDIA_BUS_FMT_UYVY8_1X16:
> +	case MEDIA_BUS_FMT_VYUY8_1X16:
> +		return true;
> +	default:
> +		return false;
> +	}
> +}
> +
> +static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
> +{
> +	int i;
> +
> +	if (modifier == DRM_FORMAT_MOD_LINEAR)
> +		return false;
> +
> +	for (i = 0 ; i < plane->modifier_count; i++)
> +		if (plane->modifiers[i] == modifier)
> +			break;
> +
> +	return (i < plane->modifier_count) ? true : false;
> +
> +}
> +
> +static bool rockchip_vop2_mod_supported(struct drm_plane *plane, uint32_t format, u64 modifier)
> +{
> +	struct vop2_win *win = to_vop2_win(plane);
> +	struct vop2 *vop2 = win->vop2;
> +
> +	if (modifier == DRM_FORMAT_MOD_INVALID)
> +		return false;
> +
> +	if (modifier == DRM_FORMAT_MOD_LINEAR)
> +		return true;
> +
> +	if (!rockchip_afbc(plane, modifier)) {
> +		drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n", modifier);
> +
> +		return false;
> +	}
> +
> +	return vop2_convert_afbc_format(format) >= 0;
> +}
> +
> +static int vop2_afbc_half_block_enable(struct drm_plane_state *pstate)
> +{
> +	if ((pstate->rotation & DRM_MODE_ROTATE_270) || (pstate->rotation & DRM_MODE_ROTATE_90))
> +		return 0;
> +	else
> +		return 1;
> +}
> +
> +static uint32_t vop2_afbc_transform_offset(struct drm_plane_state *pstate,
> +					   bool afbc_half_block_en)
> +{
> +	struct drm_rect *src = &pstate->src;
> +	struct drm_framebuffer *fb = pstate->fb;
> +	uint32_t bpp = fb->format->cpp[0] * 8;
> +	uint32_t vir_width = (fb->pitches[0] << 3) / bpp;
> +	uint32_t width = drm_rect_width(src) >> 16;
> +	uint32_t height = drm_rect_height(src) >> 16;
> +	uint32_t act_xoffset = src->x1 >> 16;
> +	uint32_t act_yoffset = src->y1 >> 16;
> +	uint32_t align16_crop = 0;
> +	uint32_t align64_crop = 0;
> +	uint32_t height_tmp = 0;
> +	uint32_t transform_tmp = 0;
> +	uint8_t transform_xoffset = 0;
> +	uint8_t transform_yoffset = 0;
> +	uint8_t top_crop = 0;
> +	uint8_t top_crop_line_num = 0;
> +	uint8_t bottom_crop_line_num = 0;
> +
> +	/* 16 pixel align */
> +	if (height & 0xf)
> +		align16_crop = 16 - (height & 0xf);
> +
> +	height_tmp = height + align16_crop;
> +
> +	/* 64 pixel align */
> +	if (height_tmp & 0x3f)
> +		align64_crop = 64 - (height_tmp & 0x3f);
> +
> +	top_crop_line_num = top_crop << 2;
> +	if (top_crop == 0)
> +		bottom_crop_line_num = align16_crop + align64_crop;
> +	else if (top_crop == 1)
> +		bottom_crop_line_num = align16_crop + align64_crop + 12;
> +	else if (top_crop == 2)
> +		bottom_crop_line_num = align16_crop + align64_crop + 8;

top_crop == 0 is always taken from what I can gather, rest is
dead code. Is this intentional? It doesn't seem intentional.

> +
> +	switch (pstate->rotation &
> +		(DRM_MODE_REFLECT_X |
> +		 DRM_MODE_REFLECT_Y |
> +		 DRM_MODE_ROTATE_90 |
> +		 DRM_MODE_ROTATE_270)) {
> +	case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
> +		transform_tmp = act_xoffset + width;
> +		transform_xoffset = 16 - (transform_tmp & 0xf);
> +		transform_tmp = bottom_crop_line_num - act_yoffset;
> +
> +		if (afbc_half_block_en)
> +			transform_yoffset = transform_tmp & 0x7;
> +		else
> +			transform_yoffset = (transform_tmp & 0xf);
> +
> +		break;
> +	case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
> +		transform_tmp = bottom_crop_line_num - act_yoffset;
> +		transform_xoffset = transform_tmp & 0xf;
> +		transform_tmp = vir_width - width - act_xoffset;
> +		transform_yoffset = transform_tmp & 0xf;
> +		break;
> +	case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
> +		transform_tmp = top_crop_line_num + act_yoffset;
> +		transform_xoffset = transform_tmp & 0xf;
> +		transform_tmp = act_xoffset;
> +		transform_yoffset = transform_tmp & 0xf;
> +		break;
> +	case DRM_MODE_REFLECT_X:
> +		transform_tmp = act_xoffset + width;
> +		transform_xoffset = 16 - (transform_tmp & 0xf);
> +		transform_tmp = top_crop_line_num + act_yoffset;
> +
> +		if (afbc_half_block_en)
> +			transform_yoffset = transform_tmp & 0x7;
> +		else
> +			transform_yoffset = transform_tmp & 0xf;
> +
> +		break;
> +	case DRM_MODE_REFLECT_Y:
> +		transform_tmp = act_xoffset;
> +		transform_xoffset = transform_tmp & 0xf;
> +		transform_tmp = bottom_crop_line_num - act_yoffset;
> +
> +		if (afbc_half_block_en)
> +			transform_yoffset = transform_tmp & 0x7;
> +		else
> +			transform_yoffset = transform_tmp & 0xf;
> +
> +		break;
> +	case DRM_MODE_ROTATE_90:
> +		transform_tmp = bottom_crop_line_num - act_yoffset;
> +		transform_xoffset = transform_tmp & 0xf;
> +		transform_tmp = act_xoffset;
> +		transform_yoffset = transform_tmp & 0xf;
> +		break;
> +	case DRM_MODE_ROTATE_270:
> +		transform_tmp = top_crop_line_num + act_yoffset;
> +		transform_xoffset = transform_tmp & 0xf;
> +		transform_tmp = vir_width - width - act_xoffset;
> +		transform_yoffset = transform_tmp & 0xf;
> +		break;
> +	case 0:
> +		transform_tmp = act_xoffset;
> +		transform_xoffset = transform_tmp & 0xf;
> +		transform_tmp = top_crop_line_num + act_yoffset;
> +
> +		if (afbc_half_block_en)
> +			transform_yoffset = transform_tmp & 0x7;
> +		else
> +			transform_yoffset = transform_tmp & 0xf;
> +
> +		break;
> +	}
> +
> +	return (transform_xoffset & 0xf) | ((transform_yoffset & 0xf) << 16);
> +}

0xf, 0x3f, 0x7 might be more clear as GENMASK.
if (afbc_half_block_en) branches can be moved out of cases and
assign a transform mask variable instead.

> +
> +/*
> + * A Cluster window has 2048 x 16 line buffer, which can
> + * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
> + * for Cluster_lb_mode register:
> + * 0: half mode, for plane input width range 2048 ~ 4096
> + * 1: half mode, for cluster work at 2 * 2048 plane mode
> + * 2: half mode, for rotate_90/270 mode
> + *
> + */
> +static int vop2_get_cluster_lb_mode(struct vop2_win *win, struct drm_plane_state *pstate)
> +{
> +	if ((pstate->rotation & DRM_MODE_ROTATE_270) || (pstate->rotation & DRM_MODE_ROTATE_90))
> +		return 2;
> +	else
> +		return 0;
> +}

What about 1?

> +
> +/*
> + * bli_sd_factor = (src - 1) / (dst - 1) << 12;
> + * avg_sd_factor:
> + * bli_su_factor:
> + * bic_su_factor:
> + * = (src - 1) / (dst - 1) << 16;
> + *
> + * gt2 enable: dst get one line from two line of the src
> + * gt4 enable: dst get one line from four line of the src.
> + *
> + */
> +static uint16_t vop2_scale_factor(enum scale_mode mode,
> +				  int32_t filter_mode,
> +				  uint32_t src, uint32_t dst)
> +{
> +	uint32_t fac;
> +	int i;
> +
> +	if (mode == SCALE_NONE)
> +		return 0;
> +
> +	/*
> +	 * A workaround to avoid zero div.
> +	 */
> +	if (dst == 1 || src == 1) {
> +		dst++;
> +		src++;
> +	}
> +
> +	if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) {
> +		fac = ((src - 1) << 12) / (dst - 1);
> +		for (i = 0; i < 100; i++) {
> +			if (fac * (dst - 1) >> 12 < (src - 1))
> +				break;
> +			fac -= 1;
> +			DRM_DEBUG("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
> +		}
> +	} else {
> +		fac = ((src - 1) << 16) / (dst - 1);
> +		for (i = 0; i < 100; i++) {
> +			if (fac * (dst - 1) >> 16 < (src - 1))
> +				break;
> +			fac -= 1;
> +			DRM_DEBUG("up fac cali:  src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
> +		}
> +	}
> +
> +	return fac;
> +}

src = 0 or dst = 0 causes an uint underflow here.

> +
> +static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
> +			     uint32_t src_w, uint32_t src_h, uint32_t dst_w,
> +			     uint32_t dst_h, uint32_t pixel_format)
> +{
> +	const struct drm_format_info *info;
> +	uint16_t cbcr_src_w;
> +	uint16_t cbcr_src_h;
> +	uint16_t yrgb_hor_scl_mode, yrgb_ver_scl_mode;
> +	uint16_t cbcr_hor_scl_mode, cbcr_ver_scl_mode;
> +	uint16_t hscl_filter_mode, vscl_filter_mode;
> +	uint8_t gt2 = 0;
> +	uint8_t gt4 = 0;
> +	uint32_t val;
> +
> +	info = drm_format_info(pixel_format);
> +
> +	cbcr_src_w = src_w / info->hsub;
> +	cbcr_src_h = src_h / info->vsub;
> +
> +	if (src_h >= (4 * dst_h)) {
> +		gt4 = 1;
> +		src_h >>= 2;
> +	} else if (src_h >= (2 * dst_h)) {
> +		gt2 = 1;
> +		src_h >>= 1;
> +	}
> +
> +	yrgb_hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
> +	yrgb_ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
> +
> +	if (yrgb_hor_scl_mode == SCALE_UP)
> +		hscl_filter_mode = VOP2_SCALE_UP_BIC;
> +	else
> +		hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
> +
> +	if (yrgb_ver_scl_mode == SCALE_UP)
> +		vscl_filter_mode = VOP2_SCALE_UP_BIL;
> +	else
> +		vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
> +
> +	/*
> +	 * RK3568 VOP Esmart/Smart dsp_w should be even pixel
> +	 * at scale down mode
> +	 */
> +	if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
> +		if ((yrgb_hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
> +			drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
> +				win->data->name, dst_w);
> +			dst_w += 1;
> +		}
> +	}
> +
> +	val = vop2_scale_factor(yrgb_hor_scl_mode, hscl_filter_mode,
> +				src_w, dst_w);
> +	vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
> +	val = vop2_scale_factor(yrgb_ver_scl_mode, vscl_filter_mode,
> +				src_h, dst_h);
> +	vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
> +
> +	vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
> +	vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
> +
> +	vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, yrgb_hor_scl_mode);
> +	vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, yrgb_ver_scl_mode);
> +
> +	if (vop2_cluster_window(win))
> +		return;
> +
> +	vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
> +	vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
> +
> +	if (info->is_yuv) {
> +		gt4 = gt2 = 0;
> +
> +		if (cbcr_src_h >= (4 * dst_h))
> +			gt4 = 1;
> +		else if (cbcr_src_h >= (2 * dst_h))
> +			gt2 = 1;
> +
> +		if (gt4)
> +			cbcr_src_h >>= 2;
> +		else if (gt2)
> +			cbcr_src_h >>= 1;
> +
> +		cbcr_hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
> +		cbcr_ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
> +
> +		val = vop2_scale_factor(cbcr_hor_scl_mode, hscl_filter_mode,
> +					cbcr_src_w, dst_w);
> +		vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
> +
> +		val = vop2_scale_factor(cbcr_ver_scl_mode, vscl_filter_mode,
> +					cbcr_src_h, dst_h);
> +		vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
> +
> +		vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
> +		vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
> +		vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, cbcr_hor_scl_mode);
> +		vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, cbcr_ver_scl_mode);
> +		vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
> +		vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
> +	}
> +}

Double-check that we do have the reg spinlock here, my
lock debugging died earlier due to a different lock bug

> +
> +static int vop2_convert_csc_mode(int csc_mode)
> +{
> +	switch (csc_mode) {
> +	case V4L2_COLORSPACE_SMPTE170M:
> +	case V4L2_COLORSPACE_470_SYSTEM_M:
> +	case V4L2_COLORSPACE_470_SYSTEM_BG:
> +		return CSC_BT601L;
> +	case V4L2_COLORSPACE_REC709:
> +	case V4L2_COLORSPACE_SMPTE240M:
> +	case V4L2_COLORSPACE_DEFAULT:
> +		return CSC_BT709L;
> +	case V4L2_COLORSPACE_JPEG:
> +		return CSC_BT601F;
> +	case V4L2_COLORSPACE_BT2020:
> +		return CSC_BT2020;
> +	default:
> +		return CSC_BT709L;
> +	}
> +}
> +
> +/*
> + * colorspace path:
> + *      Input        Win csc                     Output
> + * 1. YUV(2020)  --> Y2R->2020To709->R2Y   --> YUV_OUTPUT(601/709)
> + *    RGB        --> R2Y                  __/
> + *
> + * 2. YUV(2020)  --> bypasss               --> YUV_OUTPUT(2020)
> + *    RGB        --> 709To2020->R2Y       __/
> + *
> + * 3. YUV(2020)  --> Y2R->2020To709        --> RGB_OUTPUT(709)
> + *    RGB        --> R2Y                  __/
> + *
> + * 4. YUV(601/709)-> Y2R->709To2020->R2Y   --> YUV_OUTPUT(2020)
> + *    RGB        --> 709To2020->R2Y       __/
> + *
> + * 5. YUV(601/709)-> bypass                --> YUV_OUTPUT(709)
> + *    RGB        --> R2Y                  __/
> + *
> + * 6. YUV(601/709)-> bypass                --> YUV_OUTPUT(601)
> + *    RGB        --> R2Y(601)             __/
> + *
> + * 7. YUV        --> Y2R(709)              --> RGB_OUTPUT(709)
> + *    RGB        --> bypass               __/
> + *
> + * 8. RGB        --> 709To2020->R2Y        --> YUV_OUTPUT(2020)
> + *
> + * 9. RGB        --> R2Y(709)              --> YUV_OUTPUT(709)
> + *
> + * 10. RGB       --> R2Y(601)              --> YUV_OUTPUT(601)
> + *
> + * 11. RGB       --> bypass                --> RGB_OUTPUT(709)
> + */
> +
> +static void vop2_setup_csc_mode(struct vop2_video_port *vp,
> +				struct vop2_win *win,
> +				struct drm_plane_state *pstate)
> +{
> +	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
> +	int is_input_yuv = pstate->fb->format->is_yuv;
> +	int is_output_yuv = is_yuv_output(vcstate->bus_format);
> +	int input_csc = V4L2_COLORSPACE_DEFAULT;
> +	int output_csc = vcstate->color_space;
> +	bool r2y_en, y2r_en;
> +	int csc_mode;
> +
> +	if (is_input_yuv && !is_output_yuv) {
> +		y2r_en = 1;
> +		r2y_en = 0;

They're bools, use true/false.

> +		csc_mode = vop2_convert_csc_mode(input_csc);
> +	} else if (!is_input_yuv && is_output_yuv) {
> +		y2r_en = 0;
> +		r2y_en = 1;

ditto

> +		csc_mode = vop2_convert_csc_mode(output_csc);
> +	} else {
> +		y2r_en = 0;
> +		r2y_en = 0;

ditto

> +		csc_mode = 0;
> +	}
> +
> +	vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
> +	vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
> +	vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
> +}
> +
> +static void vop2_crtc_enable_irq(struct vop2_video_port *vp, uint32_t irq)
> +{
> +	struct vop2 *vop2 = vp->vop2;
> +
> +	vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
> +	vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
> +}
> +
> +static void vop2_crtc_disable_irq(struct vop2_video_port *vp, uint32_t irq)
> +{
> +	struct vop2 *vop2 = vp->vop2;
> +
> +	vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
> +}
> +
> +static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
> +{
> +	int ret;
> +
> +	ret = clk_prepare_enable(vop2->hclk);
> +	if (ret < 0) {
> +		drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(vop2->aclk);
> +	if (ret < 0) {
> +		drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
> +		goto err;
> +	}
> +
> +	return 0;
> +err:
> +	clk_disable_unprepare(vop2->hclk);
> +
> +	return ret;
> +}
> +
> +static void vop2_enable(struct vop2 *vop2)
> +{
> +	int ret;
> +	uint32_t v;
> +
> +	ret = pm_runtime_get_sync(vop2->dev);
> +	if (ret < 0) {
> +		drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
> +		return;
> +	}
> +
> +	ret = vop2_core_clks_prepare_enable(vop2);
> +	if (ret) {
> +		pm_runtime_put_sync(vop2->dev);
> +		return;
> +	}
> +
> +	if (vop2->data->soc_id == 3566)
> +		vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
> +
> +	vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
> +
> +	/*
> +	 * Disable auto gating, this is a workaround to
> +	 * avoid display image shift when a window enabled.
> +	 */
> +	v = vop2_readl(vop2, RK3568_SYS_AUTO_GATING_CTRL);
> +	v &= ~RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN;
> +	vop2_writel(vop2, RK3568_SYS_AUTO_GATING_CTRL, v);
> +
> +	vop2_writel(vop2, RK3568_SYS0_INT_CLR,
> +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> +	vop2_writel(vop2, RK3568_SYS0_INT_EN,
> +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> +	vop2_writel(vop2, RK3568_SYS1_INT_CLR,
> +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> +	vop2_writel(vop2, RK3568_SYS1_INT_EN,
> +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> +}

Does reg writes but doesn't have the spinlock.

> [...]
> +static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, struct drm_atomic_state *state)
> +{
> +	struct vop2_video_port *vp = to_vop2_video_port(crtc);
> +	struct vop2 *vop2 = vp->vop2;
> +	const struct vop2_data *vop2_data = vop2->data;
> +	const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
> +	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
> +	struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
> +	struct drm_display_mode *mode = &crtc->state->adjusted_mode;
> +	unsigned long clock = mode->crtc_clock * 1000;
> +	uint16_t hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
> +	uint16_t hdisplay = mode->crtc_hdisplay;
> +	uint16_t htotal = mode->crtc_htotal;
> +	uint16_t hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
> +	uint16_t hact_end = hact_st + hdisplay;
> +	uint16_t vdisplay = mode->crtc_vdisplay;
> +	uint16_t vtotal = mode->crtc_vtotal;
> +	uint16_t vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
> +	uint16_t vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
> +	uint16_t vact_end = vact_st + vdisplay;
> +	uint8_t out_mode;
> +	uint32_t dsp_ctrl = 0;
> +	int act_end;
> +	uint32_t val, polflags;
> +	int ret;
> +	struct drm_encoder *encoder;
> +
> +	drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
> +		hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
> +		drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
> +
> +	vop2_lock(vop2);
> +
> +	ret = clk_prepare_enable(vp->dclk);
> +	if (ret < 0) {
> +		drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
> +			      vp->id, ret);
> +		return;

vop2_lock is never unlocked in this branch

> +	}
> +
> +	if (!vop2->enable_count)
> +		vop2_enable(vop2);
> +
> +	vop2->enable_count++;
> +
> +	vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
> +
> +	polflags = 0;
> +	if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
> +		polflags |= POLFLAG_DCLK_INV;
> +	if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> +		polflags |= BIT(HSYNC_POSITIVE);
> +	if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> +		polflags |= BIT(VSYNC_POSITIVE);
> +
> +	drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
> +		struct device_node *node, *parent;
> +
> +		parent = of_get_parent(encoder->port);
> +
> +		for_each_endpoint_of_node(parent, node) {
> +			struct device_node *crtc_port = of_graph_get_remote_port(node);
> +			struct device_node *epn;
> +			struct of_endpoint endpoint;
> +
> +			if (crtc->port != crtc_port) {
> +				of_node_put(crtc_port);
> +				continue;
> +			}
> +
> +			of_node_put(crtc_port);
> +
> +			epn = of_graph_get_remote_endpoint(node);
> +			of_graph_parse_endpoint(epn, &endpoint);
> +			of_node_put(epn);
> +
> +			drm_dbg(vop2->drm, "vp%d is connected to %s, id %d\n",
> +					   vp->id, encoder->name, endpoint.id);
> +			rk3568_set_intf_mux(vp, endpoint.id, polflags);
> +		}
> +		of_node_put(parent);
> +	}
> +
> +	if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
> +	     !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT))
> +		out_mode = ROCKCHIP_OUT_MODE_P888;
> +	else
> +		out_mode = vcstate->output_mode;
> +
> +	dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
> +
> +	if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
> +		dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
> +
> +	if (is_yuv_output(vcstate->bus_format))
> +		dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
> +
> +	vop2_dither_setup(crtc, &dsp_ctrl);
> +
> +	vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
> +	val = hact_st << 16;
> +	val |= hact_end;
> +	vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
> +
> +	val = vact_st << 16;
> +	val |= vact_end;
> +	vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
> +
> +	if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
> +		uint16_t vact_st_f1 = vtotal + vact_st + 1;
> +		uint16_t vact_end_f1 = vact_st_f1 + vdisplay;
> +
> +		val = vact_st_f1 << 16 | vact_end_f1;
> +		vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
> +
> +		val = vtotal << 16 | (vtotal + vsync_len);
> +		vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
> +		dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
> +		dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
> +		dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
> +		vtotal += vtotal + 1;
> +		act_end = vact_end_f1;
> +	} else {
> +		act_end = vact_end;
> +	}
> +
> +	vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
> +		    (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
> +
> +	vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
> +
> +	if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
> +		dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
> +		clock *= 2;
> +	}
> +
> +	vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
> +
> +	clk_set_rate(vp->dclk, clock);
> +
> +	vop2_post_config(crtc);
> +
> +	vop2_cfg_done(vp);
> +
> +	vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
> +
> +	drm_crtc_vblank_on(crtc);
> +
> +	vop2_unlock(vop2);
> +}

Whole function does reg writes without the spinlock, caught by
assert_spin_locked.

> [...]
> +static irqreturn_t vop2_isr(int irq, void *data)
> +{
> +	struct vop2 *vop2 = data;
> +	const struct vop2_data *vop2_data = vop2->data;
> +	uint32_t axi_irqs[VOP2_SYS_AXI_BUS_NUM];
> +	int ret = IRQ_NONE;
> +	int i;
> +
> +	/*
> +	 * The irq is shared with the iommu. If the runtime-pm state of the
> +	 * vop2-device is disabled the irq has to be targeted at the iommu.
> +	 */
> +	if (!pm_runtime_get_if_in_use(vop2->dev))
> +		return IRQ_NONE;
> +
> +	for (i = 0; i < vop2_data->nr_vps; i++) {
> +		struct vop2_video_port *vp = &vop2->vps[i];
> +		struct drm_crtc *crtc = &vp->crtc;
> +		uint32_t irqs;
> +
> +		irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
> +		vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
> +
> +		if (irqs & VP_INT_DSP_HOLD_VALID) {
> +			complete(&vp->dsp_hold_completion);
> +			ret = IRQ_HANDLED;
> +		}
> +
> +		if (irqs & VP_INT_FS_FIELD) {
> +			unsigned long flags;
> +
> +			drm_crtc_handle_vblank(crtc);
> +			spin_lock_irqsave(&crtc->dev->event_lock, flags);
> +			if (vp->event) {
> +				uint32_t val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
> +				if (!(val & BIT(vp->id))) {
> +					drm_crtc_send_vblank_event(crtc, vp->event);
> +					vp->event = NULL;
> +					drm_crtc_vblank_put(crtc);
> +				}
> +			}
> +			spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
> +
> +			ret = IRQ_HANDLED;
> +		}
> +
> +		if (irqs & VP_INT_POST_BUF_EMPTY) {
> +			drm_err_ratelimited(vop2->drm,
> +					    "POST_BUF_EMPTY irq err at vp%d\n",
> +					    vp->id);
> +			ret = IRQ_HANDLED;
> +		}
> +	}
> +
> +	axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
> +	vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
> +	axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
> +	vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
> +
> +	for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
> +		if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
> +			drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
> +			ret = IRQ_HANDLED;
> +		}
> +	}
> +
> +	pm_runtime_put(vop2->dev);
> +
> +	return ret;
> +}

Does reg writes, does the ISR need the reg spinlock here? I'm not
sure.

In general there appear to be a lot of issues with the register
lock, so either I'm misunderstanding what it's supposed to protect
or the code is very thread unsafe.

Regards,
Nicolas Frattaroli




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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-20 11:06 ` [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
  2021-12-20 14:27   ` Rob Herring
@ 2021-12-21 14:31   ` Rob Herring
  2021-12-22 10:47     ` Sascha Hauer
  1 sibling, 1 reply; 45+ messages in thread
From: Rob Herring @ 2021-12-21 14:31 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis

On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> "vpll" is a misnomer. A clock input to a device should be named after
> the usage in the device, not after the clock that drives it. On the
> rk3568 the same clock is driven by the HPLL.
> To fix that, this patch renames the vpll clock to ref clock.

The problem with this series is it breaks an old kernel with new dt. You 
can partially mitigate that with stable kernel backport, but IMO keeping 
the old name is not a burden to maintain.

And given RK3399 is widely used including by me, we should not be 
breaking compatibility.

So allow for ref in addition to vpll if you like, but only use 'ref' for 
new users. And add a comment in the schema to that effect.

Rob

> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  .../bindings/display/rockchip/rockchip,dw-hdmi.yaml        | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> index 6e09dd2ee05ac..3b40219e3ea60 100644
> --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-hdmi.yaml
> @@ -47,11 +47,12 @@ properties:
>        - enum:
>            - cec
>            - grf
> -          - vpll
> +          - ref
>        - enum:
>            - grf
> -          - vpll
> -      - const: vpll
> +          - ref
> +      - const:
> +          - ref
>  
>    ddc-i2c-bus:
>      $ref: /schemas/types.yaml#/definitions/phandle
> -- 
> 2.30.2
> 
> 

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2
  2021-12-20 11:06 ` [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
  2021-12-20 14:27   ` Rob Herring
@ 2021-12-21 14:33   ` Rob Herring
  1 sibling, 0 replies; 45+ messages in thread
From: Rob Herring @ 2021-12-21 14:33 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis

On Mon, Dec 20, 2021 at 12:06:19PM +0100, Sascha Hauer wrote:
> The VOP2 is found on newer Rockchip SoCs like the rk3568 or the rk3566.
> The binding differs slightly from the existing VOP binding, so add a new
> binding file for it.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  .../display/rockchip/rockchip-vop2.yaml       | 146 ++++++++++++++++++
>  1 file changed, 146 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> 
> diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> new file mode 100644
> index 0000000000000..df14d5aa85c85
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml
> @@ -0,0 +1,146 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/rockchip/rockchip-vop2.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip SoC display controller (VOP2)
> +
> +description:
> +  VOP2 (Video Output Processor v2) is the display controller for the Rockchip
> +  series of SoCs which transfers the image data from a video memory
> +  buffer to an external LCD interface.
> +
> +maintainers:
> +  - Sandy Huang <hjc@rock-chips.com>
> +  - Heiko Stuebner <heiko@sntech.de>
> +
> +properties:
> +  compatible:
> +    enum:
> +      - rockchip,rk3566-vop
> +      - rockchip,rk3568-vop
> +
> +  reg:
> +    minItems: 1
> +    items:
> +      - description:
> +          Must contain one entry corresponding to the base address and length
> +          of the register space.
> +      - description:
> +          Can optionally contain a second entry corresponding to
> +          the CRTC gamma LUT address.
> +
> +  interrupts:
> +    maxItems: 1
> +    description:
> +      The VOP interrupt is shared by several interrupt sources, such as
> +      frame start (VSYNC), line flag and other status interrupts.
> +
> +  clocks:
> +    items:
> +      - description: Clock for ddr buffer transfer.
> +      - description: Clock for the ahb bus to R/W the phy regs.
> +      - description: Pixel clock for video port 0.
> +      - description: Pixel clock for video port 1.
> +      - description: Pixel clock for video port 2.
> +
> +  clock-names:
> +    items:
> +      - const: aclk_vop
> +      - const: hclk_vop

_vop is redundant.

> +      - const: dclk_vp0
> +      - const: dclk_vp1
> +      - const: dclk_vp2
> +
> +  rockchip,grf:
> +    $ref: /schemas/types.yaml#/definitions/phandle
> +    description:
> +      Phandle to GRF regs used for misc control
> +
> +  ports:
> +    $ref: /schemas/graph.yaml#/properties/port

s/port/ports/

> +
> +    properties:
> +      port@0:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description:
> +          Output endpoint of VP0
> +
> +      port@1:
> +        $ref: /schemas/graph.yaml#/properties/port
> +        description:
> +          Output endpoint of VP1
> +
> +      port@:

port@2

> +        $ref: /schemas/graph.yaml#/properties/port
> +        description:
> +          Output endpoint of VP2
> +

> +  assigned-clocks: true
> +
> +  assigned-clock-rates: true
> +
> +  assigned-clock-parents: true

These are automatically added.

> +
> +  iommus:
> +    maxItems: 1
> +
> +  power-domains:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - clocks
> +  - clock-names
> +  - ports
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +        #include <dt-bindings/clock/rk3568-cru.h>
> +        #include <dt-bindings/interrupt-controller/arm-gic.h>
> +        #include <dt-bindings/power/rk3568-power.h>
> +        bus {
> +            #address-cells = <2>;
> +            #size-cells = <2>;
> +            vop: vop@fe040000 {
> +                compatible = "rockchip,rk3568-vop";
> +                reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
> +                interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> +                clocks = <&cru ACLK_VOP>,
> +                         <&cru HCLK_VOP>,
> +                         <&cru DCLK_VOP0>,
> +                         <&cru DCLK_VOP1>,
> +                         <&cru DCLK_VOP2>;
> +                clock-names = "aclk_vop",
> +                              "hclk_vop",
> +                              "dclk_vp0",
> +                              "dclk_vp1",
> +                              "dclk_vp2";
> +                power-domains = <&power RK3568_PD_VO>;
> +                iommus = <&vop_mmu>;
> +                vop_out: ports {
> +                    #address-cells = <1>;
> +                    #size-cells = <0>;
> +                    vp0: port@0 {
> +                        reg = <0>;
> +                        #address-cells = <1>;
> +                        #size-cells = <0>;
> +                    };
> +                    vp1: port@1 {
> +                        reg = <1>;
> +                        #address-cells = <1>;
> +                        #size-cells = <0>;
> +                    };
> +                    vp2: port@2 {
> +                        reg = <2>;
> +                        #address-cells = <1>;
> +                        #size-cells = <0>;
> +                    };
> +                };
> +            };
> +        };
> -- 
> 2.30.2
> 
> 

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder
  2021-12-20 11:06 ` [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer
@ 2021-12-21 17:31   ` Heiko Stübner
  0 siblings, 0 replies; 45+ messages in thread
From: Heiko Stübner @ 2021-12-21 17:31 UTC (permalink / raw)
  To: dri-devel, Sascha Hauer
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang, Peter Geis,
	Sascha Hauer

Am Montag, 20. Dezember 2021, 12:06:28 CET schrieb Sascha Hauer:
> Add a device node to drm_encoder which corresponds with the port node
> in the DT description of the encoder. This allows drivers to find the
> of_graph link between a crtc and an encoder.
> 
> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> ---
>  include/drm/drm_encoder.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/drm/drm_encoder.h b/include/drm/drm_encoder.h
> index 6e91a0280f31b..3acd054b1eb3e 100644
> --- a/include/drm/drm_encoder.h
> +++ b/include/drm/drm_encoder.h
> @@ -99,6 +99,8 @@ struct drm_encoder {
>  	struct drm_device *dev;
>  	struct list_head head;
>  
> +	struct device_node *port;
> +
>  	struct drm_mode_object base;
>  	char *name;
>  	/**
> 

Is this the port that gets used in patch 3/22?
It looks like it.

So this would break bisectability. Can we order patches
sequentially so that git bisect keeps working.

Thanks
Heiko




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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-21 14:31   ` Rob Herring
@ 2021-12-22 10:47     ` Sascha Hauer
  2021-12-22 13:52       ` Rob Herring
  0 siblings, 1 reply; 45+ messages in thread
From: Sascha Hauer @ 2021-12-22 10:47 UTC (permalink / raw)
  To: Rob Herring
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis

On Tue, Dec 21, 2021 at 10:31:23AM -0400, Rob Herring wrote:
> On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> > "vpll" is a misnomer. A clock input to a device should be named after
> > the usage in the device, not after the clock that drives it. On the
> > rk3568 the same clock is driven by the HPLL.
> > To fix that, this patch renames the vpll clock to ref clock.
> 
> The problem with this series is it breaks an old kernel with new dt. You 
> can partially mitigate that with stable kernel backport, but IMO keeping 
> the old name is not a burden to maintain.

As suggested I only removed vpll from the binding document, but not from
the code. The code still handles the old binding as well.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-22 10:47     ` Sascha Hauer
@ 2021-12-22 13:52       ` Rob Herring
  2021-12-22 19:39         ` Heiko Stübner
  0 siblings, 1 reply; 45+ messages in thread
From: Rob Herring @ 2021-12-22 13:52 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: dri-devel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
	devicetree, Sascha Hauer, Andy Yan, Benjamin Gaignard,
	Michael Riesch, Sandy Huang, Heiko Stübner, Peter Geis

On Wed, Dec 22, 2021 at 6:47 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
>
> On Tue, Dec 21, 2021 at 10:31:23AM -0400, Rob Herring wrote:
> > On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> > > "vpll" is a misnomer. A clock input to a device should be named after
> > > the usage in the device, not after the clock that drives it. On the
> > > rk3568 the same clock is driven by the HPLL.
> > > To fix that, this patch renames the vpll clock to ref clock.
> >
> > The problem with this series is it breaks an old kernel with new dt. You
> > can partially mitigate that with stable kernel backport, but IMO keeping
> > the old name is not a burden to maintain.
>
> As suggested I only removed vpll from the binding document, but not from
> the code. The code still handles the old binding as well.

The problem is updating rk3399.dtsi. That change won't work with old
kernels because they won't look for 'ref'. Since you shouldn't change
it, the binding needs to cover both the old and new cases.

Rob

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
  2021-12-21 13:44   ` Nicolas Frattaroli
@ 2021-12-22 17:07     ` Nicolas Frattaroli
  2022-01-03 14:55     ` Sascha Hauer
  1 sibling, 0 replies; 45+ messages in thread
From: Nicolas Frattaroli @ 2021-12-22 17:07 UTC (permalink / raw)
  To: dri-devel, linux-rockchip
  Cc: linux-arm-kernel, linux-rockchip, devicetree, kernel, Andy Yan,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Sascha Hauer, Sascha Hauer,
	Nicolas Frattaroli

On Dienstag, 21. Dezember 2021 14:44:39 CET Nicolas Frattaroli wrote:
> On Montag, 20. Dezember 2021 12:06:30 CET Sascha Hauer wrote:
> > From: Andy Yan <andy.yan@rock-chips.com>
> >
> > The VOP2 unit is found on Rockchip SoCs beginning with rk3566/rk3568.
> > It replaces the VOP unit found in the older Rockchip SoCs.
> >
> > This driver has been derived from the downstream Rockchip Kernel and
> > heavily modified:
> >
> > - All nonstandard DRM properties have been removed
> > - dropped struct vop2_plane_state and pass around less data between
> >   functions
> > - Dropped all DRM_FORMAT_* not known on upstream
> > - rework register access to get rid of excessively used macros
> > - Drop all waiting for framesyncs
> >
> > The driver is tested with HDMI and MIPI-DSI display on a RK3568-EVB
> > board. Overlay support is tested with the modetest utility. AFBC support
> > on the cluster windows is tested with weston-simple-dmabuf-egl on
> > weston using the (yet to be upstreamed) panfrost driver support.
> >
> > Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
> > ---
>
> Hi Sascha,
>
> quick partial review of the code in-line.
>
> For reference, I debugged locking issues with the kernel lock
> debug config options and assert_spin_locked in the reg write
> functions, as well as some manual deduction.
>

As a small follow-up, I've completely mapped out the calls to
vop2_writel, vop2_readl, vop2_vp_write and vop2_win_write and
coloured in whether they were called with the lock held or not.

The conclusion is startling: Most of the code absolutely does
not care about the reg_lock.

Here's the graph as an SVG: https://overviewer.org/~pillow/up/6800427ef3/vop2_callgraph_modified.svg

vop2_isr here needs to be paid special attention, as it also
acquires a different spinlock, and we want to avoid deadlocks.

Perhaps we should precisely define which lock must be held for
what registers, such that the vop2_isr can write its interrupt
related registers without acquiring the "big" reg_lock.

I'm also not entirely sure whether I should assume vop2_readl
needs to be called with the lock held. This needs some
investigating both in terms of whether the hardware presents
a writel as an atomic write of a long, and whether the code
assumes the state between readl calls is ever a consistent view.

Regards,
Nicolas Frattaroli




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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-22 13:52       ` Rob Herring
@ 2021-12-22 19:39         ` Heiko Stübner
  2021-12-22 19:44           ` Nicolas Frattaroli
  2021-12-22 19:56           ` Rob Herring
  0 siblings, 2 replies; 45+ messages in thread
From: Heiko Stübner @ 2021-12-22 19:39 UTC (permalink / raw)
  To: Sascha Hauer, Rob Herring
  Cc: dri-devel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
	devicetree, Sascha Hauer, Andy Yan, Benjamin Gaignard,
	Michael Riesch, Sandy Huang, Peter Geis

Am Mittwoch, 22. Dezember 2021, 14:52:51 CET schrieb Rob Herring:
> On Wed, Dec 22, 2021 at 6:47 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
> >
> > On Tue, Dec 21, 2021 at 10:31:23AM -0400, Rob Herring wrote:
> > > On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> > > > "vpll" is a misnomer. A clock input to a device should be named after
> > > > the usage in the device, not after the clock that drives it. On the
> > > > rk3568 the same clock is driven by the HPLL.
> > > > To fix that, this patch renames the vpll clock to ref clock.
> > >
> > > The problem with this series is it breaks an old kernel with new dt. You
> > > can partially mitigate that with stable kernel backport, but IMO keeping
> > > the old name is not a burden to maintain.
> >
> > As suggested I only removed vpll from the binding document, but not from
> > the code. The code still handles the old binding as well.
> 
> The problem is updating rk3399.dtsi. That change won't work with old
> kernels because they won't look for 'ref'. Since you shouldn't change
> it, the binding needs to cover both the old and new cases.

is "newer dt with old kernel" really a case these days?

I do understand the new kernel old dt case - for example with the
dtb being provided by firmware.

But which user would get the idea of updating only the devicetree
while staying with an older kernel?




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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-22 19:39         ` Heiko Stübner
@ 2021-12-22 19:44           ` Nicolas Frattaroli
  2021-12-22 19:56           ` Rob Herring
  1 sibling, 0 replies; 45+ messages in thread
From: Nicolas Frattaroli @ 2021-12-22 19:44 UTC (permalink / raw)
  To: Sascha Hauer, Rob Herring, linux-rockchip
  Cc: dri-devel, linux-arm-kernel, open list:ARM/Rockchip SoC...,
	devicetree, Sascha Hauer, Andy Yan, Benjamin Gaignard,
	Michael Riesch, Sandy Huang, Peter Geis, Heiko Stübner

On Mittwoch, 22. Dezember 2021 20:39:58 CET Heiko Stübner wrote:
> Am Mittwoch, 22. Dezember 2021, 14:52:51 CET schrieb Rob Herring:
> > On Wed, Dec 22, 2021 at 6:47 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > >
> > > On Tue, Dec 21, 2021 at 10:31:23AM -0400, Rob Herring wrote:
> > > > On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> > > > > "vpll" is a misnomer. A clock input to a device should be named after
> > > > > the usage in the device, not after the clock that drives it. On the
> > > > > rk3568 the same clock is driven by the HPLL.
> > > > > To fix that, this patch renames the vpll clock to ref clock.
> > > >
> > > > The problem with this series is it breaks an old kernel with new dt. You
> > > > can partially mitigate that with stable kernel backport, but IMO keeping
> > > > the old name is not a burden to maintain.
> > >
> > > As suggested I only removed vpll from the binding document, but not from
> > > the code. The code still handles the old binding as well.
> > 
> > The problem is updating rk3399.dtsi. That change won't work with old
> > kernels because they won't look for 'ref'. Since you shouldn't change
> > it, the binding needs to cover both the old and new cases.
> 
> is "newer dt with old kernel" really a case these days?
> 
> I do understand the new kernel old dt case - for example with the
> dtb being provided by firmware.
> 
> But which user would get the idea of updating only the devicetree
> while staying with an older kernel?
> 

Side-by-side installations of LTS kernels with new kernels. LTS kernel
uses same DT as new kernel because distribution set it up this way.

Other scenario: user wants to modify their device tree. They download
the latest kernel sources from kernel.org because they can't use over-
lays and they don't want to fiddle with decompiled device trees.



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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name
  2021-12-22 19:39         ` Heiko Stübner
  2021-12-22 19:44           ` Nicolas Frattaroli
@ 2021-12-22 19:56           ` Rob Herring
  1 sibling, 0 replies; 45+ messages in thread
From: Rob Herring @ 2021-12-22 19:56 UTC (permalink / raw)
  To: Heiko Stübner
  Cc: Sascha Hauer, dri-devel, linux-arm-kernel,
	open list:ARM/Rockchip SoC...,
	devicetree, Sascha Hauer, Andy Yan, Benjamin Gaignard,
	Michael Riesch, Sandy Huang, Peter Geis

On Wed, Dec 22, 2021 at 3:40 PM Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Mittwoch, 22. Dezember 2021, 14:52:51 CET schrieb Rob Herring:
> > On Wed, Dec 22, 2021 at 6:47 AM Sascha Hauer <s.hauer@pengutronix.de> wrote:
> > >
> > > On Tue, Dec 21, 2021 at 10:31:23AM -0400, Rob Herring wrote:
> > > > On Mon, Dec 20, 2021 at 12:06:16PM +0100, Sascha Hauer wrote:
> > > > > "vpll" is a misnomer. A clock input to a device should be named after
> > > > > the usage in the device, not after the clock that drives it. On the
> > > > > rk3568 the same clock is driven by the HPLL.
> > > > > To fix that, this patch renames the vpll clock to ref clock.
> > > >
> > > > The problem with this series is it breaks an old kernel with new dt. You
> > > > can partially mitigate that with stable kernel backport, but IMO keeping
> > > > the old name is not a burden to maintain.
> > >
> > > As suggested I only removed vpll from the binding document, but not from
> > > the code. The code still handles the old binding as well.
> >
> > The problem is updating rk3399.dtsi. That change won't work with old
> > kernels because they won't look for 'ref'. Since you shouldn't change
> > it, the binding needs to cover both the old and new cases.
>
> is "newer dt with old kernel" really a case these days?

I've had complaints about it. In particular from SUSE folks that were
shipping new dtbs with old (stable) kernels.

> I do understand the new kernel old dt case - for example with the
> dtb being provided by firmware.

Yes, so update your firmware that contains a newer dtb and then you
stop booting or a device stops working.

> But which user would get the idea of updating only the devicetree
> while staying with an older kernel?

Any synchronization between firmware and OS updates is a problem.

Rob

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
  2021-12-21 13:44   ` Nicolas Frattaroli
  2021-12-22 17:07     ` Nicolas Frattaroli
@ 2022-01-03 14:55     ` Sascha Hauer
  1 sibling, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2022-01-03 14:55 UTC (permalink / raw)
  To: Nicolas Frattaroli
  Cc: dri-devel, linux-rockchip, linux-arm-kernel, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis

Hi Nicolas,

Thanks for the review. I have changed the points I don't comment on here
according to your suggestions.

> > +#include <linux/regmap.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/delay.h>
> > +#include <linux/swab.h>
> > +#include <linux/bitfield.h>
> > +#include <drm/drm_debugfs.h>
> > +#include <uapi/linux/videodev2.h>
> > +#include <drm/drm_vblank.h>
> > +#include <dt-bindings/soc/rockchip,vop2.h>
> 
> Alphabetically sort these includes? Not sure on what the
> convention is in the DRM subsystem.

Me neither. The first random file I looked at in drivers/gpu/drm/ has
the includes sorted alphabetically, so I'll do the same.

> 
> > +static void vop2_cfg_done(struct vop2_video_port *vp)
> > +{
> > +	struct vop2 *vop2 = vp->vop2;
> > +	uint32_t val;
> > +
> > +	val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
> > +
> > +	val &= 0x7;
> 
> GENMASK(2, 0) instead of 0x7, should that be a constant somewhere?
> 
> > +
> > +	vop2_writel(vop2, RK3568_REG_CFG_DONE,
> > +		    val | BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);

Replaced that with the following which doesn't need a mask:

	regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
				BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);


> > +}
> > +
> > +static void vop2_win_disable(struct vop2_win *win)
> > +{
> > +	vop2_win_write(win, VOP2_WIN_ENABLE, 0);
> > +
> > +	if (vop2_cluster_window(win))
> > +		vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
> > +}
> > +
> > +static uint32_t vop2_afbc_transform_offset(struct drm_plane_state *pstate,
> > +					   bool afbc_half_block_en)
> > +{
> > +	struct drm_rect *src = &pstate->src;
> > +	struct drm_framebuffer *fb = pstate->fb;
> > +	uint32_t bpp = fb->format->cpp[0] * 8;
> > +	uint32_t vir_width = (fb->pitches[0] << 3) / bpp;
> > +	uint32_t width = drm_rect_width(src) >> 16;
> > +	uint32_t height = drm_rect_height(src) >> 16;
> > +	uint32_t act_xoffset = src->x1 >> 16;
> > +	uint32_t act_yoffset = src->y1 >> 16;
> > +	uint32_t align16_crop = 0;
> > +	uint32_t align64_crop = 0;
> > +	uint32_t height_tmp = 0;
> > +	uint32_t transform_tmp = 0;
> > +	uint8_t transform_xoffset = 0;
> > +	uint8_t transform_yoffset = 0;
> > +	uint8_t top_crop = 0;
> > +	uint8_t top_crop_line_num = 0;
> > +	uint8_t bottom_crop_line_num = 0;
> > +
> > +	/* 16 pixel align */
> > +	if (height & 0xf)
> > +		align16_crop = 16 - (height & 0xf);
> > +
> > +	height_tmp = height + align16_crop;
> > +
> > +	/* 64 pixel align */
> > +	if (height_tmp & 0x3f)
> > +		align64_crop = 64 - (height_tmp & 0x3f);
> > +
> > +	top_crop_line_num = top_crop << 2;
> > +	if (top_crop == 0)
> > +		bottom_crop_line_num = align16_crop + align64_crop;
> > +	else if (top_crop == 1)
> > +		bottom_crop_line_num = align16_crop + align64_crop + 12;
> > +	else if (top_crop == 2)
> > +		bottom_crop_line_num = align16_crop + align64_crop + 8;
> 
> top_crop == 0 is always taken from what I can gather, rest is
> dead code. Is this intentional? It doesn't seem intentional.

It's the same in the downstream driver. I don't know what top_crop is
good for. I just removed the dead code for now.

> > +		transform_xoffset = transform_tmp & 0xf;
> > +		transform_tmp = vir_width - width - act_xoffset;
> > +		transform_yoffset = transform_tmp & 0xf;
> > +		break;
> > +	case 0:
> > +		transform_tmp = act_xoffset;
> > +		transform_xoffset = transform_tmp & 0xf;
> > +		transform_tmp = top_crop_line_num + act_yoffset;
> > +
> > +		if (afbc_half_block_en)
> > +			transform_yoffset = transform_tmp & 0x7;
> > +		else
> > +			transform_yoffset = transform_tmp & 0xf;
> > +
> > +		break;
> > +	}
> > +
> > +	return (transform_xoffset & 0xf) | ((transform_yoffset & 0xf) << 16);
> > +}
> 
> 0xf, 0x3f, 0x7 might be more clear as GENMASK.
> if (afbc_half_block_en) branches can be moved out of cases and
> assign a transform mask variable instead.

Sure. Other than that the function can be simplified a bit more.

> 
> > +
> > +/*
> > + * A Cluster window has 2048 x 16 line buffer, which can
> > + * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
> > + * for Cluster_lb_mode register:
> > + * 0: half mode, for plane input width range 2048 ~ 4096
> > + * 1: half mode, for cluster work at 2 * 2048 plane mode
> > + * 2: half mode, for rotate_90/270 mode
> > + *
> > + */
> > +static int vop2_get_cluster_lb_mode(struct vop2_win *win, struct drm_plane_state *pstate)
> > +{
> > +	if ((pstate->rotation & DRM_MODE_ROTATE_270) || (pstate->rotation & DRM_MODE_ROTATE_90))
> > +		return 2;
> > +	else
> > +		return 0;
> > +}
> 
> What about 1?

1 is used in the downstream driver for cluster sub windows. These are
currently not supported, I don't know yet where this is leading to.

> 
> > +
> > +/*
> > + * bli_sd_factor = (src - 1) / (dst - 1) << 12;
> > + * avg_sd_factor:
> > + * bli_su_factor:
> > + * bic_su_factor:
> > + * = (src - 1) / (dst - 1) << 16;
> > + *
> > + * gt2 enable: dst get one line from two line of the src
> > + * gt4 enable: dst get one line from four line of the src.
> > + *
> > + */
> > +static uint16_t vop2_scale_factor(enum scale_mode mode,
> > +				  int32_t filter_mode,
> > +				  uint32_t src, uint32_t dst)
> > +{
> > +	uint32_t fac;
> > +	int i;
> > +
> > +	if (mode == SCALE_NONE)
> > +		return 0;
> > +
> > +	/*
> > +	 * A workaround to avoid zero div.
> > +	 */
> > +	if (dst == 1 || src == 1) {
> > +		dst++;
> > +		src++;
> > +	}
> > +
> > +	if ((mode == SCALE_DOWN) && (filter_mode == VOP2_SCALE_DOWN_BIL)) {
> > +		fac = ((src - 1) << 12) / (dst - 1);
> > +		for (i = 0; i < 100; i++) {
> > +			if (fac * (dst - 1) >> 12 < (src - 1))
> > +				break;
> > +			fac -= 1;
> > +			DRM_DEBUG("down fac cali: src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
> > +		}
> > +	} else {
> > +		fac = ((src - 1) << 16) / (dst - 1);
> > +		for (i = 0; i < 100; i++) {
> > +			if (fac * (dst - 1) >> 16 < (src - 1))
> > +				break;
> > +			fac -= 1;
> > +			DRM_DEBUG("up fac cali:  src:%d, dst:%d, fac:0x%x\n", src, dst, fac);
> > +		}
> > +	}
> > +
> > +	return fac;
> > +}
> 
> src = 0 or dst = 0 causes an uint underflow here.

Right. Looking at it these loops are rather unnecessary and duplicating
the code also. The whole function goes down to:

static uint16_t vop2_scale_factor(uint32_t src, uint32_t dst)
{
	uint32_t fac;
	int shift;

	if (src == dst)
		return 0;

	if (dst < 2)
		return U16_MAX;

	if (src < 2)
		return 0;

	if (src > dst)
		shift = 12;
	else
		shift = 16;

	src--;
	dst--;

	fac = DIV_ROUND_UP(src << shift, dst) - 1;

	if (fac > U16_MAX)
		return U16_MAX;

	return fac;
}


> > +static void vop2_enable(struct vop2 *vop2)
> > +{
> > +	int ret;
> > +	uint32_t v;
> > +
> > +	ret = pm_runtime_get_sync(vop2->dev);
> > +	if (ret < 0) {
> > +		drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
> > +		return;
> > +	}
> > +
> > +	ret = vop2_core_clks_prepare_enable(vop2);
> > +	if (ret) {
> > +		pm_runtime_put_sync(vop2->dev);
> > +		return;
> > +	}
> > +
> > +	if (vop2->data->soc_id == 3566)
> > +		vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
> > +
> > +	vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
> > +
> > +	/*
> > +	 * Disable auto gating, this is a workaround to
> > +	 * avoid display image shift when a window enabled.
> > +	 */
> > +	v = vop2_readl(vop2, RK3568_SYS_AUTO_GATING_CTRL);
> > +	v &= ~RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN;
> > +	vop2_writel(vop2, RK3568_SYS_AUTO_GATING_CTRL, v);
> > +
> > +	vop2_writel(vop2, RK3568_SYS0_INT_CLR,
> > +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> > +	vop2_writel(vop2, RK3568_SYS0_INT_EN,
> > +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> > +	vop2_writel(vop2, RK3568_SYS1_INT_CLR,
> > +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> > +	vop2_writel(vop2, RK3568_SYS1_INT_EN,
> > +		    VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
> > +}
> 
> Does reg writes but doesn't have the spinlock.

I didn't care about it at all when working on this driver, so we can be
sure it's at the wrong places right now.

I think we can just drop the register spinlock. The driver uses regmap
now, so read-modify-write accesses are covered by the regmap internal
locking as long as we use regmap_update_bits(). The remaining accesses
are either orthogonal anyway or are covered by the vop2_lock mutex.

> > +	vop2_lock(vop2);
> > +
> > +	ret = clk_prepare_enable(vp->dclk);
> > +	if (ret < 0) {
> > +		drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
> > +			      vp->id, ret);
> > +		return;
> 
> vop2_lock is never unlocked in this branch

I'll move the call to vop2_lock() below the clk_prepare_enable().

> > +	}
> > +
> > +	pm_runtime_put(vop2->dev);
> > +
> > +	return ret;
> > +}
> 
> Does reg writes, does the ISR need the reg spinlock here? I'm not
> sure.
> 
> In general there appear to be a lot of issues with the register
> lock, so either I'm misunderstanding what it's supposed to protect
> or the code is very thread unsafe.

Yeah, the original driver had the spinlock and as said I kept it but
didn't maintain it. Let's remove it for now.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH 22/22] drm: rockchip: Add VOP2 driver
       [not found]   ` <a0942adc-52c1-811e-0de6-d0616266ce2d@rock-chips.com>
@ 2022-01-05 12:20     ` Sascha Hauer
  0 siblings, 0 replies; 45+ messages in thread
From: Sascha Hauer @ 2022-01-05 12:20 UTC (permalink / raw)
  To: Andy Yan
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis, Kever Yang

Hi Andy,

On Tue, Jan 04, 2022 at 07:07:23PM +0800, Andy Yan wrote:
> 
> 
> I thinks we should be very carefully about switch to regmap.
> 
> Most of the registers are take effect by frame sync(that is you write the
> config done bit and when vsync interrupt come),
> 
> Not only windows register, but also the SYS_CTRL, post processor(VP0/1/2), 
> OVERLAY, hdr and so on.

That's why I marked these as nonvolatile, so that reading the registers
comes from the cache. I may have missed some registers, these could be
added when needed.

> > +	ret = vop2_win_init(vop2);
> > +	if (ret)
> > +		return ret;
> Do you have a count about how much time the function vop2_win_init cost ?

No. Why does that matter?

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support
  2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
                   ` (22 preceding siblings ...)
       [not found] ` <20211220110630.3521121-23-s.hauer@pengutronix.de>
@ 2022-01-19 11:29 ` Piotr Oniszczuk
  2022-01-21 10:32   ` Sascha Hauer
  23 siblings, 1 reply; 45+ messages in thread
From: Piotr Oniszczuk @ 2022-01-19 11:29 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis



> Wiadomość napisana przez Sascha Hauer <s.hauer@pengutronix.de> w dniu 20.12.2021, o godz. 12:06:
> 
> 
> Third round of patches and last one for this year. I hopefully integrated
> all review feedback. Additionally the driver is now fully converted to
> regmap, so no struct vop_reg necessary anymore.
> 
> Sascha
> 
> Changes since v2:
> - Add pin names to HDMI supply pin description
> - Add hclk support to HDMI driver
> - Dual license rockchip-vop2 binding, update binding
> - Add HDMI connector to board dts files
> - drop unnecessary gamma_lut registers from vop2
> - Update dclk_vop[012] clock handling, no longer hacks needed
> - Complete regmap conversion
> 

Sascha

I'm using you VOP2 code on rk3566 tvbox (x96-x6) with very good results.

I have just few questions:

1. how support for CEC looks/prospects (plans for future, not in this code, expecting others should implement, etc)?

2. VOP2 code works nice for me for x11/glamour and for EGLFS with EGL DMAbuf rendering by Mesa EGL_LINUX_DMA_BUF_EXT.
I have issue however with app. rendering to DRM planes (GUI is DRM plane1, video is DRM pane2). 
My ppp starts/works without any errors in log - but screen stays with kernel messages content.
(it looks to me like i.e. app renders to DRM plane but DRM display driver not pass it to CRTC. just wild guess here...).

3. in kernel dmesg I have many:

"rockchip-drm display-subsystem: [drm] *ERROR* Unsupported format modifier 0x810000000000001".

It comes from MESA i think - but i suspect because VOP2 provides unknown/wrong DRM modifier to mesa?.
I'm not sure how to progress with this (talk to you or involve MESA devs or wait for VOP2 v4)?

Again: great work with VOP2 on rk356x!


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^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support
  2022-01-19 11:29 ` [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Piotr Oniszczuk
@ 2022-01-21 10:32   ` Sascha Hauer
  2022-01-21 15:43     ` Piotr Oniszczuk
  0 siblings, 1 reply; 45+ messages in thread
From: Sascha Hauer @ 2022-01-21 10:32 UTC (permalink / raw)
  To: Piotr Oniszczuk
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis

Hi Piotr,

On Wed, Jan 19, 2022 at 12:29:49PM +0100, Piotr Oniszczuk wrote:
> 
> 
> > Wiadomość napisana przez Sascha Hauer <s.hauer@pengutronix.de> w dniu 20.12.2021, o godz. 12:06:
> > 
> > 
> > Third round of patches and last one for this year. I hopefully integrated
> > all review feedback. Additionally the driver is now fully converted to
> > regmap, so no struct vop_reg necessary anymore.
> > 
> > Sascha
> > 
> > Changes since v2:
> > - Add pin names to HDMI supply pin description
> > - Add hclk support to HDMI driver
> > - Dual license rockchip-vop2 binding, update binding
> > - Add HDMI connector to board dts files
> > - drop unnecessary gamma_lut registers from vop2
> > - Update dclk_vop[012] clock handling, no longer hacks needed
> > - Complete regmap conversion
> > 
> 
> Sascha
> 
> I'm using you VOP2 code on rk3566 tvbox (x96-x6) with very good results.
> 
> I have just few questions:
> 
> 1. how support for CEC looks/prospects (plans for future, not in this code, expecting others should implement, etc)?

I had to google what CEC actually is. We don't have plans supporting it.
It looks like this is a matter of the HDMI driver supporting this and
not bound to the rockchip driver.

> 
> 2. VOP2 code works nice for me for x11/glamour and for EGLFS with EGL DMAbuf rendering by Mesa EGL_LINUX_DMA_BUF_EXT.
> I have issue however with app. rendering to DRM planes (GUI is DRM plane1, video is DRM pane2). 
> My ppp starts/works without any errors in log - but screen stays with kernel messages content.
> (it looks to me like i.e. app renders to DRM plane but DRM display driver not pass it to CRTC. just wild guess here...).

You enabled the panfrost driver with other patches, right?

> 
> 3. in kernel dmesg I have many:
> 
> "rockchip-drm display-subsystem: [drm] *ERROR* Unsupported format modifier 0x810000000000001".

This message is correct. This corresponds to
DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED and the VOP2 driver doesn't
support this. I have a similar problem here with
weston-simple-dmabuf-egl.  By default this uses DRM_FORMAT_XRGB8888
which ends up being PIPE_FORMAT_B8G8R8_UNORM in MESA. In
panfrost_afbc_format() we have:

        /* Don't allow swizzled formats on v7 */
        switch (format) {
        case PIPE_FORMAT_B8G8R8A8_UNORM:
        case PIPE_FORMAT_B8G8R8X8_UNORM:
        case PIPE_FORMAT_A8R8G8B8_UNORM:
        case PIPE_FORMAT_X8R8G8B8_UNORM:
        case PIPE_FORMAT_X8B8G8R8_UNORM:
        case PIPE_FORMAT_A8B8G8R8_UNORM:
        case PIPE_FORMAT_B8G8R8_UNORM:
        case PIPE_FORMAT_B5G6R5_UNORM:
                if (dev->arch >= 7)
                        return PIPE_FORMAT_NONE;

                break;
        default:
                break;
        }

This means the driver won't do AFBC with that format and picks
DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED instead. Now weston is
clever enough to not pass that into the VOP2 driver, apparently your
application is not and as a result you see that message.

In weston-simple-dmabuf-egl I can pass a suitable format on the command
line, in my case I use DRM_FORMAT_ABGR8888 (which becomes
PIPE_FORMAT_R8G8B8A8_UNORM). With this the panfrost driver does AFBC
which then can be rendered in the VOP2 cluster window overlay.

> 
> It comes from MESA i think - but i suspect because VOP2 provides
> unknown/wrong DRM modifier to mesa?

Nope, the modifiers the VOP2 driver propagates are correct. It doesn't
claim to support DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED.

Sascha

-- 
Pengutronix e.K.                           |                             |
Steuerwalder Str. 21                       | http://www.pengutronix.de/  |
31137 Hildesheim, Germany                  | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 45+ messages in thread

* Re: [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support
  2022-01-21 10:32   ` Sascha Hauer
@ 2022-01-21 15:43     ` Piotr Oniszczuk
  0 siblings, 0 replies; 45+ messages in thread
From: Piotr Oniszczuk @ 2022-01-21 15:43 UTC (permalink / raw)
  To: Sascha Hauer
  Cc: dri-devel, linux-arm-kernel, linux-rockchip, devicetree, kernel,
	Andy Yan, Benjamin Gaignard, Michael Riesch, Sandy Huang,
	Heiko Stübner, Peter Geis



> Wiadomość napisana przez Sascha Hauer <s.hauer@pengutronix.de> w dniu 21.01.2022, o godz. 11:32:
> 
>> 
>> 1. how support for CEC looks/prospects (plans for future, not in this code, expecting others should implement, etc)?
> 
> I had to google what CEC actually is. We don't have plans supporting it.
> It looks like this is a matter of the HDMI driver supporting this and
> not bound to the rockchip driver.

Ah ok. sure. got it!
(I asked as Rockchip hdmi driver already well supports CEC - so i was thinking on rk3566 this is more of enabling than writing support code).

> You enabled the panfrost driver with other patches, right?

Oh - i wasn't aware any patches are needed for Mesa for rk3566....
If so - may you pls point me for latest/correct patches for rk3566? 

> 
>> 
>> 3. in kernel dmesg I have many:
>> 
>> "rockchip-drm display-subsystem: [drm] *ERROR* Unsupported format modifier 0x810000000000001".
> 
> This message is correct. This corresponds to
> DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED and the VOP2 driver doesn't
> support this. I have a similar problem here with
> weston-simple-dmabuf-egl.  By default this uses DRM_FORMAT_XRGB8888
> which ends up being PIPE_FORMAT_B8G8R8_UNORM in MESA.

Ah ok. Clear now.

Thx!

btw: i added support for argb8888 in my app and now all is ok. 
no anymore errors in dmesg :-)

so summarising:
your vop2 code works for me in all supported video pipeline variants:

-x11/Glamour
-Wayland-EGL
-EGLFS/EGL-dmabuf
-EGLFS/DRM Planes 

Your vop2 work is impressive!

btw:
you mention:

> In weston-simple-dmabuf-egl I can pass a suitable format on the command
> line, in my case I use DRM_FORMAT_ABGR8888 (which becomes
> PIPE_FORMAT_R8G8B8A8_UNORM). With this the panfrost driver does AFBC
> which then can be rendered in the VOP2 cluster window overlay.

is this mean that: when my app is using ARGB8888 format - then I have AFBC on rk3566?



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^ permalink raw reply	[flat|nested] 45+ messages in thread

end of thread, other threads:[~2022-01-21 15:45 UTC | newest]

Thread overview: 45+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-12-20 11:06 [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Sascha Hauer
2021-12-20 11:06 ` [PATCH 01/22] drm/rockchip: dw_hdmi: Do not leave clock enabled in error case Sascha Hauer
2021-12-20 11:06 ` [PATCH 02/22] drm/rockchip: dw_hdmi: rename vpll clock to reference clock Sascha Hauer
2021-12-20 11:06 ` [PATCH 03/22] drm/rockchip: dw_hdmi: add rk3568 support Sascha Hauer
2021-12-20 11:06 ` [PATCH 04/22] drm/rockchip: dw_hdmi: add regulator support Sascha Hauer
2021-12-20 11:06 ` [PATCH 05/22] drm/rockchip: dw_hdmi: Add support for hclk Sascha Hauer
2021-12-20 11:06 ` [PATCH 06/22] dt-bindings: display: rockchip: dw-hdmi: Add compatible for rk3568 HDMI Sascha Hauer
2021-12-20 11:06 ` [PATCH 07/22] dt-bindings: display: rockchip: dw-hdmi: Make unwedge pinctrl optional Sascha Hauer
2021-12-20 14:27   ` Rob Herring
2021-12-20 11:06 ` [PATCH 08/22] dt-bindings: display: rockchip: dw-hdmi: use "ref" as clock name Sascha Hauer
2021-12-20 14:27   ` Rob Herring
2021-12-21 14:31   ` Rob Herring
2021-12-22 10:47     ` Sascha Hauer
2021-12-22 13:52       ` Rob Herring
2021-12-22 19:39         ` Heiko Stübner
2021-12-22 19:44           ` Nicolas Frattaroli
2021-12-22 19:56           ` Rob Herring
2021-12-20 11:06 ` [PATCH 09/22] dt-bindings: display: rockchip: dw-hdmi: Add regulator support Sascha Hauer
2021-12-20 14:27   ` Rob Herring
2021-12-20 11:06 ` [PATCH 10/22] dt-bindings: display: rockchip: dw-hdmi: Add additional clock Sascha Hauer
2021-12-20 11:06 ` [PATCH 11/22] dt-bindings: display: rockchip: Add binding for VOP2 Sascha Hauer
2021-12-20 14:27   ` Rob Herring
2021-12-21 14:33   ` Rob Herring
2021-12-20 11:06 ` [PATCH 12/22] arm64: dts: rockchip: rk3399: reorder hmdi clocks Sascha Hauer
2021-12-20 11:06 ` [PATCH 13/22] arm64: dts: rockchip: rk3399: rename HDMI ref clock to 'ref' Sascha Hauer
2021-12-20 11:06 ` [PATCH 14/22] arm64: dts: rockchip: rk356x: Add VOP2 nodes Sascha Hauer
2021-12-20 11:06 ` [PATCH 15/22] arm64: dts: rockchip: rk356x: Add HDMI nodes Sascha Hauer
2021-12-20 11:06 ` [PATCH 16/22] arm64: dts: rockchip: rk3568-evb: Enable VOP2 and hdmi Sascha Hauer
2021-12-20 11:06 ` [PATCH 17/22] arm64: dts: rockchip: enable vop2 and hdmi tx on quartz64a Sascha Hauer
2021-12-20 11:06 ` [PATCH 18/22] clk: rk3568: drop CLK_SET_RATE_PARENT from dclk_vop* Sascha Hauer
2021-12-20 11:06 ` [PATCH 19/22] clk: rk3568: Add CLK_SET_RATE_PARENT to the HDMI reference clock Sascha Hauer
2021-12-20 11:06 ` [PATCH 20/22] drm/encoder: Add of_graph port to struct drm_encoder Sascha Hauer
2021-12-21 17:31   ` Heiko Stübner
2021-12-20 11:06 ` [PATCH 21/22] drm/rockchip: Make VOP driver optional Sascha Hauer
2021-12-20 11:51 ` [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Nicolas Frattaroli
     [not found] ` <20211220110630.3521121-23-s.hauer@pengutronix.de>
2021-12-20 14:16   ` [PATCH 22/22] drm: rockchip: Add VOP2 driver Nicolas Frattaroli
2021-12-20 16:53     ` Nicolas Frattaroli
2021-12-20 18:51     ` Sascha Hauer
2021-12-21 13:44   ` Nicolas Frattaroli
2021-12-22 17:07     ` Nicolas Frattaroli
2022-01-03 14:55     ` Sascha Hauer
     [not found]   ` <a0942adc-52c1-811e-0de6-d0616266ce2d@rock-chips.com>
2022-01-05 12:20     ` Sascha Hauer
2022-01-19 11:29 ` [PATCH v3 00/22] drm/rockchip: RK356x VOP2 support Piotr Oniszczuk
2022-01-21 10:32   ` Sascha Hauer
2022-01-21 15:43     ` Piotr Oniszczuk

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as well as URLs for NNTP newsgroup(s).