Re: [PATCH] PCI: imx6: Select correct clock source for MX7D PCIe PHY

Re: [PATCH] PCI: imx6: Select correct clock source for MX7D PCIe PHY

[Marek Vasut]

On 9/28/20 3:39 AM, Richard Zhu wrote:
[...]
>>>> The internal PCIe PHY clock source cannot lock the PLL, use the
>>>> external pad one just like iMX8MQ does, which is very similar SoC in this area.
>>>>
>>> [Richard Zhu] Hi Marek:
>>> Do you know why PCIe PHY clock can't be locked when internal PLL is used as
>> PCIe REF CLK?
>>> As I know that the PCIe PHY clock can be locked on iMX7D SDB board when
>> internal PLL is selected.
>>
>> I don't know, and I can't find any useful information which could explain it either,
>> nor why iMX8 does it differently (like this patch).
>> Maybe it is related to errata e10728 ?
> [Richard Zhu] 
> iMX8MQ has two PCIe controllers, and only has one pair CLK N/P pads to output the internal PLL to
> EP. Thus, the external OSC is used as REF clock source for both RC and EP.
> Maybe one property can be introduced to distinguish the internal PLL clock or the external OSC is used
> as PCIe REF clock source. 

I am open to suggestions. I would also like to know why I need this
patch on every iMX7D board I came across so far.

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

Re: [PATCH] PCI: imx6: Select correct clock source for MX7D PCIe PHY

[Marek Vasut]

On 9/27/20 4:13 AM, Richard Zhu wrote:

[...]

Hi,

>> The internal PCIe PHY clock source cannot lock the PLL, use the external pad one
>> just like iMX8MQ does, which is very similar SoC in this area.
>>
> [Richard Zhu] Hi Marek:
> Do you know why PCIe PHY clock can't be locked when internal PLL is used as PCIe REF CLK?
> As I know that the PCIe PHY clock can be locked on iMX7D SDB board when internal PLL is selected.

I don't know, and I can't find any useful information which could
explain it either, nor why iMX8 does it differently (like this patch).
Maybe it is related to errata e10728 ?

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH] PCI: imx6: Select correct clock source for MX7D PCIe PHY

[Marek Vasut]

The internal PCIe PHY clock source cannot lock the PLL,
use the external pad one just like iMX8MQ does, which
is very similar SoC in this area.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Lucas Stach <l.stach@pengutronix.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: linux-imx@nxp.com
---
 drivers/pci/controller/dwc/pci-imx6.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 5fef2613b223..a70cf4181d57 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -636,7 +636,8 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 		break;
 	case IMX7D:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
+				   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
 		break;
 	case IMX6SX:
 		regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
-- 
2.28.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel