* [RESEND PATCH v2 0/4] Mediatek MT8195 power domain support
@ 2021-06-16 0:06 Chun-Jie Chen
2021-06-16 0:06 ` [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data Chun-Jie Chen
` (3 more replies)
0 siblings, 4 replies; 12+ messages in thread
From: Chun-Jie Chen @ 2021-06-16 0:06 UTC (permalink / raw)
To: Enric Balletbo i Serra, Matthias Brugger, Nicolas Boichat, Rob Herring
Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek,
srv_heupstream, Project_Global_Chrome_Upstream_Group
This patch series adds power domain support for MT8195
and is based on 5.13-rc3.
reason for resend v2:
- miss patch version in series
change since v1:
- fix signed-off name
- describe more detail in patch 3
- move modification of removing redundant macro to single patch
Chun-Jie Chen (4):
soc: mediatek: pm-domains: Move power status offset to power domain
data
dt-bindings: power: Add MT8195 power domains
soc: mediatek: pm-domains: Add support for mt8195
soc: mediatek: pm-domains: Remove unused macro
.../power/mediatek,power-controller.yaml | 2 +
drivers/soc/mediatek/mt8167-pm-domains.h | 16 +-
drivers/soc/mediatek/mt8173-pm-domains.h | 22 +-
drivers/soc/mediatek/mt8183-pm-domains.h | 32 +-
drivers/soc/mediatek/mt8192-pm-domains.h | 44 +-
drivers/soc/mediatek/mt8195-pm-domains.h | 738 ++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 12 +-
drivers/soc/mediatek/mtk-pm-domains.h | 8 +-
include/dt-bindings/power/mt8195-power.h | 51 ++
include/linux/soc/mediatek/infracfg.h | 103 +++
10 files changed, 1013 insertions(+), 15 deletions(-)
create mode 100644 drivers/soc/mediatek/mt8195-pm-domains.h
create mode 100644 include/dt-bindings/power/mt8195-power.h
--
2.18.0
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^ permalink raw reply [flat|nested] 12+ messages in thread* [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data 2021-06-16 0:06 [RESEND PATCH v2 0/4] Mediatek MT8195 power domain support Chun-Jie Chen @ 2021-06-16 0:06 ` Chun-Jie Chen 2021-06-25 9:12 ` Enric Balletbo i Serra 2021-06-16 0:06 ` [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains Chun-Jie Chen ` (2 subsequent siblings) 3 siblings, 1 reply; 12+ messages in thread From: Chun-Jie Chen @ 2021-06-16 0:06 UTC (permalink / raw) To: Enric Balletbo i Serra, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group, Chun-Jie Chen MT8195 has more than 32 power domains so it needs two set of pwr_sta and pwr_sta2nd registers, so move the register offset from soc data into power domain data. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> --- drivers/soc/mediatek/mt8167-pm-domains.h | 16 +++++++-- drivers/soc/mediatek/mt8173-pm-domains.h | 22 ++++++++++-- drivers/soc/mediatek/mt8183-pm-domains.h | 32 +++++++++++++++-- drivers/soc/mediatek/mt8192-pm-domains.h | 44 ++++++++++++++++++++++-- drivers/soc/mediatek/mtk-pm-domains.c | 4 +-- drivers/soc/mediatek/mtk-pm-domains.h | 4 +-- 6 files changed, 110 insertions(+), 12 deletions(-) diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h index 15559ddf26e4..4d6c32759606 100644 --- a/drivers/soc/mediatek/mt8167-pm-domains.h +++ b/drivers/soc/mediatek/mt8167-pm-domains.h @@ -18,6 +18,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mm", .sta_mask = PWR_STATUS_DISP, .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -30,6 +32,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "vdec", .sta_mask = PWR_STATUS_VDEC, .ctl_offs = SPM_VDE_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -38,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "isp", .sta_mask = PWR_STATUS_ISP, .ctl_offs = SPM_ISP_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -46,6 +52,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mfg_async", .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC, .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, .bp_infracfg = { @@ -57,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mfg_2d", .sta_mask = MT8167_PWR_STATUS_MFG_2D, .ctl_offs = SPM_MFG_2D_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -64,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -71,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = SPM_CONN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = 0, .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -85,8 +99,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { static const struct scpsys_soc_data mt8167_scpsys_data = { .domains_data = scpsys_domain_data_mt8167, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167), - .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }; #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h index 654c717e5467..a4f58c2b44b1 100644 --- a/drivers/soc/mediatek/mt8173-pm-domains.h +++ b/drivers/soc/mediatek/mt8173-pm-domains.h @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "vdec", .sta_mask = PWR_STATUS_VDEC, .ctl_offs = SPM_VDE_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "venc", .sta_mask = PWR_STATUS_VENC, .ctl_offs = SPM_VEN_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -29,6 +33,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "isp", .sta_mask = PWR_STATUS_ISP, .ctl_offs = SPM_ISP_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), }, @@ -36,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mm", .sta_mask = PWR_STATUS_DISP, .ctl_offs = SPM_DIS_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -47,6 +55,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "venc_lt", .sta_mask = PWR_STATUS_VENC_LT, .ctl_offs = SPM_VEN2_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -54,6 +64,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "audio", .sta_mask = PWR_STATUS_AUDIO, .ctl_offs = SPM_AUDIO_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -61,6 +73,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "usb", .sta_mask = PWR_STATUS_USB, .ctl_offs = SPM_USB_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), .caps = MTK_SCPD_ACTIVE_WAKEUP, @@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mfg_async", .sta_mask = PWR_STATUS_MFG_ASYNC, .ctl_offs = SPM_MFG_ASYNC_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = 0, }, @@ -76,6 +92,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mfg_2d", .sta_mask = PWR_STATUS_MFG_2D, .ctl_offs = SPM_MFG_2D_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), }, @@ -83,6 +101,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = SPM_MFG_PWR_CON, + .pwr_sta_offs = SPM_PWR_STATUS, + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, .sram_pdn_bits = GENMASK(13, 8), .sram_pdn_ack_bits = GENMASK(21, 16), .bp_infracfg = { @@ -97,8 +117,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { static const struct scpsys_soc_data mt8173_scpsys_data = { .domains_data = scpsys_domain_data_mt8173, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173), - .pwr_sta_offs = SPM_PWR_STATUS, - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, }; #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediatek/mt8183-pm-domains.h index 98a9940d05fb..71b8757e552d 100644 --- a/drivers/soc/mediatek/mt8183-pm-domains.h +++ b/drivers/soc/mediatek/mt8183-pm-domains.h @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "audio", .sta_mask = PWR_STATUS_AUDIO, .ctl_offs = 0x0314, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), }, @@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = 0x032c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, .bp_infracfg = { @@ -33,6 +37,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_async", .sta_mask = PWR_STATUS_MFG_ASYNC, .ctl_offs = 0x0334, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, }, @@ -40,6 +46,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg", .sta_mask = PWR_STATUS_MFG, .ctl_offs = 0x0338, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .caps = MTK_SCPD_DOMAIN_SUPPLY, @@ -48,6 +56,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_core0", .sta_mask = BIT(7), .ctl_offs = 0x034c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -55,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_core1", .sta_mask = BIT(20), .ctl_offs = 0x0310, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -62,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "mfg_2d", .sta_mask = PWR_STATUS_MFG_2D, .ctl_offs = 0x0348, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -75,6 +89,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "disp", .sta_mask = PWR_STATUS_DISP, .ctl_offs = 0x030c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -94,6 +110,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "cam", .sta_mask = BIT(25), .ctl_offs = 0x0344, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "isp", .sta_mask = PWR_STATUS_ISP, .ctl_offs = 0x0308, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(9, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -140,6 +160,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vdec", .sta_mask = BIT(31), .ctl_offs = 0x0300, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_smi = { @@ -153,6 +175,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "venc", .sta_mask = PWR_STATUS_VENC, .ctl_offs = 0x0304, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(15, 12), .bp_smi = { @@ -166,6 +190,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vpu_top", .sta_mask = BIT(26), .ctl_offs = 0x0324, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -193,6 +219,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vpu_core0", .sta_mask = BIT(27), .ctl_offs = 0x33c, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -211,6 +239,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { .name = "vpu_core1", .sta_mask = BIT(28), .ctl_offs = 0x0340, + .pwr_sta_offs = 0x0180, + .pwr_sta2nd_offs = 0x0184, .sram_pdn_bits = GENMASK(11, 8), .sram_pdn_ack_bits = GENMASK(13, 12), .bp_infracfg = { @@ -230,8 +260,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { static const struct scpsys_soc_data mt8183_scpsys_data = { .domains_data = scpsys_domain_data_mt8183, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), - .pwr_sta_offs = 0x0180, - .pwr_sta2nd_offs = 0x0184 }; #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h index 543dda70de01..558c4ee4784a 100644 --- a/drivers/soc/mediatek/mt8192-pm-domains.h +++ b/drivers/soc/mediatek/mt8192-pm-domains.h @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "audio", .sta_mask = BIT(21), .ctl_offs = 0x0354, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -28,6 +30,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "conn", .sta_mask = PWR_STATUS_CONN, .ctl_offs = 0x0304, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = 0, .sram_pdn_ack_bits = 0, .bp_infracfg = { @@ -50,6 +54,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg0", .sta_mask = BIT(2), .ctl_offs = 0x0308, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -57,6 +63,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg1", .sta_mask = BIT(3), .ctl_offs = 0x030c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -82,6 +90,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg2", .sta_mask = BIT(4), .ctl_offs = 0x0310, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -89,6 +99,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg3", .sta_mask = BIT(5), .ctl_offs = 0x0314, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -96,6 +108,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg4", .sta_mask = BIT(6), .ctl_offs = 0x0318, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -103,6 +117,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg5", .sta_mask = BIT(7), .ctl_offs = 0x031c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -110,6 +126,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mfg6", .sta_mask = BIT(8), .ctl_offs = 0x0320, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "disp", .sta_mask = BIT(20), .ctl_offs = 0x0350, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -146,6 +166,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "ipe", .sta_mask = BIT(14), .ctl_offs = 0x0338, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -163,6 +185,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "isp", .sta_mask = BIT(12), .ctl_offs = 0x0330, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -180,6 +204,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "isp2", .sta_mask = BIT(13), .ctl_offs = 0x0334, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -197,6 +223,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "mdp", .sta_mask = BIT(19), .ctl_offs = 0x034c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -214,6 +242,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "venc", .sta_mask = BIT(17), .ctl_offs = 0x0344, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -231,6 +261,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "vdec", .sta_mask = BIT(15), .ctl_offs = 0x033c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -248,6 +280,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "vdec2", .sta_mask = BIT(16), .ctl_offs = 0x0340, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -255,6 +289,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam", .sta_mask = BIT(23), .ctl_offs = 0x035c, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), .bp_infracfg = { @@ -284,6 +320,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam_rawa", .sta_mask = BIT(24), .ctl_offs = 0x0360, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -291,6 +329,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam_rawb", .sta_mask = BIT(25), .ctl_offs = 0x0364, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -298,6 +338,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { .name = "cam_rawc", .sta_mask = BIT(26), .ctl_offs = 0x0368, + .pwr_sta_offs = 0x016c, + .pwr_sta2nd_offs = 0x0170, .sram_pdn_bits = GENMASK(8, 8), .sram_pdn_ack_bits = GENMASK(12, 12), }, @@ -306,8 +348,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { static const struct scpsys_soc_data mt8192_scpsys_data = { .domains_data = scpsys_domain_data_mt8192, .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), - .pwr_sta_offs = 0x016c, - .pwr_sta2nd_offs = 0x0170, }; #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 0af00efa0ef8..2689f02d7a41 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -60,10 +60,10 @@ static bool scpsys_domain_is_on(struct scpsys_domain *pd) struct scpsys *scpsys = pd->scpsys; u32 status, status2; - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status); + regmap_read(scpsys->base, pd->data->pwr_sta_offs, &status); status &= pd->data->sta_mask; - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2); + regmap_read(scpsys->base, pd->data->pwr_sta2nd_offs, &status2); status2 &= pd->data->sta_mask; /* A domain is on when both status bits are set. */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 21a4e113bbec..8b86ed22ca56 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -94,13 +94,13 @@ struct scpsys_domain_data { u8 caps; const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; + int pwr_sta_offs; + int pwr_sta2nd_offs; }; struct scpsys_soc_data { const struct scpsys_domain_data *domains_data; int num_domains; - int pwr_sta_offs; - int pwr_sta2nd_offs; }; #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data 2021-06-16 0:06 ` [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data Chun-Jie Chen @ 2021-06-25 9:12 ` Enric Balletbo i Serra 0 siblings, 0 replies; 12+ messages in thread From: Enric Balletbo i Serra @ 2021-06-25 9:12 UTC (permalink / raw) To: Chun-Jie Chen, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group Hi Chun-Jie Chen, Thank you for your patch. On 16/6/21 2:06, Chun-Jie Chen wrote: > MT8195 has more than 32 power domains so it needs > two set of pwr_sta and pwr_sta2nd registers, > so move the register offset from soc data into power domain data. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> PS: Please remove all the private mailing list from the Cc, or add in Bcc instead. > --- > drivers/soc/mediatek/mt8167-pm-domains.h | 16 +++++++-- > drivers/soc/mediatek/mt8173-pm-domains.h | 22 ++++++++++-- > drivers/soc/mediatek/mt8183-pm-domains.h | 32 +++++++++++++++-- > drivers/soc/mediatek/mt8192-pm-domains.h | 44 ++++++++++++++++++++++-- > drivers/soc/mediatek/mtk-pm-domains.c | 4 +-- > drivers/soc/mediatek/mtk-pm-domains.h | 4 +-- > 6 files changed, 110 insertions(+), 12 deletions(-) > > diff --git a/drivers/soc/mediatek/mt8167-pm-domains.h b/drivers/soc/mediatek/mt8167-pm-domains.h > index 15559ddf26e4..4d6c32759606 100644 > --- a/drivers/soc/mediatek/mt8167-pm-domains.h > +++ b/drivers/soc/mediatek/mt8167-pm-domains.h > @@ -18,6 +18,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "mm", > .sta_mask = PWR_STATUS_DISP, > .ctl_offs = SPM_DIS_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -30,6 +32,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "vdec", > .sta_mask = PWR_STATUS_VDEC, > .ctl_offs = SPM_VDE_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .caps = MTK_SCPD_ACTIVE_WAKEUP, > @@ -38,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "isp", > .sta_mask = PWR_STATUS_ISP, > .ctl_offs = SPM_ISP_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > .caps = MTK_SCPD_ACTIVE_WAKEUP, > @@ -46,6 +52,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "mfg_async", > .sta_mask = MT8167_PWR_STATUS_MFG_ASYNC, > .ctl_offs = SPM_MFG_ASYNC_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = 0, > .sram_pdn_ack_bits = 0, > .bp_infracfg = { > @@ -57,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "mfg_2d", > .sta_mask = MT8167_PWR_STATUS_MFG_2D, > .ctl_offs = SPM_MFG_2D_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > }, > @@ -64,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "mfg", > .sta_mask = PWR_STATUS_MFG, > .ctl_offs = SPM_MFG_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > }, > @@ -71,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > .name = "conn", > .sta_mask = PWR_STATUS_CONN, > .ctl_offs = SPM_CONN_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = 0, > .caps = MTK_SCPD_ACTIVE_WAKEUP, > @@ -85,8 +99,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8167[] = { > static const struct scpsys_soc_data mt8167_scpsys_data = { > .domains_data = scpsys_domain_data_mt8167, > .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8167), > - .pwr_sta_offs = SPM_PWR_STATUS, > - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > }; > > #endif /* __SOC_MEDIATEK_MT8167_PM_DOMAINS_H */ > diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h > index 654c717e5467..a4f58c2b44b1 100644 > --- a/drivers/soc/mediatek/mt8173-pm-domains.h > +++ b/drivers/soc/mediatek/mt8173-pm-domains.h > @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "vdec", > .sta_mask = PWR_STATUS_VDEC, > .ctl_offs = SPM_VDE_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "venc", > .sta_mask = PWR_STATUS_VENC, > .ctl_offs = SPM_VEN_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > }, > @@ -29,6 +33,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "isp", > .sta_mask = PWR_STATUS_ISP, > .ctl_offs = SPM_ISP_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > }, > @@ -36,6 +42,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "mm", > .sta_mask = PWR_STATUS_DISP, > .ctl_offs = SPM_DIS_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -47,6 +55,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "venc_lt", > .sta_mask = PWR_STATUS_VENC_LT, > .ctl_offs = SPM_VEN2_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > }, > @@ -54,6 +64,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "audio", > .sta_mask = PWR_STATUS_AUDIO, > .ctl_offs = SPM_AUDIO_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > }, > @@ -61,6 +73,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "usb", > .sta_mask = PWR_STATUS_USB, > .ctl_offs = SPM_USB_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > .caps = MTK_SCPD_ACTIVE_WAKEUP, > @@ -69,6 +83,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "mfg_async", > .sta_mask = PWR_STATUS_MFG_ASYNC, > .ctl_offs = SPM_MFG_ASYNC_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = 0, > }, > @@ -76,6 +92,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "mfg_2d", > .sta_mask = PWR_STATUS_MFG_2D, > .ctl_offs = SPM_MFG_2D_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > }, > @@ -83,6 +101,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > .name = "mfg", > .sta_mask = PWR_STATUS_MFG, > .ctl_offs = SPM_MFG_PWR_CON, > + .pwr_sta_offs = SPM_PWR_STATUS, > + .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > .sram_pdn_bits = GENMASK(13, 8), > .sram_pdn_ack_bits = GENMASK(21, 16), > .bp_infracfg = { > @@ -97,8 +117,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = { > static const struct scpsys_soc_data mt8173_scpsys_data = { > .domains_data = scpsys_domain_data_mt8173, > .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8173), > - .pwr_sta_offs = SPM_PWR_STATUS, > - .pwr_sta2nd_offs = SPM_PWR_STATUS_2ND, > }; > > #endif /* __SOC_MEDIATEK_MT8173_PM_DOMAINS_H */ > diff --git a/drivers/soc/mediatek/mt8183-pm-domains.h b/drivers/soc/mediatek/mt8183-pm-domains.h > index 98a9940d05fb..71b8757e552d 100644 > --- a/drivers/soc/mediatek/mt8183-pm-domains.h > +++ b/drivers/soc/mediatek/mt8183-pm-domains.h > @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "audio", > .sta_mask = PWR_STATUS_AUDIO, > .ctl_offs = 0x0314, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > }, > @@ -22,6 +24,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "conn", > .sta_mask = PWR_STATUS_CONN, > .ctl_offs = 0x032c, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = 0, > .sram_pdn_ack_bits = 0, > .bp_infracfg = { > @@ -33,6 +37,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "mfg_async", > .sta_mask = PWR_STATUS_MFG_ASYNC, > .ctl_offs = 0x0334, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = 0, > .sram_pdn_ack_bits = 0, > }, > @@ -40,6 +46,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "mfg", > .sta_mask = PWR_STATUS_MFG, > .ctl_offs = 0x0338, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .caps = MTK_SCPD_DOMAIN_SUPPLY, > @@ -48,6 +56,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "mfg_core0", > .sta_mask = BIT(7), > .ctl_offs = 0x034c, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -55,6 +65,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "mfg_core1", > .sta_mask = BIT(20), > .ctl_offs = 0x0310, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -62,6 +74,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "mfg_2d", > .sta_mask = PWR_STATUS_MFG_2D, > .ctl_offs = 0x0348, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -75,6 +89,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "disp", > .sta_mask = PWR_STATUS_DISP, > .ctl_offs = 0x030c, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -94,6 +110,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "cam", > .sta_mask = BIT(25), > .ctl_offs = 0x0344, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(9, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > .bp_infracfg = { > @@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "isp", > .sta_mask = PWR_STATUS_ISP, > .ctl_offs = 0x0308, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(9, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > .bp_infracfg = { > @@ -140,6 +160,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "vdec", > .sta_mask = BIT(31), > .ctl_offs = 0x0300, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_smi = { > @@ -153,6 +175,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "venc", > .sta_mask = PWR_STATUS_VENC, > .ctl_offs = 0x0304, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(15, 12), > .bp_smi = { > @@ -166,6 +190,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "vpu_top", > .sta_mask = BIT(26), > .ctl_offs = 0x0324, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -193,6 +219,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "vpu_core0", > .sta_mask = BIT(27), > .ctl_offs = 0x33c, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > .bp_infracfg = { > @@ -211,6 +239,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > .name = "vpu_core1", > .sta_mask = BIT(28), > .ctl_offs = 0x0340, > + .pwr_sta_offs = 0x0180, > + .pwr_sta2nd_offs = 0x0184, > .sram_pdn_bits = GENMASK(11, 8), > .sram_pdn_ack_bits = GENMASK(13, 12), > .bp_infracfg = { > @@ -230,8 +260,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8183[] = { > static const struct scpsys_soc_data mt8183_scpsys_data = { > .domains_data = scpsys_domain_data_mt8183, > .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8183), > - .pwr_sta_offs = 0x0180, > - .pwr_sta2nd_offs = 0x0184 > }; > > #endif /* __SOC_MEDIATEK_MT8183_PM_DOMAINS_H */ > diff --git a/drivers/soc/mediatek/mt8192-pm-domains.h b/drivers/soc/mediatek/mt8192-pm-domains.h > index 543dda70de01..558c4ee4784a 100644 > --- a/drivers/soc/mediatek/mt8192-pm-domains.h > +++ b/drivers/soc/mediatek/mt8192-pm-domains.h > @@ -15,6 +15,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "audio", > .sta_mask = BIT(21), > .ctl_offs = 0x0354, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -28,6 +30,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "conn", > .sta_mask = PWR_STATUS_CONN, > .ctl_offs = 0x0304, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = 0, > .sram_pdn_ack_bits = 0, > .bp_infracfg = { > @@ -50,6 +54,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg0", > .sta_mask = BIT(2), > .ctl_offs = 0x0308, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -57,6 +63,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg1", > .sta_mask = BIT(3), > .ctl_offs = 0x030c, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -82,6 +90,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg2", > .sta_mask = BIT(4), > .ctl_offs = 0x0310, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -89,6 +99,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg3", > .sta_mask = BIT(5), > .ctl_offs = 0x0314, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -96,6 +108,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg4", > .sta_mask = BIT(6), > .ctl_offs = 0x0318, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -103,6 +117,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg5", > .sta_mask = BIT(7), > .ctl_offs = 0x031c, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -110,6 +126,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mfg6", > .sta_mask = BIT(8), > .ctl_offs = 0x0320, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -117,6 +135,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "disp", > .sta_mask = BIT(20), > .ctl_offs = 0x0350, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -146,6 +166,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "ipe", > .sta_mask = BIT(14), > .ctl_offs = 0x0338, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -163,6 +185,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "isp", > .sta_mask = BIT(12), > .ctl_offs = 0x0330, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -180,6 +204,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "isp2", > .sta_mask = BIT(13), > .ctl_offs = 0x0334, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -197,6 +223,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "mdp", > .sta_mask = BIT(19), > .ctl_offs = 0x034c, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -214,6 +242,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "venc", > .sta_mask = BIT(17), > .ctl_offs = 0x0344, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -231,6 +261,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "vdec", > .sta_mask = BIT(15), > .ctl_offs = 0x033c, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -248,6 +280,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "vdec2", > .sta_mask = BIT(16), > .ctl_offs = 0x0340, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -255,6 +289,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "cam", > .sta_mask = BIT(23), > .ctl_offs = 0x035c, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > .bp_infracfg = { > @@ -284,6 +320,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "cam_rawa", > .sta_mask = BIT(24), > .ctl_offs = 0x0360, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -291,6 +329,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "cam_rawb", > .sta_mask = BIT(25), > .ctl_offs = 0x0364, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -298,6 +338,8 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > .name = "cam_rawc", > .sta_mask = BIT(26), > .ctl_offs = 0x0368, > + .pwr_sta_offs = 0x016c, > + .pwr_sta2nd_offs = 0x0170, > .sram_pdn_bits = GENMASK(8, 8), > .sram_pdn_ack_bits = GENMASK(12, 12), > }, > @@ -306,8 +348,6 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8192[] = { > static const struct scpsys_soc_data mt8192_scpsys_data = { > .domains_data = scpsys_domain_data_mt8192, > .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8192), > - .pwr_sta_offs = 0x016c, > - .pwr_sta2nd_offs = 0x0170, > }; > > #endif /* __SOC_MEDIATEK_MT8192_PM_DOMAINS_H */ > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c > index 0af00efa0ef8..2689f02d7a41 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.c > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > @@ -60,10 +60,10 @@ static bool scpsys_domain_is_on(struct scpsys_domain *pd) > struct scpsys *scpsys = pd->scpsys; > u32 status, status2; > > - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta_offs, &status); > + regmap_read(scpsys->base, pd->data->pwr_sta_offs, &status); > status &= pd->data->sta_mask; > > - regmap_read(scpsys->base, scpsys->soc_data->pwr_sta2nd_offs, &status2); > + regmap_read(scpsys->base, pd->data->pwr_sta2nd_offs, &status2); > status2 &= pd->data->sta_mask; > > /* A domain is on when both status bits are set. */ > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h > index 21a4e113bbec..8b86ed22ca56 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.h > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > @@ -94,13 +94,13 @@ struct scpsys_domain_data { > u8 caps; > const struct scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA]; > const struct scpsys_bus_prot_data bp_smi[SPM_MAX_BUS_PROT_DATA]; > + int pwr_sta_offs; > + int pwr_sta2nd_offs; > }; > > struct scpsys_soc_data { > const struct scpsys_domain_data *domains_data; > int num_domains; > - int pwr_sta_offs; > - int pwr_sta2nd_offs; > }; > > #endif /* __SOC_MEDIATEK_MTK_PM_DOMAINS_H */ > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains 2021-06-16 0:06 [RESEND PATCH v2 0/4] Mediatek MT8195 power domain support Chun-Jie Chen 2021-06-16 0:06 ` [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data Chun-Jie Chen @ 2021-06-16 0:06 ` Chun-Jie Chen 2021-06-24 20:57 ` Rob Herring 2021-06-25 8:58 ` Enric Balletbo i Serra 2021-06-16 0:06 ` [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 Chun-Jie Chen 2021-06-16 0:06 ` [RESEND PATCH v2 4/4] soc: mediatek: pm-domains: Remove unused macro Chun-Jie Chen 3 siblings, 2 replies; 12+ messages in thread From: Chun-Jie Chen @ 2021-06-16 0:06 UTC (permalink / raw) To: Enric Balletbo i Serra, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group, Chun-Jie Chen Add power domains dt-bindings for MT8195. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> --- .../power/mediatek,power-controller.yaml | 2 + include/dt-bindings/power/mt8195-power.h | 51 +++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 include/dt-bindings/power/mt8195-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index f234a756c193..d6ebd77d28a7 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8173-power-controller - mediatek,mt8183-power-controller - mediatek,mt8192-power-controller + - mediatek,mt8195-power-controller '#power-domain-cells': const: 1 @@ -64,6 +65,7 @@ patternProperties: "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. + "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. maxItems: 1 clocks: diff --git a/include/dt-bindings/power/mt8195-power.h b/include/dt-bindings/power/mt8195-power.h new file mode 100644 index 000000000000..43fd36e1f538 --- /dev/null +++ b/include/dt-bindings/power/mt8195-power.h @@ -0,0 +1,51 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H +#define _DT_BINDINGS_POWER_MT8195_POWER_H + +#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 +#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 +#define MT8195_POWER_DOMAIN_PCIE_PHY 2 +#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 +#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 +#define MT8195_POWER_DOMAIN_ETHER 5 +#define MT8195_POWER_DOMAIN_ADSP 6 +#define MT8195_POWER_DOMAIN_AUDIO 7 +#define MT8195_POWER_DOMAIN_AUDIO_ASRC 8 +#define MT8195_POWER_DOMAIN_NNA 9 +#define MT8195_POWER_DOMAIN_NNA0 10 +#define MT8195_POWER_DOMAIN_NNA1 11 +#define MT8195_POWER_DOMAIN_MFG0 12 +#define MT8195_POWER_DOMAIN_MFG1 13 +#define MT8195_POWER_DOMAIN_MFG2 14 +#define MT8195_POWER_DOMAIN_MFG3 15 +#define MT8195_POWER_DOMAIN_MFG4 16 +#define MT8195_POWER_DOMAIN_MFG5 17 +#define MT8195_POWER_DOMAIN_MFG6 18 +#define MT8195_POWER_DOMAIN_VPPSYS0 19 +#define MT8195_POWER_DOMAIN_VDOSYS0 20 +#define MT8195_POWER_DOMAIN_VPPSYS1 21 +#define MT8195_POWER_DOMAIN_VDOSYS1 22 +#define MT8195_POWER_DOMAIN_DP_TX 23 +#define MT8195_POWER_DOMAIN_EPD_TX 24 +#define MT8195_POWER_DOMAIN_HDMI_TX 25 +#define MT8195_POWER_DOMAIN_HDMI_RX 26 +#define MT8195_POWER_DOMAIN_WPESYS 27 +#define MT8195_POWER_DOMAIN_VDEC0 28 +#define MT8195_POWER_DOMAIN_VDEC1 29 +#define MT8195_POWER_DOMAIN_VDEC2 30 +#define MT8195_POWER_DOMAIN_VENC 31 +#define MT8195_POWER_DOMAIN_VENC_CORE1 32 +#define MT8195_POWER_DOMAIN_IMG 33 +#define MT8195_POWER_DOMAIN_DIP 34 +#define MT8195_POWER_DOMAIN_IPE 35 +#define MT8195_POWER_DOMAIN_CAM 36 +#define MT8195_POWER_DOMAIN_CAM_RAWA 37 +#define MT8195_POWER_DOMAIN_CAM_RAWB 38 +#define MT8195_POWER_DOMAIN_CAM_MRAW 39 + +#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */ -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains 2021-06-16 0:06 ` [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains Chun-Jie Chen @ 2021-06-24 20:57 ` Rob Herring 2021-06-25 8:58 ` Enric Balletbo i Serra 1 sibling, 0 replies; 12+ messages in thread From: Rob Herring @ 2021-06-24 20:57 UTC (permalink / raw) To: Chun-Jie Chen Cc: Nicolas Boichat, linux-arm-kernel, Rob Herring, Enric Balletbo i Serra, devicetree, Project_Global_Chrome_Upstream_Group, linux-mediatek, srv_heupstream, Matthias Brugger, linux-kernel On Wed, 16 Jun 2021 08:06:56 +0800, Chun-Jie Chen wrote: > Add power domains dt-bindings for MT8195. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- > .../power/mediatek,power-controller.yaml | 2 + > include/dt-bindings/power/mt8195-power.h | 51 +++++++++++++++++++ > 2 files changed, 53 insertions(+) > create mode 100644 include/dt-bindings/power/mt8195-power.h > Acked-by: Rob Herring <robh@kernel.org> _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains 2021-06-16 0:06 ` [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains Chun-Jie Chen 2021-06-24 20:57 ` Rob Herring @ 2021-06-25 8:58 ` Enric Balletbo i Serra 1 sibling, 0 replies; 12+ messages in thread From: Enric Balletbo i Serra @ 2021-06-25 8:58 UTC (permalink / raw) To: Chun-Jie Chen, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group Hi Chun-Jie Chen, Thank you for your patch. On 16/6/21 2:06, Chun-Jie Chen wrote: > Add power domains dt-bindings for MT8195. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > .../power/mediatek,power-controller.yaml | 2 + > include/dt-bindings/power/mt8195-power.h | 51 +++++++++++++++++++ > 2 files changed, 53 insertions(+) > create mode 100644 include/dt-bindings/power/mt8195-power.h > > diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > index f234a756c193..d6ebd77d28a7 100644 > --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml > @@ -27,6 +27,7 @@ properties: > - mediatek,mt8173-power-controller > - mediatek,mt8183-power-controller > - mediatek,mt8192-power-controller > + - mediatek,mt8195-power-controller > > '#power-domain-cells': > const: 1 > @@ -64,6 +65,7 @@ patternProperties: > "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain. > "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain. > "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain. > + "include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain. > maxItems: 1 > > clocks: > diff --git a/include/dt-bindings/power/mt8195-power.h b/include/dt-bindings/power/mt8195-power.h > new file mode 100644 > index 000000000000..43fd36e1f538 > --- /dev/null > +++ b/include/dt-bindings/power/mt8195-power.h > @@ -0,0 +1,51 @@ > +/* SPDX-License-Identifier: GPL-2.0 > + * > + * Copyright (c) 2021 MediaTek Inc. > + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> > + */ > + > +#ifndef _DT_BINDINGS_POWER_MT8195_POWER_H > +#define _DT_BINDINGS_POWER_MT8195_POWER_H > + > +#define MT8195_POWER_DOMAIN_PCIE_MAC_P0 0 > +#define MT8195_POWER_DOMAIN_PCIE_MAC_P1 1 > +#define MT8195_POWER_DOMAIN_PCIE_PHY 2 > +#define MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY 3 > +#define MT8195_POWER_DOMAIN_CSI_RX_TOP 4 > +#define MT8195_POWER_DOMAIN_ETHER 5 > +#define MT8195_POWER_DOMAIN_ADSP 6 > +#define MT8195_POWER_DOMAIN_AUDIO 7 > +#define MT8195_POWER_DOMAIN_AUDIO_ASRC 8 > +#define MT8195_POWER_DOMAIN_NNA 9 > +#define MT8195_POWER_DOMAIN_NNA0 10 > +#define MT8195_POWER_DOMAIN_NNA1 11 > +#define MT8195_POWER_DOMAIN_MFG0 12 > +#define MT8195_POWER_DOMAIN_MFG1 13 > +#define MT8195_POWER_DOMAIN_MFG2 14 > +#define MT8195_POWER_DOMAIN_MFG3 15 > +#define MT8195_POWER_DOMAIN_MFG4 16 > +#define MT8195_POWER_DOMAIN_MFG5 17 > +#define MT8195_POWER_DOMAIN_MFG6 18 > +#define MT8195_POWER_DOMAIN_VPPSYS0 19 > +#define MT8195_POWER_DOMAIN_VDOSYS0 20 > +#define MT8195_POWER_DOMAIN_VPPSYS1 21 > +#define MT8195_POWER_DOMAIN_VDOSYS1 22 > +#define MT8195_POWER_DOMAIN_DP_TX 23 > +#define MT8195_POWER_DOMAIN_EPD_TX 24 > +#define MT8195_POWER_DOMAIN_HDMI_TX 25 > +#define MT8195_POWER_DOMAIN_HDMI_RX 26 > +#define MT8195_POWER_DOMAIN_WPESYS 27 > +#define MT8195_POWER_DOMAIN_VDEC0 28 > +#define MT8195_POWER_DOMAIN_VDEC1 29 > +#define MT8195_POWER_DOMAIN_VDEC2 30 > +#define MT8195_POWER_DOMAIN_VENC 31 > +#define MT8195_POWER_DOMAIN_VENC_CORE1 32 > +#define MT8195_POWER_DOMAIN_IMG 33 > +#define MT8195_POWER_DOMAIN_DIP 34 > +#define MT8195_POWER_DOMAIN_IPE 35 > +#define MT8195_POWER_DOMAIN_CAM 36 > +#define MT8195_POWER_DOMAIN_CAM_RAWA 37 > +#define MT8195_POWER_DOMAIN_CAM_RAWB 38 > +#define MT8195_POWER_DOMAIN_CAM_MRAW 39 > + > +#endif /* _DT_BINDINGS_POWER_MT8195_POWER_H */ > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 2021-06-16 0:06 [RESEND PATCH v2 0/4] Mediatek MT8195 power domain support Chun-Jie Chen 2021-06-16 0:06 ` [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data Chun-Jie Chen 2021-06-16 0:06 ` [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains Chun-Jie Chen @ 2021-06-16 0:06 ` Chun-Jie Chen 2021-06-25 9:07 ` Enric Balletbo i Serra 2021-06-16 0:06 ` [RESEND PATCH v2 4/4] soc: mediatek: pm-domains: Remove unused macro Chun-Jie Chen 3 siblings, 1 reply; 12+ messages in thread From: Chun-Jie Chen @ 2021-06-16 0:06 UTC (permalink / raw) To: Enric Balletbo i Serra, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group, Chun-Jie Chen Add domain control data including bus protection data size change due to more protection steps in mt8195 and wakeup flag in power domain for wakeup control in suspend. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> --- drivers/soc/mediatek/mt8195-pm-domains.h | 738 +++++++++++++++++++++++ drivers/soc/mediatek/mtk-pm-domains.c | 8 + drivers/soc/mediatek/mtk-pm-domains.h | 2 +- include/linux/soc/mediatek/infracfg.h | 103 ++++ 4 files changed, 850 insertions(+), 1 deletion(-) create mode 100644 drivers/soc/mediatek/mt8195-pm-domains.h diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediatek/mt8195-pm-domains.h new file mode 100644 index 000000000000..54bb7af8e9a3 --- /dev/null +++ b/drivers/soc/mediatek/mt8195-pm-domains.h @@ -0,0 +1,738 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021 MediaTek Inc. + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> + */ + +#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H +#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H + +#include "mtk-pm-domains.h" +#include <dt-bindings/power/mt8195-power.h> + +/* + * MT8195 power domain support + */ + +static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { + [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { + .name = "pcie_mac_p0", + .sta_mask = BIT(11), + .ctl_offs = 0x328, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, + MT8195_TOP_AXI_PROT_EN_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + }, + [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { + .name = "pcie_mac_p1", + .sta_mask = BIT(12), + .ctl_offs = 0x32C, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, + MT8195_TOP_AXI_PROT_EN_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + }, + [MT8195_POWER_DOMAIN_PCIE_PHY] = { + .name = "pcie_phy", + .sta_mask = BIT(13), + .ctl_offs = 0x330, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { + .name = "ssusb_pcie_phy", + .sta_mask = BIT(14), + .ctl_offs = 0x334, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { + .name = "csi_rx_top", + .sta_mask = BIT(18), + .ctl_offs = 0x3C4, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_ETHER] = { + .name = "ether", + .sta_mask = BIT(3), + .ctl_offs = 0x344, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_ADSP] = { + .name = "adsp", + .sta_mask = BIT(10), + .ctl_offs = 0x360, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + }, + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_AUDIO] = { + .name = "audio", + .sta_mask = BIT(8), + .ctl_offs = 0x358, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_AUDIO_ASRC] = { + .name = "audio_asrc", + .sta_mask = BIT(9), + .ctl_offs = 0x35C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_NNA] = { + .name = "nna", + .sta_mask = BIT(17), + .ctl_offs = 0x3C0, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA_2ND, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA, + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_NNA0] = { + .name = "nna0", + .sta_mask = BIT(15), + .ctl_offs = 0x3B8, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA0, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0, + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_NNA1] = { + .name = "nna1", + .sta_mask = BIT(16), + .ctl_offs = 0x3BC, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA1, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA1, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1, + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG0] = { + .name = "mfg0", + .sta_mask = BIT(1), + .ctl_offs = 0x300, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG1] = { + .name = "mfg1", + .sta_mask = BIT(2), + .ctl_offs = 0x304, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, + MT8195_TOP_AXI_PROT_EN_1_SET, + MT8195_TOP_AXI_PROT_EN_1_CLR, + MT8195_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG2] = { + .name = "mfg2", + .sta_mask = BIT(3), + .ctl_offs = 0x308, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG3] = { + .name = "mfg3", + .sta_mask = BIT(4), + .ctl_offs = 0x30C, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG4] = { + .name = "mfg4", + .sta_mask = BIT(5), + .ctl_offs = 0x310, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG5] = { + .name = "mfg5", + .sta_mask = BIT(6), + .ctl_offs = 0x314, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_MFG6] = { + .name = "mfg6", + .sta_mask = BIT(7), + .ctl_offs = 0x318, + .pwr_sta_offs = 0x174, + .pwr_sta2nd_offs = 0x178, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VPPSYS0] = { + .name = "vppsys0", + .sta_mask = BIT(11), + .ctl_offs = 0x364, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VDOSYS0] = { + .name = "vdosys0", + .sta_mask = BIT(13), + .ctl_offs = 0x36C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_SET, + MT8195_TOP_AXI_PROT_EN_CLR, + MT8195_TOP_AXI_PROT_EN_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VPPSYS1] = { + .name = "vppsys1", + .sta_mask = BIT(12), + .ctl_offs = 0x368, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VDOSYS1] = { + .name = "vdosys1", + .sta_mask = BIT(14), + .ctl_offs = 0x370, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_DP_TX] = { + .name = "dp_tx", + .sta_mask = BIT(16), + .ctl_offs = 0x378, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_EPD_TX] = { + .name = "epd_tx", + .sta_mask = BIT(17), + .ctl_offs = 0x37C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_HDMI_TX] = { + .name = "hdmi_tx", + .sta_mask = BIT(18), + .ctl_offs = 0x380, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_HDMI_RX] = { + .name = "hdmi_rx", + .sta_mask = BIT(19), + .ctl_offs = 0x384, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, + }, + [MT8195_POWER_DOMAIN_WPESYS] = { + .name = "wpesys", + .sta_mask = BIT(15), + .ctl_offs = 0x374, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + }, + [MT8195_POWER_DOMAIN_VDEC0] = { + .name = "vdec0", + .sta_mask = BIT(20), + .ctl_offs = 0x388, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VDEC1] = { + .name = "vdec1", + .sta_mask = BIT(21), + .ctl_offs = 0x38C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VDEC2] = { + .name = "vdec2", + .sta_mask = BIT(22), + .ctl_offs = 0x390, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VENC] = { + .name = "venc", + .sta_mask = BIT(23), + .ctl_offs = 0x394, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_VENC_CORE1] = { + .name = "venc_core1", + .sta_mask = BIT(24), + .ctl_offs = 0x398, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_IMG] = { + .name = "img", + .sta_mask = BIT(29), + .ctl_offs = 0x3AC, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IMG, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_DIP] = { + .name = "dip", + .sta_mask = BIT(30), + .ctl_offs = 0x3B0, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_IPE] = { + .name = "ipe", + .sta_mask = BIT(31), + .ctl_offs = 0x3B4, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM] = { + .name = "cam", + .sta_mask = BIT(25), + .ctl_offs = 0x39C, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .bp_infracfg = { + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, + MT8195_TOP_AXI_PROT_EN_2_SET, + MT8195_TOP_AXI_PROT_EN_2_CLR, + MT8195_TOP_AXI_PROT_EN_2_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, + MT8195_TOP_AXI_PROT_EN_1_SET, + MT8195_TOP_AXI_PROT_EN_1_CLR, + MT8195_TOP_AXI_PROT_EN_1_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, + MT8195_TOP_AXI_PROT_EN_MM_SET, + MT8195_TOP_AXI_PROT_EN_MM_CLR, + MT8195_TOP_AXI_PROT_EN_MM_STA1), + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, + MT8195_TOP_AXI_PROT_EN_MM_2_SET, + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), + }, + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM_RAWA] = { + .name = "cam_rawa", + .sta_mask = BIT(26), + .ctl_offs = 0x3A0, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM_RAWB] = { + .name = "cam_rawb", + .sta_mask = BIT(27), + .ctl_offs = 0x3A4, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, + [MT8195_POWER_DOMAIN_CAM_MRAW] = { + .name = "cam_mraw", + .sta_mask = BIT(28), + .ctl_offs = 0x3A8, + .pwr_sta_offs = 0x16c, + .pwr_sta2nd_offs = 0x170, + .sram_pdn_bits = GENMASK(8, 8), + .sram_pdn_ack_bits = GENMASK(12, 12), + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, + }, +}; + +static const struct scpsys_soc_data mt8195_scpsys_data = { + .domains_data = scpsys_domain_data_mt8195, + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), +}; + +#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c index 2689f02d7a41..d705860b47a7 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.c +++ b/drivers/soc/mediatek/mtk-pm-domains.c @@ -20,6 +20,7 @@ #include "mt8173-pm-domains.h" #include "mt8183-pm-domains.h" #include "mt8192-pm-domains.h" +#include "mt8195-pm-domains.h" #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -446,6 +447,9 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no pd->genpd.power_off = scpsys_power_off; pd->genpd.power_on = scpsys_power_on; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP)) + pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; + if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) pm_genpd_init(&pd->genpd, NULL, true); else @@ -576,6 +580,10 @@ static const struct of_device_id scpsys_of_match[] = { .compatible = "mediatek,mt8192-power-controller", .data = &mt8192_scpsys_data, }, + { + .compatible = "mediatek,mt8195-power-controller", + .data = &mt8195_scpsys_data, + }, { } }; diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index 8b86ed22ca56..caaa38100093 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -37,7 +37,7 @@ #define PWR_STATUS_AUDIO BIT(24) #define PWR_STATUS_USB BIT(25) -#define SPM_MAX_BUS_PROT_DATA 5 +#define SPM_MAX_BUS_PROT_DATA 6 #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ .bus_prot_mask = (_mask), \ diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h index 4615a228da51..3e90fb9b926a 100644 --- a/include/linux/soc/mediatek/infracfg.h +++ b/include/linux/soc/mediatek/infracfg.h @@ -2,6 +2,109 @@ #ifndef __SOC_MEDIATEK_INFRACFG_H #define __SOC_MEDIATEK_INFRACFG_H +#define MT8195_TOP_AXI_PROT_EN_STA1 0x228 +#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 +#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 +#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 +#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 +#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac +#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 +#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 +#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec +#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 +#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 +#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 +#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 +#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 +#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 +#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc +#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 +#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 + +#define MT8195_TOP_AXI_PROT_EN_NNA0 BIT(1) +#define MT8195_TOP_AXI_PROT_EN_NNA1 BIT(2) +#define MT8195_TOP_AXI_PROT_EN_NNA GENMASK(2, 1) +#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) +#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) +#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21) +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) +#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19) +#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) +#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) +#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5) +#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC (BIT(8) | BIT(17)) +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11)) +#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14)) +#define MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND BIT(19) +#define MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND BIT(20) +#define MT8195_TOP_AXI_PROT_EN_2_NNA_2ND GENMASK(20, 19) +#define MT8195_TOP_AXI_PROT_EN_2_NNA0 BIT(21) +#define MT8195_TOP_AXI_PROT_EN_2_NNA1 BIT(22) +#define MT8195_TOP_AXI_PROT_EN_2_NNA GENMASK(22, 21) +#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4)) +#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) +#define MT8195_TOP_AXI_PROT_EN_MM_IMG (BIT(1) | BIT(3)) +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0 (GENMASK(2, 0) | GENMASK(8, 6) | \ + GENMASK(12, 10) | GENMASK(21, 19) | \ + BIT(31)) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 (GENMASK(5, 3) | BIT(9) | \ + GENMASK(14, 13) | GENMASK(21, 17) | \ + BIT(30)) +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5) +#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11)) +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12)) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) +#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) +#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) +#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND GENMASK(29, 22) +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(7, 0) | GENMASK(18, 11)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 (GENMASK(9, 8) | GENMASK(22, 21) | BIT(24)) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) +#define MT8195_TOP_AXI_PROT_EN_MM_2_IMG BIT(16) +#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0 BIT(23) +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28)) +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29)) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19)) +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0 BIT(25) +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1 BIT(26) +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA GENMASK(26, 25) + #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 2021-06-16 0:06 ` [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 Chun-Jie Chen @ 2021-06-25 9:07 ` Enric Balletbo i Serra 2021-06-28 13:15 ` Chun-Jie Chen 0 siblings, 1 reply; 12+ messages in thread From: Enric Balletbo i Serra @ 2021-06-25 9:07 UTC (permalink / raw) To: Chun-Jie Chen, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group Hi Chun-Jie Chen, Thank you for your patch. On 16/6/21 2:06, Chun-Jie Chen wrote: > Add domain control data including bus protection data size > change due to more protection steps in mt8195 and wakeup flag > in power domain for wakeup control in suspend. > The wakeup flag is used for different SoCs apart from mt8195, isn't it? I'd add this on a separate patch so it is not dependent on the mt8195 changes. This will also make more clear that is not really a mt8195 thing and can help in case at some point we need to run a bisection because something is broken on another SoC. Thanks, Enric > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > --- > drivers/soc/mediatek/mt8195-pm-domains.h | 738 +++++++++++++++++++++++ > drivers/soc/mediatek/mtk-pm-domains.c | 8 + > drivers/soc/mediatek/mtk-pm-domains.h | 2 +- > include/linux/soc/mediatek/infracfg.h | 103 ++++ > 4 files changed, 850 insertions(+), 1 deletion(-) > create mode 100644 drivers/soc/mediatek/mt8195-pm-domains.h > > diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h b/drivers/soc/mediatek/mt8195-pm-domains.h > new file mode 100644 > index 000000000000..54bb7af8e9a3 > --- /dev/null > +++ b/drivers/soc/mediatek/mt8195-pm-domains.h > @@ -0,0 +1,738 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) 2021 MediaTek Inc. > + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> > + */ > + > +#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > +#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > + > +#include "mtk-pm-domains.h" > +#include <dt-bindings/power/mt8195-power.h> > + > +/* > + * MT8195 power domain support > + */ > + > +static const struct scpsys_domain_data scpsys_domain_data_mt8195[] = { > + [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { > + .name = "pcie_mac_p0", > + .sta_mask = BIT(11), > + .ctl_offs = 0x328, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0, > + MT8195_TOP_AXI_PROT_EN_VDNR_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { > + .name = "pcie_mac_p1", > + .sta_mask = BIT(12), > + .ctl_offs = 0x32C, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1, > + MT8195_TOP_AXI_PROT_EN_VDNR_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_PCIE_PHY] = { > + .name = "pcie_phy", > + .sta_mask = BIT(13), > + .ctl_offs = 0x330, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { > + .name = "ssusb_pcie_phy", > + .sta_mask = BIT(14), > + .ctl_offs = 0x334, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { > + .name = "csi_rx_top", > + .sta_mask = BIT(18), > + .ctl_offs = 0x3C4, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_ETHER] = { > + .name = "ether", > + .sta_mask = BIT(3), > + .ctl_offs = 0x344, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8195_POWER_DOMAIN_ADSP] = { > + .name = "adsp", > + .sta_mask = BIT(10), > + .ctl_offs = 0x360, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + }, > + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8195_POWER_DOMAIN_AUDIO] = { > + .name = "audio", > + .sta_mask = BIT(8), > + .ctl_offs = 0x358, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_AUDIO_ASRC] = { > + .name = "audio_asrc", > + .sta_mask = BIT(9), > + .ctl_offs = 0x35C, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_NNA] = { > + .name = "nna", > + .sta_mask = BIT(17), > + .ctl_offs = 0x3C0, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA_2ND, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_NNA0] = { > + .name = "nna0", > + .sta_mask = BIT(15), > + .ctl_offs = 0x3B8, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA0, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA0, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_NNA1] = { > + .name = "nna1", > + .sta_mask = BIT(16), > + .ctl_offs = 0x3BC, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA1, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA1, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG0] = { > + .name = "mfg0", > + .sta_mask = BIT(1), > + .ctl_offs = 0x300, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG1] = { > + .name = "mfg1", > + .sta_mask = BIT(2), > + .ctl_offs = 0x304, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, > + MT8195_TOP_AXI_PROT_EN_1_SET, > + MT8195_TOP_AXI_PROT_EN_1_CLR, > + MT8195_TOP_AXI_PROT_EN_1_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG2] = { > + .name = "mfg2", > + .sta_mask = BIT(3), > + .ctl_offs = 0x308, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG3] = { > + .name = "mfg3", > + .sta_mask = BIT(4), > + .ctl_offs = 0x30C, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG4] = { > + .name = "mfg4", > + .sta_mask = BIT(5), > + .ctl_offs = 0x310, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG5] = { > + .name = "mfg5", > + .sta_mask = BIT(6), > + .ctl_offs = 0x314, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_MFG6] = { > + .name = "mfg6", > + .sta_mask = BIT(7), > + .ctl_offs = 0x318, > + .pwr_sta_offs = 0x174, > + .pwr_sta2nd_offs = 0x178, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_VPPSYS0] = { > + .name = "vppsys0", > + .sta_mask = BIT(11), > + .ctl_offs = 0x364, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_VDOSYS0] = { > + .name = "vdosys0", > + .sta_mask = BIT(13), > + .ctl_offs = 0x36C, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, > + MT8195_TOP_AXI_PROT_EN_SET, > + MT8195_TOP_AXI_PROT_EN_CLR, > + MT8195_TOP_AXI_PROT_EN_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR, > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_VPPSYS1] = { > + .name = "vppsys1", > + .sta_mask = BIT(12), > + .ctl_offs = 0x368, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_VDOSYS1] = { > + .name = "vdosys1", > + .sta_mask = BIT(14), > + .ctl_offs = 0x370, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_DP_TX] = { > + .name = "dp_tx", > + .sta_mask = BIT(16), > + .ctl_offs = 0x378, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_EPD_TX] = { > + .name = "epd_tx", > + .sta_mask = BIT(17), > + .ctl_offs = 0x37C, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_HDMI_TX] = { > + .name = "hdmi_tx", > + .sta_mask = BIT(18), > + .ctl_offs = 0x380, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8195_POWER_DOMAIN_HDMI_RX] = { > + .name = "hdmi_rx", > + .sta_mask = BIT(19), > + .ctl_offs = 0x384, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP, > + }, > + [MT8195_POWER_DOMAIN_WPESYS] = { > + .name = "wpesys", > + .sta_mask = BIT(15), > + .ctl_offs = 0x374, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + }, > + [MT8195_POWER_DOMAIN_VDEC0] = { > + .name = "vdec0", > + .sta_mask = BIT(20), > + .ctl_offs = 0x388, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_VDEC1] = { > + .name = "vdec1", > + .sta_mask = BIT(21), > + .ctl_offs = 0x38C, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_VDEC2] = { > + .name = "vdec2", > + .sta_mask = BIT(22), > + .ctl_offs = 0x390, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_VENC] = { > + .name = "venc", > + .sta_mask = BIT(23), > + .ctl_offs = 0x394, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_VENC_CORE1] = { > + .name = "venc_core1", > + .sta_mask = BIT(24), > + .ctl_offs = 0x398, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_IMG] = { > + .name = "img", > + .sta_mask = BIT(29), > + .ctl_offs = 0x3AC, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IMG, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_DIP] = { > + .name = "dip", > + .sta_mask = BIT(30), > + .ctl_offs = 0x3B0, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_IPE] = { > + .name = "ipe", > + .sta_mask = BIT(31), > + .ctl_offs = 0x3B4, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_CAM] = { > + .name = "cam", > + .sta_mask = BIT(25), > + .ctl_offs = 0x39C, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .bp_infracfg = { > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, > + MT8195_TOP_AXI_PROT_EN_2_SET, > + MT8195_TOP_AXI_PROT_EN_2_CLR, > + MT8195_TOP_AXI_PROT_EN_2_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, > + MT8195_TOP_AXI_PROT_EN_1_SET, > + MT8195_TOP_AXI_PROT_EN_1_CLR, > + MT8195_TOP_AXI_PROT_EN_1_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, > + MT8195_TOP_AXI_PROT_EN_MM_SET, > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > + }, > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_CAM_RAWA] = { > + .name = "cam_rawa", > + .sta_mask = BIT(26), > + .ctl_offs = 0x3A0, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_CAM_RAWB] = { > + .name = "cam_rawb", > + .sta_mask = BIT(27), > + .ctl_offs = 0x3A4, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > + [MT8195_POWER_DOMAIN_CAM_MRAW] = { > + .name = "cam_mraw", > + .sta_mask = BIT(28), > + .ctl_offs = 0x3A8, > + .pwr_sta_offs = 0x16c, > + .pwr_sta2nd_offs = 0x170, > + .sram_pdn_bits = GENMASK(8, 8), > + .sram_pdn_ack_bits = GENMASK(12, 12), > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > + }, > +}; > + > +static const struct scpsys_soc_data mt8195_scpsys_data = { > + .domains_data = scpsys_domain_data_mt8195, > + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), > +}; > + > +#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c > index 2689f02d7a41..d705860b47a7 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.c > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > @@ -20,6 +20,7 @@ > #include "mt8173-pm-domains.h" > #include "mt8183-pm-domains.h" > #include "mt8192-pm-domains.h" > +#include "mt8195-pm-domains.h" > > #define MTK_POLL_DELAY_US 10 > #define MTK_POLL_TIMEOUT USEC_PER_SEC > @@ -446,6 +447,9 @@ generic_pm_domain *scpsys_add_one_domain(struct scpsys *scpsys, struct device_no > pd->genpd.power_off = scpsys_power_off; > pd->genpd.power_on = scpsys_power_on; > > + if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP)) > + pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; > + > if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) > pm_genpd_init(&pd->genpd, NULL, true); > else > @@ -576,6 +580,10 @@ static const struct of_device_id scpsys_of_match[] = { > .compatible = "mediatek,mt8192-power-controller", > .data = &mt8192_scpsys_data, > }, > + { > + .compatible = "mediatek,mt8195-power-controller", > + .data = &mt8195_scpsys_data, > + }, > { } > }; > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h > index 8b86ed22ca56..caaa38100093 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.h > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > @@ -37,7 +37,7 @@ > #define PWR_STATUS_AUDIO BIT(24) > #define PWR_STATUS_USB BIT(25) > > -#define SPM_MAX_BUS_PROT_DATA 5 > +#define SPM_MAX_BUS_PROT_DATA 6 > > #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { \ > .bus_prot_mask = (_mask), \ > diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h > index 4615a228da51..3e90fb9b926a 100644 > --- a/include/linux/soc/mediatek/infracfg.h > +++ b/include/linux/soc/mediatek/infracfg.h > @@ -2,6 +2,109 @@ > #ifndef __SOC_MEDIATEK_INFRACFG_H > #define __SOC_MEDIATEK_INFRACFG_H > > +#define MT8195_TOP_AXI_PROT_EN_STA1 0x228 > +#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 > +#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 > +#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 > +#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 > +#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac > +#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 > +#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 > +#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec > +#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 > +#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 > +#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 > +#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc > +#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 > +#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 > + > +#define MT8195_TOP_AXI_PROT_EN_NNA0 BIT(1) > +#define MT8195_TOP_AXI_PROT_EN_NNA1 BIT(2) > +#define MT8195_TOP_AXI_PROT_EN_NNA GENMASK(2, 1) > +#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) > +#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) > +#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK(22, 21) > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) > +#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK(20, 19) > +#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) > +#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5) > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC (BIT(8) | BIT(17)) > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) | BIT(11)) > +#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12) | GENMASK(16, 14)) > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND BIT(19) > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND BIT(20) > +#define MT8195_TOP_AXI_PROT_EN_2_NNA_2ND GENMASK(20, 19) > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0 BIT(21) > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1 BIT(22) > +#define MT8195_TOP_AXI_PROT_EN_2_NNA GENMASK(22, 21) > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4)) > +#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG (BIT(1) | BIT(3)) > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0 (GENMASK(2, 0) | GENMASK(8, 6) | \ > + GENMASK(12, 10) | GENMASK(21, 19) | \ > + BIT(31)) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 (GENMASK(5, 3) | BIT(9) | \ > + GENMASK(14, 13) | GENMASK(21, 17) | \ > + BIT(30)) > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5) > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) | BIT(11)) > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10) | BIT(12)) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) > +#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND GENMASK(29, 22) > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(7, 0) | GENMASK(18, 11)) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) | BIT(15)) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) | BIT(17)) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMASK(7, 6) | BIT(18)) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 (GENMASK(9, 8) | GENMASK(22, 21) | BIT(24)) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_IMG BIT(16) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0 BIT(23) > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11) | BIT(28)) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12) | BIT(29)) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | BIT(19)) > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0 BIT(25) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1 BIT(26) > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA GENMASK(26, 25) > + > #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 > #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 > #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 2021-06-25 9:07 ` Enric Balletbo i Serra @ 2021-06-28 13:15 ` Chun-Jie Chen 2021-06-30 7:40 ` Matthias Brugger 0 siblings, 1 reply; 12+ messages in thread From: Chun-Jie Chen @ 2021-06-28 13:15 UTC (permalink / raw) To: Enric Balletbo i Serra, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group On Fri, 2021-06-25 at 11:07 +0200, Enric Balletbo i Serra wrote: > Hi Chun-Jie Chen, > > Thank you for your patch. > > On 16/6/21 2:06, Chun-Jie Chen wrote: > > Add domain control data including bus protection data size > > change due to more protection steps in mt8195 and wakeup flag > > in power domain for wakeup control in suspend. > > > > The wakeup flag is used for different SoCs apart from mt8195, isn't > it? I'd add > this on a separate patch so it is not dependent on the mt8195 > changes. This will > also make more clear that is not really a mt8195 thing and can help > in case at > some point we need to run a bisection because something is broken on > another SoC. > > Thanks, > Enric > > Yes, this wakeup flag also is used by other SoC like MT8173, but missing this flag in new power domain driver(mtk-pm-domain.c). I will separate this modification of wakeup flag from this patch but put it in same series. Best Regards, Chun-Jie > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > --- > > drivers/soc/mediatek/mt8195-pm-domains.h | 738 > > +++++++++++++++++++++++ > > drivers/soc/mediatek/mtk-pm-domains.c | 8 + > > drivers/soc/mediatek/mtk-pm-domains.h | 2 +- > > include/linux/soc/mediatek/infracfg.h | 103 ++++ > > 4 files changed, 850 insertions(+), 1 deletion(-) > > create mode 100644 drivers/soc/mediatek/mt8195-pm-domains.h > > > > diff --git a/drivers/soc/mediatek/mt8195-pm-domains.h > > b/drivers/soc/mediatek/mt8195-pm-domains.h > > new file mode 100644 > > index 000000000000..54bb7af8e9a3 > > --- /dev/null > > +++ b/drivers/soc/mediatek/mt8195-pm-domains.h > > @@ -0,0 +1,738 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +/* > > + * Copyright (c) 2021 MediaTek Inc. > > + * Author: Chun-Jie Chen <chun-jie.chen@mediatek.com> > > + */ > > + > > +#ifndef __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > > +#define __SOC_MEDIATEK_MT8195_PM_DOMAINS_H > > + > > +#include "mtk-pm-domains.h" > > +#include <dt-bindings/power/mt8195-power.h> > > + > > +/* > > + * MT8195 power domain support > > + */ > > + > > +static const struct scpsys_domain_data scpsys_domain_data_mt8195[] > > = { > > + [MT8195_POWER_DOMAIN_PCIE_MAC_P0] = { > > + .name = "pcie_mac_p0", > > + .sta_mask = BIT(11), > > + .ctl_offs = 0x328, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MA > > C_P0, > > + MT8195_TOP_AXI_PROT_EN_VDNR_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_ > > MAC_P0, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1) > > , > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_PCIE_MAC_P1] = { > > + .name = "pcie_mac_p1", > > + .sta_mask = BIT(12), > > + .ctl_offs = 0x32C, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MA > > C_P1, > > + MT8195_TOP_AXI_PROT_EN_VDNR_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_ > > MAC_P1, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1) > > , > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_PCIE_PHY] = { > > + .name = "pcie_phy", > > + .sta_mask = BIT(13), > > + .ctl_offs = 0x330, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > > + }, > > + [MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY] = { > > + .name = "ssusb_pcie_phy", > > + .sta_mask = BIT(14), > > + .ctl_offs = 0x334, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > > + }, > > + [MT8195_POWER_DOMAIN_CSI_RX_TOP] = { > > + .name = "csi_rx_top", > > + .sta_mask = BIT(18), > > + .ctl_offs = 0x3C4, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_ETHER] = { > > + .name = "ether", > > + .sta_mask = BIT(3), > > + .ctl_offs = 0x344, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_ACTIVE_WAKEUP, > > + }, > > + [MT8195_POWER_DOMAIN_ADSP] = { > > + .name = "adsp", > > + .sta_mask = BIT(10), > > + .ctl_offs = 0x360, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_ADSP, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + }, > > + .caps = MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP, > > + }, > > + [MT8195_POWER_DOMAIN_AUDIO] = { > > + .name = "audio", > > + .sta_mask = BIT(8), > > + .ctl_offs = 0x358, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_AUDIO_ASRC] = { > > + .name = "audio_asrc", > > + .sta_mask = BIT(9), > > + .ctl_offs = 0x35C, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC > > , > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_NNA] = { > > + .name = "nna", > > + .sta_mask = BIT(17), > > + .ctl_offs = 0x3C0, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA_2ND, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1) > > , > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_NNA0] = { > > + .name = "nna0", > > + .sta_mask = BIT(15), > > + .ctl_offs = 0x3B8, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA0, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA0, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1) > > , > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_NNA1] = { > > + .name = "nna1", > > + .sta_mask = BIT(16), > > + .ctl_offs = 0x3BC, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_NNA1, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA1, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1) > > , > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG0] = { > > + .name = "mfg0", > > + .sta_mask = BIT(1), > > + .ctl_offs = 0x300, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG1] = { > > + .name = "mfg1", > > + .sta_mask = BIT(2), > > + .ctl_offs = 0x304, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_MFG1, > > + MT8195_TOP_AXI_PROT_EN_1_SET, > > + MT8195_TOP_AXI_PROT_EN_1_CLR, > > + MT8195_TOP_AXI_PROT_EN_1_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MFG1_2ND, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_MFG1, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_SET, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_CLR, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG2] = { > > + .name = "mfg2", > > + .sta_mask = BIT(3), > > + .ctl_offs = 0x308, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG3] = { > > + .name = "mfg3", > > + .sta_mask = BIT(4), > > + .ctl_offs = 0x30C, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG4] = { > > + .name = "mfg4", > > + .sta_mask = BIT(5), > > + .ctl_offs = 0x310, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG5] = { > > + .name = "mfg5", > > + .sta_mask = BIT(6), > > + .ctl_offs = 0x314, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_MFG6] = { > > + .name = "mfg6", > > + .sta_mask = BIT(7), > > + .ctl_offs = 0x318, > > + .pwr_sta_offs = 0x174, > > + .pwr_sta2nd_offs = 0x178, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_VPPSYS0] = { > > + .name = "vppsys0", > > + .sta_mask = BIT(11), > > + .ctl_offs = 0x364, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_VPPSY > > S0, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_2_VPP > > SYS0, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 > > _2ND, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_VPPSYS0, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_SET, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_CLR, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_VDOSYS0] = { > > + .name = "vdosys0", > > + .sta_mask = BIT(13), > > + .ctl_offs = 0x36C, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_VDOSY > > S0, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR_IGN(MT8195_TOP_AXI_PROT_EN_MM_2_VDO > > SYS0, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDOSYS0, > > + MT8195_TOP_AXI_PROT_EN_SET, > > + MT8195_TOP_AXI_PROT_EN_CLR, > > + MT8195_TOP_AXI_PROT_EN_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2 > > ND, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_VDOSYS0, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_SET, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_CLR, > > + MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VD > > NR_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_VPPSYS1] = { > > + .name = "vppsys1", > > + .sta_mask = BIT(12), > > + .ctl_offs = 0x368, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2 > > ND, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 > > , > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_VDOSYS1] = { > > + .name = "vdosys1", > > + .sta_mask = BIT(14), > > + .ctl_offs = 0x370, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2 > > ND, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 > > , > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_DP_TX] = { > > + .name = "dp_tx", > > + .sta_mask = BIT(16), > > + .ctl_offs = 0x378, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX > > , > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1) > > , > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_EPD_TX] = { > > + .name = "epd_tx", > > + .sta_mask = BIT(17), > > + .ctl_offs = 0x37C, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_T > > X, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_SET, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR, > > + MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1) > > , > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_HDMI_TX] = { > > + .name = "hdmi_tx", > > + .sta_mask = BIT(18), > > + .ctl_offs = 0x380, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | > > MTK_SCPD_ACTIVE_WAKEUP, > > + }, > > + [MT8195_POWER_DOMAIN_HDMI_RX] = { > > + .name = "hdmi_rx", > > + .sta_mask = BIT(19), > > + .ctl_offs = 0x384, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | > > MTK_SCPD_ACTIVE_WAKEUP, > > + }, > > + [MT8195_POWER_DOMAIN_WPESYS] = { > > + .name = "wpesys", > > + .sta_mask = BIT(15), > > + .ctl_offs = 0x374, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_WPESYS, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_ > > 2ND, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + }, > > + [MT8195_POWER_DOMAIN_VDEC0] = { > > + .name = "vdec0", > > + .sta_mask = BIT(20), > > + .ctl_offs = 0x388, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND > > , > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2 > > ND, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_VDEC1] = { > > + .name = "vdec1", > > + .sta_mask = BIT(21), > > + .ctl_offs = 0x38C, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND > > , > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_VDEC2] = { > > + .name = "vdec2", > > + .sta_mask = BIT(22), > > + .ctl_offs = 0x390, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2 > > ND, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_VENC] = { > > + .name = "venc", > > + .sta_mask = BIT(23), > > + .ctl_offs = 0x394, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_VENC_CORE1] = { > > + .name = "venc_core1", > > + .sta_mask = BIT(24), > > + .ctl_offs = 0x398, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE > > 1, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CO > > RE1, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_IMG] = { > > + .name = "img", > > + .sta_mask = BIT(29), > > + .ctl_offs = 0x3AC, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IMG, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_DIP] = { > > + .name = "dip", > > + .sta_mask = BIT(30), > > + .ctl_offs = 0x3B0, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_IPE] = { > > + .name = "ipe", > > + .sta_mask = BIT(31), > > + .ctl_offs = 0x3B4, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_IPE, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_IPE, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_CAM] = { > > + .name = "cam", > > + .sta_mask = BIT(25), > > + .ctl_offs = 0x39C, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .bp_infracfg = { > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_2_CAM, > > + MT8195_TOP_AXI_PROT_EN_2_SET, > > + MT8195_TOP_AXI_PROT_EN_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_2_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_1_CAM, > > + MT8195_TOP_AXI_PROT_EN_1_SET, > > + MT8195_TOP_AXI_PROT_EN_1_CLR, > > + MT8195_TOP_AXI_PROT_EN_1_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND, > > + MT8195_TOP_AXI_PROT_EN_MM_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_STA1), > > + BUS_PROT_WR(MT8195_TOP_AXI_PROT_EN_MM_2_CAM, > > + MT8195_TOP_AXI_PROT_EN_MM_2_SET, > > + MT8195_TOP_AXI_PROT_EN_MM_2_CLR, > > + MT8195_TOP_AXI_PROT_EN_MM_2_STA1), > > + }, > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_CAM_RAWA] = { > > + .name = "cam_rawa", > > + .sta_mask = BIT(26), > > + .ctl_offs = 0x3A0, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_CAM_RAWB] = { > > + .name = "cam_rawb", > > + .sta_mask = BIT(27), > > + .ctl_offs = 0x3A4, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > + [MT8195_POWER_DOMAIN_CAM_MRAW] = { > > + .name = "cam_mraw", > > + .sta_mask = BIT(28), > > + .ctl_offs = 0x3A8, > > + .pwr_sta_offs = 0x16c, > > + .pwr_sta2nd_offs = 0x170, > > + .sram_pdn_bits = GENMASK(8, 8), > > + .sram_pdn_ack_bits = GENMASK(12, 12), > > + .caps = MTK_SCPD_KEEP_DEFAULT_OFF, > > + }, > > +}; > > + > > +static const struct scpsys_soc_data mt8195_scpsys_data = { > > + .domains_data = scpsys_domain_data_mt8195, > > + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8195), > > +}; > > + > > +#endif /* __SOC_MEDIATEK_MT8195_PM_DOMAINS_H */ > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.c > > b/drivers/soc/mediatek/mtk-pm-domains.c > > index 2689f02d7a41..d705860b47a7 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.c > > +++ b/drivers/soc/mediatek/mtk-pm-domains.c > > @@ -20,6 +20,7 @@ > > #include "mt8173-pm-domains.h" > > #include "mt8183-pm-domains.h" > > #include "mt8192-pm-domains.h" > > +#include "mt8195-pm-domains.h" > > > > #define MTK_POLL_DELAY_US 10 > > #define MTK_POLL_TIMEOUT USEC_PER_SEC > > @@ -446,6 +447,9 @@ generic_pm_domain *scpsys_add_one_domain(struct > > scpsys *scpsys, struct device_no > > pd->genpd.power_off = scpsys_power_off; > > pd->genpd.power_on = scpsys_power_on; > > > > + if (MTK_SCPD_CAPS(pd, MTK_SCPD_ACTIVE_WAKEUP)) > > + pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP; > > + > > if (MTK_SCPD_CAPS(pd, MTK_SCPD_KEEP_DEFAULT_OFF)) > > pm_genpd_init(&pd->genpd, NULL, true); > > else > > @@ -576,6 +580,10 @@ static const struct of_device_id > > scpsys_of_match[] = { > > .compatible = "mediatek,mt8192-power-controller", > > .data = &mt8192_scpsys_data, > > }, > > + { > > + .compatible = "mediatek,mt8195-power-controller", > > + .data = &mt8195_scpsys_data, > > + }, > > { } > > }; > > > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h > > b/drivers/soc/mediatek/mtk-pm-domains.h > > index 8b86ed22ca56..caaa38100093 100644 > > --- a/drivers/soc/mediatek/mtk-pm-domains.h > > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > > @@ -37,7 +37,7 @@ > > #define PWR_STATUS_AUDIO BIT(24) > > #define PWR_STATUS_USB BIT(25) > > > > -#define SPM_MAX_BUS_PROT_DATA 5 > > +#define SPM_MAX_BUS_PROT_DATA 6 > > > > #define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) { > > \ > > .bus_prot_mask = (_mask), \ > > diff --git a/include/linux/soc/mediatek/infracfg.h > > b/include/linux/soc/mediatek/infracfg.h > > index 4615a228da51..3e90fb9b926a 100644 > > --- a/include/linux/soc/mediatek/infracfg.h > > +++ b/include/linux/soc/mediatek/infracfg.h > > @@ -2,6 +2,109 @@ > > #ifndef __SOC_MEDIATEK_INFRACFG_H > > #define __SOC_MEDIATEK_INFRACFG_H > > > > +#define MT8195_TOP_AXI_PROT_EN_STA1 0x228 > > +#define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258 > > +#define MT8195_TOP_AXI_PROT_EN_SET 0x2a0 > > +#define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4 > > +#define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8 > > +#define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac > > +#define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4 > > +#define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8 > > +#define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec > > +#define MT8195_TOP_AXI_PROT_EN_2_SET 0x714 > > +#define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718 > > +#define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8 > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4 > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0 > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8 > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0 > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8 > > + > > +#define MT8195_TOP_AXI_PROT_EN_NNA0 BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_NNA1 BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_NNA GENMASK(2, 1) > > +#define MT8195_TOP_AXI_PROT_EN_VDOSYS0 BIT(6) > > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0 BIT(10) > > +#define MT8195_TOP_AXI_PROT_EN_MFG1 BIT(11) > > +#define MT8195_TOP_AXI_PROT_EN_MFG1_2ND GENMASK > > (22, 21) > > +#define MT8195_TOP_AXI_PROT_EN_VPPSYS0_2ND BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_1_MFG1 GENMASK > > (20, 19) > > +#define MT8195_TOP_AXI_PROT_EN_1_CAM BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0) > > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1_2ND GENMASK(6, 5) > > +#define MT8195_TOP_AXI_PROT_EN_2_MFG1 BIT(7) > > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO_ASRC (BIT(8) > > | BIT(17)) > > +#define MT8195_TOP_AXI_PROT_EN_2_AUDIO (BIT(9) > > | BIT(11)) > > +#define MT8195_TOP_AXI_PROT_EN_2_ADSP (BIT(12 > > ) | GENMASK(16, 14)) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0_2ND BIT(19) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1_2ND BIT(20) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA_2ND GENMASK(20, 19) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA0 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA1 BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_2_NNA GENMASK > > (22, 21) > > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) > > | BIT(2) | BIT(4)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IPE BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG (BIT(1) > > | BIT(3)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS0 (GENMASK(2, 0) > > | GENMASK(8, 6) | \ > > + GENMASK(12, 10) > > | GENMASK(21, 19) | \ > > + BIT(31)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0 (GENMASK(5, 3) > > | BIT(9) | \ > > + GENMASK(14, 13) > > | GENMASK(21, 17) | \ > > + BIT(30)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1 GENMASK(8, 5) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC (BIT(9) > > | BIT(11)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_CORE1 (BIT(10 > > ) | BIT(12)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0 BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1 BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1_2ND BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VPPSYS1_2ND BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_MM_CAM_2ND BIT(24) > > +#define MT8195_TOP_AXI_PROT_EN_MM_IMG_2ND BIT(25) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VENC_2ND BIT(26) > > +#define MT8195_TOP_AXI_PROT_EN_MM_WPESYS BIT(27) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC0_2ND BIT(28) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDEC1_2ND BIT(29) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS0_2ND GENMASK > > (29, 22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_VDOSYS1 GENMASK(31, 30) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMAS > > K(7, 0) | GENMASK(18, 11)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VENC_CORE1 (BIT(3) > > | BIT(15)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_CAM (BIT(5) > > | BIT(17)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS1 (GENMAS > > K(7, 6) | BIT(18)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0 (GENMAS > > K(9, 8) | GENMASK(22, 21) | BIT(24)) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS1 BIT(10) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2_2ND BIT(12) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0_2ND BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS_2ND BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_IMG BIT(16) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_IPE BIT(16) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC2 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDEC0 BIT(22) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_VDOSYS0 BIT(23) > > +#define MT8195_TOP_AXI_PROT_EN_MM_2_WPESYS GENMASK(24, 23) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_EPD_TX BIT(1) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_DP_TX BIT(2) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P0 (BIT(11 > > ) | BIT(28)) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_PCIE_MAC_P1 (BIT(12 > > ) | BIT(29)) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P0 BIT(13) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_1_PCIE_MAC_P1 BIT(14) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1 (BIT(17) | > > BIT(19)) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0 BIT(20) > > +#define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0 BIT(21) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA0 BIT(25) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA1 BIT(26) > > +#define MT8195_TOP_AXI_PROT_EN_VDNR_2_NNA GENMASK(26, 25) > > + > > #define MT8192_TOP_AXI_PROT_EN_STA1 0x228 > > #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258 > > #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 2021-06-28 13:15 ` Chun-Jie Chen @ 2021-06-30 7:40 ` Matthias Brugger 0 siblings, 0 replies; 12+ messages in thread From: Matthias Brugger @ 2021-06-30 7:40 UTC (permalink / raw) To: Chun-Jie Chen, Enric Balletbo i Serra, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group On 28/06/2021 15:15, Chun-Jie Chen wrote: > On Fri, 2021-06-25 at 11:07 +0200, Enric Balletbo i Serra wrote: >> Hi Chun-Jie Chen, >> >> Thank you for your patch. >> >> On 16/6/21 2:06, Chun-Jie Chen wrote: >>> Add domain control data including bus protection data size >>> change due to more protection steps in mt8195 and wakeup flag >>> in power domain for wakeup control in suspend. >>> >> >> The wakeup flag is used for different SoCs apart from mt8195, isn't >> it? I'd add >> this on a separate patch so it is not dependent on the mt8195 >> changes. This will >> also make more clear that is not really a mt8195 thing and can help >> in case at >> some point we need to run a bisection because something is broken on >> another SoC. >> >> Thanks, >> Enric >> >> > > Yes, this wakeup flag also is used by other SoC like MT8173, but > missing this flag in new power domain driver(mtk-pm-domain.c). > I will separate this modification of wakeup flag from this patch but > put it in same series. > Sounds perfect. Regards, Matthias _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [RESEND PATCH v2 4/4] soc: mediatek: pm-domains: Remove unused macro 2021-06-16 0:06 [RESEND PATCH v2 0/4] Mediatek MT8195 power domain support Chun-Jie Chen ` (2 preceding siblings ...) 2021-06-16 0:06 ` [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 Chun-Jie Chen @ 2021-06-16 0:06 ` Chun-Jie Chen 2021-06-25 8:57 ` Enric Balletbo i Serra 3 siblings, 1 reply; 12+ messages in thread From: Chun-Jie Chen @ 2021-06-16 0:06 UTC (permalink / raw) To: Enric Balletbo i Serra, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group, Chun-Jie Chen Due to clk resource data will be allocated dynamically by searching parent count of clk in power domain node, so remove the unused marco MAX_SUBSYS_CLKS for static allocation. Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> --- drivers/soc/mediatek/mtk-pm-domains.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h index caaa38100093..1b8967b9829e 100644 --- a/drivers/soc/mediatek/mtk-pm-domains.h +++ b/drivers/soc/mediatek/mtk-pm-domains.h @@ -72,8 +72,6 @@ struct scpsys_bus_prot_data { bool ignore_clr_ack; }; -#define MAX_SUBSYS_CLKS 10 - /** * struct scpsys_domain_data - scp domain data for power on/off flow * @name: The name of the power domain. -- 2.18.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RESEND PATCH v2 4/4] soc: mediatek: pm-domains: Remove unused macro 2021-06-16 0:06 ` [RESEND PATCH v2 4/4] soc: mediatek: pm-domains: Remove unused macro Chun-Jie Chen @ 2021-06-25 8:57 ` Enric Balletbo i Serra 0 siblings, 0 replies; 12+ messages in thread From: Enric Balletbo i Serra @ 2021-06-25 8:57 UTC (permalink / raw) To: Chun-Jie Chen, Matthias Brugger, Nicolas Boichat, Rob Herring Cc: linux-arm-kernel, linux-kernel, devicetree, linux-mediatek, srv_heupstream, Project_Global_Chrome_Upstream_Group Hi Chun-Jie Chen, Thank you for your patch. On 16/6/21 2:06, Chun-Jie Chen wrote: > Due to clk resource data will be allocated dynamically by > searching parent count of clk in power domain node, so remove > the unused marco MAX_SUBSYS_CLKS for static allocation. > > Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > drivers/soc/mediatek/mtk-pm-domains.h | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h > index caaa38100093..1b8967b9829e 100644 > --- a/drivers/soc/mediatek/mtk-pm-domains.h > +++ b/drivers/soc/mediatek/mtk-pm-domains.h > @@ -72,8 +72,6 @@ struct scpsys_bus_prot_data { > bool ignore_clr_ack; > }; > > -#define MAX_SUBSYS_CLKS 10 > - > /** > * struct scpsys_domain_data - scp domain data for power on/off flow > * @name: The name of the power domain. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2021-06-30 7:43 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2021-06-16 0:06 [RESEND PATCH v2 0/4] Mediatek MT8195 power domain support Chun-Jie Chen 2021-06-16 0:06 ` [RESEND PATCH v2 1/4] soc: mediatek: pm-domains: Move power status offset to power domain data Chun-Jie Chen 2021-06-25 9:12 ` Enric Balletbo i Serra 2021-06-16 0:06 ` [RESEND PATCH v2 2/4] dt-bindings: power: Add MT8195 power domains Chun-Jie Chen 2021-06-24 20:57 ` Rob Herring 2021-06-25 8:58 ` Enric Balletbo i Serra 2021-06-16 0:06 ` [RESEND PATCH v2 3/4] soc: mediatek: pm-domains: Add support for mt8195 Chun-Jie Chen 2021-06-25 9:07 ` Enric Balletbo i Serra 2021-06-28 13:15 ` Chun-Jie Chen 2021-06-30 7:40 ` Matthias Brugger 2021-06-16 0:06 ` [RESEND PATCH v2 4/4] soc: mediatek: pm-domains: Remove unused macro Chun-Jie Chen 2021-06-25 8:57 ` Enric Balletbo i Serra
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