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From: John Garry <john.garry@huawei.com>
To: Sudeep Holla <sudeep.holla@arm.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Steven Price <steven.price@arm.com>,
	"harb@amperecomputing.com" <harb@amperecomputing.com>,
	Will Deacon <will@kernel.org>
Subject: Re: [PATCH 5/5] arm/arm64: smccc: Add ARCH_SOC_ID support
Date: Fri, 1 May 2020 16:25:27 +0100	[thread overview]
Message-ID: <426ff8ab-9c13-4301-a91e-989c19c4ff58@huawei.com> (raw)
In-Reply-To: <20200430114814.14116-6-sudeep.holla@arm.com>

On 30/04/2020 12:48, Sudeep Holla wrote:
> +static int __init smccc_soc_init(void)
> +{
> +	struct device *dev;
> +	int ret, soc_id_rev;
> +	struct arm_smccc_res res;
> +	static char soc_id_str[8], soc_id_rev_str[12];
> +
> +	if (arm_smccc_get_version() < ARM_SMCCC_VERSION_1_2)
> +		return 0;
> +
> +	ret = smccc_soc_id_support_check();
> +	if (ret)
> +		return ret;
> +
> +	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 0, &res);
> +
> +	ret = smccc_map_error_codes(res.a0);
> +	if (ret)
> +		return ret;
> +
> +	soc_id_version = res.a0;
> +
> +	arm_smccc_1_1_invoke(ARM_SMCCC_ARCH_SOC_ID, 1, &res);
> +
> +	ret = smccc_map_error_codes(res.a0);
> +	if (ret)
> +		return ret;
> +
> +	soc_id_rev = res.a0;
> +
> +	soc_dev_attr = kzalloc(sizeof(*soc_dev_attr), GFP_KERNEL);
> +	if (!soc_dev_attr)
> +		return -ENOMEM;
> +
> +	sprintf(soc_id_str, "0x%04x", IMP_DEF_SOC_ID(soc_id_version));
> +	sprintf(soc_id_rev_str, "0x%08x", soc_id_rev);
> +
> +	soc_dev_attr->soc_id = soc_id_str;
> +	soc_dev_attr->revision = soc_id_rev_str;
> +
> +	soc_dev = soc_device_register(soc_dev_attr);
> +	if (IS_ERR(soc_dev)) {
> +		ret = PTR_ERR(soc_dev);
> +		goto free_soc;
> +	}
> +
> +	dev = soc_device_to_device(soc_dev);
> +

Just wondering, what about if the platform already had a SoC driver - 
now it could have another one, such that we may have multiple sysfs soc 
devices, right?

Thanks,
John

> +	ret = devm_device_add_groups(dev, jep106_id_groups);
> +	if (ret) {
> +		dev_err(dev, "sysfs create failed: %d\n", ret);
> +		goto unregister_soc;
> +	}
> +
> +	pr_info("SMCCC SoC ID: %s Revision %s\n", soc_dev_attr->soc_id,
> +		soc_dev_attr->revision);
> +
> +	return 0;


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  parent reply	other threads:[~2020-05-01 15:26 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-30 11:48 [PATCH 0/5] arm/arm64: smccc: Add ARCH_SOC_ID support Sudeep Holla
2020-04-30 11:48 ` [PATCH 1/5] arm/arm64: smccc: Update link to latest SMCCC specification Sudeep Holla
2020-05-01 14:46   ` Steven Price
2020-04-30 11:48 ` [PATCH 2/5] arm/arm64: smccc: Add the definition for SMCCCv1.2 version/error codes Sudeep Holla
2020-05-01 14:46   ` Steven Price
2020-04-30 11:48 ` [PATCH 3/5] arm/arm64: smccc: Drop smccc_version enum and use ARM_SMCCC_VERSION_1_x instead Sudeep Holla
2020-05-01 14:48   ` Steven Price
2020-04-30 11:48 ` [PATCH 4/5] firmware: psci: Add function to fetch SMCCC version Sudeep Holla
2020-04-30 11:48 ` [PATCH 5/5] arm/arm64: smccc: Add ARCH_SOC_ID support Sudeep Holla
2020-05-01 15:07   ` Steven Price
2020-05-01 15:57     ` Sudeep Holla
2020-05-01 15:25   ` John Garry [this message]
2020-05-01 16:05     ` Sudeep Holla
2020-05-01 16:40       ` John Garry

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