Re: [PATCH 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1

From: Stephen Warren <swarren@wwwdotorg.org>
To: Dmitry Osipenko <digetx@gmail.com>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
	linux-tegra@vger.kernel.org,
	Michael Turquette <mturquette@baylibre.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1
Date: Thu, 3 Oct 2019 10:34:14 -0600	[thread overview]
Message-ID: <485c9828-120a-8e62-bf85-c5d8407d3513@wwwdotorg.org> (raw)
In-Reply-To: <437f030b-9e20-43e5-42ce-f98430d2149b@gmail.com>

On 10/3/19 5:27 AM, Dmitry Osipenko wrote:
> 02.10.2019 00:13, Stephen Warren пишет:
>> From: Stephen Warren <swarren@nvidia.com>
>>
>> For a little over a year, U-Boot has configured the flow controller to
>> perform automatic RAM re-repair on off->on power transitions of the CPU
>> rail1]. This is mandatory for correct operation of Tegra124. However, RAM
>> re-repair relies on certain clocks, which the kernel must enable and
>> leave running. PLLP is one of those clocks. This clock is shut down
>> during LP1 in order to save power. Enable bypass (which I believe routes
>> osc_div_clk, essentially the crystal clock, to the PLL output) so that
>> this clock signal toggles even though the PLL is not active. This is
>> required so that LP1 power mode (system suspend) operates correctly.
>>
>> The bypass configuration must then be undone when resuming from LP1, so
>> that all peripheral clocks run at the expected rate. Without this, many
>> peripherals won't work correctly; for example, the UART baud rate would
>> be incorrect.
>>
>> NVIDIA's downstream kernel code only does this if not compiled for
>> Tegra30, so the added code is made conditional upon the chip ID. NVIDIA's
>> downstream code makes this change conditional upon the active CPU
>> cluster. The upstream kernel currently doesn't support cluster switching,
>> so this patch doesn't test the active CPU cluster ID.
>>
>> [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
>>
>> Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
>> Cc: stable@vger.kernel.org
>> Signed-off-by: Stephen Warren <swarren@nvidia.com>
>> ---
>>   arch/arm/mach-tegra/sleep-tegra30.S | 11 +++++++++++
>>   1 file changed, 11 insertions(+)
>>
>> diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
>> index b408fa56eb89..6922dd8d3e2d 100644
>> --- a/arch/arm/mach-tegra/sleep-tegra30.S
>> +++ b/arch/arm/mach-tegra/sleep-tegra30.S
>> @@ -370,6 +370,14 @@ _pll_m_c_x_done:
>>   	pll_locked r1, r0, CLK_RESET_PLLC_BASE
>>   	pll_locked r1, r0, CLK_RESET_PLLX_BASE
>>   
>> +	tegra_get_soc_id TEGRA_APB_MISC_BASE, r1
>> +	cmp	r1, #TEGRA30
>> +	beq	1f
> 
> What about T114, or does it need enabled PLLP as well?

I'm nowhere near as familiar with T114 as T124, so I can't be 100% sure. 
However, a very quick look at the CAR section in the T114 TRM does show 
the same gate/mux structure around a reshift and fuse clock, so I assume 
the requirement is identical there.

Also, NVIDIA's downstream kernel has a compile-time ifdef around the 
code I've added here. It's not compiled for T30 specifically, and is 
compiled for anything else, which I believe means both T114 and T124.

In patch 1 in this series, I only enabled the fuse clock for T124, since 
I don't have a T114 system to test any more. However, the revised patch 
1 that Thierry and I are discussing would enable the fuse clock on all 
SoCs, and hence make the code work identically on T114 as it does on T124.

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