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From: Dmitry Osipenko <digetx@gmail.com>
To: Stephen Warren <swarren@wwwdotorg.org>,
	Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
	linux-tegra@vger.kernel.org,
	Michael Turquette <mturquette@baylibre.com>,
	linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 1/4] clk: tegra: Enable fuse clock on Tegra124
Date: Thu, 3 Oct 2019 14:23:17 +0300	[thread overview]
Message-ID: <7f8934d9-8192-f88e-a329-630209d42a85@gmail.com> (raw)
In-Reply-To: <20191001211346.104400-1-swarren@wwwdotorg.org>

02.10.2019 00:13, Stephen Warren пишет:
> From: Stephen Warren <swarren@nvidia.com>
> 
> For a little over a year, U-Boot has configured the flow controller to
> perform automatic RAM re-repair on off->on power transitions of the CPU
> rail1]. This is mandatory for correct operation of Tegra124. However, RAM
> re-repair relies on certain clocks, which the kernel must enable and
> leave running. The fuse clock is one of those clocks. Enable this clock
> so that LP1 power mode (system suspend) operates correctly.
> 
> [1] 3cc7942a4ae5 ARM: tegra: implement RAM repair
> 
> Reported-by: Jonathan Hunter <jonathanh@nvidia.com>
> Cc: stable@vger.kernel.org
> Signed-off-by: Stephen Warren <swarren@nvidia.com>
> ---
>  drivers/clk/tegra/clk-tegra124.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
> index 0224fdc4766f..f53f6315c646 100644
> --- a/drivers/clk/tegra/clk-tegra124.c
> +++ b/drivers/clk/tegra/clk-tegra124.c
> @@ -1291,6 +1291,7 @@ static struct tegra_clk_init_table common_init_table[] __initdata = {
>  };
>  
>  static struct tegra_clk_init_table tegra124_init_table[] __initdata = {
> +	{ TEGRA124_CLK_FUSE, -1, 0, 1 },
>  	{ TEGRA124_CLK_SOC_THERM, TEGRA124_CLK_PLL_P, 51000000, 0 },
>  	{ TEGRA124_CLK_CCLK_G, TEGRA124_CLK_CLK_MAX, 0, 1 },
>  	{ TEGRA124_CLK_HDA, TEGRA124_CLK_PLL_P, 102000000, 0 },
> 

Hello Stephen,

Does this mean that devices which are using older U-Boot version were always in a trouble?
It sounds to me that the RAM re-repair should be also enabled by the kernel's flow
controller driver in a case if bootloader did not enable it.
If enabling RAM re-repair is a change that won't be easily backportable to stable kernels,
then may be it's worth to simply force-disable LP1 on T124 for the older kernels.

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  parent reply	other threads:[~2019-10-03 11:23 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-01 21:13 [PATCH 1/4] clk: tegra: Enable fuse clock on Tegra124 Stephen Warren
2019-10-01 21:13 ` [PATCH 2/4] ARM: tegra: Enable PLLP bypass during Tegra124 LP1 Stephen Warren
2019-10-03 11:27   ` Dmitry Osipenko
2019-10-03 16:34     ` Stephen Warren
2019-10-03 18:00       ` Dmitry Osipenko
2019-10-01 21:13 ` [PATCH 3/4] ARM: tegra: modify reshift divider during LP1 Stephen Warren
2019-10-01 21:13 ` PATCH 4/4] ARM: tegra: use clk_m CPU on Tegra124 LP1 resume Stephen Warren
2019-10-02 11:04 ` [PATCH 1/4] clk: tegra: Enable fuse clock on Tegra124 Thierry Reding
2019-10-02 20:59   ` Stephen Warren
2019-10-04 12:18     ` Thierry Reding
2019-10-04 16:07       ` Stephen Warren
2019-10-03 11:23 ` Dmitry Osipenko [this message]
2019-10-03 16:28   ` Stephen Warren

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