Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its domain as parent

From: Robin Murphy <robin.murphy@arm.com>
To: Marc Zyngier <maz@kernel.org>, Jason Gunthorpe <jgg@nvidia.com>
Cc: Nipun Gupta <nipun.gupta@amd.com>,
	robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
	gregkh@linuxfoundation.org, rafael@kernel.org,
	eric.auger@redhat.com, alex.williamson@redhat.com,
	cohuck@redhat.com, puneet.gupta@amd.com,
	song.bao.hua@hisilicon.com, mchehab+huawei@kernel.org,
	f.fainelli@gmail.com, jeffrey.l.hugo@gmail.com,
	saravanak@google.com, Michael.Srba@seznam.cz, mani@kernel.org,
	yishaih@nvidia.com, will@kernel.org, joro@8bytes.org,
	masahiroy@kernel.org, ndesaulniers@google.com,
	linux-arm-kernel@lists.infradead.org,
	linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, kvm@vger.kernel.org,
	okaya@kernel.org, harpreet.anand@amd.com, nikhil.agarwal@amd.com,
	michal.simek@amd.com, aleksandar.radovanovic@amd.com,
	git@amd.com
Subject: Re: [RFC PATCH v3 4/7] bus/cdx: add cdx-MSI domain with gic-its domain as parent
Date: Wed, 7 Sep 2022 12:33:12 +0100	[thread overview]
Message-ID: <4ca6383e-bd21-59bf-cc4e-cf3313164957@arm.com> (raw)
In-Reply-To: <87leqvv3g7.wl-maz@kernel.org>

On 2022-09-07 12:17, Marc Zyngier wrote:
> On Tue, 06 Sep 2022 18:19:06 +0100,
> Jason Gunthorpe <jgg@nvidia.com> wrote:
>>
>> On Tue, Sep 06, 2022 at 07:17:58PM +0530, Nipun Gupta wrote:
>>
>>> +static void cdx_msi_write_msg(struct irq_data *irq_data,
>>> +			      struct msi_msg *msg)
>>> +{
>>> +	/*
>>> +	 * Do nothing as CDX devices have these pre-populated
>>> +	 * in the hardware itself.
>>> +	 */
>>> +}
>>
>> Huh?
>>
>> There is no way it can be pre-populated, the addr/data pair,
>> especially on ARM, is completely under SW control.
> 
> There is nothing in the GIC spec that says that.
> 
>> There is some commonly used IOVA base in Linux for the ITS page, but
>> no HW should hardwire that.
> 
> That's not strictly true. It really depends on how this block is
> integrated, and there is a number of existing blocks that know *in HW*
> how to signal an LPI.
> 
> See, as the canonical example, how the mbigen driver doesn't need to
> know about the address of GITS_TRANSLATER.
> 
> Yes, this messes with translation (the access is downstream of the
> SMMU) if you relied on it to have some isolation, and it has a "black
> hole" effect as nobody can have an IOVA that overlaps with the
> physical address of the GITS_TRANSLATER register.
> 
> But is it illegal as per the architecture? No. It's just stupid.

If that were the case, then we'd also need a platform quirk so the SMMU 
driver knows about it. Yuck.

But even then, are you suggesting there is some way to convince the ITS 
driver to allocate a specific predetermined EventID when a driver 
requests an MSI? Asking for a friend...

Cheers,
Robin.

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