Re: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency

From: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
To: Alan Cooper <alcooperx@gmail.com>
Cc: Stefan Wahren <stefan.wahren@i2se.com>,
	Nicolas Saenz Julienne <nsaenz@kernel.org>,
	"moderated list:BROADCOM BCM7XXX ARM ARCHITECTURE"
	<linux-arm-kernel@lists.infradead.org>,
	linux-mmc <linux-mmc@vger.kernel.org>,
	 DTML <devicetree@vger.kernel.org>,
	BCM Kernel Feedback <bcm-kernel-feedback-list@broadcom.com>,
	linux-rpi-kernel@lists.infradead.org,
	 Florian Fainelli <f.fainelli@gmail.com>,
	phil@raspberrypi.com, Tim Gover <tim.gover@raspberrypi.com>,
	Scott Branden <sbranden@broadcom.com>,
	Adrian Hunter <adrian.hunter@intel.com>,
	": Linux Kernel Mailing List" <linux-kernel@vger.kernel.org>,
	Ulf Hansson <ulf.hansson@linaro.org>,
	Rob Herring <robh+dt@kernel.org>
Subject: Re: [PATCH 4/4] ARM: dts: Fix-up EMMC2 controller's frequency
Date: Mon, 05 Apr 2021 10:45:29 +0200	[thread overview]
Message-ID: <4d4e3de99dbee711cf47878bf98a7cc34c3f1e65.camel@suse.de> (raw)
In-Reply-To: <CAOGqxeUxOA_s6=KUh_XWFtRF_EWZgQH_y2MEdxUeDQTYMeb+3A@mail.gmail.com>

[-- Attachment #1.1: Type: text/plain, Size: 1596 bytes --]

Hi Alan,

On Thu, 2021-04-01 at 11:23 -0400, Alan Cooper wrote:
> Nicolas,
> 
> Sorry, I just noticed this thread.
> This is a known bug in some newer Arasan cores.
> The problem happens when the difference between the core clock and the bus
> clock is too great.
> Limiting the clock to 200KHz minimum should be a good fix.

Great, that's what I was hoping to hear :). Out of curiosity, can you share
more details on how the failure occurs?

> In my experience, it's only eMMC that needs the clock to be retried

> below 400KHz and not SD or SDIO. That's because the CMD signal for
> eMMC starts out as open-drain during identification and the size of
> the pull-up on the CMD signal can require the <400KHz clock. Once eMMC
> is out of identification mode the CMD signal is switched to push-pull
> and can run at much higher clock rates.

Fair enough, I need to do some tests, some of the compute modules use an eMMC.

> I don't think that SD and SDIO have any open-drain signals, so they
> shouldn't need to retry at slower clock speeds.

Noted.

> I'm trying to get more detail on the bug, like the exact ratio of core
> clock to bus clock that causes the problem. When I first found this
> bug I was told that the failure would not happen at 200KHz, but we
> were using a 405MHz core clock.

That would be nice to have.

> One other question. Why are you using polling for the SD card, this
> newer controller supports the interrupt driven "Card Inserted" signal
> and avoids wasting time polling?

I believe the line isn't routed on RPi4.

> Al

[-- Attachment #1.2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel