Re: [PATCH 6/6] arm64: tegra: Add support for PCIe endpoint mode in P2972-0000 platform

[Vidya Sagar <vidyas@nvidia.com>]

On 11/25/2019 12:55 PM, Thierry Reding wrote:
> On Mon, Nov 25, 2019 at 12:30:53PM +0530, Vidya Sagar wrote:
>> On 11/22/2019 6:55 PM, Thierry Reding wrote:
>>> On Fri, Nov 22, 2019 at 04:15:05PM +0530, Vidya Sagar wrote:
>>>> Add endpoint mode support for PCIe C5 controller in P2972-0000 platform
>>>> with information about supplies, PHY, PERST GPIO and GPIO that controls
>>>> PCIe reference clock coming from the host system.
>>>>
>>>> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
>>>> ---
>>>>    .../boot/dts/nvidia/tegra194-p2972-0000.dts   | 29 +++++++++++++++++++
>>>>    1 file changed, 29 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
>>>> index 7eb64b816e08..58c3a9677bc8 100644
>>>> --- a/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
>>>> +++ b/arch/arm64/boot/dts/nvidia/tegra194-p2972-0000.dts
>>>> @@ -43,6 +43,19 @@
>>>>    		gpio@c2f0000 {
>>>>    			status = "okay";
>>>> +			/*
>>>> +			 * Change the below node's status to 'okay' when
>>>> +			 * PCIe C5 controller is enabled to operate in endpoint
>>>> +			 * to allow REFCLK from the host system to flow into
>>>> +			 * the controller.
>>>> +			 */
>>>> +			pex-refclk-sel-high {
>>>> +				gpio-hog;
>>>> +				output-high;
>>>> +				gpios = <TEGRA194_AON_GPIO(AA, 5) 0>;
>>>> +				label = "pex_refclk_sel_high";
>>>> +				status = "disabled";
>>>> +			};
>>>
>>> Why don't we put this into the PCIe controller's node as a reference to
>>> that GPIO? Seems like the controller would know exactly when this pin
>>> needs to go high or low, so why does it have to be a hog?
>>>
>>> Thierry
>> Are you saying something like 'nvidia,enable-refclk-in'?
>> I was thinking, since this is like a board level configuration specific to Jetson-Xavier,
>> it would suffice to just hog it according to the mode of operation of PCIe controller.
>> But, I see one advantage of referencing it in the PCIe node (so that the driver can configure
>> it as and when needed) is that one has to be careful just to enable either PCIe RP or EP
>> node and not worry about other thing (like this).
>> Let me know if I got this right.
> 
> Yeah, that's exactly why I think referencing this from the controller
> and controlling it in the driver is preferable.
> 
> If this is some sort of select signal I think it makes sense to name it
> "nvidia,refclk-select-gpios" or something. Does this appear in the
> schematic somewhere? Or does the IP have a name for this? Those are
> usually good places to look for inspiration on the name because it's
> what hardware designers will be familiar with and they are technically
> the ones who should write the DT, even if that's rarely the case.
Schematic has "PEX_REFCLK_SEL" name.
I would go with 'nvidia,refclk-select-gpios' and make the change.

- Vidya Sagar
> 
> Thierry
> 
>>
>> - Vidya Sagar
>>
>>>
>>>>    		};
>>>>    		pwm@c340000 {
>>>> @@ -144,6 +157,22 @@
>>>>    			    "p2u-5", "p2u-6", "p2u-7";
>>>>    	};
>>>> +	pcie_ep@141a0000 {
>>>> +		status = "disabled";
>>>> +
>>>> +		vddio-pex-ctl-supply = <&vdd_1v8ao>;
>>>> +
>>>> +		nvidia,pex-rst-gpio = <&gpio TEGRA194_MAIN_GPIO(GG, 1)
>>>> +					GPIO_ACTIVE_LOW>;
>>>> +
>>>> +		phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>,
>>>> +		       <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>,
>>>> +		       <&p2u_nvhs_6>, <&p2u_nvhs_7>;
>>>> +
>>>> +		phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4",
>>>> +			    "p2u-5", "p2u-6", "p2u-7";
>>>> +	};
>>>> +
>>>>    	fan: fan {
>>>>    		compatible = "pwm-fan";
>>>>    		pwms = <&pwm4 0 45334>;
>>>> -- 
>>>> 2.17.1
>>>>
>>


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