* [PATCH] ARM: tegra: don't unlock MMIO access to DBGLAR
@ 2013-02-19 10:16 Joseph Lo
2013-03-06 20:42 ` Stephen Warren
0 siblings, 1 reply; 2+ messages in thread
From: Joseph Lo @ 2013-02-19 10:16 UTC (permalink / raw)
To: linux-arm-kernel
There is no need to unlock MMIO access to the DBGLAR all the time. Doing
so may even cause problems if a SW bug causes writes to that MMIO region.
Cortex-A15 processors do not support the CP14 register write the code
currently uses to unlock the DBGLAR; the instruction throws an undefined
instruction exceptions. This prevents tegra_secondary_startup() from
executing on Tegra114, and hence prevents SMP.
Remove the code that unlocks this access.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
---
arch/arm/mach-tegra/headsmp.S | 3 ---
arch/arm/mach-tegra/reset-handler.S | 3 ---
2 files changed, 6 deletions(-)
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fd473f2..045c16f 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,8 +7,5 @@
ENTRY(tegra_secondary_startup)
bl v7_invalidate_l1
- /* Enable coresight */
- mov32 r0, 0xC5ACCE55
- mcr p14, 0, r0, c7, c12, 6
b secondary_startup
ENDPROC(tegra_secondary_startup)
diff --git a/arch/arm/mach-tegra/reset-handler.S b/arch/arm/mach-tegra/reset-handler.S
index 54382ce..68b8bfc 100644
--- a/arch/arm/mach-tegra/reset-handler.S
+++ b/arch/arm/mach-tegra/reset-handler.S
@@ -41,9 +41,6 @@
*/
ENTRY(tegra_resume)
bl v7_invalidate_l1
- /* Enable coresight */
- mov32 r0, 0xC5ACCE55
- mcr p14, 0, r0, c7, c12, 6
cpu_id r0
cmp r0, #0 @ CPU0?
--
1.8.1.1
^ permalink raw reply related [flat|nested] 2+ messages in thread
* [PATCH] ARM: tegra: don't unlock MMIO access to DBGLAR
2013-02-19 10:16 [PATCH] ARM: tegra: don't unlock MMIO access to DBGLAR Joseph Lo
@ 2013-03-06 20:42 ` Stephen Warren
0 siblings, 0 replies; 2+ messages in thread
From: Stephen Warren @ 2013-03-06 20:42 UTC (permalink / raw)
To: linux-arm-kernel
On 02/19/2013 03:16 AM, Joseph Lo wrote:
> There is no need to unlock MMIO access to the DBGLAR all the time. Doing
> so may even cause problems if a SW bug causes writes to that MMIO region.
>
> Cortex-A15 processors do not support the CP14 register write the code
> currently uses to unlock the DBGLAR; the instruction throws an undefined
> instruction exceptions. This prevents tegra_secondary_startup() from
> executing on Tegra114, and hence prevents SMP.
>
> Remove the code that unlocks this access.
I have applied this to Tegra's for-3.10/fixes branch.
^ permalink raw reply [flat|nested] 2+ messages in thread
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