* [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock
@ 2014-09-06 6:45 Chen-Yu Tsai
2014-09-06 15:55 ` Emilio López
2014-09-13 8:08 ` Maxime Ripard
0 siblings, 2 replies; 3+ messages in thread
From: Chen-Yu Tsai @ 2014-09-06 6:45 UTC (permalink / raw)
To: linux-arm-kernel
The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.
This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.
This patch adds a proper divider table for it, so the correct
clock rate can be calculated.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
drivers/clk/sunxi/clk-sunxi.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index b654b7b..2cf6581 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -762,10 +762,19 @@ static const struct div_data sun4i_ahb_data __initconst = {
.width = 2,
};
+static const struct clk_div_table sun4i_apb0_table[] __initconst = {
+ { .val = 0, .div = 2 },
+ { .val = 1, .div = 2 },
+ { .val = 2, .div = 4 },
+ { .val = 3, .div = 8 },
+ { } /* sentinel */
+};
+
static const struct div_data sun4i_apb0_data __initconst = {
.shift = 8,
.pow = 1,
.width = 2,
+ .table = sun4i_apb0_table,
};
static const struct div_data sun6i_a31_apb2_div_data __initconst = {
--
2.1.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock
2014-09-06 6:45 [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock Chen-Yu Tsai
@ 2014-09-06 15:55 ` Emilio López
2014-09-13 8:08 ` Maxime Ripard
1 sibling, 0 replies; 3+ messages in thread
From: Emilio López @ 2014-09-06 15:55 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
El 06/09/14 a las 03:45, Chen-Yu Tsai escibi?:
> The sun4i-apb0 clock, as found on all platforms using it, is a
> power-of-two-based divider clock, with a special divider of 2
> for value 0.
>
> This was causing the clock framework to incorrectly calculate
> the clock rate for apb1 and related modules on sun6i and sun8i.
> On sun[4/5/7]i, u-boot SPL configures the divider with value 1
> for /2 divider, so no suprises there.
>
> This patch adds a proper divider table for it, so the correct
> clock rate can be calculated.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
From a quick look at the A10 manual,
Acked-by: Emilio L?pez <emilio@elopez.com.ar>
I'll see about testing it on hardware today/tomorrow
Thanks!
Emilio
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock
2014-09-06 6:45 [PATCH] clk: sunxi: add correct divider table for sun4i-apb0 clock Chen-Yu Tsai
2014-09-06 15:55 ` Emilio López
@ 2014-09-13 8:08 ` Maxime Ripard
1 sibling, 0 replies; 3+ messages in thread
From: Maxime Ripard @ 2014-09-13 8:08 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Sep 06, 2014 at 02:45:10PM +0800, Chen-Yu Tsai wrote:
> The sun4i-apb0 clock, as found on all platforms using it, is a
> power-of-two-based divider clock, with a special divider of 2
> for value 0.
>
> This was causing the clock framework to incorrectly calculate
> the clock rate for apb1 and related modules on sun6i and sun8i.
> On sun[4/5/7]i, u-boot SPL configures the divider with value 1
> for /2 divider, so no suprises there.
>
> This patch adds a proper divider table for it, so the correct
> clock rate can be calculated.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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2014-09-06 15:55 ` Emilio López
2014-09-13 8:08 ` Maxime Ripard
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