* [PATCH v8 0/17] Add Analogix Core Display Port Driver
@ 2015-10-28 8:15 Yakir Yang
2015-10-28 8:19 ` [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
` (22 more replies)
0 siblings, 23 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288 and exynos only need to keep
some platform code. Cause I can't find the exact IP name of exynos dp
controller, so I decide to name dp core driver with "analogix" which I
find in rk3288 eDP TRM
But there are still three light registers setting differents bewteen
exynos and rk3288.
1. RK3288 have five special pll resigters which not indicata in exynos
dp controller.
2. The address of DP_PHY_PD(dp phy power manager register) are different
between rk3288 and exynos.
3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
register).
This series have been well tested on Rockchip platform with eDP panel on
Jerry Chromebook and Display Port Monitor on RK3288 board. Also I have
tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at Samsung
help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
glad to say that things works rightlly.
Thanks,
- Yakir
Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)
- Modify the commit subject name. (Heiko)
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof)
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
- Simplify the commit message. (Kishon)
Changes in v6:
- Fix the wrong code in previous series, and test on Samsung snow Chromebook
successfully, here are the detail changes:
=============>
- if (!dp->panel && !dp->bridge) {
+ if (!dp->panel && !dp->ptn_bridge) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
=============>
+ encoder->bridge = bridge;
bridge->driver_private = dp;
bridge->encoder = encoder;
bridge->funcs = &exynos_dp_bridge_funcs;
ret = drm_bridge_attach(drm_dev, bridge);
- Fix the Kconfig recursive dependency (Javier)
- Fix Peach Pit hpd property name error:
- hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios = <&gpx2 6 0>;
Changes in v5:
- Correct the check condition of gpio_is_valid when driver try to get
the "hpd-gpios" DT propery. (Heiko)
- Move the platform attach callback in the front of core driver bridge
attch function. Cause once platform failed at attach, core driver should
still failed, so no need to init connector before platform attached (Krzysztof)
- Keep code style no changes with the previous exynos_dp_code.c in this
patch, and update commit message about the new export symbol (Krzysztof)
- Gather the device type patch (v4 11/16) into this one. (Krzysztof)
- leave out the connector registration to analogix platform driver. (Thierry)
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit message, and
remove some controversial style (Krzysztof)
- analogix_dp_write_byte_to_dpcd(
- dp, DP_TEST_RESPONSE,
+ analogix_dp_write_byte_to_dpcd(dp,
+ DP_TEST_RESPONSE,
DP_TEST_EDID_CHECKSUM_WRITE);
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfacs
would modify the original drm_display_mode timing directly (whether those
properties exists or not).
- Correct the misspell in commit message. (Krzysztof)
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example DT node, and remove the regulator iomux setting
in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfaces. (Heiko)
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in document. (Rob & Heiko)
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
video mode, but hard code CRTC video output mode to RGBaaa.
Changes in v4:
- Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
- Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
- Create a separate folder for analogix code in bridge/ (Archit)
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
- Provide backword compatibility with samsung. (Krzysztof)
- Split all DTS changes, and provide backward compatibility. Mark old
properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
"analogix,color-space" & "analogix,color-depth" &
"analogix,link-rate" & "analogix,lane-count" &
"analogix,ycbcr-coeff" & "analogix,dynamic-range" &
"vsync-active-high" & "hsync-active-high" & "interlaces"
- Separate all DTS changes to a separate patch. (Krzysztof)
- Remove some deprecated DT properties in rockchip dp document.
- Add commit message, and remove the redundant rockchip_dp_phy_init()
function, move those code to probe() method. And remove driver .owner
number. (Kishon)
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
- Take Jingoo suggest, add commit messages.
- Call drm_panel_prepare() in .get_modes function, ensure panel should
power on before driver try to read edid message.
Changes in v3:
- Move exynos's video_timing code to analogix_dp-exynos platform driver,
add get_modes method to struct analogix_dp_plat_data. (Thierry)
- Rename some "samsung*" dts propery to "analogix*". (Heiko)
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those as hardware limite. For example, RK3288
only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
like "link-rate = 0x0a" "lane-count = 4". (Thierry)
- Dynamic parse video timing info from struct drm_display_mode and
struct drm_display_info. (Thierry)
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
and leave "sclk_edp" to analogix dp core driver which name to "dp",
and leave "pclk_edp" to rockchip dp platform driver which name to
"pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
- Suggest, add rockchip dp phy driver, collect the phy clocks and
power control. (Heiko)
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
- move dp hpd detect to connector detect function.
- Add edid modes parse support
Changes in v2:
- Keep author name list no changed (Jingoo)
- Remove new copyright (Jingoo)
- Fix compiled failed due to analogix_dp_device misspell
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(......);
- Get panel node with remote-endpoint method, and create devicetree binding
for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
- Fix compile failed dut to phy_pd_addr variable misspell error
Mark Yao (1):
drm: rockchip: vop: add bpc and color mode setting
Yakir Yang (16):
drm: exynos: dp: convert to drm bridge mode
drm: bridge: analogix/dp: split exynos dp driver to bridge directory
drm: bridge: analogix/dp: fix some obvious code style
drm: bridge: analogix/dp: remove duplicate configuration of link rate
and link count
drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
dynamic_range
dt-bindings: add document for analogix display port driver
ARM: dts: exynos/dp: remove some properties that deprecated by
analogix_dp driver
drm: rockchip: dp: add rockchip platform dp driver
dt-bindings: add document for rockchip variant of analogix_dp
phy: Add driver for rockchip Display Port PHY
dt-bindings: add document for rockchip dp phy
drm: bridge: analogix/dp: add some rk3288 special registers setting
drm: bridge: analogix/dp: add max link rate and lane count limit for
RK3288
drm: bridge: analogix/dp: try force hpd after plug in lookup failed
drm: bridge: analogix/dp: move hpd detect to connector detect function
drm: bridge: analogix/dp: add edid modes parse in get_modes method
.../bindings/display/bridge/analogix_dp.txt | 52 +
.../bindings/display/exynos/exynos_dp.txt | 66 +-
.../display/rockchip/analogix_dp-rockchip.txt | 91 ++
.../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 +
arch/arm/boot/dts/exynos5250-arndale.dts | 2 -
arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 -
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +-
arch/arm/boot/dts/exynos5250-spring.dts | 4 +-
arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +-
arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 -
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +-
drivers/gpu/drm/bridge/Kconfig | 2 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/analogix/Kconfig | 3 +
drivers/gpu/drm/bridge/analogix/Makefile | 1 +
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1373 +++++++++++++++++++
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 286 ++++
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 1294 ++++++++++++++++++
.../analogix/analogix_dp_reg.h} | 270 ++--
drivers/gpu/drm/exynos/Kconfig | 3 +-
drivers/gpu/drm/exynos/Makefile | 2 +-
drivers/gpu/drm/exynos/exynos_dp.c | 349 +++++
drivers/gpu/drm/exynos/exynos_dp_core.c | 1404 --------------------
drivers/gpu/drm/exynos/exynos_dp_core.h | 281 ----
drivers/gpu/drm/exynos/exynos_dp_reg.c | 1263 ------------------
drivers/gpu/drm/rockchip/Kconfig | 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 457 +++++++
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 +-
drivers/phy/Kconfig | 7 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 155 +++
include/drm/bridge/analogix_dp.h | 42 +
35 files changed, 4348 insertions(+), 3145 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
create mode 100644 drivers/phy/phy-rockchip-dp.c
create mode 100644 include/drm/bridge/analogix_dp.h
--
1.9.1
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
@ 2015-10-28 8:19 ` Yakir Yang
2016-03-22 22:22 ` Inki Dae
2015-10-28 8:23 ` [PATCH v8 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
` (21 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix the wrong code in previous series, and test on Samsung snow Chromebook
successfully, here are the detail changes:
=============>
- if (!dp->panel && !dp->bridge) {
+ if (!dp->panel && !dp->ptn_bridge) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
=============>
+ encoder->bridge = bridge;
bridge->driver_private = dp;
bridge->encoder = encoder;
bridge->funcs = &exynos_dp_bridge_funcs;
ret = drm_bridge_attach(drm_dev, bridge);
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Keep author name list no changed (Jingoo)
drivers/gpu/drm/exynos/exynos_dp_core.c | 103 ++++++++++++++++++++++++--------
drivers/gpu/drm/exynos/exynos_dp_core.h | 1 +
2 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
index 124fb9a..aedd074 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.c
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
@@ -1009,9 +1009,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
{
int ret;
- encoder->bridge = dp->bridge;
- dp->bridge->encoder = encoder;
- ret = drm_bridge_attach(encoder->dev, dp->bridge);
+ encoder->bridge->next = dp->ptn_bridge;
+ dp->ptn_bridge->encoder = encoder;
+ ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
if (ret) {
DRM_ERROR("Failed to attach bridge to drm\n");
return ret;
@@ -1020,14 +1020,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
return 0;
}
-static int exynos_dp_create_connector(struct drm_encoder *encoder)
+static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
{
- struct exynos_dp_device *dp = encoder_to_dp(encoder);
+ struct exynos_dp_device *dp = bridge->driver_private;
+ struct drm_encoder *encoder = &dp->encoder;
struct drm_connector *connector = &dp->connector;
int ret;
/* Pre-empt DP connector creation if there's a bridge */
- if (dp->bridge) {
+ if (dp->ptn_bridge) {
ret = exynos_drm_attach_lcd_bridge(dp, encoder);
if (!ret)
return 0;
@@ -1052,22 +1053,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
return ret;
}
-static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
- const struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
- return true;
-}
-
-static void exynos_dp_mode_set(struct drm_encoder *encoder,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode)
-{
-}
-
-static void exynos_dp_enable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
{
- struct exynos_dp_device *dp = encoder_to_dp(encoder);
+ struct exynos_dp_device *dp = bridge->driver_private;
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
if (dp->dpms_mode == DRM_MODE_DPMS_ON)
@@ -1092,9 +1080,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
dp->dpms_mode = DRM_MODE_DPMS_ON;
}
-static void exynos_dp_disable(struct drm_encoder *encoder)
+static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
{
- struct exynos_dp_device *dp = encoder_to_dp(encoder);
+ struct exynos_dp_device *dp = bridge->driver_private;
struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
if (dp->dpms_mode != DRM_MODE_DPMS_ON)
@@ -1123,6 +1111,69 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
dp->dpms_mode = DRM_MODE_DPMS_OFF;
}
+static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
+{
+ /* do nothing */
+}
+
+static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
+ .enable = exynos_dp_bridge_enable,
+ .disable = exynos_dp_bridge_disable,
+ .pre_enable = exynos_dp_bridge_nop,
+ .post_disable = exynos_dp_bridge_nop,
+ .attach = exynos_dp_bridge_attach,
+};
+
+static int exynos_dp_create_connector(struct drm_encoder *encoder)
+{
+ struct exynos_dp_device *dp = encoder_to_dp(encoder);
+ struct drm_device *drm_dev = dp->drm_dev;
+ struct drm_bridge *bridge;
+ int ret;
+
+ bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
+ if (!bridge) {
+ DRM_ERROR("failed to allocate for drm bridge\n");
+ return -ENOMEM;
+ }
+
+ dp->bridge = bridge;
+
+ encoder->bridge = bridge;
+ bridge->driver_private = dp;
+ bridge->encoder = encoder;
+ bridge->funcs = &exynos_dp_bridge_funcs;
+
+ ret = drm_bridge_attach(drm_dev, bridge);
+ if (ret) {
+ DRM_ERROR("failed to attach drm bridge\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+static void exynos_dp_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+}
+
+static void exynos_dp_enable(struct drm_encoder *encoder)
+{
+}
+
+static void exynos_dp_disable(struct drm_encoder *encoder)
+{
+}
+
static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
.mode_fixup = exynos_dp_mode_fixup,
.mode_set = exynos_dp_mode_set,
@@ -1238,7 +1289,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
}
}
- if (!dp->panel && !dp->bridge) {
+ if (!dp->panel && !dp->ptn_bridge) {
ret = exynos_dp_dt_parse_panel(dp);
if (ret)
return ret;
@@ -1365,9 +1416,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
if (endpoint) {
bridge_node = of_graph_get_remote_port_parent(endpoint);
if (bridge_node) {
- dp->bridge = of_drm_find_bridge(bridge_node);
+ dp->ptn_bridge = of_drm_find_bridge(bridge_node);
of_node_put(bridge_node);
- if (!dp->bridge)
+ if (!dp->ptn_bridge)
return -EPROBE_DEFER;
} else
return -EPROBE_DEFER;
diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
index e413b6f..66eec4b 100644
--- a/drivers/gpu/drm/exynos/exynos_dp_core.h
+++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
@@ -153,6 +153,7 @@ struct exynos_dp_device {
struct drm_connector connector;
struct drm_panel *panel;
struct drm_bridge *bridge;
+ struct drm_bridge *ptn_bridge;
struct clk *clock;
unsigned int irq;
void __iomem *reg_base;
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 03/17] drm: bridge: analogix/dp: fix some obvious code style
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-10-28 8:19 ` [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
@ 2015-10-28 8:23 ` Yakir Yang
2015-10-28 8:24 ` [PATCH v8 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
` (20 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:23 UTC (permalink / raw)
To: linux-arm-kernel
Fix some obvious alignment problems, like alignment and line
over 80 characters problems, make this easy to be maintained
later.
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Resequence this patch after analogix_dp driver have been split
from exynos_dp code, and rephrase reasonable commit message, and
remove some controversial style (Krzysztof)
- analogix_dp_write_byte_to_dpcd(
- dp, DP_TEST_RESPONSE,
+ analogix_dp_write_byte_to_dpcd(dp,
+ DP_TEST_RESPONSE,
DP_TEST_EDID_CHECKSUM_WRITE);
Changes in v4: None
Changes in v3: None
Changes in v2:
- Improved commit message more readable, and avoid using some
uncommon style like bellow: (Joe Preches)
- retval = exynos_dp_read_bytes_from_i2c(...
...);
+ retval =
+ exynos_dp_read_bytes_from_i2c(......);
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 129 ++++++++++-----------
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 72 ++++++------
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 124 ++++++++++----------
3 files changed, 163 insertions(+), 162 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index e561590..334181c 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -61,7 +61,7 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
while (analogix_dp_get_plug_in_status(dp) != 0) {
timeout_loop++;
- if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+ if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "failed to get hpd plug status\n");
return -ETIMEDOUT;
}
@@ -98,8 +98,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
/* Read Extension Flag, Number of 128-byte EDID extension blocks */
retval = analogix_dp_read_byte_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
- EDID_EXTENSION_FLAG,
- &extend_block);
+ EDID_EXTENSION_FLAG,
+ &extend_block);
if (retval)
return retval;
@@ -107,7 +107,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
dev_dbg(dp->dev, "EDID data includes a single extension!\n");
/* Read EDID data */
- retval = analogix_dp_read_bytes_from_i2c(dp, I2C_EDID_DEVICE_ADDR,
+ retval = analogix_dp_read_bytes_from_i2c(dp,
+ I2C_EDID_DEVICE_ADDR,
EDID_HEADER_PATTERN,
EDID_BLOCK_LENGTH,
&edid[EDID_HEADER_PATTERN]);
@@ -138,7 +139,7 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
}
analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
- &test_vector);
+ &test_vector);
if (test_vector & DP_TEST_LINK_EDID_READ) {
analogix_dp_write_byte_to_dpcd(dp,
DP_TEST_EDID_CHECKSUM,
@@ -152,10 +153,8 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
/* Read EDID data */
retval = analogix_dp_read_bytes_from_i2c(dp,
- I2C_EDID_DEVICE_ADDR,
- EDID_HEADER_PATTERN,
- EDID_BLOCK_LENGTH,
- &edid[EDID_HEADER_PATTERN]);
+ I2C_EDID_DEVICE_ADDR, EDID_HEADER_PATTERN,
+ EDID_BLOCK_LENGTH, &edid[EDID_HEADER_PATTERN]);
if (retval != 0) {
dev_err(dp->dev, "EDID Read failed!\n");
return -EIO;
@@ -166,16 +165,13 @@ static int analogix_dp_read_edid(struct analogix_dp_device *dp)
return -EIO;
}
- analogix_dp_read_byte_from_dpcd(dp,
- DP_TEST_REQUEST,
- &test_vector);
+ analogix_dp_read_byte_from_dpcd(dp, DP_TEST_REQUEST,
+ &test_vector);
if (test_vector & DP_TEST_LINK_EDID_READ) {
analogix_dp_write_byte_to_dpcd(dp,
- DP_TEST_EDID_CHECKSUM,
- edid[EDID_CHECKSUM]);
+ DP_TEST_EDID_CHECKSUM, edid[EDID_CHECKSUM]);
analogix_dp_write_byte_to_dpcd(dp,
- DP_TEST_RESPONSE,
- DP_TEST_EDID_CHECKSUM_WRITE);
+ DP_TEST_RESPONSE, DP_TEST_EDID_CHECKSUM_WRITE);
}
}
@@ -190,8 +186,7 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
int retval;
/* Read DPCD DP_DPCD_REV~RECEIVE_PORT1_CAP_1 */
- retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV,
- 12, buf);
+ retval = analogix_dp_read_bytes_from_dpcd(dp, DP_DPCD_REV, 12, buf);
if (retval)
return retval;
@@ -205,8 +200,9 @@ static int analogix_dp_handle_edid(struct analogix_dp_device *dp)
return retval;
}
-static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
- bool enable)
+static void
+analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp,
+ bool enable)
{
u8 data;
@@ -214,11 +210,11 @@ static void analogix_dp_enable_rx_to_enhanced_mode(struct analogix_dp_device *dp
if (enable)
analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
- DP_LANE_COUNT_ENHANCED_FRAME_EN |
- DPCD_LANE_COUNT_SET(data));
+ DP_LANE_COUNT_ENHANCED_FRAME_EN |
+ DPCD_LANE_COUNT_SET(data));
else
analogix_dp_write_byte_to_dpcd(dp, DP_LANE_COUNT_SET,
- DPCD_LANE_COUNT_SET(data));
+ DPCD_LANE_COUNT_SET(data));
}
static int analogix_dp_is_enhanced_mode_available(struct analogix_dp_device *dp)
@@ -245,13 +241,13 @@ static void analogix_dp_training_pattern_dis(struct analogix_dp_device *dp)
{
analogix_dp_set_training_pattern(dp, DP_NONE);
- analogix_dp_write_byte_to_dpcd(dp,
- DP_TRAINING_PATTERN_SET,
- DP_TRAINING_PATTERN_DISABLE);
+ analogix_dp_write_byte_to_dpcd(dp, DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
}
-static void analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
- int pre_emphasis, int lane)
+static void
+analogix_dp_set_lane_lane_pre_emphasis(struct analogix_dp_device *dp,
+ int pre_emphasis, int lane)
{
switch (lane) {
case 0:
@@ -291,8 +287,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
/* Setup RX configuration */
buf[0] = dp->link_train.link_rate;
buf[1] = dp->link_train.lane_count;
- retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET,
- 2, buf);
+ retval = analogix_dp_write_bytes_to_dpcd(dp, DP_LINK_BW_SET, 2, buf);
if (retval)
return retval;
@@ -328,7 +323,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
retval = analogix_dp_write_bytes_to_dpcd(dp, DP_TRAINING_LANE0_SET,
- lane_count, buf);
+ lane_count, buf);
return retval;
}
@@ -336,7 +331,7 @@ static int analogix_dp_link_start(struct analogix_dp_device *dp)
static unsigned char analogix_dp_get_lane_status(u8 link_status[2], int lane)
{
int shift = (lane & 1) * 4;
- u8 link_value = link_status[lane>>1];
+ u8 link_value = link_status[lane >> 1];
return (link_value >> shift) & 0xf;
}
@@ -355,7 +350,7 @@ static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count)
}
static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
- int lane_count)
+ int lane_count)
{
int lane;
u8 lane_status;
@@ -373,11 +368,11 @@ static int analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align,
return 0;
}
-static unsigned char analogix_dp_get_adjust_request_voltage(u8 adjust_request[2],
- int lane)
+static unsigned char
+analogix_dp_get_adjust_request_voltage(u8 adjust_request[2], int lane)
{
int shift = (lane & 1) * 4;
- u8 link_value = adjust_request[lane>>1];
+ u8 link_value = adjust_request[lane >> 1];
return (link_value >> shift) & 0x3;
}
@@ -387,13 +382,13 @@ static unsigned char analogix_dp_get_adjust_request_pre_emphasis(
int lane)
{
int shift = (lane & 1) * 4;
- u8 link_value = adjust_request[lane>>1];
+ u8 link_value = adjust_request[lane >> 1];
return ((link_value >> shift) & 0xc) >> 2;
}
static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
- u8 training_lane_set, int lane)
+ u8 training_lane_set, int lane)
{
switch (lane) {
case 0:
@@ -413,9 +408,9 @@ static void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp,
}
}
-static unsigned int analogix_dp_get_lane_link_training(
- struct analogix_dp_device *dp,
- int lane)
+static unsigned int
+analogix_dp_get_lane_link_training(struct analogix_dp_device *dp,
+ int lane)
{
u32 reg;
@@ -449,7 +444,7 @@ static void analogix_dp_reduce_link_rate(struct analogix_dp_device *dp)
}
static void analogix_dp_get_adjust_training_lane(struct analogix_dp_device *dp,
- u8 adjust_request[2])
+ u8 adjust_request[2])
{
int lane, lane_count;
u8 voltage_swing, pre_emphasis, training_lane;
@@ -622,7 +617,7 @@ static int analogix_dp_process_equalizer_training(struct analogix_dp_device *dp)
}
static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
- u8 *bandwidth)
+ u8 *bandwidth)
{
u8 data;
@@ -635,7 +630,7 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
}
static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
- u8 *lane_count)
+ u8 *lane_count)
{
u8 data;
@@ -648,8 +643,8 @@ static void analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp,
}
static void analogix_dp_init_training(struct analogix_dp_device *dp,
- enum link_lane_count_type max_lane,
- enum link_rate_type max_rate)
+ enum link_lane_count_type max_lane,
+ enum link_rate_type max_rate)
{
/*
* MACRO_RST must be applied after the PLL_LOCK to avoid
@@ -662,7 +657,7 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
- (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+ (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate);
dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -722,8 +717,7 @@ static int analogix_dp_sw_link_training(struct analogix_dp_device *dp)
}
static int analogix_dp_set_link_train(struct analogix_dp_device *dp,
- u32 count,
- u32 bwtype)
+ u32 count, u32 bwtype)
{
int i;
int retval;
@@ -759,7 +753,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
timeout_loop++;
if (analogix_dp_is_slave_video_stream_clock_on(dp) == 0)
break;
- if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+ if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT;
}
@@ -790,7 +784,7 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
} else if (done_count) {
done_count = 0;
}
- if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
+ if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
dev_err(dp->dev, "Timeout of video streamclk ok\n");
return -ETIMEDOUT;
}
@@ -804,25 +798,24 @@ static int analogix_dp_config_video(struct analogix_dp_device *dp)
return retval;
}
-static void analogix_dp_enable_scramble(struct analogix_dp_device *dp, bool enable)
+static void analogix_dp_enable_scramble(struct analogix_dp_device *dp,
+ bool enable)
{
u8 data;
if (enable) {
analogix_dp_enable_scrambling(dp);
- analogix_dp_read_byte_from_dpcd(dp,
- DP_TRAINING_PATTERN_SET,
- &data);
+ analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+ &data);
analogix_dp_write_byte_to_dpcd(dp,
DP_TRAINING_PATTERN_SET,
(u8)(data & ~DP_LINK_SCRAMBLING_DISABLE));
} else {
analogix_dp_disable_scrambling(dp);
- analogix_dp_read_byte_from_dpcd(dp,
- DP_TRAINING_PATTERN_SET,
- &data);
+ analogix_dp_read_byte_from_dpcd(dp, DP_TRAINING_PATTERN_SET,
+ &data);
analogix_dp_write_byte_to_dpcd(dp,
DP_TRAINING_PATTERN_SET,
(u8)(data | DP_LINK_SCRAMBLING_DISABLE));
@@ -895,7 +888,7 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
}
ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
- dp->video_info->link_rate);
+ dp->video_info->link_rate);
if (ret) {
dev_err(dp->dev, "unable to do link train\n");
return;
@@ -1083,8 +1076,8 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
struct device_node *dp_node = dev->of_node;
struct video_info *dp_video_config;
- dp_video_config = devm_kzalloc(dev,
- sizeof(*dp_video_config), GFP_KERNEL);
+ dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
+ GFP_KERNEL);
if (!dp_video_config)
return ERR_PTR(-ENOMEM);
@@ -1098,37 +1091,37 @@ static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
of_property_read_bool(dp_node, "interlaced");
if (of_property_read_u32(dp_node, "samsung,color-space",
- &dp_video_config->color_space)) {
+ &dp_video_config->color_space)) {
dev_err(dev, "failed to get color-space\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,dynamic-range",
- &dp_video_config->dynamic_range)) {
+ &dp_video_config->dynamic_range)) {
dev_err(dev, "failed to get dynamic-range\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
- &dp_video_config->ycbcr_coeff)) {
+ &dp_video_config->ycbcr_coeff)) {
dev_err(dev, "failed to get ycbcr-coeff\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,color-depth",
- &dp_video_config->color_depth)) {
+ &dp_video_config->color_depth)) {
dev_err(dev, "failed to get color-depth\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,link-rate",
- &dp_video_config->link_rate)) {
+ &dp_video_config->link_rate)) {
dev_err(dev, "failed to get link-rate\n");
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(dp_node, "samsung,lane-count",
- &dp_video_config->lane_count)) {
+ &dp_video_config->lane_count)) {
dev_err(dev, "failed to get lane-count\n");
return ERR_PTR(-EINVAL);
}
@@ -1239,7 +1232,7 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
analogix_dp_init_dp(dp);
ret = devm_request_irq(&pdev->dev, dp->irq, analogix_dp_irq_handler,
- irq_flags, "analogix-dp", dp);
+ irq_flags, "analogix-dp", dp);
if (ret) {
dev_err(&pdev->dev, "failed to request irq\n");
return ret;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 65ce7f1..14d20be 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -187,50 +187,55 @@ int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp);
void analogix_dp_enable_sw_function(struct analogix_dp_device *dp);
int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp);
int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned char data);
+ unsigned int reg_addr,
+ unsigned char data);
int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned char *data);
+ unsigned int reg_addr,
+ unsigned char *data);
int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char data[]);
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[]);
int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char data[]);
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[]);
int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
- unsigned int device_addr,
- unsigned int reg_addr);
+ unsigned int device_addr,
+ unsigned int reg_addr);
int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
- unsigned int device_addr,
- unsigned int reg_addr,
- unsigned int *data);
+ unsigned int device_addr,
+ unsigned int reg_addr,
+ unsigned int *data);
int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
- unsigned int device_addr,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char edid[]);
+ unsigned int device_addr,
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char edid[]);
void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype);
void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype);
void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count);
void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count);
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+ bool enable);
void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
- enum pattern_set pattern);
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level);
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level);
+ enum pattern_set pattern);
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level);
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level);
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level);
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level);
void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
- u32 training_lane);
+ u32 training_lane);
void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
- u32 training_lane);
+ u32 training_lane);
void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
- u32 training_lane);
+ u32 training_lane);
void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
- u32 training_lane);
+ u32 training_lane);
u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp);
u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp);
@@ -241,11 +246,12 @@ void analogix_dp_init_video(struct analogix_dp_device *dp);
void analogix_dp_set_video_color_format(struct analogix_dp_device *dp);
int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp);
void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
- enum clock_recovery_m_value_type type,
- u32 m_value,
- u32 n_value);
+ enum clock_recovery_m_value_type type,
+ u32 m_value,
+ u32 n_value);
void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type);
-void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable);
+void analogix_dp_enable_video_master(struct analogix_dp_device *dp,
+ bool enable);
void analogix_dp_start_video(struct analogix_dp_device *dp);
int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 442cc66..a388c0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -54,10 +54,10 @@ void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable)
if (enable)
reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
- LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
+ LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
else
reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
- LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
+ LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP);
}
@@ -202,8 +202,8 @@ void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable)
}
void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
- enum analog_power_block block,
- bool enable)
+ enum analog_power_block block,
+ bool enable)
{
u32 reg;
@@ -399,8 +399,8 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
analogix_dp_reset_aux(dp);
/* Disable AUX transaction H/W retry */
- reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
- AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+ reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
+ AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
@@ -483,8 +483,8 @@ int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp)
}
int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned char data)
+ unsigned int reg_addr,
+ unsigned char data)
{
u32 reg;
int i;
@@ -519,17 +519,16 @@ int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp,
retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0)
break;
- else
- dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
- __func__);
+
+ dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
}
return retval;
}
int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned char *data)
+ unsigned int reg_addr,
+ unsigned char *data)
{
u32 reg;
int i;
@@ -560,9 +559,8 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0)
break;
- else
- dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
- __func__);
+
+ dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
}
/* Read data buffer */
@@ -573,9 +571,9 @@ int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp,
}
int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char data[])
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[])
{
u32 reg;
unsigned int start_offset;
@@ -608,8 +606,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
for (cur_data_idx = 0; cur_data_idx < cur_data_count;
cur_data_idx++) {
reg = data[start_offset + cur_data_idx];
- writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0
- + 4 * cur_data_idx);
+ writel(reg, dp->reg_base +
+ ANALOGIX_DP_BUF_DATA_0 +
+ 4 * cur_data_idx);
}
/*
@@ -625,9 +624,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0)
break;
- else
- dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
- __func__);
+
+ dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+ __func__);
}
start_offset += cur_data_count;
@@ -637,9 +636,9 @@ int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp,
}
int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char data[])
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char data[])
{
u32 reg;
unsigned int start_offset;
@@ -683,9 +682,9 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0)
break;
- else
- dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
- __func__);
+
+ dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+ __func__);
}
for (cur_data_idx = 0; cur_data_idx < cur_data_count;
@@ -703,8 +702,8 @@ int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp,
}
int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
- unsigned int device_addr,
- unsigned int reg_addr)
+ unsigned int device_addr,
+ unsigned int reg_addr)
{
u32 reg;
int retval;
@@ -736,9 +735,9 @@ int analogix_dp_select_i2c_device(struct analogix_dp_device *dp,
}
int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
- unsigned int device_addr,
- unsigned int reg_addr,
- unsigned int *data)
+ unsigned int device_addr,
+ unsigned int reg_addr,
+ unsigned int *data)
{
u32 reg;
int i;
@@ -750,7 +749,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL);
/* Select EDID device */
- retval = analogix_dp_select_i2c_device(dp, device_addr, reg_addr);
+ retval = analogix_dp_select_i2c_device(dp, device_addr,
+ reg_addr);
if (retval != 0)
continue;
@@ -767,9 +767,8 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0)
break;
- else
- dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
- __func__);
+
+ dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
}
/* Read data */
@@ -780,10 +779,10 @@ int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp,
}
int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
- unsigned int device_addr,
- unsigned int reg_addr,
- unsigned int count,
- unsigned char edid[])
+ unsigned int device_addr,
+ unsigned int reg_addr,
+ unsigned int count,
+ unsigned char edid[])
{
u32 reg;
unsigned int i, j;
@@ -828,15 +827,14 @@ int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp,
retval = analogix_dp_start_aux_transaction(dp);
if (retval == 0)
break;
- else
- dev_dbg(dp->dev,
- "%s: Aux Transaction fail!\n",
- __func__);
+
+ dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
+ __func__);
}
/* Check if Rx sends defer */
reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM);
if (reg == AUX_RX_COMM_AUX_DEFER ||
- reg == AUX_RX_COMM_I2C_DEFER) {
+ reg == AUX_RX_COMM_I2C_DEFER) {
dev_err(dp->dev, "Defer: %d\n\n", reg);
defer = 1;
}
@@ -885,7 +883,8 @@ void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count)
*count = reg;
}
-void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable)
+void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp,
+ bool enable)
{
u32 reg;
@@ -901,7 +900,7 @@ void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, bool enable
}
void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
- enum pattern_set pattern)
+ enum pattern_set pattern)
{
u32 reg;
@@ -933,7 +932,8 @@ void analogix_dp_set_training_pattern(struct analogix_dp_device *dp,
}
}
-void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level)
{
u32 reg;
@@ -943,7 +943,8 @@ void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, u32 level
writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL);
}
-void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level)
{
u32 reg;
@@ -953,7 +954,8 @@ void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, u32 level
writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL);
}
-void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level)
{
u32 reg;
@@ -963,7 +965,8 @@ void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, u32 level
writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL);
}
-void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level)
+void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp,
+ u32 level)
{
u32 reg;
@@ -974,7 +977,7 @@ void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, u32 level
}
void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
- u32 training_lane)
+ u32 training_lane)
{
u32 reg;
@@ -983,7 +986,7 @@ void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp,
}
void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp,
- u32 training_lane)
+ u32 training_lane)
{
u32 reg;
@@ -1001,7 +1004,7 @@ void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp,
}
void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp,
- u32 training_lane)
+ u32 training_lane)
{
u32 reg;
@@ -1125,9 +1128,8 @@ int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp)
}
void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp,
- enum clock_recovery_m_value_type type,
- u32 m_value,
- u32 n_value)
+ enum clock_recovery_m_value_type type,
+ u32 m_value, u32 n_value)
{
u32 reg;
@@ -1221,7 +1223,7 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
u32 reg;
reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
- reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
+ reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N);
reg |= MASTER_VID_FUNC_EN_N;
writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1);
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-10-28 8:19 ` [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2015-10-28 8:23 ` [PATCH v8 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
@ 2015-10-28 8:24 ` Yakir Yang
2015-10-28 8:25 ` [PATCH v8 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
` (19 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:24 UTC (permalink / raw)
To: linux-arm-kernel
link_rate and lane_count already configured in analogix_dp_set_link_train(),
so we don't need to config those repeatly after training finished, just
remove them out.
Beside Display Port 1.2 already support 5.4Gbps link rate, the maximum sets
would change from {1.62Gbps, 2.7Gbps} to {1.62Gbps, 2.7Gbps, 5.4Gbps}.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Update commit message more readable. (Jingoo)
- Adjust the order from 05 to 04
Changes in v3:
- The link_rate and lane_count shouldn't config to the DT property value
directly, but we can take those as hardware limite. For example, RK3288
only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
like "link-rate = 0x0a" "lane-count = 4". (Thierry)
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 8 ++++----
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 5 +++--
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 334181c..96afb67 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -624,6 +624,8 @@ static void analogix_dp_get_max_rx_bandwidth(struct analogix_dp_device *dp,
/*
* For DP rev.1.1, Maximum link rate of Main Link lanes
* 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps
+ * For DP rev.1.2, Maximum link rate of Main Link lanes
+ * 0x06 = 1.62 Gbps, 0x0a = 2.7 Gbps, 0x14 = 5.4Gbps
*/
analogix_dp_read_byte_from_dpcd(dp, DP_MAX_LINK_RATE, &data);
*bandwidth = data;
@@ -657,7 +659,8 @@ static void analogix_dp_init_training(struct analogix_dp_device *dp,
analogix_dp_get_max_rx_lane_count(dp, &dp->link_train.lane_count);
if ((dp->link_train.link_rate != LINK_RATE_1_62GBPS) &&
- (dp->link_train.link_rate != LINK_RATE_2_70GBPS)) {
+ (dp->link_train.link_rate != LINK_RATE_2_70GBPS) &&
+ (dp->link_train.link_rate != LINK_RATE_5_40GBPS)) {
dev_err(dp->dev, "Rx Max Link Rate is abnormal :%x !\n",
dp->link_train.link_rate);
dp->link_train.link_rate = LINK_RATE_1_62GBPS;
@@ -898,9 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
analogix_dp_enable_rx_to_enhanced_mode(dp, 1);
analogix_dp_enable_enhanced_mode(dp, 1);
- analogix_dp_set_lane_count(dp, dp->video_info->lane_count);
- analogix_dp_set_link_bandwidth(dp, dp->video_info->link_rate);
-
analogix_dp_init_video(dp);
ret = analogix_dp_config_video(dp);
if (ret)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 14d20be..9a90a18 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -21,8 +21,9 @@
#define MAX_EQ_LOOP 5
enum link_rate_type {
- LINK_RATE_1_62GBPS = 0x06,
- LINK_RATE_2_70GBPS = 0x0a
+ LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
+ LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
+ LINK_RATE_5_40GBPS = DP_LINK_BW_5_4,
};
enum link_lane_count_type {
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (2 preceding siblings ...)
2015-10-28 8:24 ` [PATCH v8 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
@ 2015-10-28 8:25 ` Yakir Yang
2015-10-28 8:26 ` [PATCH v8 06/17] dt-bindings: add document for analogix display port driver Yakir Yang
` (18 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:25 UTC (permalink / raw)
To: linux-arm-kernel
Both hsync/vsync polarity and interlace mode can be parsed from
drm display mode, and dynamic_range and ycbcr_coeff can be judge
by the video code.
But presumably Exynos still relies on the DT properties, so take
good use of mode_fixup() in to achieve the compatibility hacks.
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7:
- Back to use the of_property_read_bool() interfacs to provoid backward
compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
to avoid -EOVERFLOW error (Krzysztof)
Changes in v6: None
Changes in v5:
- Switch video timing type to "u32", so driver could use "of_property_read_u32"
to get the backword timing values. Krzysztof suggest me that driver could use
the "of_property_read_bool" to get backword timing values, but that interfacs
would modify the original drm_display_mode timing directly (whether those
properties exists or not).
Changes in v4:
- Provide backword compatibility with samsung. (Krzysztof)
Changes in v3:
- Dynamic parse video timing info from struct drm_display_mode and
struct drm_display_info. (Thierry)
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 148 +++++++++++++--------
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 +-
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 14 +-
3 files changed, 103 insertions(+), 61 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 96afb67..6307060 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
return;
}
- ret = analogix_dp_set_link_train(dp, dp->video_info->lane_count,
- dp->video_info->link_rate);
+ ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
+ dp->video_info.link_rate);
if (ret) {
dev_err(dp->dev, "unable to do link train\n");
return;
@@ -1030,6 +1030,85 @@ static void analogix_dp_bridge_disable(struct drm_bridge *bridge)
dp->dpms_mode = DRM_MODE_DPMS_OFF;
}
+static void analogix_dp_bridge_mode_set(struct drm_bridge *bridge,
+ struct drm_display_mode *orig_mode,
+ struct drm_display_mode *mode)
+{
+ struct analogix_dp_device *dp = bridge->driver_private;
+ struct drm_display_info *display_info = &dp->connector->display_info;
+ struct video_info *video = &dp->video_info;
+ struct device_node *dp_node = dp->dev->of_node;
+ int vic;
+
+ /* Input video interlaces & hsync pol & vsync pol */
+ video->interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
+ video->v_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NVSYNC);
+ video->h_sync_polarity = !!(mode->flags & DRM_MODE_FLAG_NHSYNC);
+
+ /* Input video dynamic_range & colorimetry */
+ vic = drm_match_cea_mode(mode);
+ if ((vic == 6) || (vic == 7) || (vic == 21) || (vic == 22) ||
+ (vic == 2) || (vic == 3) || (vic == 17) || (vic == 18)) {
+ video->dynamic_range = CEA;
+ video->ycbcr_coeff = COLOR_YCBCR601;
+ } else if (vic) {
+ video->dynamic_range = CEA;
+ video->ycbcr_coeff = COLOR_YCBCR709;
+ } else {
+ video->dynamic_range = VESA;
+ video->ycbcr_coeff = COLOR_YCBCR709;
+ }
+
+ /* Input vide bpc and color_formats */
+ switch (display_info->bpc) {
+ case 12:
+ video->color_depth = COLOR_12;
+ break;
+ case 10:
+ video->color_depth = COLOR_10;
+ break;
+ case 8:
+ video->color_depth = COLOR_8;
+ break;
+ case 6:
+ video->color_depth = COLOR_6;
+ break;
+ default:
+ video->color_depth = COLOR_8;
+ break;
+ }
+ if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB444)
+ video->color_space = COLOR_YCBCR444;
+ else if (display_info->color_formats & DRM_COLOR_FORMAT_YCRCB422)
+ video->color_space = COLOR_YCBCR422;
+ else if (display_info->color_formats & DRM_COLOR_FORMAT_RGB444)
+ video->color_space = COLOR_RGB;
+ else
+ video->color_space = COLOR_RGB;
+
+ /*
+ * NOTE: those property parsing code is used for providing backward
+ * compatibility for samsung platform.
+ * Due to we used the "of_property_read_u32" interfaces, when this
+ * property isn't present, the "video_info" can keep the original
+ * values and wouldn't be modified.
+ */
+ of_property_read_u32(dp_node, "samsung,color-space",
+ &video->color_space);
+ of_property_read_u32(dp_node, "samsung,dynamic-range",
+ &video->dynamic_range);
+ of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
+ &video->ycbcr_coeff);
+ of_property_read_u32(dp_node, "samsung,color-depth",
+ &video->color_depth);
+ if (of_property_read_bool(dp_node, "hsync-active-high"))
+ video->h_sync_polarity = true;
+ if (of_property_read_bool(dp_node, "vsync-active-high"))
+ video->v_sync_polarity = true;
+ if (of_property_read_bool(dp_node, "interlaced"))
+ video->interlaced = true;
+}
+
static void analogix_dp_bridge_nop(struct drm_bridge *bridge)
{
/* do nothing */
@@ -1040,6 +1119,7 @@ static const struct drm_bridge_funcs analogix_dp_bridge_funcs = {
.disable = analogix_dp_bridge_disable,
.pre_enable = analogix_dp_bridge_nop,
.post_disable = analogix_dp_bridge_nop,
+ .mode_set = analogix_dp_bridge_mode_set,
.attach = analogix_dp_bridge_attach,
};
@@ -1071,62 +1151,24 @@ static int analogix_dp_create_bridge(struct drm_device *drm_dev,
return 0;
}
-static struct video_info *analogix_dp_dt_parse_pdata(struct device *dev)
+static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
{
- struct device_node *dp_node = dev->of_node;
- struct video_info *dp_video_config;
-
- dp_video_config = devm_kzalloc(dev, sizeof(*dp_video_config),
- GFP_KERNEL);
- if (!dp_video_config)
- return ERR_PTR(-ENOMEM);
-
- dp_video_config->h_sync_polarity =
- of_property_read_bool(dp_node, "hsync-active-high");
-
- dp_video_config->v_sync_polarity =
- of_property_read_bool(dp_node, "vsync-active-high");
-
- dp_video_config->interlaced =
- of_property_read_bool(dp_node, "interlaced");
-
- if (of_property_read_u32(dp_node, "samsung,color-space",
- &dp_video_config->color_space)) {
- dev_err(dev, "failed to get color-space\n");
- return ERR_PTR(-EINVAL);
- }
-
- if (of_property_read_u32(dp_node, "samsung,dynamic-range",
- &dp_video_config->dynamic_range)) {
- dev_err(dev, "failed to get dynamic-range\n");
- return ERR_PTR(-EINVAL);
- }
-
- if (of_property_read_u32(dp_node, "samsung,ycbcr-coeff",
- &dp_video_config->ycbcr_coeff)) {
- dev_err(dev, "failed to get ycbcr-coeff\n");
- return ERR_PTR(-EINVAL);
- }
-
- if (of_property_read_u32(dp_node, "samsung,color-depth",
- &dp_video_config->color_depth)) {
- dev_err(dev, "failed to get color-depth\n");
- return ERR_PTR(-EINVAL);
- }
+ struct device_node *dp_node = dp->dev->of_node;
+ struct video_info *video_info = &dp->video_info;
if (of_property_read_u32(dp_node, "samsung,link-rate",
- &dp_video_config->link_rate)) {
- dev_err(dev, "failed to get link-rate\n");
- return ERR_PTR(-EINVAL);
+ &video_info->link_rate)) {
+ dev_err(dp->dev, "failed to get link-rate\n");
+ return -EINVAL;
}
if (of_property_read_u32(dp_node, "samsung,lane-count",
- &dp_video_config->lane_count)) {
- dev_err(dev, "failed to get lane-count\n");
- return ERR_PTR(-EINVAL);
+ &video_info->lane_count)) {
+ dev_err(dp->dev, "failed to get lane-count\n");
+ return -EINVAL;
}
- return dp_video_config;
+ return 0;
}
int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
@@ -1159,9 +1201,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
*/
dp->plat_data = plat_data;
- dp->video_info = analogix_dp_dt_parse_pdata(&pdev->dev);
- if (IS_ERR(dp->video_info))
- return PTR_ERR(dp->video_info);
+ ret = analogix_dp_dt_parse_pdata(dp);
+ if (ret)
+ return ret;
dp->phy = devm_phy_get(dp->dev, "dp");
if (IS_ERR(dp->phy)) {
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index 9a90a18..e37cef6 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -154,7 +154,7 @@ struct analogix_dp_device {
unsigned int irq;
void __iomem *reg_base;
- struct video_info *video_info;
+ struct video_info video_info;
struct link_train link_train;
struct work_struct hotplug_work;
struct phy *phy;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index a388c0a..861097a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -1084,15 +1084,15 @@ void analogix_dp_set_video_color_format(struct analogix_dp_device *dp)
u32 reg;
/* Configure the input color depth, color space, dynamic range */
- reg = (dp->video_info->dynamic_range << IN_D_RANGE_SHIFT) |
- (dp->video_info->color_depth << IN_BPC_SHIFT) |
- (dp->video_info->color_space << IN_COLOR_F_SHIFT);
+ reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) |
+ (dp->video_info.color_depth << IN_BPC_SHIFT) |
+ (dp->video_info.color_space << IN_COLOR_F_SHIFT);
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2);
/* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3);
reg &= ~IN_YC_COEFFI_MASK;
- if (dp->video_info->ycbcr_coeff)
+ if (dp->video_info.ycbcr_coeff)
reg |= IN_YC_COEFFI_ITU709;
else
reg |= IN_YC_COEFFI_ITU601;
@@ -1229,17 +1229,17 @@ void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp)
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~INTERACE_SCAN_CFG;
- reg |= (dp->video_info->interlaced << 2);
+ reg |= (dp->video_info.interlaced << 2);
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~VSYNC_POLARITY_CFG;
- reg |= (dp->video_info->v_sync_polarity << 1);
+ reg |= (dp->video_info.v_sync_polarity << 1);
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg &= ~HSYNC_POLARITY_CFG;
- reg |= (dp->video_info->h_sync_polarity << 0);
+ reg |= (dp->video_info.h_sync_polarity << 0);
writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10);
reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 06/17] dt-bindings: add document for analogix display port driver
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (3 preceding siblings ...)
2015-10-28 8:25 ` [PATCH v8 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
@ 2015-10-28 8:26 ` Yakir Yang
2015-10-28 20:02 ` Heiko Stuebner
2015-10-28 8:27 ` [PATCH v8 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
` (17 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:26 UTC (permalink / raw)
To: linux-arm-kernel
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8:
- Correct the right document path of display-timing.txt (Heiko)
- Correct the misspell of 'from' to 'frm'. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Split all DTS changes, and provide backward compatibility. Mark old
properties as deprecated but still support them. (Krzysztof)
- Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
- Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
"analogix,color-space" & "analogix,color-depth" &
"analogix,link-rate" & "analogix,lane-count" &
"analogix,ycbcr-coeff" & "analogix,dynamic-range" &
"vsync-active-high" & "hsync-active-high" & "interlaces"
Changes in v3:
- Add devicetree binding documents. (Heiko)
- Remove sync pol & colorimetry properies from the new analogix dp driver
devicetree binding. (Thierry)
- Update the exist exynos dtsi file with the latest DP DT properies.
Changes in v2: None
.../bindings/display/bridge/analogix_dp.txt | 50 +++++++++++++++++
.../bindings/display/exynos/exynos_dp.txt | 65 ++++++++--------------
2 files changed, 72 insertions(+), 43 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
new file mode 100644
index 0000000..7659a7a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -0,0 +1,50 @@
+Analogix Display Port bridge bindings
+
+Required properties for dp-controller:
+ -compatible:
+ platform specific such as:
+ * "samsung,exynos5-dp"
+ * "rockchip,rk3288-dp"
+ -reg:
+ physical base address of the controller and length
+ of memory mapped region.
+ -interrupts:
+ interrupt combiner values.
+ -clocks:
+ from common clock binding: handle to dp clock.
+ -clock-names:
+ from common clock binding: Shall be "dp".
+ -interrupt-parent:
+ phandle to Interrupt combiner node.
+ -phys:
+ from general PHY binding: the phandle for the PHY device.
+ -phy-names:
+ from general PHY binding: Should be "dp".
+
+Optional properties for dp-controller:
+ -hpd-gpios:
+ Hotplug detect GPIO.
+ Indicates which GPIO should be used for hotplug detection
+ -port@[X]: SoC specific port nodes with endpoint definitions as defined
+ in Documentation/devicetree/bindings/media/video-interfaces.txt,
+ please refer to the SoC specific binding document:
+ * Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+ * Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
+
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+-------------------------------------------------------------------------------
+
+Example:
+
+ dp-controller {
+ compatible = "samsung,exynos5-dp";
+ reg = <0x145b0000 0x10000>;
+ interrupts = <10 3>;
+ interrupt-parent = <&combiner>;
+ clocks = <&clock 342>;
+ clock-names = "dp";
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+ };
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index 7a3a9cd..9905081 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -31,45 +31,31 @@ Required properties for dp-controller:
from general PHY binding: the phandle for the PHY device.
-phy-names:
from general PHY binding: Should be "dp".
- -samsung,color-space:
- input video data format.
- COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
- -samsung,dynamic-range:
- dynamic range for input video data.
- VESA = 0, CEA = 1
- -samsung,ycbcr-coeff:
- YCbCr co-efficients for input video.
- COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
- -samsung,color-depth:
- number of bits per colour component.
- COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
- -samsung,link-rate:
- link rate supported by the panel.
- LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
- -samsung,lane-count:
- number of lanes supported by the panel.
- LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
- - display-timings: timings for the connected panel as described by
- Documentation/devicetree/bindings/video/display-timing.txt
Optional properties for dp-controller:
- -interlaced:
- interlace scan mode.
- Progressive if defined, Interlaced if not defined
- -vsync-active-high:
- VSYNC polarity configuration.
- High if defined, Low if not defined
- -hsync-active-high:
- HSYNC polarity configuration.
- High if defined, Low if not defined
- -samsung,hpd-gpio:
- Hotplug detect GPIO.
- Indicates which GPIO should be used for hotplug
- detection
- -video interfaces: Device node can contain video interface port
- nodes according to [1].
+ - display-timings: timings for the connected panel as described by
+ Documentation/devicetree/bindings/display/panel/display-timing.txt
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+ -phys (required)
+ -phy-names (required)
+ -hpd-gpios (optional)
+ -video interfaces (optional)
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+Deprecated properties for DisplayPort:
+-interlaced: deprecated prop that can parsed from drm_display_mode.
+-vsync-active-high: deprecated prop that can parsed from drm_display_mode.
+-hsync-active-high: deprecated prop that can parsed from drm_display_mode.
+-samsung,ycbcr-coeff: deprecated prop that can parsed from drm_display_mode.
+-samsung,dynamic-range: deprecated prop that can parsed from drm_display_mode.
+-samsung,color-space: deprecated prop that can parsed from drm_display_info.
+-samsung,color-depth: deprecated prop that can parsed from drm_display_info.
+-samsung,link-rate: deprecated prop that can reading from monitor by dpcd method.
+-samsung,lane-count: deprecated prop that can reading from monitor by dpcd method.
+-samsung,hpd-gpio: deprecated name for hpd-gpios.
+
+-------------------------------------------------------------------------------
Example:
@@ -88,13 +74,6 @@ SOC specific portion:
Board Specific portion:
dp-controller {
- samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
- samsung,color-depth = <1>;
- samsung,link-rate = <0x0a>;
- samsung,lane-count = <4>;
-
display-timings {
native-mode = <&lcd_timing>;
lcd_timing: 1366x768 {
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (4 preceding siblings ...)
2015-10-28 8:26 ` [PATCH v8 06/17] dt-bindings: add document for analogix display port driver Yakir Yang
@ 2015-10-28 8:27 ` Yakir Yang
2015-10-28 8:27 ` [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
` (16 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:27 UTC (permalink / raw)
To: linux-arm-kernel
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6:
- Fix Peach Pit hpd property name error:
- hpd-gpio = <&gpx2 6 0>;
+ hpd-gpios = <&gpx2 6 0>;
Changes in v5:
- Correct the misspell in commit message. (Krzysztof)
Changes in v4:
- Separate all DTS changes to a separate patch. (Krzysztof)
Changes in v3: None
Changes in v2: None
arch/arm/boot/dts/exynos5250-arndale.dts | 2 --
arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 --
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +---
arch/arm/boot/dts/exynos5250-spring.dts | 4 +---
arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +---
arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 --
arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +---
7 files changed, 4 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts
index c000532..b1790cf 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts/exynos5250-arndale.dts
@@ -124,8 +124,6 @@
&dp {
status = "okay";
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 0f5dcd4..f30c2db 100644
--- a/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -80,8 +80,6 @@
&dp {
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5250-snow-common.dtsi b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
index 0a7f408..ee94110 100644
--- a/arch/arm/boot/dts/exynos5250-snow-common.dtsi
+++ b/arch/arm/boot/dts/exynos5250-snow-common.dtsi
@@ -236,12 +236,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx0 7 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpx0 7 GPIO_ACTIVE_HIGH>;
ports {
port at 0 {
diff --git a/arch/arm/boot/dts/exynos5250-spring.dts b/arch/arm/boot/dts/exynos5250-spring.dts
index c1edd6d..91881d7 100644
--- a/arch/arm/boot/dts/exynos5250-spring.dts
+++ b/arch/arm/boot/dts/exynos5250-spring.dts
@@ -74,12 +74,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <1>;
- samsung,hpd-gpio = <&gpc3 0 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpc3 0 GPIO_ACTIVE_HIGH>;
};
&ehci {
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts
index 72ba6f0..8baf40a 100644
--- a/arch/arm/boot/dts/exynos5420-peach-pit.dts
+++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts
@@ -148,12 +148,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x06>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
ports {
port at 0 {
diff --git a/arch/arm/boot/dts/exynos5420-smdk5420.dts b/arch/arm/boot/dts/exynos5420-smdk5420.dts
index ac35aef..f67344f 100644
--- a/arch/arm/boot/dts/exynos5420-smdk5420.dts
+++ b/arch/arm/boot/dts/exynos5420-smdk5420.dts
@@ -93,8 +93,6 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
diff --git a/arch/arm/boot/dts/exynos5800-peach-pi.dts b/arch/arm/boot/dts/exynos5800-peach-pi.dts
index 49a4f43..e5a4cd5 100644
--- a/arch/arm/boot/dts/exynos5800-peach-pi.dts
+++ b/arch/arm/boot/dts/exynos5800-peach-pi.dts
@@ -142,12 +142,10 @@
pinctrl-names = "default";
pinctrl-0 = <&dp_hpd_gpio>;
samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <2>;
- samsung,hpd-gpio = <&gpx2 6 GPIO_ACTIVE_HIGH>;
+ hpd-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>;
panel = <&panel>;
};
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (5 preceding siblings ...)
2015-10-28 8:27 ` [PATCH v8 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
@ 2015-10-28 8:27 ` Yakir Yang
2015-11-27 8:41 ` Heiko Stübner
2015-10-28 8:28 ` [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
` (15 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:27 UTC (permalink / raw)
To: linux-arm-kernel
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Remove the empty line at the end of document, and correct the endpoint
numbers in the example DT node, and remove the regulator iomux setting
in driver code while using the pinctl in devicetree instead. (Heiko)
- Add device type declared, cause the previous "platform device type
support (v4 11/16)" already merge into (v5 02/14).
- Implement connector registration code. (Thierry)
Changes in v4:
- Remove some deprecated DT properties in rockchip dp document.
Changes in v3:
- Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
and leave "sclk_edp" to analogix dp core driver which name to "dp",
and leave "pclk_edp" to rockchip dp platform driver which name to
"pclk". (Thierry & Heiko)
- Add devicetree binding document. (Heiko)
- Remove "rockchip,panel" DT property, take use of remote point to get panel
node. (Heiko)
- Add the new function point dp_platdata->get_modes() init.
Changes in v2:
- Get panel node with remote-endpoint method, and create devicetree binding
for driver. (Heiko)
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
drivers/gpu/drm/rockchip/Kconfig | 9 +
drivers/gpu/drm/rockchip/Makefile | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 442 ++++++++++++++++++++++++
include/drm/bridge/analogix_dp.h | 1 +
4 files changed, 453 insertions(+)
create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
diff --git a/drivers/gpu/drm/rockchip/Kconfig b/drivers/gpu/drm/rockchip/Kconfig
index 35215f6..c2ba945 100644
--- a/drivers/gpu/drm/rockchip/Kconfig
+++ b/drivers/gpu/drm/rockchip/Kconfig
@@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
for the Synopsys DesignWare HDMI driver. If you want to
enable HDMI on RK3288 based SoC, you should selet this
option.
+
+config ROCKCHIP_ANALOGIX_DP
+ tristate "Rockchip specific extensions for Analogix DP driver"
+ depends on DRM_ROCKCHIP
+ select DRM_ANALOGIX_DP
+ help
+ This selects support for Rockchip SoC specific extensions
+ for the Analogix Core DP driver. If you want to enable DP
+ on RK3288 based SoC, you should selet this option.
diff --git a/drivers/gpu/drm/rockchip/Makefile b/drivers/gpu/drm/rockchip/Makefile
index f3d8a19..8ad01fb 100644
--- a/drivers/gpu/drm/rockchip/Makefile
+++ b/drivers/gpu/drm/rockchip/Makefile
@@ -6,5 +6,6 @@ rockchipdrm-y := rockchip_drm_drv.o rockchip_drm_fb.o rockchip_drm_fbdev.o \
rockchip_drm_gem.o
obj-$(CONFIG_ROCKCHIP_DW_HDMI) += dw_hdmi-rockchip.o
+obj-$(CONFIG_ROCKCHIP_ANALOGIX_DP) += analogix_dp-rockchip.o
obj-$(CONFIG_DRM_ROCKCHIP) += rockchipdrm.o rockchip_drm_vop.o
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
new file mode 100644
index 0000000..2c82a9a
--- /dev/null
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -0,0 +1,442 @@
+/*
+ * Rockchip SoC DP (Display Port) interface driver.
+ *
+ * Copyright (C) Fuzhou Rockchip Electronics Co., Ltd.
+ * Author: Andy Yan <andy.yan@rock-chips.com>
+ * Yakir Yang <ykk@rock-chips.com>
+ * Jeff Chen <jeff.chen@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/component.h>
+#include <linux/mfd/syscon.h>
+#include <linux/of_graph.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/clk.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_dp_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+
+#include <video/of_videomode.h>
+#include <video/videomode.h>
+
+#include <drm/bridge/analogix_dp.h>
+
+#include "rockchip_drm_drv.h"
+#include "rockchip_drm_vop.h"
+
+#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
+
+/* dp grf register offset */
+#define GRF_SOC_CON6 0x025c
+#define GRF_EDP_LCD_SEL_MASK BIT(5)
+#define GRF_EDP_SEL_VOP_LIT BIT(5)
+#define GRF_EDP_SEL_VOP_BIG 0
+
+struct rockchip_dp_device {
+ struct drm_device *drm_dev;
+ struct device *dev;
+ struct drm_encoder encoder;
+ struct drm_connector connector;
+ struct drm_display_mode mode;
+
+ struct clk *pclk;
+ struct regmap *grf;
+ struct reset_control *rst;
+
+ struct analogix_dp_plat_data plat_data;
+};
+
+static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
+{
+ reset_control_assert(dp->rst);
+ usleep_range(10, 20);
+ reset_control_deassert(dp->rst);
+
+ return 0;
+}
+
+static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
+{
+ struct rockchip_dp_device *dp = to_dp(plat_data);
+ int ret;
+
+ ret = clk_prepare_enable(dp->pclk);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+ return ret;
+ }
+
+ ret = rockchip_dp_pre_init(dp);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to dp pre init %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
+{
+ struct rockchip_dp_device *dp = to_dp(plat_data);
+
+ clk_disable_unprepare(dp->pclk);
+
+ return 0;
+}
+
+static int rockchip_dp_get_modes(struct drm_connector *connector)
+{
+ struct rockchip_dp_device *dp = to_dp(connector);
+
+ return analogix_dp_get_modes(dp->dev);
+}
+
+static struct drm_encoder *
+rockchip_dp_best_encoder(struct drm_connector *connector)
+{
+ struct rockchip_dp_device *dp = to_dp(connector);
+
+ return &dp->encoder;
+}
+
+static struct drm_connector_helper_funcs rockchip_dp_connector_helper_funcs = {
+ .get_modes = rockchip_dp_get_modes,
+ .best_encoder = rockchip_dp_best_encoder,
+};
+
+static enum drm_connector_status
+rockchip_dp_detect(struct drm_connector *connector, bool force)
+{
+ struct rockchip_dp_device *dp = to_dp(connector);
+
+ return analogix_dp_detect(dp->dev, force);
+}
+
+static void rockchip_dp_connector_destroy(struct drm_connector *connector)
+{
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+
+static struct drm_connector_funcs rockchip_dp_connector_funcs = {
+ .dpms = drm_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = rockchip_dp_detect,
+ .destroy = rockchip_dp_connector_destroy,
+};
+
+static int rockchip_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
+ struct drm_bridge *bridge)
+{
+ struct rockchip_dp_device *dp = to_dp(plat_data);
+ struct drm_connector *connector = &dp->connector;
+ struct drm_encoder *encoder = &dp->encoder;
+ int ret;
+
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+ ret = drm_connector_init(dp->drm_dev, connector,
+ &rockchip_dp_connector_funcs,
+ DRM_MODE_CONNECTOR_eDP);
+ if (ret) {
+ DRM_ERROR("Failed to initialize connector with drm\n");
+ return ret;
+ }
+
+ drm_connector_helper_add(connector,
+ &rockchip_dp_connector_helper_funcs);
+ drm_mode_connector_attach_encoder(connector, encoder);
+
+ dp->plat_data.connector = connector;
+
+ return 0;
+}
+
+static bool
+rockchip_dp_drm_encoder_mode_fixup(struct drm_encoder *encoder,
+ const struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ /* do nothing */
+ return true;
+}
+
+static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted)
+{
+ /* do nothing */
+}
+
+static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
+{
+ struct rockchip_dp_device *dp = to_dp(encoder);
+ u32 val;
+ int ret;
+
+ ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+ DRM_MODE_CONNECTOR_eDP,
+ ROCKCHIP_OUT_MODE_AAAA);
+ if (ret < 0) {
+ dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+ return;
+ }
+
+ ret = rockchip_drm_encoder_get_mux_id(dp->dev->of_node, encoder);
+ if (ret < 0)
+ return;
+
+ if (ret)
+ val = GRF_EDP_SEL_VOP_LIT | (GRF_EDP_LCD_SEL_MASK << 16);
+ else
+ val = GRF_EDP_SEL_VOP_BIG | (GRF_EDP_LCD_SEL_MASK << 16);
+
+ dev_dbg(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON6, val);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not write to GRF: %d\n", ret);
+ return;
+ }
+}
+
+static void rockchip_dp_drm_encoder_nop(struct drm_encoder *encoder)
+{
+ /* do nothing */
+}
+
+static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
+ .mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
+ .mode_set = rockchip_dp_drm_encoder_mode_set,
+ .prepare = rockchip_dp_drm_encoder_prepare,
+ .commit = rockchip_dp_drm_encoder_nop,
+ .disable = rockchip_dp_drm_encoder_nop,
+};
+
+static void rockchip_dp_drm_encoder_destroy(struct drm_encoder *encoder)
+{
+ drm_encoder_cleanup(encoder);
+}
+
+static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
+ .destroy = rockchip_dp_drm_encoder_destroy,
+};
+
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "failed to get rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ dp->pclk = devm_clk_get(dev, "pclk");
+ if (IS_ERR(dp->pclk)) {
+ dev_err(dev, "failed to get pclk property\n");
+ return PTR_ERR(dp->pclk);
+ }
+
+ dp->rst = devm_reset_control_get(dev, "dp");
+ if (IS_ERR(dp->rst)) {
+ dev_err(dev, "failed to get dp reset control\n");
+ return PTR_ERR(dp->rst);
+ }
+
+ ret = clk_prepare_enable(dp->pclk);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to enable pclk %d\n", ret);
+ return ret;
+ }
+
+ ret = rockchip_dp_pre_init(dp);
+ if (ret < 0) {
+ dev_err(dp->dev, "failed to pre init %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int rockchip_dp_drm_create_encoder(struct rockchip_dp_device *dp)
+{
+ struct drm_encoder *encoder = &dp->encoder;
+ struct drm_device *drm_dev = dp->drm_dev;
+ struct device *dev = dp->dev;
+ int ret;
+
+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
+ dev->of_node);
+ DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
+
+ ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
+ DRM_MODE_ENCODER_TMDS);
+ if (ret) {
+ DRM_ERROR("failed to initialize encoder with drm\n");
+ return ret;
+ }
+
+ drm_encoder_helper_add(encoder, &rockchip_dp_encoder_helper_funcs);
+
+ return 0;
+}
+
+static int rockchip_dp_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct rockchip_dp_device *dp = dev_get_drvdata(dev);
+ struct drm_device *drm_dev = data;
+ int ret;
+
+ /*
+ * Just like the probe function said, we don't need the
+ * device drvrate anymore, we should leave the charge to
+ * analogix dp driver, set the device drvdata to NULL.
+ */
+ dev_set_drvdata(dev, NULL);
+
+ ret = rockchip_dp_init(dp);
+ if (ret < 0)
+ return ret;
+
+ dp->drm_dev = drm_dev;
+
+ ret = rockchip_dp_drm_create_encoder(dp);
+ if (ret) {
+ DRM_ERROR("failed to create drm encoder\n");
+ return ret;
+ }
+
+ dp->plat_data.encoder = &dp->encoder;
+
+ dp->plat_data.dev_type = RK3288_DP;
+ dp->plat_data.power_on = rockchip_dp_poweron;
+ dp->plat_data.power_off = rockchip_dp_powerdown;
+ dp->plat_data.attach = rockchip_dp_bridge_attach;
+
+ return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
+}
+
+static void rockchip_dp_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ return analogix_dp_unbind(dev, master, data);
+}
+
+static const struct component_ops rockchip_dp_component_ops = {
+ .bind = rockchip_dp_bind,
+ .unbind = rockchip_dp_unbind,
+};
+
+static int rockchip_dp_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *panel_node, *port, *endpoint;
+ struct rockchip_dp_device *dp;
+ struct drm_panel *panel;
+
+ port = of_graph_get_port_by_id(dev->of_node, 1);
+ if (!port) {
+ dev_err(dev, "can't find output port\n");
+ return -EINVAL;
+ }
+
+ endpoint = of_get_child_by_name(port, "endpoint");
+ of_node_put(port);
+ if (!endpoint) {
+ dev_err(dev, "no output endpoint found\n");
+ return -EINVAL;
+ }
+
+ panel_node = of_graph_get_remote_port_parent(endpoint);
+ of_node_put(endpoint);
+ if (!panel_node) {
+ dev_err(dev, "no output node found\n");
+ return -EINVAL;
+ }
+
+ panel = of_drm_find_panel(panel_node);
+ if (!panel) {
+ DRM_ERROR("failed to find panel\n");
+ of_node_put(panel_node);
+ return -EPROBE_DEFER;
+ }
+
+ of_node_put(panel_node);
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (!dp)
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ dp->plat_data.panel = panel;
+
+ /*
+ * We just use the drvdata until driver run into component
+ * add function, and then we would set drvdata to null, so
+ * that analogix dp driver could take charge of the drvdata.
+ */
+ platform_set_drvdata(pdev, dp);
+
+ return component_add(dev, &rockchip_dp_component_ops);
+}
+
+static int rockchip_dp_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &rockchip_dp_component_ops);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int rockchip_dp_suspend(struct device *dev)
+{
+ return analogix_dp_suspend(dev);
+}
+
+static int rockchip_dp_resume(struct device *dev)
+{
+ return analogix_dp_resume(dev);
+}
+#endif
+
+static const struct dev_pm_ops rockchip_dp_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
+};
+
+static const struct of_device_id rockchip_dp_dt_ids[] = {
+ {.compatible = "rockchip,rk3288-dp",},
+ {}
+};
+MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);
+
+static struct platform_driver rockchip_dp_driver = {
+ .probe = rockchip_dp_probe,
+ .remove = rockchip_dp_remove,
+ .driver = {
+ .name = "rockchip-dp",
+ .owner = THIS_MODULE,
+ .pm = &rockchip_dp_pm_ops,
+ .of_match_table = of_match_ptr(rockchip_dp_dt_ids),
+ },
+};
+
+module_platform_driver(rockchip_dp_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_AUTHOR("Jeff chen <jeff.chen@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip Specific Analogix-DP Driver Extension");
+MODULE_LICENSE("GPL v2");
diff --git a/include/drm/bridge/analogix_dp.h b/include/drm/bridge/analogix_dp.h
index 134638af..7d9857a 100644
--- a/include/drm/bridge/analogix_dp.h
+++ b/include/drm/bridge/analogix_dp.h
@@ -15,6 +15,7 @@
enum analogix_dp_devtype {
EXYNOS_DP,
+ RK3288_DP,
};
struct analogix_dp_plat_data {
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (6 preceding siblings ...)
2015-10-28 8:27 ` [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
@ 2015-10-28 8:28 ` Yakir Yang
2015-10-30 16:46 ` Rob Herring
2015-10-28 8:30 ` [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
` (14 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:28 UTC (permalink / raw)
To: linux-arm-kernel
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../display/rockchip/analogix_dp-rockchip.txt | 90 ++++++++++++++++++++++
1 file changed, 90 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..ec93917
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -0,0 +1,90 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+
+- clock-names: from common clock binding:
+ Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: contain a port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+ dp-controller: dp at ff970000 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0xff970000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ rockchip,grf = <&grf>;
+ resets = <&cru 111>;
+ reset-names = "dp";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+ edp_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+
+ edp_out: port at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>
+ };
+ };
+ };
+ };
+
+ pinctrl {
+ edp {
+ edp_hpd: edp-hpd {
+ rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (7 preceding siblings ...)
2015-10-28 8:28 ` [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
@ 2015-10-28 8:30 ` Yakir Yang
2015-10-28 20:36 ` Heiko Stuebner
2015-11-11 23:23 ` Heiko Stuebner
2015-10-28 8:31 ` [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy Yakir Yang
` (13 subsequent siblings)
22 siblings, 2 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:30 UTC (permalink / raw)
To: linux-arm-kernel
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
Changes in v7:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfaces. (Heiko)
Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
function, move those code to probe() method. And remove driver .owner
number. (Kishon)
Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
power control. (Heiko)
Changes in v2: None
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 155 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 163 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-dp.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859d..7355819 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_DP
+ tristate "Rockchip Display Port PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip Display Port PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..b1700cd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..c82c22f
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,155 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12 0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON 0
+#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
+
+struct rockchip_dp_phy {
+ struct device *dev;
+ struct regmap *grf;
+ struct clk *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+ int ret;
+
+ if (enable) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_ON);
+ if (ret < 0) {
+ dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ } else {
+ clk_disable_unprepare(dp->phy_24m);
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_OFF);
+ }
+
+ return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+ .power_on = rockchip_dp_phy_power_on,
+ .power_off = rockchip_dp_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct phy_provider *phy_provider;
+ struct rockchip_dp_phy *dp;
+ struct resource *res;
+ struct phy *phy;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (IS_ERR(dp))
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ dp->phy_24m = devm_clk_get(dev, "24m");
+ if (IS_ERR(dp->phy_24m)) {
+ dev_err(dev, "cannot get clock 24m\n");
+ return PTR_ERR(dp->phy_24m);
+ }
+
+ ret = clk_set_rate(dp->phy_24m, 24000000);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+ return ret;
+ }
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+ GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+ return ret;
+ }
+
+ phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, dp);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3288-dp-phy" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+ .probe = rockchip_dp_phy_probe,
+ .driver = {
+ .name = "rockchip-dp-phy",
+ .of_match_table = rockchip_dp_phy_dt_ids,
+ },
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (8 preceding siblings ...)
2015-10-28 8:30 ` [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
@ 2015-10-28 8:31 ` Yakir Yang
2015-10-30 16:42 ` Rob Herring
2015-10-28 8:52 ` [PATCH v8 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
` (12 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:31 UTC (permalink / raw)
To: linux-arm-kernel
Add dt binding documentation for rockchip display port PHY.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8:
- Remove the specific address in the example node name. (Heiko)
Changes in v7:
- Simplify the commit message. (Kishon)
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Update the rockchip,grf explain in document, and correct the clock required
elemets in document. (Rob & Heiko)
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
new file mode 100644
index 0000000..00902cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
@@ -0,0 +1,22 @@
+Rockchip Soc Seroes Display Port PHY
+------------------------------------
+
+Required properties:
+- compatible : should be one of the following supported values:
+ - "rockchip.rk3288-dp-phy"
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+- clock-names: from common clock binding:
+ Required elements: "24m"
+- rockchip,grf: phandle to the syscon managing the "general register files"
+- #phy-cells : from the generic PHY bindings, must be 0;
+
+Example:
+
+edp_phy: edp-phy {
+ compatible = "rockchip,rk3288-dp-phy";
+ rockchip,grf = <&grf>;
+ clocks = <&cru SCLK_EDP_24M>;
+ clock-names = "24m";
+ #phy-cells = <0>;
+};
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 12/17] drm: rockchip: vop: add bpc and color mode setting
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (9 preceding siblings ...)
2015-10-28 8:31 ` [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy Yakir Yang
@ 2015-10-28 8:52 ` Yakir Yang
2015-10-28 8:55 ` [PATCH v8 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
` (11 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:52 UTC (permalink / raw)
To: linux-arm-kernel
From: Mark Yao <yzq@rock-chips.com>
Add bpc and color mode setting in rockchip_drm_vop driver, so
connector could try to use the edid drm_display_info to config
vop output mode.
Signed-off-by: Mark Yao <yzq@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- Fix compiled error (Heiko)
- Using the connector display info message to configure eDP driver input
video mode, but hard code CRTC video output mode to RGBaaa.
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 25 +++++++++++++++----
drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 ++++++++++++++++++++++---
4 files changed, 51 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 2c82a9a..3990951 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -180,14 +180,29 @@ static void rockchip_dp_drm_encoder_mode_set(struct drm_encoder *encoder,
static void rockchip_dp_drm_encoder_prepare(struct drm_encoder *encoder)
{
struct rockchip_dp_device *dp = to_dp(encoder);
+ struct drm_connector *cn = &dp->connector;
+ int ret = -1;
u32 val;
- int ret;
- ret = rockchip_drm_crtc_mode_config(encoder->crtc,
- DRM_MODE_CONNECTOR_eDP,
- ROCKCHIP_OUT_MODE_AAAA);
+ /*
+ * FIXME(Yakir): driver should configure the CRTC output video
+ * mode with the display information which indicated the monitor
+ * support colorimetry.
+ *
+ * But don't know why the CRTC driver seems could only output the
+ * RGBaaa rightly. For example, if connect the "innolux,n116bge"
+ * eDP screen, EDID would indicated that screen only accepted the
+ * 6bpc mode. But if I configure CRTC to RGB666 output, then eDP
+ * screen would show a blue picture (RGB888 show a green picture).
+ * But if I configure CTRC to RGBaaa, and eDP driver still keep
+ * RGB666 input video mode, then screen would works prefect.
+ */
+ if (cn->display_info.color_formats & DRM_COLOR_FORMAT_RGB444)
+ ret = rockchip_drm_crtc_mode_config(encoder->crtc,
+ DRM_MODE_CONNECTOR_eDP,
+ 10, DRM_COLOR_FORMAT_RGB444);
if (ret < 0) {
- dev_err(dp->dev, "Could not set crtc mode config: %d.\n", ret);
+ dev_err(dp->dev, "Could not set crtc mode config (%d)\n", ret);
return;
}
diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
index 80d6fc8..428a3c1 100644
--- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
+++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c
@@ -215,7 +215,7 @@ static void dw_hdmi_rockchip_encoder_commit(struct drm_encoder *encoder)
static void dw_hdmi_rockchip_encoder_prepare(struct drm_encoder *encoder)
{
rockchip_drm_crtc_mode_config(encoder->crtc, DRM_MODE_CONNECTOR_HDMIA,
- ROCKCHIP_OUT_MODE_AAAA);
+ 10, DRM_COLOR_FORMAT_RGB444);
}
static struct drm_encoder_helper_funcs dw_hdmi_rockchip_encoder_helper_funcs = {
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index dc4e5f0..ef1d7fb 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -59,7 +59,7 @@ void rockchip_unregister_crtc_funcs(struct drm_device *dev, int pipe);
int rockchip_drm_encoder_get_mux_id(struct device_node *node,
struct drm_encoder *encoder);
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc, int connector_type,
- int out_mode);
+ int bpc, int color);
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
struct device *dev);
void rockchip_drm_dma_detach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 5d8ae5e..9ef4a1f 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -1062,14 +1062,40 @@ static const struct drm_plane_funcs vop_plane_funcs = {
int rockchip_drm_crtc_mode_config(struct drm_crtc *crtc,
int connector_type,
- int out_mode)
+ int bpc, int color)
{
struct vop *vop = to_vop(crtc);
+ /*
+ * RK3288 vop only support RGB Color output.
+ */
+ if (color != DRM_COLOR_FORMAT_RGB444) {
+ DRM_ERROR("Only support output RGB444, not support%d\n",
+ color);
+ return -EINVAL;
+ }
+
vop->connector_type = connector_type;
- vop->connector_out_mode = out_mode;
- return 0;
+ /*
+ * Fixme: I don't know how to describe the ROCKCHIP_OUT_MODE_P565's
+ * bpc, 5 or 6?
+ */
+ if (bpc >= 10) {
+ bpc = 10;
+ vop->connector_out_mode = ROCKCHIP_OUT_MODE_AAAA;
+ } else if (bpc >= 8) {
+ bpc = 8;
+ vop->connector_out_mode = ROCKCHIP_OUT_MODE_P888;
+ } else if (bpc >= 6) {
+ bpc = 6;
+ vop->connector_out_mode = ROCKCHIP_OUT_MODE_P666;
+ } else {
+ DRM_ERROR("unsupport bpc %d\n", bpc);
+ return -EINVAL;
+ }
+
+ return bpc;
}
EXPORT_SYMBOL_GPL(rockchip_drm_crtc_mode_config);
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (10 preceding siblings ...)
2015-10-28 8:52 ` [PATCH v8 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
@ 2015-10-28 8:55 ` Yakir Yang
2015-10-28 8:56 ` [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
` (10 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:55 UTC (permalink / raw)
To: linux-arm-kernel
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 76 ++++++++++++++---------
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h | 12 ++++
2 files changed, 60 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 861097a..21a3287 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -15,6 +15,8 @@
#include <linux/delay.h>
#include <linux/gpio.h>
+#include <drm/bridge/analogix_dp.h>
+
#include "analogix_dp_core.h"
#include "analogix_dp_reg.h"
@@ -72,6 +74,14 @@ void analogix_dp_init_analog_param(struct analogix_dp_device *dp)
reg = SEL_24M | TX_DVDD_BIT_1_0625V;
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2);
+ if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) {
+ writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1);
+ writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2);
+ writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3);
+ writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4);
+ writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5);
+ }
+
reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3);
@@ -206,81 +216,85 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
bool enable)
{
u32 reg;
+ u32 phy_pd_addr = ANALOGIX_DP_PHY_PD;
+
+ if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+ phy_pd_addr = ANALOGIX_DP_PD;
switch (block) {
case AUX_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= AUX_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~AUX_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH0_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH0_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH0_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH1_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH1_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH1_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH2_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH2_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH2_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case CH3_BLOCK:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= CH3_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~CH3_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case ANALOG_TOTAL:
if (enable) {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg |= DP_PHY_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- reg = readl(dp->reg_base + ANALOGIX_DP_PHY_PD);
+ reg = readl(dp->reg_base + phy_pd_addr);
reg &= ~DP_PHY_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
}
break;
case POWER_ALL:
if (enable) {
reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
CH1_PD | CH0_PD;
- writel(reg, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(reg, dp->reg_base + phy_pd_addr);
} else {
- writel(0x00, dp->reg_base + ANALOGIX_DP_PHY_PD);
+ writel(0x00, dp->reg_base + phy_pd_addr);
}
break;
default:
@@ -399,8 +413,14 @@ void analogix_dp_init_aux(struct analogix_dp_device *dp)
analogix_dp_reset_aux(dp);
/* Disable AUX transaction H/W retry */
- reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0) |
- AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+ if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP))
+ reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) |
+ AUX_HW_RETRY_COUNT_SEL(3) |
+ AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
+ else
+ reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) |
+ AUX_HW_RETRY_COUNT_SEL(0) |
+ AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL);
/* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
index 738db4c..337912b 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.h
@@ -22,6 +22,14 @@
#define ANALOGIX_DP_VIDEO_CTL_8 0x3C
#define ANALOGIX_DP_VIDEO_CTL_10 0x44
+#define ANALOGIX_DP_PLL_REG_1 0xfc
+#define ANALOGIX_DP_PLL_REG_2 0x9e4
+#define ANALOGIX_DP_PLL_REG_3 0x9e8
+#define ANALOGIX_DP_PLL_REG_4 0x9ec
+#define ANALOGIX_DP_PLL_REG_5 0xa00
+
+#define ANALOGIX_DP_PD 0x12c
+
#define ANALOGIX_DP_LANE_MAP 0x35C
#define ANALOGIX_DP_ANALOG_CTL_1 0x370
@@ -154,6 +162,10 @@
#define VSYNC_POLARITY_CFG (0x1 << 1)
#define HSYNC_POLARITY_CFG (0x1 << 0)
+/* ANALOGIX_DP_PLL_REG_1 */
+#define REF_CLK_24M (0x1 << 1)
+#define REF_CLK_27M (0x0 << 1)
+
/* ANALOGIX_DP_LANE_MAP */
#define LANE3_MAP_LOGIC_LANE_0 (0x0 << 6)
#define LANE3_MAP_LOGIC_LANE_1 (0x1 << 6)
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (11 preceding siblings ...)
2015-10-28 8:55 ` [PATCH v8 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
@ 2015-10-28 8:56 ` Yakir Yang
2015-11-27 13:32 ` Heiko Stübner
2015-10-28 9:12 ` [PATCH v8 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
` (9 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 8:56 UTC (permalink / raw)
To: linux-arm-kernel
There are some IP limit on rk3288 that only support 4 physical lanes
of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Seprate the link-rate and lane-count limit out with the device_type
flag. (Thierry)
Changes in v3: None
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 33 ++++++++++++++--------
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 4 +--
2 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 6307060..563ffb1d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
return;
}
- ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
- dp->video_info.link_rate);
+ ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
+ dp->video_info.max_link_rate);
if (ret) {
dev_err(dp->dev, "unable to do link train\n");
return;
@@ -1156,16 +1156,25 @@ static int analogix_dp_dt_parse_pdata(struct analogix_dp_device *dp)
struct device_node *dp_node = dp->dev->of_node;
struct video_info *video_info = &dp->video_info;
- if (of_property_read_u32(dp_node, "samsung,link-rate",
- &video_info->link_rate)) {
- dev_err(dp->dev, "failed to get link-rate\n");
- return -EINVAL;
- }
-
- if (of_property_read_u32(dp_node, "samsung,lane-count",
- &video_info->lane_count)) {
- dev_err(dp->dev, "failed to get lane-count\n");
- return -EINVAL;
+ switch (dp->plat_data && dp->plat_data->dev_type) {
+ case RK3288_DP:
+ /*
+ * Like Rk3288 DisplayPort TRM indicate that "Main link
+ * containing 4 physical lanes of 2.7/1.62 Gbps/lane".
+ */
+ video_info->max_link_rate = 0x0A;
+ video_info->max_lane_count = 0x04;
+ break;
+ case EXYNOS_DP:
+ /*
+ * NOTE: those property parseing code is used for
+ * providing backward compatibility for samsung platform.
+ */
+ of_property_read_u32(dp_node, "samsung,link-rate",
+ &video_info->max_link_rate);
+ of_property_read_u32(dp_node, "samsung,lane-count",
+ &video_info->max_lane_count);
+ break;
}
return 0;
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index e37cef6..e6f8243 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -129,8 +129,8 @@ struct video_info {
enum color_coefficient ycbcr_coeff;
enum color_depth color_depth;
- enum link_rate_type link_rate;
- enum link_lane_count_type lane_count;
+ enum link_rate_type max_link_rate;
+ enum link_lane_count_type max_lane_count;
};
struct link_train {
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (12 preceding siblings ...)
2015-10-28 8:56 ` [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
@ 2015-10-28 9:12 ` Yakir Yang
2015-10-28 9:13 ` [PATCH v8 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
` (8 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 9:12 UTC (permalink / raw)
To: linux-arm-kernel
This change just make a little clean to make code more like
drm core expect, move hdp detect code from bridge->enable(),
and place them into connector->detect().
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Take Jingoo suggest, add commit messages.
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 11 +++++------
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 3842dbd..216d33d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
DRM_ERROR("failed to disable the panel\n");
}
- ret = analogix_dp_detect_hpd(dp);
- if (ret) {
- /* Cable has been disconnected, we're done */
- return;
- }
-
ret = analogix_dp_handle_edid(dp);
if (ret) {
dev_err(dp->dev, "unable to handle edid\n");
@@ -941,6 +935,11 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
enum drm_connector_status analogix_dp_detect(struct device *dev, bool force)
{
+ struct analogix_dp_device *dp = dev_get_drvdata(dev);
+
+ if (analogix_dp_detect_hpd(dp))
+ return connector_status_disconnected;
+
return connector_status_connected;
}
EXPORT_SYMBOL_GPL(analogix_dp_detect);
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (13 preceding siblings ...)
2015-10-28 9:12 ` [PATCH v8 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
@ 2015-10-28 9:13 ` Yakir Yang
2015-10-29 1:58 ` [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
` (7 subsequent siblings)
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-28 9:13 UTC (permalink / raw)
To: linux-arm-kernel
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4:
- Call drm_panel_prepare() in .get_modes function, ensure panel should
power on before driver try to read edid message.
Changes in v3:
- Add edid modes parse support
Changes in v2: None
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 24 +++++++----
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 46 +++++++++++-----------
2 files changed, 40 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 216d33d..4fa5f69 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -107,7 +107,7 @@ static unsigned char analogix_dp_calc_edid_check_sum(unsigned char *edid_data)
static int analogix_dp_read_edid(struct analogix_dp_device *dp)
{
- unsigned char edid[EDID_BLOCK_LENGTH * 2];
+ unsigned char *edid = dp->edid;
unsigned int extend_block = 0;
unsigned char sum;
unsigned char test_vector;
@@ -901,12 +901,6 @@ static void analogix_dp_commit(struct analogix_dp_device *dp)
DRM_ERROR("failed to disable the panel\n");
}
- ret = analogix_dp_handle_edid(dp);
- if (ret) {
- dev_err(dp->dev, "unable to handle edid\n");
- return;
- }
-
ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
dp->video_info.max_link_rate);
if (ret) {
@@ -947,8 +941,24 @@ EXPORT_SYMBOL_GPL(analogix_dp_detect);
int analogix_dp_get_modes(struct device *dev)
{
struct analogix_dp_device *dp = dev_get_drvdata(dev);
+ struct edid *edid = (struct edid *)dp->edid;
int num_modes = 0;
+ if (dp->plat_data && dp->plat_data->panel) {
+ if (drm_panel_prepare(dp->plat_data->panel)) {
+ DRM_ERROR("failed to setup the panel\n");
+ return -EINVAL;
+ }
+ }
+
+ if (analogix_dp_handle_edid(dp)) {
+ dev_err(dp->dev, "unable to handle edid\n");
+ return -EINVAL;
+ }
+
+ drm_mode_connector_update_edid_property(dp->connector, edid);
+ num_modes += drm_add_edid_modes(dp->connector, edid);
+
if (dp->plat_data->panel)
num_modes += drm_panel_get_modes(dp->plat_data->panel);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index d3c7e0a..2bd2e0d 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -20,6 +20,28 @@
#define MAX_CR_LOOP 5
#define MAX_EQ_LOOP 5
+/* I2C EDID Chip ID, Slave Address */
+#define I2C_EDID_DEVICE_ADDR 0x50
+#define I2C_E_EDID_DEVICE_ADDR 0x30
+
+#define EDID_BLOCK_LENGTH 0x80
+#define EDID_HEADER_PATTERN 0x00
+#define EDID_EXTENSION_FLAG 0x7e
+#define EDID_CHECKSUM 0x7f
+
+/* DP_MAX_LANE_COUNT */
+#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
+#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
+
+/* DP_LANE_COUNT_SET */
+#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
+
+/* DP_TRAINING_LANE0_SET */
+#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
+#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
+#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
+#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
+
enum link_rate_type {
LINK_RATE_1_62GBPS = DP_LINK_BW_1_62,
LINK_RATE_2_70GBPS = DP_LINK_BW_2_7,
@@ -161,6 +183,7 @@ struct analogix_dp_device {
int dpms_mode;
int hpd_gpio;
bool need_force_hpd;
+ unsigned char edid[EDID_BLOCK_LENGTH * 2];
struct analogix_dp_plat_data *plat_data;
};
@@ -260,27 +283,4 @@ int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp);
void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp);
void analogix_dp_enable_scrambling(struct analogix_dp_device *dp);
void analogix_dp_disable_scrambling(struct analogix_dp_device *dp);
-
-/* I2C EDID Chip ID, Slave Address */
-#define I2C_EDID_DEVICE_ADDR 0x50
-#define I2C_E_EDID_DEVICE_ADDR 0x30
-
-#define EDID_BLOCK_LENGTH 0x80
-#define EDID_HEADER_PATTERN 0x00
-#define EDID_EXTENSION_FLAG 0x7e
-#define EDID_CHECKSUM 0x7f
-
-/* DP_MAX_LANE_COUNT */
-#define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
-#define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
-
-/* DP_LANE_COUNT_SET */
-#define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
-
-/* DP_TRAINING_LANE0_SET */
-#define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
-#define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
-#define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
-#define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
-
#endif /* _ANALOGIX_DP_CORE_H */
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 06/17] dt-bindings: add document for analogix display port driver
2015-10-28 8:26 ` [PATCH v8 06/17] dt-bindings: add document for analogix display port driver Yakir Yang
@ 2015-10-28 20:02 ` Heiko Stuebner
2015-10-29 1:12 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Heiko Stuebner @ 2015-10-28 20:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> index 7a3a9cd..9905081 100644
> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> @@ -31,45 +31,31 @@ Required properties for dp-controller:
> from general PHY binding: the phandle for the PHY device.
> -phy-names:
> from general PHY binding: Should be "dp".
> - -samsung,color-space:
> - input video data format.
> - COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
> - -samsung,dynamic-range:
> - dynamic range for input video data.
> - VESA = 0, CEA = 1
> - -samsung,ycbcr-coeff:
> - YCbCr co-efficients for input video.
> - COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
> - -samsung,color-depth:
> - number of bits per colour component.
> - COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
> - -samsung,link-rate:
> - link rate supported by the panel.
> - LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
> - -samsung,lane-count:
> - number of lanes supported by the panel.
> - LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
> - - display-timings: timings for the connected panel as described by
> - Documentation/devicetree/bindings/video/display-timing.txt
^^ display/display-timings.txt
otherwise this patch does not apply.
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-28 8:30 ` [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
@ 2015-10-28 20:36 ` Heiko Stuebner
2015-10-29 1:14 ` Yakir Yang
2015-11-11 23:23 ` Heiko Stuebner
1 sibling, 1 reply; 52+ messages in thread
From: Heiko Stuebner @ 2015-10-28 20:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp_phy *dp;
> + struct resource *res;
drivers/phy/phy-rockchip-dp.c: In function 'rockchip_dp_phy_probe':
drivers/phy/phy-rockchip-dp.c:86:19: warning: unused variable 'res' [-Wunused-variable]
> + struct phy *phy;
> + int ret;
> +
> + if (!np)
> + return -ENODEV;
> +
> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> + if (IS_ERR(dp))
> + return -ENOMEM;
> +
> + dp->dev = dev;
> +
> + dp->phy_24m = devm_clk_get(dev, "24m");
> + if (IS_ERR(dp->phy_24m)) {
> + dev_err(dev, "cannot get clock 24m\n");
> + return PTR_ERR(dp->phy_24m);
> + }
> +
> + ret = clk_set_rate(dp->phy_24m, 24000000);
> + if (ret < 0) {
> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> + return ret;
> + }
> +
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 06/17] dt-bindings: add document for analogix display port driver
2015-10-28 20:02 ` Heiko Stuebner
@ 2015-10-29 1:12 ` Yakir Yang
2015-10-29 8:40 ` Heiko Stuebner
0 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-29 1:12 UTC (permalink / raw)
To: linux-arm-kernel
Hi Heiko,
On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
>> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
>> index 7a3a9cd..9905081 100644
>> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
>> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
>> @@ -31,45 +31,31 @@ Required properties for dp-controller:
>> from general PHY binding: the phandle for the PHY device.
>> -phy-names:
>> from general PHY binding: Should be "dp".
>> - -samsung,color-space:
>> - input video data format.
>> - COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
>> - -samsung,dynamic-range:
>> - dynamic range for input video data.
>> - VESA = 0, CEA = 1
>> - -samsung,ycbcr-coeff:
>> - YCbCr co-efficients for input video.
>> - COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
>> - -samsung,color-depth:
>> - number of bits per colour component.
>> - COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
>> - -samsung,link-rate:
>> - link rate supported by the panel.
>> - LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
>> - -samsung,lane-count:
>> - number of lanes supported by the panel.
>> - LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
>> - - display-timings: timings for the connected panel as described by
>> - Documentation/devicetree/bindings/video/display-timing.txt
> ^^ display/display-timings.txt
> otherwise this patch does not apply.
I thought I have deleted this old path of "display-timing.txt", and
changed it to
- Documentation/devicetree/bindings/video/display-timing.txt
+ Documentation/devicetree/bindings/display/panel/display-timing.txt
And the real path of "display-timing.txt" in linux-next [tag 20151022]
do under
the "display/panel/", those change should be right.
Thanks,
- Yakir
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-28 20:36 ` Heiko Stuebner
@ 2015-10-29 1:14 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-29 1:14 UTC (permalink / raw)
To: linux-arm-kernel
Hi Heiko,
On 10/29/2015 04:36 AM, Heiko Stuebner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
>> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct phy_provider *phy_provider;
>> + struct rockchip_dp_phy *dp;
>> + struct resource *res;
> drivers/phy/phy-rockchip-dp.c: In function 'rockchip_dp_phy_probe':
> drivers/phy/phy-rockchip-dp.c:86:19: warning: unused variable 'res' [-Wunused-variable]
Oh, thanks, would send v9 of this one alone.
- Yakir
>> + struct phy *phy;
>> + int ret;
>> +
>> + if (!np)
>> + return -ENODEV;
>> +
>> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
>> + if (IS_ERR(dp))
>> + return -ENOMEM;
>> +
>> + dp->dev = dev;
>> +
>> + dp->phy_24m = devm_clk_get(dev, "24m");
>> + if (IS_ERR(dp->phy_24m)) {
>> + dev_err(dev, "cannot get clock 24m\n");
>> + return PTR_ERR(dp->phy_24m);
>> + }
>> +
>> + ret = clk_set_rate(dp->phy_24m, 24000000);
>> + if (ret < 0) {
>> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
>> + return ret;
>> + }
>> +
>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (14 preceding siblings ...)
2015-10-28 9:13 ` [PATCH v8 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
@ 2015-10-29 1:58 ` Yakir Yang
2015-11-03 4:38 ` Brian Norris
2015-10-29 17:49 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Heiko Stuebner
` (6 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-29 1:58 UTC (permalink / raw)
To: linux-arm-kernel
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused head file.
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
Changes in v7:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfaces. (Heiko)
Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
function, move those code to probe() method. And remove driver .owner
number. (Kishon)
Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
power control. (Heiko)
Changes in v2: None
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 159 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-dp.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859d..7355819 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_DP
+ tristate "Rockchip Display Port PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip Display Port PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..b1700cd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..f3e0058
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12 0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON 0
+#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
+
+struct rockchip_dp_phy {
+ struct device *dev;
+ struct regmap *grf;
+ struct clk *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+ int ret;
+
+ if (enable) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_ON);
+ if (ret < 0) {
+ dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ } else {
+ clk_disable_unprepare(dp->phy_24m);
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_OFF);
+ }
+
+ return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+ .power_on = rockchip_dp_phy_power_on,
+ .power_off = rockchip_dp_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct phy_provider *phy_provider;
+ struct rockchip_dp_phy *dp;
+ struct phy *phy;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (IS_ERR(dp))
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ dp->phy_24m = devm_clk_get(dev, "24m");
+ if (IS_ERR(dp->phy_24m)) {
+ dev_err(dev, "cannot get clock 24m\n");
+ return PTR_ERR(dp->phy_24m);
+ }
+
+ ret = clk_set_rate(dp->phy_24m, 24000000);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+ return ret;
+ }
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+ GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+ return ret;
+ }
+
+ phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, dp);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3288-dp-phy" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+ .probe = rockchip_dp_phy_probe,
+ .driver = {
+ .name = "rockchip-dp-phy",
+ .of_match_table = rockchip_dp_phy_dt_ids,
+ },
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 06/17] dt-bindings: add document for analogix display port driver
2015-10-29 1:12 ` Yakir Yang
@ 2015-10-29 8:40 ` Heiko Stuebner
0 siblings, 0 replies; 52+ messages in thread
From: Heiko Stuebner @ 2015-10-29 8:40 UTC (permalink / raw)
To: linux-arm-kernel
Am Donnerstag, 29. Oktober 2015, 09:12:21 schrieb Yakir Yang:
> Hi Heiko,
>
> On 10/29/2015 04:02 AM, Heiko Stuebner wrote:
> > Hi Yakir,
> >
> > Am Mittwoch, 28. Oktober 2015, 16:26:33 schrieb Yakir Yang:
> >> diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> >> index 7a3a9cd..9905081 100644
> >> --- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> >> +++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
> >> @@ -31,45 +31,31 @@ Required properties for dp-controller:
> >> from general PHY binding: the phandle for the PHY device.
> >> -phy-names:
> >> from general PHY binding: Should be "dp".
> >> - -samsung,color-space:
> >> - input video data format.
> >> - COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
> >> - -samsung,dynamic-range:
> >> - dynamic range for input video data.
> >> - VESA = 0, CEA = 1
> >> - -samsung,ycbcr-coeff:
> >> - YCbCr co-efficients for input video.
> >> - COLOR_YCBCR601 = 0, COLOR_YCBCR709 = 1
> >> - -samsung,color-depth:
> >> - number of bits per colour component.
> >> - COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
> >> - -samsung,link-rate:
> >> - link rate supported by the panel.
> >> - LINK_RATE_1_62GBPS = 0x6, LINK_RATE_2_70GBPS = 0x0A
> >> - -samsung,lane-count:
> >> - number of lanes supported by the panel.
> >> - LANE_COUNT1 = 1, LANE_COUNT2 = 2, LANE_COUNT4 = 4
> >> - - display-timings: timings for the connected panel as described by
> >> - Documentation/devicetree/bindings/video/display-timing.txt
> > ^^ display/display-timings.txt
> > otherwise this patch does not apply.
>
> I thought I have deleted this old path of "display-timing.txt", and
> changed it to
>
> - Documentation/devicetree/bindings/video/display-timing.txt
in the changes I got from Rob Hering's dt-branch [0] the path in the file
is already display/display-timing.txt so applying a change with video/...
in it fails. Anyway, as this will probably only make it in after the merge-
window, we can see how this ends up before anyway :-) .
>
> + Documentation/devicetree/bindings/display/panel/display-timing.txt
>
> And the real path of "display-timing.txt" in linux-next [tag 20151022]
> do under
> the "display/panel/", those change should be right.
Heiko
[0] https://git.kernel.org/cgit/linux/kernel/git/robh/linux.git/commit/?h=dt/next&id=efdbd7345f8836f7495f3ac6ee237d86cb3bb6b0
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 0/17] Add Analogix Core Display Port Driver
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (15 preceding siblings ...)
2015-10-29 1:58 ` [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
@ 2015-10-29 17:49 ` Heiko Stuebner
2015-10-30 1:05 ` Yakir Yang
2015-10-30 1:09 ` [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
` (5 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Heiko Stuebner @ 2015-10-29 17:49 UTC (permalink / raw)
To: linux-arm-kernel
Am Mittwoch, 28. Oktober 2015, 16:15:43 schrieb Yakir Yang:
> Hi all,
>
> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM
>
> But there are still three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
> dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
> between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
> register).
>
> This series have been well tested on Rockchip platform with eDP panel on
> Jerry Chromebook and Display Port Monitor on RK3288 board. Also I have
> tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at Samsung
> help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
> glad to say that things works rightlly.
Patch 15/17 looks like it didn't make it? I haven't found it in neither my
inbox nor in the linux-rockchip list archive? So I've used the v7 version
for my tests.
This series on a rk3288-veyron-pinky and rk3288-veyron-jerry
Tested-by: Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 0/17] Add Analogix Core Display Port Driver
2015-10-29 17:49 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Heiko Stuebner
@ 2015-10-30 1:05 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-30 1:05 UTC (permalink / raw)
To: linux-arm-kernel
Hi Heiko,
On 10/30/2015 01:49 AM, Heiko Stuebner wrote:
> Am Mittwoch, 28. Oktober 2015, 16:15:43 schrieb Yakir Yang:
>> Hi all,
>>
>> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
>> share the same IP, so a lot of parts can be re-used. I split the common
>> code into bridge directory, then rk3288 and exynos only need to keep
>> some platform code. Cause I can't find the exact IP name of exynos dp
>> controller, so I decide to name dp core driver with "analogix" which I
>> find in rk3288 eDP TRM
>>
>> But there are still three light registers setting differents bewteen
>> exynos and rk3288.
>> 1. RK3288 have five special pll resigters which not indicata in exynos
>> dp controller.
>> 2. The address of DP_PHY_PD(dp phy power manager register) are different
>> between rk3288 and exynos.
>> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
>> register).
>>
>> This series have been well tested on Rockchip platform with eDP panel on
>> Jerry Chromebook and Display Port Monitor on RK3288 board. Also I have
>> tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at Samsung
>> help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
>> glad to say that things works rightlly.
> Patch 15/17 looks like it didn't make it? I haven't found it in neither my
> inbox nor in the linux-rockchip list archive? So I've used the v7 version
> for my tests.
Oops, thanks for your reminding, I would send it now.
> This series on a rk3288-veyron-pinky and rk3288-veyron-jerry
> Tested-by: Heiko Stuebner <heiko@sntech.de>
>
Thanks,
- Yakir
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (16 preceding siblings ...)
2015-10-29 17:49 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Heiko Stuebner
@ 2015-10-30 1:09 ` Yakir Yang
2015-11-11 23:10 ` Rob Herring
2015-10-31 6:30 ` [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
` (4 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-30 1:09 UTC (permalink / raw)
To: linux-arm-kernel
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Tested-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v9: None
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Add "analogix,need-force-hpd" to indicate whether driver need foce
hpd when hpd detect failed.
Changes in v2: None
.../bindings/display/bridge/analogix_dp.txt | 4 ++-
.../bindings/display/exynos/exynos_dp.txt | 1 +
.../display/rockchip/analogix_dp-rockchip.txt | 1 +
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 ++
drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 9 ++++++
6 files changed, 47 insertions(+), 6 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
index 7659a7a..74f0e80 100644
--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
@@ -22,6 +22,9 @@ Required properties for dp-controller:
from general PHY binding: Should be "dp".
Optional properties for dp-controller:
+ -analogix,need-force-hpd:
+ Indicate driver need force hpd when hpd detect failed, this
+ is used for some eDP screen which don't have hpd signal.
-hpd-gpios:
Hotplug detect GPIO.
Indicates which GPIO should be used for hotplug detection
@@ -31,7 +34,6 @@ Optional properties for dp-controller:
* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
* Documentation/devicetree/bindings/video/analogix_dp-rockchip.txt
-
[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-------------------------------------------------------------------------------
diff --git a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
index 9905081..8800164 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
@@ -41,6 +41,7 @@ For the below properties, please refer to Analogix DP binding document:
-phys (required)
-phy-names (required)
-hpd-gpios (optional)
+ -analogix,need-force-hpd (optional)
-video interfaces (optional)
Deprecated properties for DisplayPort:
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
index ec93917..be18388 100644
--- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -31,6 +31,7 @@ For the below properties, please refer to Analogix DP binding document:
- phys (required)
- phy-names (required)
- hpd-gpios (optional)
+- analogix,need-force-hpd (optional)
-------------------------------------------------------------------------------
Example:
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 563ffb1d..3842dbd 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -59,15 +59,38 @@ static int analogix_dp_detect_hpd(struct analogix_dp_device *dp)
{
int timeout_loop = 0;
- while (analogix_dp_get_plug_in_status(dp) != 0) {
+ while (timeout_loop < DP_TIMEOUT_LOOP_COUNT) {
+ if (analogix_dp_get_plug_in_status(dp) == 0)
+ return 0;
+
timeout_loop++;
- if (timeout_loop > DP_TIMEOUT_LOOP_COUNT) {
- dev_err(dp->dev, "failed to get hpd plug status\n");
- return -ETIMEDOUT;
- }
usleep_range(10, 11);
}
+ /*
+ * Some edp screen do not have hpd signal, so we can't just
+ * return failed when hpd plug in detect failed, DT property
+ * "need-force-hpd" would indicate whether driver need this.
+ */
+ if (!dp->need_force_hpd)
+ return -ETIMEDOUT;
+
+ /*
+ * The eDP TRM indicate that if HPD_STATUS(RO) is 0, AUX CH
+ * will not work, so we need to give a force hpd action to
+ * set HPD_STATUS manually.
+ */
+ dev_dbg(dp->dev, "failed to get hpd plug status, try to force hpd\n");
+
+ analogix_dp_force_hpd(dp);
+
+ if (analogix_dp_get_plug_in_status(dp) != 0) {
+ dev_err(dp->dev, "failed to get hpd plug in status\n");
+ return -EINVAL;
+ }
+
+ dev_dbg(dp->dev, "success to get plug in status after force hpd\n");
+
return 0;
}
@@ -1244,6 +1267,9 @@ int analogix_dp_bind(struct device *dev, struct drm_device *drm_dev,
if (IS_ERR(dp->reg_base))
return PTR_ERR(dp->reg_base);
+ dp->need_force_hpd =
+ of_property_read_bool(dev->of_node, "analogix,need-force-hpd");
+
dp->hpd_gpio = of_get_named_gpio(dev->of_node, "hpd-gpios", 0);
if (!gpio_is_valid(dp->hpd_gpio))
dp->hpd_gpio = of_get_named_gpio(dev->of_node,
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
index e6f8243..d3c7e0a 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
@@ -160,6 +160,7 @@ struct analogix_dp_device {
struct phy *phy;
int dpms_mode;
int hpd_gpio;
+ bool need_force_hpd;
struct analogix_dp_plat_data *plat_data;
};
@@ -180,6 +181,7 @@ void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp,
bool enable);
void analogix_dp_init_analog_func(struct analogix_dp_device *dp);
void analogix_dp_init_hpd(struct analogix_dp_device *dp);
+void analogix_dp_force_hpd(struct analogix_dp_device *dp);
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp);
void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp);
void analogix_dp_reset_aux(struct analogix_dp_device *dp);
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
index 21a3287..c7e2959 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
@@ -365,6 +365,15 @@ void analogix_dp_init_hpd(struct analogix_dp_device *dp)
writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
}
+void analogix_dp_force_hpd(struct analogix_dp_device *dp)
+{
+ u32 reg;
+
+ reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+ reg = (F_HPD | HPD_CTRL);
+ writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3);
+}
+
enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp)
{
u32 reg;
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy
2015-10-28 8:31 ` [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy Yakir Yang
@ 2015-10-30 16:42 ` Rob Herring
2015-10-31 3:13 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2015-10-30 16:42 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> Add dt binding documentation for rockchip display port PHY.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes in v8:
> - Remove the specific address in the example node name. (Heiko)
>
> Changes in v7:
> - Simplify the commit message. (Kishon)
>
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
> elemets in document. (Rob & Heiko)
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> new file mode 100644
> index 0000000..00902cb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> @@ -0,0 +1,22 @@
> +Rockchip Soc Seroes Display Port PHY
> +------------------------------------
> +
> +Required properties:
> +- compatible : should be one of the following supported values:
> + - "rockchip.rk3288-dp-phy"
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +- clock-names: from common clock binding:
> + Required elements: "24m"
> +- rockchip,grf: phandle to the syscon managing the "general register files"
> +- #phy-cells : from the generic PHY bindings, must be 0;
> +
> +Example:
> +
> +edp_phy: edp-phy {
> + compatible = "rockchip,rk3288-dp-phy";
> + rockchip,grf = <&grf>;
> + clocks = <&cru SCLK_EDP_24M>;
> + clock-names = "24m";
> + #phy-cells = <0>;
> +};
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-28 8:28 ` [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
@ 2015-10-30 16:46 ` Rob Herring
2015-10-31 3:15 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2015-10-30 16:46 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Oct 28, 2015 at 3:28 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> Rockchip DP driver is a helper driver of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
Looks mostly fine to me.
[...]
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: contain a port node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
Please document that you have 2 ports 0 and 1, port0 has 2 endpoints
for ? and port1 has 1 endpoint connected to a panel(or another
bridge). Otherwise that is only evident from the example.
Rob
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy
2015-10-30 16:42 ` Rob Herring
@ 2015-10-31 3:13 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-31 3:13 UTC (permalink / raw)
To: linux-arm-kernel
On 10/31/2015 12:42 AM, Rob Herring wrote:
> On Wed, Oct 28, 2015 at 3:31 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Add dt binding documentation for rockchip display port PHY.
>>
>> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> Acked-by: Rob Herring <robh@kernel.org>
Thanks,
- Yakir
>> ---
>> Changes in v8:
>> - Remove the specific address in the example node name. (Heiko)
>>
>> Changes in v7:
>> - Simplify the commit message. (Kishon)
>>
>> Changes in v6: None
>> Changes in v5:
>> - Split binding doc's from driver changes. (Rob)
>> - Update the rockchip,grf explain in document, and correct the clock required
>> elemets in document. (Rob & Heiko)
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> new file mode 100644
>> index 0000000..00902cb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
>> @@ -0,0 +1,22 @@
>> +Rockchip Soc Seroes Display Port PHY
>> +------------------------------------
>> +
>> +Required properties:
>> +- compatible : should be one of the following supported values:
>> + - "rockchip.rk3288-dp-phy"
>> +- clocks: from common clock binding: handle to dp clock.
>> + of memory mapped region.
>> +- clock-names: from common clock binding:
>> + Required elements: "24m"
>> +- rockchip,grf: phandle to the syscon managing the "general register files"
>> +- #phy-cells : from the generic PHY bindings, must be 0;
>> +
>> +Example:
>> +
>> +edp_phy: edp-phy {
>> + compatible = "rockchip,rk3288-dp-phy";
>> + rockchip,grf = <&grf>;
>> + clocks = <&cru SCLK_EDP_24M>;
>> + clock-names = "24m";
>> + #phy-cells = <0>;
>> +};
>> --
>> 1.9.1
>>
>>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-30 16:46 ` Rob Herring
@ 2015-10-31 3:15 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-31 3:15 UTC (permalink / raw)
To: linux-arm-kernel
Hi Rob,
On 10/31/2015 12:46 AM, Rob Herring wrote:
> On Wed, Oct 28, 2015 at 3:28 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
> Looks mostly fine to me.
>
> [...]
>
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: contain a port node with endpoint definitions as defined in
>> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> Please document that you have 2 ports 0 and 1, port0 has 2 endpoints
> for ? and port1 has 1 endpoint connected to a panel(or another
> bridge). Otherwise that is only evident from the example.
Okay, looks great.
Thanks,
- Yakir
> Rob
>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (17 preceding siblings ...)
2015-10-30 1:09 ` [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
@ 2015-10-31 6:30 ` Yakir Yang
2015-10-31 6:40 ` Yakir Yang
2015-10-31 6:42 ` [PATCH v10 " Yakir Yang
` (3 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-31 6:30 UTC (permalink / raw)
To: linux-arm-kernel
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
---
Changes in v9:
- Document more details for 'ports' property.
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../display/rockchip/analogix_dp-rockchip.txt | 91 ++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..dae86c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -0,0 +1,91 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+
+- clock-names: from common clock binding:
+ Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: there are 2 port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ Port 0: contained 2 endpoints, connecting to the ouput of vop.
+ Port 1: contained 1 endpoint, connecting to the input of panel.
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+ dp-controller: dp at ff970000 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0xff970000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ rockchip,grf = <&grf>;
+ resets = <&cru 111>;
+ reset-names = "dp";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+ edp_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+
+ edp_out: port at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>
+ };
+ };
+ };
+ };
+
+ pinctrl {
+ edp {
+ edp_hpd: edp-hpd {
+ rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-31 6:30 ` [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
@ 2015-10-31 6:40 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-10-31 6:40 UTC (permalink / raw)
To: linux-arm-kernel
On 10/31/2015 02:30 PM, Yakir Yang wrote:
> Rockchip DP driver is a helper driver of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Sorry about the duplicate signed-off, I would send a new version now.
> ---
> Changes in v9:
> - Document more details for 'ports' property.
>
> Changes in v8:
> - Modify the commit subject name. (Heiko)
>
> Changes in v7: None
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver changes. (Rob)
> - Add eDP hotplug pinctrl property. (Heiko)
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../display/rockchip/analogix_dp-rockchip.txt | 91 ++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> new file mode 100644
> index 0000000..dae86c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> @@ -0,0 +1,91 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +
> +- clock-names: from common clock binding:
> + Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +
> +- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
> +- pinctrl-0: pin-control mode. should be <&edp_hpd>
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: there are 2 port nodes with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> + Port 0: contained 2 endpoints, connecting to the ouput of vop.
> + Port 1: contained 1 endpoint, connecting to the input of panel.
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +-------------------------------------------------------------------------------
> +
> +Example:
> + dp-controller: dp at ff970000 {
> + compatible = "rockchip,rk3288-dp";
> + reg = <0xff970000 0x4000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> + clock-names = "dp", "pclk";
> + phys = <&dp_phy>;
> + phy-names = "dp";
> +
> + rockchip,grf = <&grf>;
> + resets = <&cru 111>;
> + reset-names = "dp";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_hpd>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_in: port at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_in_vopb: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_edp>;
> + };
> + edp_in_vopl: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_edp>;
> + };
> + };
> +
> + edp_out: port at 1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_out_panel: endpoint {
> + reg = <0>;
> + remote-endpoint = <&panel_in_edp>
> + };
> + };
> + };
> + };
> +
> + pinctrl {
> + edp {
> + edp_hpd: edp-hpd {
> + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> + };
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v10 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (18 preceding siblings ...)
2015-10-31 6:30 ` [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
@ 2015-10-31 6:42 ` Yakir Yang
2015-10-31 18:37 ` Rob Herring
2015-11-17 13:09 ` [PATCH v10 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
` (2 subsequent siblings)
22 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-10-31 6:42 UTC (permalink / raw)
To: linux-arm-kernel
Rockchip DP driver is a helper driver of analogix_dp coder driver,
so most of the DT property should be descriped in analogix_dp document.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v10:
- Removed the duplicated signed-of.
Changes in v9:
- Document more details for 'ports' property.
Changes in v8:
- Modify the commit subject name. (Heiko)
Changes in v7: None
Changes in v6: None
Changes in v5:
- Split binding doc's from driver changes. (Rob)
- Add eDP hotplug pinctrl property. (Heiko)
Changes in v4: None
Changes in v3: None
Changes in v2: None
.../display/rockchip/analogix_dp-rockchip.txt | 91 ++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
new file mode 100644
index 0000000..dae86c4
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
@@ -0,0 +1,91 @@
+Rockchip RK3288 specific extensions to the Analogix Display Port
+================================
+
+Required properties:
+- compatible: "rockchip,rk3288-edp";
+
+- reg: physical base address of the controller and length
+
+- clocks: from common clock binding: handle to dp clock.
+ of memory mapped region.
+
+- clock-names: from common clock binding:
+ Required elements: "dp" "pclk"
+
+- resets: Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+
+- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+- pinctrl-0: pin-control mode. should be <&edp_hpd>
+
+- reset-names: Must include the name "dp"
+
+- rockchip,grf: this soc should set GRF regs, so need get grf here.
+
+- ports: there are 2 port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ Port 0: contained 2 endpoints, connecting to the ouput of vop.
+ Port 1: contained 1 endpoint, connecting to the input of panel.
+
+For the below properties, please refer to Analogix DP binding document:
+ * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
+- phys (required)
+- phy-names (required)
+- hpd-gpios (optional)
+-------------------------------------------------------------------------------
+
+Example:
+ dp-controller: dp at ff970000 {
+ compatible = "rockchip,rk3288-dp";
+ reg = <0xff970000 0x4000>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+ clock-names = "dp", "pclk";
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ rockchip,grf = <&grf>;
+ resets = <&cru 111>;
+ reset-names = "dp";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&edp_hpd>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in: port at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_in_vopb: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vopb_out_edp>;
+ };
+ edp_in_vopl: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vopl_out_edp>;
+ };
+ };
+
+ edp_out: port at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ edp_out_panel: endpoint {
+ reg = <0>;
+ remote-endpoint = <&panel_in_edp>
+ };
+ };
+ };
+ };
+
+ pinctrl {
+ edp {
+ edp_hpd: edp-hpd {
+ rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+ };
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v10 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-31 6:42 ` [PATCH v10 " Yakir Yang
@ 2015-10-31 18:37 ` Rob Herring
2015-11-02 0:41 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2015-10-31 18:37 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Oct 31, 2015 at 1:42 AM, Yakir Yang <ykk@rock-chips.com> wrote:
> Rockchip DP driver is a helper driver of analogix_dp coder driver,
> so most of the DT property should be descriped in analogix_dp document.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> Changes in v10:
> - Removed the duplicated signed-of.
>
> Changes in v9:
> - Document more details for 'ports' property.
>
> Changes in v8:
> - Modify the commit subject name. (Heiko)
>
> Changes in v7: None
> Changes in v6: None
> Changes in v5:
> - Split binding doc's from driver changes. (Rob)
> - Add eDP hotplug pinctrl property. (Heiko)
>
> Changes in v4: None
> Changes in v3: None
> Changes in v2: None
>
> .../display/rockchip/analogix_dp-rockchip.txt | 91 ++++++++++++++++++++++
> 1 file changed, 91 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>
> diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> new file mode 100644
> index 0000000..dae86c4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> @@ -0,0 +1,91 @@
> +Rockchip RK3288 specific extensions to the Analogix Display Port
> +================================
> +
> +Required properties:
> +- compatible: "rockchip,rk3288-edp";
> +
> +- reg: physical base address of the controller and length
> +
> +- clocks: from common clock binding: handle to dp clock.
> + of memory mapped region.
> +
> +- clock-names: from common clock binding:
> + Required elements: "dp" "pclk"
> +
> +- resets: Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> +
> +- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
> +- pinctrl-0: pin-control mode. should be <&edp_hpd>
> +
> +- reset-names: Must include the name "dp"
> +
> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
> +
> +- ports: there are 2 port nodes with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> + Port 0: contained 2 endpoints, connecting to the ouput of vop.
> + Port 1: contained 1 endpoint, connecting to the input of panel.
> +
> +For the below properties, please refer to Analogix DP binding document:
> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
> +- phys (required)
> +- phy-names (required)
> +- hpd-gpios (optional)
> +-------------------------------------------------------------------------------
> +
> +Example:
> + dp-controller: dp at ff970000 {
> + compatible = "rockchip,rk3288-dp";
> + reg = <0xff970000 0x4000>;
> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
> + clock-names = "dp", "pclk";
> + phys = <&dp_phy>;
> + phy-names = "dp";
> +
> + rockchip,grf = <&grf>;
> + resets = <&cru 111>;
> + reset-names = "dp";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&edp_hpd>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_in: port at 0 {
> + reg = <0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_in_vopb: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&vopb_out_edp>;
> + };
> + edp_in_vopl: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&vopl_out_edp>;
> + };
> + };
> +
> + edp_out: port at 1 {
> + reg = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + edp_out_panel: endpoint {
> + reg = <0>;
> + remote-endpoint = <&panel_in_edp>
> + };
> + };
> + };
> + };
> +
> + pinctrl {
> + edp {
> + edp_hpd: edp-hpd {
> + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
> + };
> + };
> + };
> --
> 1.9.1
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v10 09/17] dt-bindings: add document for rockchip variant of analogix_dp
2015-10-31 18:37 ` Rob Herring
@ 2015-11-02 0:41 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-11-02 0:41 UTC (permalink / raw)
To: linux-arm-kernel
On 11/01/2015 02:37 AM, Rob Herring wrote:
> On Sat, Oct 31, 2015 at 1:42 AM, Yakir Yang <ykk@rock-chips.com> wrote:
>> Rockchip DP driver is a helper driver of analogix_dp coder driver,
>> so most of the DT property should be descriped in analogix_dp document.
>>
>> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> Acked-by: Rob Herring <robh@kernel.org>
Thanks,
- Yakir
>> ---
>> Changes in v10:
>> - Removed the duplicated signed-of.
>>
>> Changes in v9:
>> - Document more details for 'ports' property.
>>
>> Changes in v8:
>> - Modify the commit subject name. (Heiko)
>>
>> Changes in v7: None
>> Changes in v6: None
>> Changes in v5:
>> - Split binding doc's from driver changes. (Rob)
>> - Add eDP hotplug pinctrl property. (Heiko)
>>
>> Changes in v4: None
>> Changes in v3: None
>> Changes in v2: None
>>
>> .../display/rockchip/analogix_dp-rockchip.txt | 91 ++++++++++++++++++++++
>> 1 file changed, 91 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>>
>> diff --git a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>> new file mode 100644
>> index 0000000..dae86c4
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
>> @@ -0,0 +1,91 @@
>> +Rockchip RK3288 specific extensions to the Analogix Display Port
>> +================================
>> +
>> +Required properties:
>> +- compatible: "rockchip,rk3288-edp";
>> +
>> +- reg: physical base address of the controller and length
>> +
>> +- clocks: from common clock binding: handle to dp clock.
>> + of memory mapped region.
>> +
>> +- clock-names: from common clock binding:
>> + Required elements: "dp" "pclk"
>> +
>> +- resets: Must contain an entry for each entry in reset-names.
>> + See ../reset/reset.txt for details.
>> +
>> +- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
>> +- pinctrl-0: pin-control mode. should be <&edp_hpd>
>> +
>> +- reset-names: Must include the name "dp"
>> +
>> +- rockchip,grf: this soc should set GRF regs, so need get grf here.
>> +
>> +- ports: there are 2 port nodes with endpoint definitions as defined in
>> + Documentation/devicetree/bindings/media/video-interfaces.txt.
>> + Port 0: contained 2 endpoints, connecting to the ouput of vop.
>> + Port 1: contained 1 endpoint, connecting to the input of panel.
>> +
>> +For the below properties, please refer to Analogix DP binding document:
>> + * Documentation/devicetree/bindings/drm/bridge/analogix_dp.txt
>> +- phys (required)
>> +- phy-names (required)
>> +- hpd-gpios (optional)
>> +-------------------------------------------------------------------------------
>> +
>> +Example:
>> + dp-controller: dp at ff970000 {
>> + compatible = "rockchip,rk3288-dp";
>> + reg = <0xff970000 0x4000>;
>> + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
>> + clock-names = "dp", "pclk";
>> + phys = <&dp_phy>;
>> + phy-names = "dp";
>> +
>> + rockchip,grf = <&grf>;
>> + resets = <&cru 111>;
>> + reset-names = "dp";
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&edp_hpd>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + edp_in: port at 0 {
>> + reg = <0>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + edp_in_vopb: endpoint at 0 {
>> + reg = <0>;
>> + remote-endpoint = <&vopb_out_edp>;
>> + };
>> + edp_in_vopl: endpoint at 1 {
>> + reg = <1>;
>> + remote-endpoint = <&vopl_out_edp>;
>> + };
>> + };
>> +
>> + edp_out: port at 1 {
>> + reg = <1>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + edp_out_panel: endpoint {
>> + reg = <0>;
>> + remote-endpoint = <&panel_in_edp>
>> + };
>> + };
>> + };
>> + };
>> +
>> + pinctrl {
>> + edp {
>> + edp_hpd: edp-hpd {
>> + rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
>> + };
>> + };
>> + };
>> --
>> 1.9.1
>>
>>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-29 1:58 ` [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
@ 2015-11-03 4:38 ` Brian Norris
2015-11-04 0:48 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Brian Norris @ 2015-11-03 4:38 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
> Add phy driver for the Rockchip DisplayPort PHY module. This
> is required to get DisplayPort working in Rockchip SoCs.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
...
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..f3e0058
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,151 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12 0x0274
> +
> +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
Why are the above two macros the same? Judging by the RK3288 manual and
other downstream drivers, it seems like you want the _MASK one to be
shifted left by 16 (i.e., BIT(20)).
> +
> +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
> +#define GRF_EDP_PHY_SIDDQ_ON 0
> +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
> +
...
> + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
> + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
IOW, the above is writing:
BIT(4) | BIT(4)
whereas I think you want:
BIT(4) | BIT(20)
> + if (ret != 0) {
> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> + return ret;
> + }
> +
...
(FYI, I came across this by inspection when comparing Heiko's
'somewhat-stable' branch [1] with this series. The former brings up eDP
fine on veyron-jaq, whereas this one doesn't yet, even with the above
change. Still debugging the issue.)
Brian
[1] https://github.com/mmind/linux-rockchip/tree/devel/somewhat-stable
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY
2015-11-03 4:38 ` Brian Norris
@ 2015-11-04 0:48 ` Yakir Yang
2015-11-04 1:13 ` Brian Norris
0 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-11-04 0:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi Brain,
On 11/03/2015 12:38 PM, Brian Norris wrote:
> Hi Yakir,
>
> On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
>> Add phy driver for the Rockchip DisplayPort PHY module. This
>> is required to get DisplayPort working in Rockchip SoCs.
>>
>> Reviewed-by: Heiko Stuebner<heiko@sntech.de>
>> Signed-off-by: Yakir Yang<ykk@rock-chips.com>
>> ---
> ...
>> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
>> new file mode 100644
>> index 0000000..f3e0058
>> --- /dev/null
>> +++ b/drivers/phy/phy-rockchip-dp.c
>> @@ -0,0 +1,151 @@
>> +/*
>> + * Rockchip DP PHY driver
>> + *
>> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
>> + * Author: Yakir Yang<ykk@@rock-chips.com>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/clk.h>
>> +#include <linux/phy/phy.h>
>> +#include <linux/regmap.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define GRF_SOC_CON12 0x0274
>> +
>> +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
>> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
> Why are the above two macros the same? Judging by the RK3288 manual and
> other downstream drivers, it seems like you want the _MASK one to be
> shifted left by 16 (i.e., BIT(20)).
Oops, yes, you're right, it should be BIT(20), thanks for the catch.
>> +
>> +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
>> +#define GRF_EDP_PHY_SIDDQ_ON 0
>> +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
>> +
> ...
>
>> + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
>> + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
> IOW, the above is writing:
>
> BIT(4) | BIT(4)
>
> whereas I think you want:
>
> BIT(4) | BIT(20)
>
>> + if (ret != 0) {
>> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
>> + return ret;
>> + }
>> +
> ...
>
> (FYI, I came across this by inspection when comparing Heiko's
> 'somewhat-stable' branch [1] with this series. The former brings up eDP
> fine on veyron-jaq, whereas this one doesn't yet, even with the above
> change. Still debugging the issue.)
Hmm... I'm not sure whether your eDP screen have the hotplug signal, so I
think you can try to add "analogix,force-hpd" flag into
rk3288-veyron-jaq.dts
&edp {
analogix,need-force-hpd;
}
If that changes couldn't fix the problem, guess you may need max the panel
power up delay time which pointed by Heiko. Like:
Thanks,
- Yakir
diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
index 4fa5f69..546a506 100644
--- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
+++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
@@ -82,6 +82,13 @@ static int analogix_dp_detect_hpd(struct
analogix_dp_device *dp)
*/
dev_dbg(dp->dev, "failed to get hpd plug status, try to force
hpd\n");
+ /*
+ * Hotplug signal would indicate the right time to operate
+ * panel after poweron, but if the hotplug is missing, then
+ * panel would need wait hundreds of milliseconds at here.
+ */
+ mdelay(100);
+
analogix_dp_force_hpd(dp);
if (analogix_dp_get_plug_in_status(dp) != 0) {
> Brian
>
> [1]https://github.com/mmind/linux-rockchip/tree/devel/somewhat-stable
>
>
>
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY
2015-11-04 0:48 ` Yakir Yang
@ 2015-11-04 1:13 ` Brian Norris
2015-11-05 23:45 ` Brian Norris
0 siblings, 1 reply; 52+ messages in thread
From: Brian Norris @ 2015-11-04 1:13 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
> On 11/03/2015 12:38 PM, Brian Norris wrote:
> >On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
> >(FYI, I came across this by inspection when comparing Heiko's
> >'somewhat-stable' branch [1] with this series. The former brings up eDP
> >fine on veyron-jaq, whereas this one doesn't yet, even with the above
> >change. Still debugging the issue.)
>
> Hmm... I'm not sure whether your eDP screen have the hotplug signal, so I
I believe hotplug is hooked up but...
> think you can try to add "analogix,force-hpd" flag into
> rk3288-veyron-jaq.dts
>
> &edp {
> analogix,need-force-hpd;
> }
...already tried, just in case. No luck.
> If that changes couldn't fix the problem, guess you may need max the panel
> power up delay time which pointed by Heiko. Like:
>
> Thanks,
> - Yakir
>
>
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> index 4fa5f69..546a506 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -82,6 +82,13 @@ static int analogix_dp_detect_hpd(struct
> analogix_dp_device *dp)
> */
> dev_dbg(dp->dev, "failed to get hpd plug status, try to
> force hpd\n");
>
> + /*
> + * Hotplug signal would indicate the right time to operate
> + * panel after poweron, but if the hotplug is missing, then
> + * panel would need wait hundreds of milliseconds at here.
> + */
> + mdelay(100);
> +
> analogix_dp_force_hpd(dp);
>
> if (analogix_dp_get_plug_in_status(dp) != 0) {
I'll give that a try. Per Heiko's suggestion, I've already hacked around
with adding delays in the regulator node, but this could give slightly
different behavior. I doubt it'll help, but I'll let you know if it
does.
Regards,
Brian
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY
2015-11-04 1:13 ` Brian Norris
@ 2015-11-05 23:45 ` Brian Norris
2015-11-17 12:58 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Brian Norris @ 2015-11-05 23:45 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
A few updates:
On Tue, Nov 03, 2015 at 05:13:48PM -0800, Brian Norris wrote:
> On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
> > On 11/03/2015 12:38 PM, Brian Norris wrote:
> > >On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
> > >(FYI, I came across this by inspection when comparing Heiko's
> > >'somewhat-stable' branch [1] with this series. The former brings up eDP
> > >fine on veyron-jaq, whereas this one doesn't yet, even with the above
> > >change. Still debugging the issue.)
Some time after the above comment, I managed to kill the panel on my
Jaq :( I think the wiring around the hinge was a bit flaky, and it
finally went out for good.
> > Hmm... I'm not sure whether your eDP screen have the hotplug signal, so I
>
> I believe hotplug is hooked up but...
>
> > think you can try to add "analogix,force-hpd" flag into
> > rk3288-veyron-jaq.dts
> >
> > &edp {
> > analogix,need-force-hpd;
> > }
>
> ...already tried, just in case. No luck.
However, now when testing a different Jaq device, now this series +
Heiko's DTS updates + the "analogix,force-hpd" (i.e., [1]) works fine,
modulo a few log warnings, some of which are probably expected (for
instance, I believe the EDID is known not-so-helpful). Snippets:
[ 3.170176] rockchip-dp ff970000.dp: AUX CH command reply failed!
[ 3.178058] rockchip-dp ff970000.dp: AUX CH command reply failed!
[ 3.184166] rockchip-dp ff970000.dp: unable to handle edid
and later:
[ 3.953300] rockchip-dp ff970000.dp: EDID data does not include any extensions.
[ 3.966731] rockchip-dp ff970000.dp: EDID data does not include any extensions.
[ 3.979409] rockchip-dp ff970000.dp: EDID data does not include any extensions.
[ 3.998730] rockchip-dp ff970000.dp: Link Training Clock Recovery success
[ 4.007046] rockchip-dp ff970000.dp: Link Training success!
[ 4.115040] rockchip-dp ff970000.dp: Timeout of video streamclk ok
[ 4.121211] rockchip-dp ff970000.dp: unable to config video
[ 4.127616] rockchip-dp ff970000.dp: EDID data does not include any extensions.
So, I'll chalk that earlier failure up to a hardware failure (or
possibly a still yet-undiagnosed hardware difference; my new Jaq has
some small differences from the previous unit).
Also, it's still not real clear why HPD isn't working upstream (and we
have to use the "force-hpd" property), when it appears to work on our
downstream Chrome OS tree.
Finally, I'll leave you with some small bits I've noticed from exploring
this issue on Jaq:
* The Chrome OS driver for this IP has a much longer timeout in (the
equivalent of) analogix_dp_detect_hpd; it polls in 10-20 ms intervals
(rather than 10-11 us) and takes something around 60 to 120 ms to
notice the panel.
* AFAICT, the Chrome OS driver never actually used the HPD interrupt;
it was only polling the HPD status bit. So I can't claim that the
functionality that Yakir is supporting here has ever been tested on
these platforms. (Now, I'm not sure this is extremely important,
since we still can fall back to polled status checks; see
drm_kms_helper_poll_init().)
That's all I've got for now.
Regards,
Brian
[1] https://github.com/mmind/linux-rockchip/commits/tmp/analogixdp-veyron
plus this diff:
diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
index 5c97e3153526..e77ae4c5531e 100644
--- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
+++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
@@ -88,6 +88,18 @@
};
};
+&backlight {
+ power-supply = <&backlight_regulator>;
+};
+
+&panel {
+ power-supply = <&panel_regulator>;
+};
+
+&edp {
+ analogix,need-force-hpd;
+};
+
&rk808 {
pinctrl-names = "default";
pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
index c82c22f3d0e1..994189f49db5 100644
--- a/drivers/phy/phy-rockchip-dp.c
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -22,7 +22,7 @@
#define GRF_SOC_CON12 0x0274
-#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
2015-10-30 1:09 ` [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
@ 2015-11-11 23:10 ` Rob Herring
[not found] ` <5643EAF9.9020508@rock-chips.com>
0 siblings, 1 reply; 52+ messages in thread
From: Rob Herring @ 2015-11-11 23:10 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Oct 30, 2015 at 09:09:15AM +0800, Yakir Yang wrote:
> Some edp screen do not have hpd signal, so we can't just return
> failed when hpd plug in detect failed.
>
> This is an hardware property, so we need add a devicetree property
> "analogix,need-force-hpd" to indicate this sutiation.
>
> Tested-by: Heiko Stuebner <heiko@sntech.de>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
I didn't find this one in v10. Did it get dropped?
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> Changes in v6: None
> Changes in v5: None
> Changes in v4: None
> Changes in v3:
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
> hpd when hpd detect failed.
>
> Changes in v2: None
>
> .../bindings/display/bridge/analogix_dp.txt | 4 ++-
> .../bindings/display/exynos/exynos_dp.txt | 1 +
> .../display/rockchip/analogix_dp-rockchip.txt | 1 +
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 36 +++++++++++++++++++---
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 2 ++
> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 9 ++++++
> 6 files changed, 47 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> index 7659a7a..74f0e80 100644
> --- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> +++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> @@ -22,6 +22,9 @@ Required properties for dp-controller:
> from general PHY binding: Should be "dp".
>
> Optional properties for dp-controller:
> + -analogix,need-force-hpd:
> + Indicate driver need force hpd when hpd detect failed, this
> + is used for some eDP screen which don't have hpd signal.
This should be a generic property.
Rob
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-28 8:30 ` [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-10-28 20:36 ` Heiko Stuebner
@ 2015-11-11 23:23 ` Heiko Stuebner
[not found] ` <5643FB43.6090408@rock-chips.com>
1 sibling, 1 reply; 52+ messages in thread
From: Heiko Stuebner @ 2015-11-11 23:23 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> Add phy driver for the Rockchip DisplayPort PHY module. This
> is required to get DisplayPort working in Rockchip SoCs.
>
> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
a general thing I have been pondering, we should probably move the
dp-phy under the GRF. Similar to the new power-domains being
a full child of the PMU, the dp-phy is a full child-device of the GRF.
That would include:
- making the GRF a simply-mfd (just adding that property)
- moving the dts node under it
- making the driver get its regmap from its parent (just like
drivers/soc/rockchip/pm_domains.c does)
The usbphy is another example of that, and I think I'll be moving it
below the grf as well.
Heiko
> ---
> Changes in v8:
> - Fix the mixed spacers on macro definitions. (Heiko)
> - Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
>
> Changes in v7:
> - Simply the commit message. (Kishon)
> - Symmetrical enable/disbale the phy clock and power. (Kishon)
>
> Changes in v6: None
> Changes in v5:
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> the exist "grf" syscon already. And rename the example DT node from
> "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
> struct" to "static const struct". And correct the input paramters of
> devm_phy_create() interfaces. (Heiko)
>
> Changes in v4:
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
> function, move those code to probe() method. And remove driver .owner
> number. (Kishon)
>
> Changes in v3:
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
> power control. (Heiko)
>
> Changes in v2: None
>
> drivers/phy/Kconfig | 7 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-dp.c | 155 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 163 insertions(+)
> create mode 100644 drivers/phy/phy-rockchip-dp.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 7eb5859d..7355819 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB
> help
> Enable this to support the Rockchip USB 2.0 PHY.
>
> +config PHY_ROCKCHIP_DP
> + tristate "Rockchip Display Port PHY Driver"
> + depends on ARCH_ROCKCHIP && OF
> + select GENERIC_PHY
> + help
> + Enable this to support the Rockchip Display Port PHY.
> +
> config PHY_ST_SPEAR1310_MIPHY
> tristate "ST SPEAR1310-MIPHY driver"
> select GENERIC_PHY
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 075db1a..b1700cd 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> +obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
> obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
> obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
> obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> new file mode 100644
> index 0000000..c82c22f
> --- /dev/null
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -0,0 +1,155 @@
> +/*
> + * Rockchip DP PHY driver
> + *
> + * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
> + * Author: Yakir Yang <ykk@@rock-chips.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License.
> + */
> +
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/clk.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/platform_device.h>
> +
> +#define GRF_SOC_CON12 0x0274
> +
> +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
> +#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
> +
> +#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
> +#define GRF_EDP_PHY_SIDDQ_ON 0
> +#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
> +
> +struct rockchip_dp_phy {
> + struct device *dev;
> + struct regmap *grf;
> + struct clk *phy_24m;
> +};
> +
> +static int rockchip_set_phy_state(struct phy *phy, bool enable)
> +{
> + struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
> + int ret;
> +
> + if (enable) {
> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
> + GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
> + GRF_EDP_PHY_SIDDQ_ON);
> + if (ret < 0) {
> + dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
> + return ret;
> + }
> +
> + ret = clk_prepare_enable(dp->phy_24m);
> + } else {
> + clk_disable_unprepare(dp->phy_24m);
> +
> + ret = regmap_write(dp->grf, GRF_SOC_CON12,
> + GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
> + GRF_EDP_PHY_SIDDQ_OFF);
> + }
> +
> + return ret;
> +}
> +
> +static int rockchip_dp_phy_power_on(struct phy *phy)
> +{
> + return rockchip_set_phy_state(phy, true);
> +}
> +
> +static int rockchip_dp_phy_power_off(struct phy *phy)
> +{
> + return rockchip_set_phy_state(phy, false);
> +}
> +
> +static const struct phy_ops rockchip_dp_phy_ops = {
> + .power_on = rockchip_dp_phy_power_on,
> + .power_off = rockchip_dp_phy_power_off,
> + .owner = THIS_MODULE,
> +};
> +
> +static int rockchip_dp_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct phy_provider *phy_provider;
> + struct rockchip_dp_phy *dp;
> + struct resource *res;
> + struct phy *phy;
> + int ret;
> +
> + if (!np)
> + return -ENODEV;
> +
> + dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
> + if (IS_ERR(dp))
> + return -ENOMEM;
> +
> + dp->dev = dev;
> +
> + dp->phy_24m = devm_clk_get(dev, "24m");
> + if (IS_ERR(dp->phy_24m)) {
> + dev_err(dev, "cannot get clock 24m\n");
> + return PTR_ERR(dp->phy_24m);
> + }
> +
> + ret = clk_set_rate(dp->phy_24m, 24000000);
> + if (ret < 0) {
> + dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
> + return ret;
> + }
> +
> + dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
> + if (IS_ERR(dp->grf)) {
> + dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
> + return PTR_ERR(dp->grf);
> + }
> +
> + ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
> + GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
> + if (ret != 0) {
> + dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
> + return ret;
> + }
> +
> + phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
> + if (IS_ERR(phy)) {
> + dev_err(dev, "failed to create phy\n");
> + return PTR_ERR(phy);
> + }
> + phy_set_drvdata(phy, dp);
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
> + { .compatible = "rockchip,rk3288-dp-phy" },
> + {}
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
> +
> +static struct platform_driver rockchip_dp_phy_driver = {
> + .probe = rockchip_dp_phy_probe,
> + .driver = {
> + .name = "rockchip-dp-phy",
> + .of_match_table = rockchip_dp_phy_dt_ids,
> + },
> +};
> +
> +module_platform_driver(rockchip_dp_phy_driver);
> +
> +MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
> +MODULE_DESCRIPTION("Rockchip DP PHY driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY
[not found] ` <5643FB43.6090408@rock-chips.com>
@ 2015-11-12 9:21 ` Heiko Stuebner
0 siblings, 0 replies; 52+ messages in thread
From: Heiko Stuebner @ 2015-11-12 9:21 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Donnerstag, 12. November 2015, 10:36:51 schrieb Yakir Yang:
> On 11/12/2015 07:23 AM, Heiko Stuebner wrote:
> > Am Mittwoch, 28. Oktober 2015, 16:30:33 schrieb Yakir Yang:
> >> Add phy driver for the Rockchip DisplayPort PHY module. This
> >> is required to get DisplayPort working in Rockchip SoCs.
> >>
> >> Reviewed-by: Heiko Stuebner <heiko@sntech.de>
> >> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> > a general thing I have been pondering, we should probably move the
> > dp-phy under the GRF. Similar to the new power-domains being
> > a full child of the PMU, the dp-phy is a full child-device of the GRF.
> >
> > That would include:
> > - making the GRF a simply-mfd (just adding that property)
> > - moving the dts node under it
> > - making the driver get its regmap from its parent (just like
> > drivers/soc/rockchip/pm_domains.c does)
> >
> >
> > The usbphy is another example of that, and I think I'll be moving it
> > below the grf as well.
>
> Sounds great, pretty cool to collect those scattered "GRF" driver,
> if you want me do some rebase on your changes, please note me :)
nope, that won't be necessary ... I'm currently doing some usbphy
reorganization/cleanups for 4.5 first, so to keep conflicts down I'll do
the move probably for 4.6. As I expect your edp series to make it into
4.5 we'll also not have conflicts here then :-)
Heiko
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed
[not found] ` <5643EAF9.9020508@rock-chips.com>
@ 2015-11-12 23:38 ` Rob Herring
0 siblings, 0 replies; 52+ messages in thread
From: Rob Herring @ 2015-11-12 23:38 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Nov 12, 2015 at 09:27:21AM +0800, Yakir Yang wrote:
> Hi Rob,
>
> On 11/12/2015 07:10 AM, Rob Herring wrote:
> >On Fri, Oct 30, 2015 at 09:09:15AM +0800, Yakir Yang wrote:
> >>Some edp screen do not have hpd signal, so we can't just return
> >>failed when hpd plug in detect failed.
> >>
> >>This is an hardware property, so we need add a devicetree property
> >>"analogix,need-force-hpd" to indicate this sutiation.
> >>
> >>Tested-by: Heiko Stuebner <heiko@sntech.de>
> >>Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> >>Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> >>---
> >I didn't find this one in v10. Did it get dropped?
>
> You are in my 'to' list, but I haven't send the whole v10 out,
> most of them don't need update :)
Okay, it's just gmail's inability to follow threading...
> This series should be:
> ---- [v8 0/17 ...]
> |---- [v8 1/17 ...]
> |---- [v8 2/17 ...]
> |---- [v8 3/17 ...]
> |---- [...]
> |---- [v8 15/17 ...]
> |---- [v8 16/17 ...]
> |---- [v8 17/17 ...]
> |
> |---- [v9 10/17 ...]
> |---- [v9 15/17 ...]
> |---- We are here
> |---- [v9 09/17 ...]
> |---- [v10 09/17 ...]
> |---- Received an acked from you
> >>diff --git a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> >>index 7659a7a..74f0e80 100644
> >>--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> >>+++ b/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> >>@@ -22,6 +22,9 @@ Required properties for dp-controller:
> >> from general PHY binding: Should be "dp".
> >> Optional properties for dp-controller:
> >>+ -analogix,need-force-hpd:
> >>+ Indicate driver need force hpd when hpd detect failed, this
> >>+ is used for some eDP screen which don't have hpd signal.
> >This should be a generic property.
>
> This property would only need in some no-hpd case, it would be dropped if
> panel keep the hotplug signal, that's why I thought it should be optional.
I agree it is optional. I just mean drop the analogix and put in a
common binding doc (i.e. create a display/bridge/common.txt). Needing to
ignore HPD is probably a common problem.
> I thought if we put this a property to generic property, then we must need
> to define it in normal device node, not sure whether it is right :)
Sorry, I don't follow.
Rob
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY
2015-11-05 23:45 ` Brian Norris
@ 2015-11-17 12:58 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-11-17 12:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi Brian,
Thank you for debugging, and fell sorry for the delay reply
On 11/06/2015 07:45 AM, Brian Norris wrote:
> Hi,
>
> A few updates:
>
> On Tue, Nov 03, 2015 at 05:13:48PM -0800, Brian Norris wrote:
>> On Wed, Nov 04, 2015 at 08:48:38AM +0800, Yakir Yang wrote:
>>> On 11/03/2015 12:38 PM, Brian Norris wrote:
>>>> On Thu, Oct 29, 2015 at 09:58:38AM +0800, Yakir Yang wrote:
>>>> (FYI, I came across this by inspection when comparing Heiko's
>>>> 'somewhat-stable' branch [1] with this series. The former brings up eDP
>>>> fine on veyron-jaq, whereas this one doesn't yet, even with the above
>>>> change. Still debugging the issue.)
> Some time after the above comment, I managed to kill the panel on my
> Jaq :( I think the wiring around the hinge was a bit flaky, and it
> finally went out for good.
>
>>> Hmm... I'm not sure whether your eDP screen have the hotplug signal, so I
>> I believe hotplug is hooked up but...
>>
>>> think you can try to add "analogix,force-hpd" flag into
>>> rk3288-veyron-jaq.dts
>>>
>>> &edp {
>>> analogix,need-force-hpd;
>>> }
>> ...already tried, just in case. No luck.
> However, now when testing a different Jaq device, now this series +
> Heiko's DTS updates + the "analogix,force-hpd" (i.e., [1]) works fine,
> modulo a few log warnings, some of which are probably expected (for
> instance, I believe the EDID is known not-so-helpful). Snippets:
>
> [ 3.170176] rockchip-dp ff970000.dp: AUX CH command reply failed!
> [ 3.178058] rockchip-dp ff970000.dp: AUX CH command reply failed!
> [ 3.184166] rockchip-dp ff970000.dp: unable to handle edid
>
> and later:
>
> [ 3.953300] rockchip-dp ff970000.dp: EDID data does not include any extensions.
> [ 3.966731] rockchip-dp ff970000.dp: EDID data does not include any extensions.
> [ 3.979409] rockchip-dp ff970000.dp: EDID data does not include any extensions.
> [ 3.998730] rockchip-dp ff970000.dp: Link Training Clock Recovery success
> [ 4.007046] rockchip-dp ff970000.dp: Link Training success!
> [ 4.115040] rockchip-dp ff970000.dp: Timeout of video streamclk ok
> [ 4.121211] rockchip-dp ff970000.dp: unable to config video
> [ 4.127616] rockchip-dp ff970000.dp: EDID data does not include any extensions.
>
>
> So, I'll chalk that earlier failure up to a hardware failure (or
> possibly a still yet-undiagnosed hardware difference; my new Jaq has
> some small differences from the previous unit).
Yeah, I have saw this failed on some chromebook too, but finally it transmit
successfully, so I guess this maybe caused by hardware different.
>
> Also, it's still not real clear why HPD isn't working upstream (and we
> have to use the "force-hpd" property), when it appears to work on our
> downstream Chrome OS tree.
I have tested that driver do receive the hpd interrupt when i
plugged/unplugged the
eDP screen, and at that time driver would read the HPD connected status
rightly.
But I haven't fingered out why driver couldn't get the right HPD status
in the early time,
need debug more...
> Finally, I'll leave you with some small bits I've noticed from exploring
> this issue on Jaq:
>
> * The Chrome OS driver for this IP has a much longer timeout in (the
> equivalent of) analogix_dp_detect_hpd; it polls in 10-20 ms intervals
> (rather than 10-11 us) and takes something around 60 to 120 ms to
> notice the panel.
Thanks, I have noticed it too, also I try to expand the hotplug timeout,
but Jingoo
suggested not to do that, cause it would bring external delay on Exynos
platform.
Besides from what Heiko reply, expand this delay time wouldn't give any help
on those Jaq no display case, delay the panel power up time would be the
right
way to fix that, so maybe no need to expand the hotpulg timeout.
- Thanks
> * AFAICT, the Chrome OS driver never actually used the HPD interrupt;
> it was only polling the HPD status bit. So I can't claim that the
> functionality that Yakir is supporting here has ever been tested on
> these platforms. (Now, I'm not sure this is extremely important,
> since we still can fall back to polled status checks; see
> drm_kms_helper_poll_init().)
> That's all I've got for now.
>
> Regards,
> Brian
>
> [1] https://github.com/mmind/linux-rockchip/commits/tmp/analogixdp-veyron
>
> plus this diff:
>
> diff --git a/arch/arm/boot/dts/rk3288-veyron-jaq.dts b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
> index 5c97e3153526..e77ae4c5531e 100644
> --- a/arch/arm/boot/dts/rk3288-veyron-jaq.dts
> +++ b/arch/arm/boot/dts/rk3288-veyron-jaq.dts
> @@ -88,6 +88,18 @@
> };
> };
>
> +&backlight {
> + power-supply = <&backlight_regulator>;
> +};
> +
> +&panel {
> + power-supply = <&panel_regulator>;
> +};
> +
> +&edp {
> + analogix,need-force-hpd;
> +};
> +
> &rk808 {
> pinctrl-names = "default";
> pinctrl-0 = <&pmic_int_l &dvs_1 &dvs_2>;
> diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
> index c82c22f3d0e1..994189f49db5 100644
> --- a/drivers/phy/phy-rockchip-dp.c
> +++ b/drivers/phy/phy-rockchip-dp.c
> @@ -22,7 +22,7 @@
>
> #define GRF_SOC_CON12 0x0274
>
> -#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(4)
> +#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
> #define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
>
> #define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v10 10/17] phy: Add driver for rockchip Display Port PHY
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (19 preceding siblings ...)
2015-10-31 6:42 ` [PATCH v10 " Yakir Yang
@ 2015-11-17 13:09 ` Yakir Yang
2015-11-17 13:31 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
[not found] ` <1446020519-625-1-git-send-email-ykk@rock-chips.com>
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-11-17 13:09 UTC (permalink / raw)
To: linux-arm-kernel
Add phy driver for the Rockchip DisplayPort PHY module. This
is required to get DisplayPort working in Rockchip SoCs.
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
---
Changes in v10:
- Fix the wrong macro value of GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK (Brian)
BIT(4) -> BIT(20)
Changes in v9:
- Removed the unused the variable "res" in probe function. (Heiko)
- Removed the unused head file.
Changes in v8:
- Fix the mixed spacers on macro definitions. (Heiko)
- Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
Changes in v7:
- Simply the commit message. (Kishon)
- Symmetrical enable/disbale the phy clock and power. (Kishon)
Changes in v6: None
Changes in v5:
- Remove "reg" DT property, cause driver could poweron/poweroff phy via
the exist "grf" syscon already. And rename the example DT node from
"edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
- Add deivce_node at the front of driver, update phy_ops type from "static
struct" to "static const struct". And correct the input paramters of
devm_phy_create() interfaces. (Heiko)
Changes in v4:
- Add commit message, and remove the redundant rockchip_dp_phy_init()
function, move those code to probe() method. And remove driver .owner
number. (Kishon)
Changes in v3:
- Suggest, add rockchip dp phy driver, collect the phy clocks and
power control. (Heiko)
Changes in v2: None
drivers/phy/Kconfig | 7 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-rockchip-dp.c | 151 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 159 insertions(+)
create mode 100644 drivers/phy/phy-rockchip-dp.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7eb5859d..7355819 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -319,6 +319,13 @@ config PHY_ROCKCHIP_USB
help
Enable this to support the Rockchip USB 2.0 PHY.
+config PHY_ROCKCHIP_DP
+ tristate "Rockchip Display Port PHY Driver"
+ depends on ARCH_ROCKCHIP && OF
+ select GENERIC_PHY
+ help
+ Enable this to support the Rockchip Display Port PHY.
+
config PHY_ST_SPEAR1310_MIPHY
tristate "ST SPEAR1310-MIPHY driver"
select GENERIC_PHY
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 075db1a..b1700cd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -35,6 +35,7 @@ phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
+obj-$(CONFIG_PHY_ROCKCHIP_DP) += phy-rockchip-dp.o
obj-$(CONFIG_PHY_QCOM_IPQ806X_SATA) += phy-qcom-ipq806x-sata.o
obj-$(CONFIG_PHY_ST_SPEAR1310_MIPHY) += phy-spear1310-miphy.o
obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
diff --git a/drivers/phy/phy-rockchip-dp.c b/drivers/phy/phy-rockchip-dp.c
new file mode 100644
index 0000000..3cb3bf8
--- /dev/null
+++ b/drivers/phy/phy-rockchip-dp.c
@@ -0,0 +1,151 @@
+/*
+ * Rockchip DP PHY driver
+ *
+ * Copyright (C) 2015 FuZhou Rockchip Co., Ltd.
+ * Author: Yakir Yang <ykk@@rock-chips.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/clk.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+
+#define GRF_SOC_CON12 0x0274
+
+#define GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK BIT(20)
+#define GRF_EDP_REF_CLK_SEL_INTER BIT(4)
+
+#define GRF_EDP_PHY_SIDDQ_HIWORD_MASK BIT(21)
+#define GRF_EDP_PHY_SIDDQ_ON 0
+#define GRF_EDP_PHY_SIDDQ_OFF BIT(5)
+
+struct rockchip_dp_phy {
+ struct device *dev;
+ struct regmap *grf;
+ struct clk *phy_24m;
+};
+
+static int rockchip_set_phy_state(struct phy *phy, bool enable)
+{
+ struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
+ int ret;
+
+ if (enable) {
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_ON);
+ if (ret < 0) {
+ dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
+ return ret;
+ }
+
+ ret = clk_prepare_enable(dp->phy_24m);
+ } else {
+ clk_disable_unprepare(dp->phy_24m);
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12,
+ GRF_EDP_PHY_SIDDQ_HIWORD_MASK |
+ GRF_EDP_PHY_SIDDQ_OFF);
+ }
+
+ return ret;
+}
+
+static int rockchip_dp_phy_power_on(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, true);
+}
+
+static int rockchip_dp_phy_power_off(struct phy *phy)
+{
+ return rockchip_set_phy_state(phy, false);
+}
+
+static const struct phy_ops rockchip_dp_phy_ops = {
+ .power_on = rockchip_dp_phy_power_on,
+ .power_off = rockchip_dp_phy_power_off,
+ .owner = THIS_MODULE,
+};
+
+static int rockchip_dp_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct phy_provider *phy_provider;
+ struct rockchip_dp_phy *dp;
+ struct phy *phy;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
+ if (IS_ERR(dp))
+ return -ENOMEM;
+
+ dp->dev = dev;
+
+ dp->phy_24m = devm_clk_get(dev, "24m");
+ if (IS_ERR(dp->phy_24m)) {
+ dev_err(dev, "cannot get clock 24m\n");
+ return PTR_ERR(dp->phy_24m);
+ }
+
+ ret = clk_set_rate(dp->phy_24m, 24000000);
+ if (ret < 0) {
+ dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
+ return ret;
+ }
+
+ dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
+ if (IS_ERR(dp->grf)) {
+ dev_err(dev, "rk3288-dp needs rockchip,grf property\n");
+ return PTR_ERR(dp->grf);
+ }
+
+ ret = regmap_write(dp->grf, GRF_SOC_CON12, GRF_EDP_REF_CLK_SEL_INTER |
+ GRF_EDP_REF_CLK_SEL_INTER_HIWORD_MASK);
+ if (ret != 0) {
+ dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
+ return ret;
+ }
+
+ phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create phy\n");
+ return PTR_ERR(phy);
+ }
+ phy_set_drvdata(phy, dp);
+
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
+ { .compatible = "rockchip,rk3288-dp-phy" },
+ {}
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
+
+static struct platform_driver rockchip_dp_phy_driver = {
+ .probe = rockchip_dp_phy_probe,
+ .driver = {
+ .name = "rockchip-dp-phy",
+ .of_match_table = rockchip_dp_phy_dt_ids,
+ },
+};
+
+module_platform_driver(rockchip_dp_phy_driver);
+
+MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
+MODULE_DESCRIPTION("Rockchip DP PHY driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
^ permalink raw reply related [flat|nested] 52+ messages in thread
* [PATCH v8 0/17] Add Analogix Core Display Port Driver
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
` (20 preceding siblings ...)
2015-11-17 13:09 ` [PATCH v10 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
@ 2015-11-17 13:31 ` Yakir Yang
[not found] ` <1446020519-625-1-git-send-email-ykk@rock-chips.com>
22 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-11-17 13:31 UTC (permalink / raw)
To: linux-arm-kernel
Hi Jingoo & Exynos DRM Maintainers (Inki & Andrzej & Joonyoung) & Bridge
Maintainers (Thierry?):
Ping.......
The front part of this series (exynos_dp to analogix_dp) haven't received
more comments in the pasted several months. Is it difficult to carry those
patches without new changes but rebased on the latest kernel again and
again. If you thought those patches is fine, it would be very grateful to
give some ACKs to those changes.
Thanks,
- Yakir
On 10/28/2015 04:15 PM, Yakir Yang wrote:
> Hi all,
>
> The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
> share the same IP, so a lot of parts can be re-used. I split the common
> code into bridge directory, then rk3288 and exynos only need to keep
> some platform code. Cause I can't find the exact IP name of exynos dp
> controller, so I decide to name dp core driver with "analogix" which I
> find in rk3288 eDP TRM
>
> But there are still three light registers setting differents bewteen
> exynos and rk3288.
> 1. RK3288 have five special pll resigters which not indicata in exynos
> dp controller.
> 2. The address of DP_PHY_PD(dp phy power manager register) are different
> between rk3288 and exynos.
> 3. Rk3288 and exynos have different setting with AUX_HW_RETRY_CTL(dp debug
> register).
>
> This series have been well tested on Rockchip platform with eDP panel on
> Jerry Chromebook and Display Port Monitor on RK3288 board. Also I have
> tested on Samsung Snow and Peach Pit Chromebooks, and thanks to Javier at Samsung
> help to retest the whole series on Samsung Exynos5800 Peach Pi Chromebook,
> glad to say that things works rightlly.
>
> Thanks,
> - Yakir
>
>
> Changes in v8:
> - Correct the right document path of display-timing.txt (Heiko)
> - Correct the misspell of 'from' to 'frm'. (Heiko)
> - Modify the commit subject name. (Heiko)
> - Fix the mixed spacers on macro definitions. (Heiko)
> - Remove the unnecessary empty line after clk_prepare_enable. (Heiko)
> - Remove the specific address in the example node name. (Heiko)
>
> Changes in v7:
> - Back to use the of_property_read_bool() interfacs to provoid backward
> compatibility of "hsync-active-high" "vsync-active-high" "interlaced"
> to avoid -EOVERFLOW error (Krzysztof)
> - Simply the commit message. (Kishon)
> - Symmetrical enable/disbale the phy clock and power. (Kishon)
> - Simplify the commit message. (Kishon)
>
> Changes in v6:
> - Fix the wrong code in previous series, and test on Samsung snow Chromebook
> successfully, here are the detail changes:
> =============>
> - if (!dp->panel && !dp->bridge) {
> + if (!dp->panel && !dp->ptn_bridge) {
> ret = exynos_dp_dt_parse_panel(dp);
> if (ret)
> =============>
> + encoder->bridge = bridge;
> bridge->driver_private = dp;
> bridge->encoder = encoder;
> bridge->funcs = &exynos_dp_bridge_funcs;
> ret = drm_bridge_attach(drm_dev, bridge);
> - Fix the Kconfig recursive dependency (Javier)
> - Fix Peach Pit hpd property name error:
> - hpd-gpio = <&gpx2 6 0>;
> + hpd-gpios = <&gpx2 6 0>;
>
> Changes in v5:
> - Correct the check condition of gpio_is_valid when driver try to get
> the "hpd-gpios" DT propery. (Heiko)
> - Move the platform attach callback in the front of core driver bridge
> attch function. Cause once platform failed at attach, core driver should
> still failed, so no need to init connector before platform attached (Krzysztof)
> - Keep code style no changes with the previous exynos_dp_code.c in this
> patch, and update commit message about the new export symbol (Krzysztof)
> - Gather the device type patch (v4 11/16) into this one. (Krzysztof)
> - leave out the connector registration to analogix platform driver. (Thierry)
> - Resequence this patch after analogix_dp driver have been split
> from exynos_dp code, and rephrase reasonable commit message, and
> remove some controversial style (Krzysztof)
> - analogix_dp_write_byte_to_dpcd(
> - dp, DP_TEST_RESPONSE,
> + analogix_dp_write_byte_to_dpcd(dp,
> + DP_TEST_RESPONSE,
> DP_TEST_EDID_CHECKSUM_WRITE);
> - Switch video timing type to "u32", so driver could use "of_property_read_u32"
> to get the backword timing values. Krzysztof suggest me that driver could use
> the "of_property_read_bool" to get backword timing values, but that interfacs
> would modify the original drm_display_mode timing directly (whether those
> properties exists or not).
> - Correct the misspell in commit message. (Krzysztof)
> - Remove the empty line at the end of document, and correct the endpoint
> numbers in the example DT node, and remove the regulator iomux setting
> in driver code while using the pinctl in devicetree instead. (Heiko)
> - Add device type declared, cause the previous "platform device type
> support (v4 11/16)" already merge into (v5 02/14).
> - Implement connector registration code. (Thierry)
> - Split binding doc's from driver changes. (Rob)
> - Add eDP hotplug pinctrl property. (Heiko)
> - Remove "reg" DT property, cause driver could poweron/poweroff phy via
> the exist "grf" syscon already. And rename the example DT node from
> "edp_phy: phy at ff770274" to "edp_phy: edp-phy" directly. (Heiko)
> - Add deivce_node at the front of driver, update phy_ops type from "static
> struct" to "static const struct". And correct the input paramters of
> devm_phy_create() interfaces. (Heiko)
> - Split binding doc's from driver changes. (Rob)
> - Update the rockchip,grf explain in document, and correct the clock required
> elemets in document. (Rob & Heiko)
> - Fix compiled error (Heiko)
> - Using the connector display info message to configure eDP driver input
> video mode, but hard code CRTC video output mode to RGBaaa.
>
> Changes in v4:
> - Update "analogix,hpd-gpios" to "hpd-gpios" DT propery. (Rob)
> - Rename "analogix_dp-exynos.c" file name to "exynos_dp.c" (Jingoo)
> - Create a separate folder for analogix code in bridge/ (Archit)
> - Update commit message more readable. (Jingoo)
> - Adjust the order from 05 to 04
> - Provide backword compatibility with samsung. (Krzysztof)
> - Split all DTS changes, and provide backward compatibility. Mark old
> properties as deprecated but still support them. (Krzysztof)
> - Update "analogix,hpd-gpio" to "hpd-gpios" prop name. (Rob)
> - Deprecated some properties which could parsed from Edid/Mode/DPCD. (Thierry)
> "analogix,color-space" & "analogix,color-depth" &
> "analogix,link-rate" & "analogix,lane-count" &
> "analogix,ycbcr-coeff" & "analogix,dynamic-range" &
> "vsync-active-high" & "hsync-active-high" & "interlaces"
> - Separate all DTS changes to a separate patch. (Krzysztof)
> - Remove some deprecated DT properties in rockchip dp document.
> - Add commit message, and remove the redundant rockchip_dp_phy_init()
> function, move those code to probe() method. And remove driver .owner
> number. (Kishon)
> - Seprate the link-rate and lane-count limit out with the device_type
> flag. (Thierry)
> - Take Jingoo suggest, add commit messages.
> - Call drm_panel_prepare() in .get_modes function, ensure panel should
> power on before driver try to read edid message.
>
> Changes in v3:
> - Move exynos's video_timing code to analogix_dp-exynos platform driver,
> add get_modes method to struct analogix_dp_plat_data. (Thierry)
> - Rename some "samsung*" dts propery to "analogix*". (Heiko)
> - The link_rate and lane_count shouldn't config to the DT property value
> directly, but we can take those as hardware limite. For example, RK3288
> only support 4 physical lanes of 2.7/1.62 Gbps/lane, so DT property would
> like "link-rate = 0x0a" "lane-count = 4". (Thierry)
> - Dynamic parse video timing info from struct drm_display_mode and
> struct drm_display_info. (Thierry)
> - Add devicetree binding documents. (Heiko)
> - Remove sync pol & colorimetry properies from the new analogix dp driver
> devicetree binding. (Thierry)
> - Update the exist exynos dtsi file with the latest DP DT properies.
> - Leave "sclk_edp_24m" to rockchip dp phy driver which name to "24m",
> and leave "sclk_edp" to analogix dp core driver which name to "dp",
> and leave "pclk_edp" to rockchip dp platform driver which name to
> "pclk". (Thierry & Heiko)
> - Add devicetree binding document. (Heiko)
> - Remove "rockchip,panel" DT property, take use of remote point to get panel
> node. (Heiko)
> - Add the new function point dp_platdata->get_modes() init.
> - Suggest, add rockchip dp phy driver, collect the phy clocks and
> power control. (Heiko)
> - Add "analogix,need-force-hpd" to indicate whether driver need foce
> hpd when hpd detect failed.
> - move dp hpd detect to connector detect function.
> - Add edid modes parse support
>
> Changes in v2:
> - Keep author name list no changed (Jingoo)
> - Remove new copyright (Jingoo)
> - Fix compiled failed due to analogix_dp_device misspell
> - Improved commit message more readable, and avoid using some
> uncommon style like bellow: (Joe Preches)
> - retval = exynos_dp_read_bytes_from_i2c(...
> ...);
> + retval =
> + exynos_dp_read_bytes_from_i2c(......);
> - Get panel node with remote-endpoint method, and create devicetree binding
> for driver. (Heiko)
> - Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
> leave those clock to rockchip dp phy driver.
> - Fix compile failed dut to phy_pd_addr variable misspell error
>
> Mark Yao (1):
> drm: rockchip: vop: add bpc and color mode setting
>
> Yakir Yang (16):
> drm: exynos: dp: convert to drm bridge mode
> drm: bridge: analogix/dp: split exynos dp driver to bridge directory
> drm: bridge: analogix/dp: fix some obvious code style
> drm: bridge: analogix/dp: remove duplicate configuration of link rate
> and link count
> drm: bridge: analogix/dp: dynamic parse sync_pol & interlace &
> dynamic_range
> dt-bindings: add document for analogix display port driver
> ARM: dts: exynos/dp: remove some properties that deprecated by
> analogix_dp driver
> drm: rockchip: dp: add rockchip platform dp driver
> dt-bindings: add document for rockchip variant of analogix_dp
> phy: Add driver for rockchip Display Port PHY
> dt-bindings: add document for rockchip dp phy
> drm: bridge: analogix/dp: add some rk3288 special registers setting
> drm: bridge: analogix/dp: add max link rate and lane count limit for
> RK3288
> drm: bridge: analogix/dp: try force hpd after plug in lookup failed
> drm: bridge: analogix/dp: move hpd detect to connector detect function
> drm: bridge: analogix/dp: add edid modes parse in get_modes method
>
> .../bindings/display/bridge/analogix_dp.txt | 52 +
> .../bindings/display/exynos/exynos_dp.txt | 66 +-
> .../display/rockchip/analogix_dp-rockchip.txt | 91 ++
> .../devicetree/bindings/phy/rockchip-dp-phy.txt | 22 +
> arch/arm/boot/dts/exynos5250-arndale.dts | 2 -
> arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 -
> arch/arm/boot/dts/exynos5250-snow-common.dtsi | 4 +-
> arch/arm/boot/dts/exynos5250-spring.dts | 4 +-
> arch/arm/boot/dts/exynos5420-peach-pit.dts | 4 +-
> arch/arm/boot/dts/exynos5420-smdk5420.dts | 2 -
> arch/arm/boot/dts/exynos5800-peach-pi.dts | 4 +-
> drivers/gpu/drm/bridge/Kconfig | 2 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/analogix/Kconfig | 3 +
> drivers/gpu/drm/bridge/analogix/Makefile | 1 +
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c | 1373 +++++++++++++++++++
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.h | 286 ++++
> drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c | 1294 ++++++++++++++++++
> .../analogix/analogix_dp_reg.h} | 270 ++--
> drivers/gpu/drm/exynos/Kconfig | 3 +-
> drivers/gpu/drm/exynos/Makefile | 2 +-
> drivers/gpu/drm/exynos/exynos_dp.c | 349 +++++
> drivers/gpu/drm/exynos/exynos_dp_core.c | 1404 --------------------
> drivers/gpu/drm/exynos/exynos_dp_core.h | 281 ----
> drivers/gpu/drm/exynos/exynos_dp_reg.c | 1263 ------------------
> drivers/gpu/drm/rockchip/Kconfig | 9 +
> drivers/gpu/drm/rockchip/Makefile | 1 +
> drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 457 +++++++
> drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 2 +-
> drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
> drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 32 +-
> drivers/phy/Kconfig | 7 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-rockchip-dp.c | 155 +++
> include/drm/bridge/analogix_dp.h | 42 +
> 35 files changed, 4348 insertions(+), 3145 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
> create mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
> create mode 100644 drivers/gpu/drm/bridge/analogix/Kconfig
> create mode 100644 drivers/gpu/drm/bridge/analogix/Makefile
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_core.h
> create mode 100644 drivers/gpu/drm/bridge/analogix/analogix_dp_reg.c
> rename drivers/gpu/drm/{exynos/exynos_dp_reg.h => bridge/analogix/analogix_dp_reg.h} (62%)
> create mode 100644 drivers/gpu/drm/exynos/exynos_dp.c
> delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.c
> delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_core.h
> delete mode 100644 drivers/gpu/drm/exynos/exynos_dp_reg.c
> create mode 100644 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
> create mode 100644 drivers/phy/phy-rockchip-dp.c
> create mode 100644 include/drm/bridge/analogix_dp.h
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
[not found] ` <1446020519-625-1-git-send-email-ykk@rock-chips.com>
@ 2015-11-26 17:30 ` Heiko Stübner
2015-11-27 1:20 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Heiko Stübner @ 2015-11-26 17:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:21:59 schrieb Yakir Yang:
> Split the dp core driver from exynos directory to bridge directory,
> and rename the core driver to analogix_dp_*, rename the platform
> code to exynos_dp.
>
> Beside the new analogix_dp driver would export four hooks.
> "analogix_dp_bind()" and "analogix_dp_unbind()"
> "analogix_dp_detect()" and "analogix_dp_get_modes()"
>
> The bind/unbind symbols is used for analogix platform driver to connect
> with analogix_dp core driver. And the detect/get_modes is used for analogix
> platform driver to init the connector.
>
> They reason why connector need register in helper driver is rockchip drm
> haven't implement the atomic API, but Exynos drm have implement it, so
> there would need two different connector helper functions, that's why we
> leave the connector register in helper driver.
>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
[...]
> diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
> index bd1a415..5f74f80 100644
> --- a/drivers/gpu/drm/exynos/Kconfig
> +++ b/drivers/gpu/drm/exynos/Kconfig
> @@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
> This enables support for Exynos MIPI-DSI device.
>
> config DRM_EXYNOS_DP
> - bool "EXYNOS DRM DP driver support"
> + bool "EXYNOS specific extensions for Analogix DP driver"
> depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
> + select DRM_ANALOGIX_DP
> default DRM_EXYNOS
> select DRM_PANEL
> help
This doesn't apply anymore to 4.4-rc due to other changes in there. The
exynos/Makefile is affected as well.
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
2015-11-26 17:30 ` [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Heiko Stübner
@ 2015-11-27 1:20 ` Yakir Yang
2015-11-27 8:42 ` Heiko Stübner
0 siblings, 1 reply; 52+ messages in thread
From: Yakir Yang @ 2015-11-27 1:20 UTC (permalink / raw)
To: linux-arm-kernel
Hi Heiko,
Thanks you for feedback, I do see some conflicts in Exynos Make/Kconfig
file [02/17] and dtsi file [07/17] when I try to apply this series on
4.4-rc1
branch.
Hmm... Due to I have update some patches to version 10 already, this
series may be become harder to reviewed, should I just send the whole
series out that update the version to v10.
Thanks
- Yakir
On 11/27/2015 01:30 AM, Heiko St?bner wrote:
> Hi Yakir,
>
> Am Mittwoch, 28. Oktober 2015, 16:21:59 schrieb Yakir Yang:
>> Split the dp core driver from exynos directory to bridge directory,
>> and rename the core driver to analogix_dp_*, rename the platform
>> code to exynos_dp.
>>
>> Beside the new analogix_dp driver would export four hooks.
>> "analogix_dp_bind()" and "analogix_dp_unbind()"
>> "analogix_dp_detect()" and "analogix_dp_get_modes()"
>>
>> The bind/unbind symbols is used for analogix platform driver to connect
>> with analogix_dp core driver. And the detect/get_modes is used for analogix
>> platform driver to init the connector.
>>
>> They reason why connector need register in helper driver is rockchip drm
>> haven't implement the atomic API, but Exynos drm have implement it, so
>> there would need two different connector helper functions, that's why we
>> leave the connector register in helper driver.
>>
>> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> [...]
>
>> diff --git a/drivers/gpu/drm/exynos/Kconfig b/drivers/gpu/drm/exynos/Kconfig
>> index bd1a415..5f74f80 100644
>> --- a/drivers/gpu/drm/exynos/Kconfig
>> +++ b/drivers/gpu/drm/exynos/Kconfig
>> @@ -55,8 +55,9 @@ config DRM_EXYNOS_DSI
>> This enables support for Exynos MIPI-DSI device.
>>
>> config DRM_EXYNOS_DP
>> - bool "EXYNOS DRM DP driver support"
>> + bool "EXYNOS specific extensions for Analogix DP driver"
>> depends on DRM_EXYNOS && (DRM_EXYNOS_FIMD || DRM_EXYNOS7_DECON)
>> + select DRM_ANALOGIX_DP
>> default DRM_EXYNOS
>> select DRM_PANEL
>> help
> This doesn't apply anymore to 4.4-rc due to other changes in there. The
> exynos/Makefile is affected as well.
>
>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver
2015-10-28 8:27 ` [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
@ 2015-11-27 8:41 ` Heiko Stübner
0 siblings, 0 replies; 52+ messages in thread
From: Heiko Stübner @ 2015-11-27 8:41 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Mittwoch, 28. Oktober 2015, 16:27:45 schrieb Yakir Yang:
> Rockchip have three clocks for dp controller, we leave pclk_edp
> to analogix_dp driver control, and keep the sclk_edp_24m and
> sclk_edp in platform driver.
>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
> diff --git a/drivers/gpu/drm/rockchip/Kconfig
> b/drivers/gpu/drm/rockchip/Kconfig index 35215f6..c2ba945 100644
> --- a/drivers/gpu/drm/rockchip/Kconfig
> +++ b/drivers/gpu/drm/rockchip/Kconfig
> @@ -25,3 +25,12 @@ config ROCKCHIP_DW_HDMI
> for the Synopsys DesignWare HDMI driver. If you want to
> enable HDMI on RK3288 based SoC, you should selet this
> option.
> +
> +config ROCKCHIP_ANALOGIX_DP
> + tristate "Rockchip specific extensions for Analogix DP driver"
> + depends on DRM_ROCKCHIP
> + select DRM_ANALOGIX_DP
> + help
the indentation should probably be tabs here, ROCKCHIP_DW_HDMI also does it
wrong it seems, but DRM_ROCKCHIP looks correct :-)
Heiko
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory
2015-11-27 1:20 ` Yakir Yang
@ 2015-11-27 8:42 ` Heiko Stübner
0 siblings, 0 replies; 52+ messages in thread
From: Heiko Stübner @ 2015-11-27 8:42 UTC (permalink / raw)
To: linux-arm-kernel
Hi Yakir,
Am Freitag, 27. November 2015, 09:20:44 schrieb Yakir Yang:
> Hi Heiko,
>
> Thanks you for feedback, I do see some conflicts in Exynos Make/Kconfig
> file [02/17] and dtsi file [07/17] when I try to apply this series on
> 4.4-rc1
> branch.
>
> Hmm... Due to I have update some patches to version 10 already, this
> series may be become harder to reviewed, should I just send the whole
> series out that update the version to v10.
yes, that might make sense, also because people are generally reluctant to
fixup patches when simply reviewing/testing.
Heiko
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
2015-10-28 8:56 ` [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
@ 2015-11-27 13:32 ` Heiko Stübner
2015-12-02 10:46 ` Yakir Yang
0 siblings, 1 reply; 52+ messages in thread
From: Heiko Stübner @ 2015-11-27 13:32 UTC (permalink / raw)
To: linux-arm-kernel
Am Mittwoch, 28. Oktober 2015, 16:56:01 schrieb Yakir Yang:
> There are some IP limit on rk3288 that only support 4 physical lanes
> of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
> ---
[...]
> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
> 6307060..563ffb1d 100644
> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device
> *dp) return;
> }
>
> - ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
> - dp->video_info.link_rate);
> + ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
> + dp->video_info.max_link_rate);
> if (ret) {
> dev_err(dp->dev, "unable to do link train\n");
> return;
> @@ -1156,16 +1156,25 @@ static int analogix_dp_dt_parse_pdata(struct
> analogix_dp_device *dp) struct device_node *dp_node = dp->dev->of_node;
> struct video_info *video_info = &dp->video_info;
>
> - if (of_property_read_u32(dp_node, "samsung,link-rate",
> - &video_info->link_rate)) {
> - dev_err(dp->dev, "failed to get link-rate\n");
> - return -EINVAL;
> - }
> -
> - if (of_property_read_u32(dp_node, "samsung,lane-count",
> - &video_info->lane_count)) {
> - dev_err(dp->dev, "failed to get lane-count\n");
> - return -EINVAL;
> + switch (dp->plat_data && dp->plat_data->dev_type) {
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c: In function ?analogix_dp_dt_parse_pdata?:
drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:1191:10: warning: switch condition has boolean value [-Wswitch-bool]
switch (dp->plat_data && dp->plat_data->dev_type) {
^
As I think we always will need to distinguish between implementations,
I guess it should be safe to exit with an error, it that implementation-data
is not available, like just doing before the switch a:
if (!dp->plat_data)
return -EINVAL;
Heiko
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
2015-11-27 13:32 ` Heiko Stübner
@ 2015-12-02 10:46 ` Yakir Yang
0 siblings, 0 replies; 52+ messages in thread
From: Yakir Yang @ 2015-12-02 10:46 UTC (permalink / raw)
To: linux-arm-kernel
Hi Heiko,
On 11/27/2015 09:32 PM, Heiko St?bner wrote:
> Am Mittwoch, 28. Oktober 2015, 16:56:01 schrieb Yakir Yang:
>> There are some IP limit on rk3288 that only support 4 physical lanes
>> of 2.7/1.6 Gbps/lane, so seprate them out by device_type flag.
>>
>> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
>> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
>> ---
> [...]
>
>> diff --git a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c index
>> 6307060..563ffb1d 100644
>> --- a/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> +++ b/drivers/gpu/drm/bridge/analogix/analogix_dp_core.c
>> @@ -890,8 +890,8 @@ static void analogix_dp_commit(struct analogix_dp_device
>> *dp) return;
>> }
>>
>> - ret = analogix_dp_set_link_train(dp, dp->video_info.lane_count,
>> - dp->video_info.link_rate);
>> + ret = analogix_dp_set_link_train(dp, dp->video_info.max_lane_count,
>> + dp->video_info.max_link_rate);
>> if (ret) {
>> dev_err(dp->dev, "unable to do link train\n");
>> return;
>> @@ -1156,16 +1156,25 @@ static int analogix_dp_dt_parse_pdata(struct
>> analogix_dp_device *dp) struct device_node *dp_node = dp->dev->of_node;
>> struct video_info *video_info = &dp->video_info;
>>
>> - if (of_property_read_u32(dp_node, "samsung,link-rate",
>> - &video_info->link_rate)) {
>> - dev_err(dp->dev, "failed to get link-rate\n");
>> - return -EINVAL;
>> - }
>> -
>> - if (of_property_read_u32(dp_node, "samsung,lane-count",
>> - &video_info->lane_count)) {
>> - dev_err(dp->dev, "failed to get lane-count\n");
>> - return -EINVAL;
>> + switch (dp->plat_data && dp->plat_data->dev_type) {
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c: In function ?analogix_dp_dt_parse_pdata?:
> drivers/gpu/drm/bridge/analogix/analogix_dp_core.c:1191:10: warning: switch condition has boolean value [-Wswitch-bool]
> switch (dp->plat_data && dp->plat_data->dev_type) {
> ^
>
> As I think we always will need to distinguish between implementations,
> I guess it should be safe to exit with an error, it that implementation-data
> is not available, like just doing before the switch a:
>
> if (!dp->plat_data)
> return -EINVAL;
Done, thanks
- Yakir
>
> Heiko
>
>
>
^ permalink raw reply [flat|nested] 52+ messages in thread
* [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode
2015-10-28 8:19 ` [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
@ 2016-03-22 22:22 ` Inki Dae
0 siblings, 0 replies; 52+ messages in thread
From: Inki Dae @ 2016-03-22 22:22 UTC (permalink / raw)
To: linux-arm-kernel
2015? 10? 28? 17:19? Yakir Yang ?(?) ? ?:
> In order to move exynos dp code to bridge directory,
> we need to convert driver drm bridge mode first. As
> dp driver already have a ptn3460 bridge, so we need
> to move ptn bridge to the next bridge of dp bridge.
>
> Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
> Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Thanks,
Inki Dae
> ---
> Changes in v8: None
> Changes in v7: None
> Changes in v6:
> - Fix the wrong code in previous series, and test on Samsung snow Chromebook
> successfully, here are the detail changes:
> =============>
> - if (!dp->panel && !dp->bridge) {
> + if (!dp->panel && !dp->ptn_bridge) {
> ret = exynos_dp_dt_parse_panel(dp);
> if (ret)
> =============>
> + encoder->bridge = bridge;
> bridge->driver_private = dp;
> bridge->encoder = encoder;
> bridge->funcs = &exynos_dp_bridge_funcs;
> ret = drm_bridge_attach(drm_dev, bridge);
>
> Changes in v5: None
> Changes in v4: None
> Changes in v3: None
> Changes in v2:
> - Keep author name list no changed (Jingoo)
>
> drivers/gpu/drm/exynos/exynos_dp_core.c | 103 ++++++++++++++++++++++++--------
> drivers/gpu/drm/exynos/exynos_dp_core.h | 1 +
> 2 files changed, 78 insertions(+), 26 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.c b/drivers/gpu/drm/exynos/exynos_dp_core.c
> index 124fb9a..aedd074 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.c
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.c
> @@ -1009,9 +1009,9 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> {
> int ret;
>
> - encoder->bridge = dp->bridge;
> - dp->bridge->encoder = encoder;
> - ret = drm_bridge_attach(encoder->dev, dp->bridge);
> + encoder->bridge->next = dp->ptn_bridge;
> + dp->ptn_bridge->encoder = encoder;
> + ret = drm_bridge_attach(encoder->dev, dp->ptn_bridge);
> if (ret) {
> DRM_ERROR("Failed to attach bridge to drm\n");
> return ret;
> @@ -1020,14 +1020,15 @@ static int exynos_drm_attach_lcd_bridge(struct exynos_dp_device *dp,
> return 0;
> }
>
> -static int exynos_dp_create_connector(struct drm_encoder *encoder)
> +static int exynos_dp_bridge_attach(struct drm_bridge *bridge)
> {
> - struct exynos_dp_device *dp = encoder_to_dp(encoder);
> + struct exynos_dp_device *dp = bridge->driver_private;
> + struct drm_encoder *encoder = &dp->encoder;
> struct drm_connector *connector = &dp->connector;
> int ret;
>
> /* Pre-empt DP connector creation if there's a bridge */
> - if (dp->bridge) {
> + if (dp->ptn_bridge) {
> ret = exynos_drm_attach_lcd_bridge(dp, encoder);
> if (!ret)
> return 0;
> @@ -1052,22 +1053,9 @@ static int exynos_dp_create_connector(struct drm_encoder *encoder)
> return ret;
> }
>
> -static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
> - const struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> -{
> - return true;
> -}
> -
> -static void exynos_dp_mode_set(struct drm_encoder *encoder,
> - struct drm_display_mode *mode,
> - struct drm_display_mode *adjusted_mode)
> -{
> -}
> -
> -static void exynos_dp_enable(struct drm_encoder *encoder)
> +static void exynos_dp_bridge_enable(struct drm_bridge *bridge)
> {
> - struct exynos_dp_device *dp = encoder_to_dp(encoder);
> + struct exynos_dp_device *dp = bridge->driver_private;
> struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
>
> if (dp->dpms_mode == DRM_MODE_DPMS_ON)
> @@ -1092,9 +1080,9 @@ static void exynos_dp_enable(struct drm_encoder *encoder)
> dp->dpms_mode = DRM_MODE_DPMS_ON;
> }
>
> -static void exynos_dp_disable(struct drm_encoder *encoder)
> +static void exynos_dp_bridge_disable(struct drm_bridge *bridge)
> {
> - struct exynos_dp_device *dp = encoder_to_dp(encoder);
> + struct exynos_dp_device *dp = bridge->driver_private;
> struct exynos_drm_crtc *crtc = dp_to_crtc(dp);
>
> if (dp->dpms_mode != DRM_MODE_DPMS_ON)
> @@ -1123,6 +1111,69 @@ static void exynos_dp_disable(struct drm_encoder *encoder)
> dp->dpms_mode = DRM_MODE_DPMS_OFF;
> }
>
> +static void exynos_dp_bridge_nop(struct drm_bridge *bridge)
> +{
> + /* do nothing */
> +}
> +
> +static const struct drm_bridge_funcs exynos_dp_bridge_funcs = {
> + .enable = exynos_dp_bridge_enable,
> + .disable = exynos_dp_bridge_disable,
> + .pre_enable = exynos_dp_bridge_nop,
> + .post_disable = exynos_dp_bridge_nop,
> + .attach = exynos_dp_bridge_attach,
> +};
> +
> +static int exynos_dp_create_connector(struct drm_encoder *encoder)
> +{
> + struct exynos_dp_device *dp = encoder_to_dp(encoder);
> + struct drm_device *drm_dev = dp->drm_dev;
> + struct drm_bridge *bridge;
> + int ret;
> +
> + bridge = devm_kzalloc(drm_dev->dev, sizeof(*bridge), GFP_KERNEL);
> + if (!bridge) {
> + DRM_ERROR("failed to allocate for drm bridge\n");
> + return -ENOMEM;
> + }
> +
> + dp->bridge = bridge;
> +
> + encoder->bridge = bridge;
> + bridge->driver_private = dp;
> + bridge->encoder = encoder;
> + bridge->funcs = &exynos_dp_bridge_funcs;
> +
> + ret = drm_bridge_attach(drm_dev, bridge);
> + if (ret) {
> + DRM_ERROR("failed to attach drm bridge\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static bool exynos_dp_mode_fixup(struct drm_encoder *encoder,
> + const struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> + return true;
> +}
> +
> +static void exynos_dp_mode_set(struct drm_encoder *encoder,
> + struct drm_display_mode *mode,
> + struct drm_display_mode *adjusted_mode)
> +{
> +}
> +
> +static void exynos_dp_enable(struct drm_encoder *encoder)
> +{
> +}
> +
> +static void exynos_dp_disable(struct drm_encoder *encoder)
> +{
> +}
> +
> static struct drm_encoder_helper_funcs exynos_dp_encoder_helper_funcs = {
> .mode_fixup = exynos_dp_mode_fixup,
> .mode_set = exynos_dp_mode_set,
> @@ -1238,7 +1289,7 @@ static int exynos_dp_bind(struct device *dev, struct device *master, void *data)
> }
> }
>
> - if (!dp->panel && !dp->bridge) {
> + if (!dp->panel && !dp->ptn_bridge) {
> ret = exynos_dp_dt_parse_panel(dp);
> if (ret)
> return ret;
> @@ -1365,9 +1416,9 @@ static int exynos_dp_probe(struct platform_device *pdev)
> if (endpoint) {
> bridge_node = of_graph_get_remote_port_parent(endpoint);
> if (bridge_node) {
> - dp->bridge = of_drm_find_bridge(bridge_node);
> + dp->ptn_bridge = of_drm_find_bridge(bridge_node);
> of_node_put(bridge_node);
> - if (!dp->bridge)
> + if (!dp->ptn_bridge)
> return -EPROBE_DEFER;
> } else
> return -EPROBE_DEFER;
> diff --git a/drivers/gpu/drm/exynos/exynos_dp_core.h b/drivers/gpu/drm/exynos/exynos_dp_core.h
> index e413b6f..66eec4b 100644
> --- a/drivers/gpu/drm/exynos/exynos_dp_core.h
> +++ b/drivers/gpu/drm/exynos/exynos_dp_core.h
> @@ -153,6 +153,7 @@ struct exynos_dp_device {
> struct drm_connector connector;
> struct drm_panel *panel;
> struct drm_bridge *bridge;
> + struct drm_bridge *ptn_bridge;
> struct clk *clock;
> unsigned int irq;
> void __iomem *reg_base;
>
^ permalink raw reply [flat|nested] 52+ messages in thread
end of thread, other threads:[~2016-03-22 22:22 UTC | newest]
Thread overview: 52+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-10-28 8:15 [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
2015-10-28 8:19 ` [PATCH v8 01/17] drm: exynos: dp: convert to drm bridge mode Yakir Yang
2016-03-22 22:22 ` Inki Dae
2015-10-28 8:23 ` [PATCH v8 03/17] drm: bridge: analogix/dp: fix some obvious code style Yakir Yang
2015-10-28 8:24 ` [PATCH v8 04/17] drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count Yakir Yang
2015-10-28 8:25 ` [PATCH v8 05/17] drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range Yakir Yang
2015-10-28 8:26 ` [PATCH v8 06/17] dt-bindings: add document for analogix display port driver Yakir Yang
2015-10-28 20:02 ` Heiko Stuebner
2015-10-29 1:12 ` Yakir Yang
2015-10-29 8:40 ` Heiko Stuebner
2015-10-28 8:27 ` [PATCH v8 07/17] ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver Yakir Yang
2015-10-28 8:27 ` [PATCH v8 08/17] drm: rockchip: dp: add rockchip platform dp driver Yakir Yang
2015-11-27 8:41 ` Heiko Stübner
2015-10-28 8:28 ` [PATCH v8 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2015-10-30 16:46 ` Rob Herring
2015-10-31 3:15 ` Yakir Yang
2015-10-28 8:30 ` [PATCH v8 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-10-28 20:36 ` Heiko Stuebner
2015-10-29 1:14 ` Yakir Yang
2015-11-11 23:23 ` Heiko Stuebner
[not found] ` <5643FB43.6090408@rock-chips.com>
2015-11-12 9:21 ` Heiko Stuebner
2015-10-28 8:31 ` [PATCH v8 11/17] dt-bindings: add document for rockchip dp phy Yakir Yang
2015-10-30 16:42 ` Rob Herring
2015-10-31 3:13 ` Yakir Yang
2015-10-28 8:52 ` [PATCH v8 12/17] drm: rockchip: vop: add bpc and color mode setting Yakir Yang
2015-10-28 8:55 ` [PATCH v8 13/17] drm: bridge: analogix/dp: add some rk3288 special registers setting Yakir Yang
2015-10-28 8:56 ` [PATCH v8 14/17] drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288 Yakir Yang
2015-11-27 13:32 ` Heiko Stübner
2015-12-02 10:46 ` Yakir Yang
2015-10-28 9:12 ` [PATCH v8 16/17] drm: bridge: analogix/dp: move hpd detect to connector detect function Yakir Yang
2015-10-28 9:13 ` [PATCH v8 17/17] drm: bridge: analogix/dp: add edid modes parse in get_modes method Yakir Yang
2015-10-29 1:58 ` [PATCH v9 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-11-03 4:38 ` Brian Norris
2015-11-04 0:48 ` Yakir Yang
2015-11-04 1:13 ` Brian Norris
2015-11-05 23:45 ` Brian Norris
2015-11-17 12:58 ` Yakir Yang
2015-10-29 17:49 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Heiko Stuebner
2015-10-30 1:05 ` Yakir Yang
2015-10-30 1:09 ` [PATCH v9 15/17] drm: bridge: analogix/dp: try force hpd after plug in lookup failed Yakir Yang
2015-11-11 23:10 ` Rob Herring
[not found] ` <5643EAF9.9020508@rock-chips.com>
2015-11-12 23:38 ` Rob Herring
2015-10-31 6:30 ` [PATCH v9 09/17] dt-bindings: add document for rockchip variant of analogix_dp Yakir Yang
2015-10-31 6:40 ` Yakir Yang
2015-10-31 6:42 ` [PATCH v10 " Yakir Yang
2015-10-31 18:37 ` Rob Herring
2015-11-02 0:41 ` Yakir Yang
2015-11-17 13:09 ` [PATCH v10 10/17] phy: Add driver for rockchip Display Port PHY Yakir Yang
2015-11-17 13:31 ` [PATCH v8 0/17] Add Analogix Core Display Port Driver Yakir Yang
[not found] ` <1446020519-625-1-git-send-email-ykk@rock-chips.com>
2015-11-26 17:30 ` [PATCH v8 02/17] drm: bridge: analogix/dp: split exynos dp driver to bridge directory Heiko Stübner
2015-11-27 1:20 ` Yakir Yang
2015-11-27 8:42 ` Heiko Stübner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).