[PATCH net-next 0/2] net:axienet: Add a DT property to configure frequency of the MDIO bus

[PATCH net-next 0/2] net:axienet: Add a DT property to configure frequency of the MDIO bus

[Andy Chiu]

Some FPGA platforms have to set frequency of the MDIO bus lower than 2.5
MHz. Thus, we add a DT property to work with them at boot time. The
default 2.5 MHz would be set if the property is not pressent.

Andy Chiu (2):
  net:xilinx_axi: set mdio frequency according to DT
  dt-bindings: add mdio frequency description

 .../bindings/net/xilinx_axienet.txt           |  3 +++
 .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 25 ++++++++++++++++---
 2 files changed, 24 insertions(+), 4 deletions(-)

-- 
2.36.0


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[PATCH net-next 1/2] net:xilinx_axi: set mdio frequency according to DT

[Andy Chiu]

Some FPGA platforms has 80KHz MDIO bus frequency constraint when
conecting Ethernet to its on-board external Marvell PHY. Thus, we may
have to set MDIO clock according to the DT. Otherwise, use the default
2.5 MHz, as specified by 802.3, if the entry is not present.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
---
 .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 25 ++++++++++++++++---
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
index 0b3b6935c558..d07c39d3bcf0 100644
--- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
+++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
@@ -18,6 +18,7 @@
 #include "xilinx_axienet.h"
 
 #define MAX_MDIO_FREQ		2500000 /* 2.5 MHz */
+#define MDIO_CLK_DIV_MASK	0x3f /* bits[5:0] */
 #define DEFAULT_HOST_CLOCK	150000000 /* 150 MHz */
 
 /* Wait till MDIO interface is ready to accept a new transaction.*/
@@ -155,7 +156,9 @@ static int axienet_mdio_write(struct mii_bus *bus, int phy_id, int reg,
  **/
 int axienet_mdio_enable(struct axienet_local *lp)
 {
+	u32 clk_div;
 	u32 host_clock;
+	u32 mdio_freq;
 
 	lp->mii_clk_div = 0;
 
@@ -184,6 +187,13 @@ int axienet_mdio_enable(struct axienet_local *lp)
 			    host_clock);
 	}
 
+	if (of_property_read_u32(lp->dev->of_node, "xlnx,mdio-freq",
+				 &mdio_freq)) {
+		mdio_freq = MAX_MDIO_FREQ;
+		netdev_info(lp->ndev, "Setting default mdio clock to %u\n",
+			    mdio_freq);
+	}
+
 	/* clk_div can be calculated by deriving it from the equation:
 	 * fMDIO = fHOST / ((1 + clk_div) * 2)
 	 *
@@ -209,13 +219,20 @@ int axienet_mdio_enable(struct axienet_local *lp)
 	 * "clock-frequency" from the CPU
 	 */
 
-	lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
+	clk_div = (host_clock / (mdio_freq * 2)) - 1;
 	/* If there is any remainder from the division of
-	 * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
+	 * fHOST / (mdio_freq * 2), then we need to add
 	 * 1 to the clock divisor or we will surely be above 2.5 MHz
 	 */
-	if (host_clock % (MAX_MDIO_FREQ * 2))
-		lp->mii_clk_div++;
+	if (host_clock % (mdio_freq * 2))
+		clk_div++;
+
+	/* Check for overflow of mii_clk_div */
+	if (clk_div & ~MDIO_CLK_DIV_MASK) {
+		netdev_dbg(lp->ndev, "MDIO clock divisor overflow, setting to maximum value\n");
+		clk_div = MDIO_CLK_DIV_MASK;
+	}
+	lp->mii_clk_div = (u8)clk_div;
 
 	netdev_dbg(lp->ndev,
 		   "Setting MDIO clock divisor to %u/%u Hz host clock.\n",
-- 
2.36.0


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Re: [PATCH net-next 1/2] net:xilinx_axi: set mdio frequency according to DT

[Alexander Stein]

Hi,

Am Donnerstag, 20. Oktober 2022, 11:41:05 CEST schrieb Andy Chiu:
> Some FPGA platforms has 80KHz MDIO bus frequency constraint when
> conecting Ethernet to its on-board external Marvell PHY. Thus, we may
> have to set MDIO clock according to the DT. Otherwise, use the default
> 2.5 MHz, as specified by 802.3, if the entry is not present.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>  .../net/ethernet/xilinx/xilinx_axienet_mdio.c | 25 ++++++++++++++++---
>  1 file changed, 21 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c index
> 0b3b6935c558..d07c39d3bcf0 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
> @@ -18,6 +18,7 @@
>  #include "xilinx_axienet.h"
> 
>  #define MAX_MDIO_FREQ		2500000 /* 2.5 MHz */
> +#define MDIO_CLK_DIV_MASK	0x3f /* bits[5:0] */
>  #define DEFAULT_HOST_CLOCK	150000000 /* 150 MHz */
> 
>  /* Wait till MDIO interface is ready to accept a new transaction.*/
> @@ -155,7 +156,9 @@ static int axienet_mdio_write(struct mii_bus *bus, int
> phy_id, int reg, **/
>  int axienet_mdio_enable(struct axienet_local *lp)
>  {
> +	u32 clk_div;
>  	u32 host_clock;
> +	u32 mdio_freq;
> 
>  	lp->mii_clk_div = 0;
> 
> @@ -184,6 +187,13 @@ int axienet_mdio_enable(struct axienet_local *lp)
>  			    host_clock);
>  	}
> 
> +	if (of_property_read_u32(lp->dev->of_node, "xlnx,mdio-freq",
> +				 &mdio_freq)) {
> +		mdio_freq = MAX_MDIO_FREQ;
> +		netdev_info(lp->ndev, "Setting default mdio clock to 
%u\n",
> +			    mdio_freq);

I would opt to print this message only if using non-default frequency.

Best regards,
Alexander

> +	}
> +
>  	/* clk_div can be calculated by deriving it from the equation:
>  	 * fMDIO = fHOST / ((1 + clk_div) * 2)
>  	 *
> @@ -209,13 +219,20 @@ int axienet_mdio_enable(struct axienet_local *lp)
>  	 * "clock-frequency" from the CPU
>  	 */
> 
> -	lp->mii_clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1;
> +	clk_div = (host_clock / (mdio_freq * 2)) - 1;
>  	/* If there is any remainder from the division of
> -	 * fHOST / (MAX_MDIO_FREQ * 2), then we need to add
> +	 * fHOST / (mdio_freq * 2), then we need to add
>  	 * 1 to the clock divisor or we will surely be above 2.5 MHz
>  	 */
> -	if (host_clock % (MAX_MDIO_FREQ * 2))
> -		lp->mii_clk_div++;
> +	if (host_clock % (mdio_freq * 2))
> +		clk_div++;
> +
> +	/* Check for overflow of mii_clk_div */
> +	if (clk_div & ~MDIO_CLK_DIV_MASK) {
> +		netdev_dbg(lp->ndev, "MDIO clock divisor overflow, 
setting to maximum
> value\n"); +		clk_div = MDIO_CLK_DIV_MASK;
> +	}
> +	lp->mii_clk_div = (u8)clk_div;
> 
>  	netdev_dbg(lp->ndev,
>  		   "Setting MDIO clock divisor to %u/%u Hz host clock.
\n",





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[PATCH net-next 2/2] dt-bindings: add mdio frequency description

[Andy Chiu]

Add a property to set mdio bus frequency at runtime by DT.

Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
---
 Documentation/devicetree/bindings/net/xilinx_axienet.txt | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
index 1aa4c6006cd0..d78cf402aa2a 100644
--- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
+++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
@@ -43,6 +43,9 @@ Optional properties:
 		  support both 1000BaseX and SGMII modes. If set, the phy-mode
 		  should be set to match the mode selected on core reset (i.e.
 		  by the basex_or_sgmii core input line).
+- xlnx,mdio-freq: Define the clock frequency of the MDIO bus. If the property
+		  does not pressent on the DT, then the mdio driver would use
+		  the default 2.5 MHz clock, as mentioned on 802.3 spc.
 - clock-names: 	  Tuple listing input clock names. Possible clocks:
 		  s_axi_lite_clk: Clock for AXI register slave interface
 		  axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
-- 
2.36.0


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Re: [PATCH net-next 2/2] dt-bindings: add mdio frequency description

[Michal Simek]

On 10/20/22 11:41, Andy Chiu wrote:
> CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
> 
> 
> Add a property to set mdio bus frequency at runtime by DT.
> 
> Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
> ---
>   Documentation/devicetree/bindings/net/xilinx_axienet.txt | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> index 1aa4c6006cd0..d78cf402aa2a 100644
> --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> @@ -43,6 +43,9 @@ Optional properties:
>                    support both 1000BaseX and SGMII modes. If set, the phy-mode
>                    should be set to match the mode selected on core reset (i.e.
>                    by the basex_or_sgmii core input line).
> +- xlnx,mdio-freq: Define the clock frequency of the MDIO bus. If the property
> +                 does not pressent on the DT, then the mdio driver would use
> +                 the default 2.5 MHz clock, as mentioned on 802.3 spc.

Isn't it better to specify it based on ccf description. It means &clk and used 
clock framework to find value?

Thanks,
Michal

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Re: [PATCH net-next 2/2] dt-bindings: add mdio frequency description

[Rob Herring]

On Thu, Oct 20, 2022 at 12:39:46PM +0200, Michal Simek wrote:
> 
> 
> On 10/20/22 11:41, Andy Chiu wrote:
> > CAUTION: This message has originated from an External Source. Please use proper judgment and caution when opening attachments, clicking links, or responding to this email.
> > 
> > 
> > Add a property to set mdio bus frequency at runtime by DT.
> > 
> > Signed-off-by: Andy Chiu <andy.chiu@sifive.com>
> > Reviewed-by: Greentime Hu <greentime.hu@sifive.com>
> > ---
> >   Documentation/devicetree/bindings/net/xilinx_axienet.txt | 3 +++
> >   1 file changed, 3 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/net/xilinx_axienet.txt b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > index 1aa4c6006cd0..d78cf402aa2a 100644
> > --- a/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > +++ b/Documentation/devicetree/bindings/net/xilinx_axienet.txt
> > @@ -43,6 +43,9 @@ Optional properties:
> >                    support both 1000BaseX and SGMII modes. If set, the phy-mode
> >                    should be set to match the mode selected on core reset (i.e.
> >                    by the basex_or_sgmii core input line).
> > +- xlnx,mdio-freq: Define the clock frequency of the MDIO bus. If the property
> > +                 does not pressent on the DT, then the mdio driver would use
> > +                 the default 2.5 MHz clock, as mentioned on 802.3 spc.
> 
> Isn't it better to specify it based on ccf description. It means &clk and
> used clock framework to find value?

Or use 'bus-frequency' which IIRC is defined for MDIO.

Rob

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Re: [PATCH net-next 2/2] dt-bindings: add mdio frequency description

[Andy Chiu]

> > > +- xlnx,mdio-freq: Define the clock frequency of the MDIO bus. If the property
> > > +                 does not pressent on the DT, then the mdio driver would use
> > > +                 the default 2.5 MHz clock, as mentioned on 802.3 spc.
> >
> > Isn't it better to specify it based on ccf description. It means &clk and
> > used clock framework to find value?
>
Maybe I missed something, but I'd prefer using a number to define the
frequency of the bus rather than basing on the ccf description for our
use case. First, it is more straightforward because ccf requires us to
define a separate DT node and point to it. And currently we don't need
to do extra management that would benefit from using ccf. All we need
to do with the clock is to get its frequency.

> Or use 'bus-frequency' which IIRC is defined for MDIO.
>
I found that "bus-frequency" first appeared in fsl driver but was
replaced later by the standard one, which is "clock-frequency" as
defined in mdio.yaml. We will submit a v2 patch to configure
non-convention MDIO bus frequency with that DT entry.

Thanks and regards,
Andy

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