* [PATCH v1 0/2] Add power domain support for MT8188
@ 2022-09-16 5:52 Garmin.Chang
2022-09-16 5:52 ` [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains Garmin.Chang
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Garmin.Chang @ 2022-09-16 5:52 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Garmin.Chang
Base on tag: next-20220915, linux-next/master
Garmin.Chang (2):
dt-bindings: power: Add MT8188 power domains
soc: mediatek: pm-domains: Add support for mt8188
.../power/mediatek,power-controller.yaml | 2 +
drivers/soc/mediatek/mt8188-pm-domains.h | 623 ++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 5 +
.../dt-bindings/power/mediatek,mt8188-power.h | 44 ++
include/linux/soc/mediatek/infracfg.h | 121 ++++
5 files changed, 795 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8188-pm-domains.h
create mode 100644 include/dt-bindings/power/mediatek,mt8188-power.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains
2022-09-16 5:52 [PATCH v1 0/2] Add power domain support for MT8188 Garmin.Chang
@ 2022-09-16 5:52 ` Garmin.Chang
2022-09-16 6:24 ` Bo-Chen Chen
2022-09-18 9:42 ` Krzysztof Kozlowski
2022-09-16 5:52 ` [PATCH v1 2/2] soc: mediatek: pm-domains: Add support for mt8188 Garmin.Chang
2022-09-16 6:22 ` [PATCH v1 0/2] Add power domain support for MT8188 Bo-Chen Chen
2 siblings, 2 replies; 7+ messages in thread
From: Garmin.Chang @ 2022-09-16 5:52 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Garmin.Chang
Add power domains dt-bindings for MT8188.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Change-Id: I62dff8af2bd74d6148712bfaa1caafc0b49e4b0c
---
.../power/mediatek,power-controller.yaml | 2 +
.../dt-bindings/power/mediatek,mt8188-power.h | 44 +++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 include/dt-bindings/power/mediatek,mt8188-power.h
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 605ec7ab5f63..c9acef80f452 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -28,6 +28,7 @@ properties:
- mediatek,mt8173-power-controller
- mediatek,mt8183-power-controller
- mediatek,mt8186-power-controller
+ - mediatek,mt8188-power-controller
- mediatek,mt8192-power-controller
- mediatek,mt8195-power-controller
@@ -84,6 +85,7 @@ $defs:
"include/dt-bindings/power/mt8167-power.h" - for MT8167 type power domain.
"include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
"include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
+ "include/dt-bindings/power/mediatek,mt8188-power.h" - for MT8188 type power domain.
"include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
"include/dt-bindings/power/mt8195-power.h" - for MT8195 type power domain.
maxItems: 1
diff --git a/include/dt-bindings/power/mediatek,mt8188-power.h b/include/dt-bindings/power/mediatek,mt8188-power.h
new file mode 100644
index 000000000000..57e75cf3aa2c
--- /dev/null
+++ b/include/dt-bindings/power/mediatek,mt8188-power.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Garmin Chang <garmin.chang@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_POWER_MT8188_POWER_H
+#define _DT_BINDINGS_POWER_MT8188_POWER_H
+
+#define MT8188_POWER_DOMAIN_MFG0 0
+#define MT8188_POWER_DOMAIN_MFG1 1
+#define MT8188_POWER_DOMAIN_MFG2 2
+#define MT8188_POWER_DOMAIN_MFG3 3
+#define MT8188_POWER_DOMAIN_MFG4 4
+#define MT8188_POWER_DOMAIN_PEXTP_MAC_P0 5
+#define MT8188_POWER_DOMAIN_PEXTP_PHY_TOP 6
+#define MT8188_POWER_DOMAIN_CSIRX_TOP 7
+#define MT8188_POWER_DOMAIN_ETHER 8
+#define MT8188_POWER_DOMAIN_HDMI_TX 9
+#define MT8188_POWER_DOMAIN_ADSP_AO 10
+#define MT8188_POWER_DOMAIN_ADSP_INFRA 11
+#define MT8188_POWER_DOMAIN_ADSP 12
+#define MT8188_POWER_DOMAIN_AUDIO 13
+#define MT8188_POWER_DOMAIN_AUDIO_ASRC 14
+#define MT8188_POWER_DOMAIN_VPPSYS0 15
+#define MT8188_POWER_DOMAIN_VDOSYS0 16
+#define MT8188_POWER_DOMAIN_VDOSYS1 17
+#define MT8188_POWER_DOMAIN_DP_TX 18
+#define MT8188_POWER_DOMAIN_EDP_TX 19
+#define MT8188_POWER_DOMAIN_VPPSYS1 20
+#define MT8188_POWER_DOMAIN_WPE 21
+#define MT8188_POWER_DOMAIN_VDEC0 22
+#define MT8188_POWER_DOMAIN_VDEC1 23
+#define MT8188_POWER_DOMAIN_VENC 24
+#define MT8188_POWER_DOMAIN_IMG_VCORE 25
+#define MT8188_POWER_DOMAIN_IMG_MAIN 26
+#define MT8188_POWER_DOMAIN_DIP 27
+#define MT8188_POWER_DOMAIN_IPE 28
+#define MT8188_POWER_DOMAIN_CAM_VCORE 29
+#define MT8188_POWER_DOMAIN_CAM_MAIN 30
+#define MT8188_POWER_DOMAIN_CAM_SUBA 31
+#define MT8188_POWER_DOMAIN_CAM_SUBB 32
+
+#endif /* _DT_BINDINGS_POWER_MT8188_POWER_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v1 2/2] soc: mediatek: pm-domains: Add support for mt8188
2022-09-16 5:52 [PATCH v1 0/2] Add power domain support for MT8188 Garmin.Chang
2022-09-16 5:52 ` [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains Garmin.Chang
@ 2022-09-16 5:52 ` Garmin.Chang
2022-09-16 6:30 ` Bo-Chen Chen
2022-09-16 6:22 ` [PATCH v1 0/2] Add power domain support for MT8188 Bo-Chen Chen
2 siblings, 1 reply; 7+ messages in thread
From: Garmin.Chang @ 2022-09-16 5:52 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Garmin.Chang
Add domain control data including bus protection data size
change due to more protection steps in mt8188.
Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
Change-Id: I70ea02e6905b9bfb913123cb00d3b1d9983ef75f
---
drivers/soc/mediatek/mt8188-pm-domains.h | 623 +++++++++++++++++++++++
drivers/soc/mediatek/mtk-pm-domains.c | 5 +
include/linux/soc/mediatek/infracfg.h | 121 +++++
3 files changed, 749 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8188-pm-domains.h
diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h b/drivers/soc/mediatek/mt8188-pm-domains.h
new file mode 100644
index 000000000000..fc66db60e706
--- /dev/null
+++ b/drivers/soc/mediatek/mt8188-pm-domains.h
@@ -0,0 +1,623 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Garmin Chang <garmin.chang@mediatek.com>
+ */
+
+#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
+#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
+
+#include "mtk-pm-domains.h"
+#include <dt-bindings/power/mt8188-power.h>
+
+/*
+ * MT8188 power domain support
+ */
+
+static const struct scpsys_domain_data scpsys_domain_data_mt8188[] = {
+ [MT8188_POWER_DOMAIN_MFG0] = {
+ .name = "mfg0",
+ .sta_mask = BIT(1),
+ .ctl_offs = 0x300,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
+ },
+ [MT8188_POWER_DOMAIN_MFG1] = {
+ .name = "mfg1",
+ .sta_mask = BIT(2),
+ .ctl_offs = 0x304,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_1_SET,
+ MT8188_TOP_AXI_PROT_EN_1_CLR,
+ MT8188_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_MFG2] = {
+ .name = "mfg2",
+ .sta_mask = BIT(3),
+ .ctl_offs = 0x308,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_MFG3] = {
+ .name = "mfg3",
+ .sta_mask = BIT(4),
+ .ctl_offs = 0x30C,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_MFG4] = {
+ .name = "mfg4",
+ .sta_mask = BIT(5),
+ .ctl_offs = 0x310,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = {
+ .name = "pextp_mac_p0",
+ .sta_mask = BIT(10),
+ .ctl_offs = 0x324,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = {
+ .name = "pextp_phy_top",
+ .sta_mask = BIT(12),
+ .ctl_offs = 0x328,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_CSIRX_TOP] = {
+ .name = "pextp_csirx_top",
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x3C4,
+ .pwr_sta_offs = 0x174,
+ .pwr_sta2nd_offs = 0x178,
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_ETHER] = {
+ .name = "ether",
+ .sta_mask = BIT(1),
+ .ctl_offs = 0x338,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8188_POWER_DOMAIN_HDMI_TX] = {
+ .name = "hdmi_tx",
+ .sta_mask = BIT(18),
+ .ctl_offs = 0x37C,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8188_POWER_DOMAIN_ADSP_AO] = {
+ .name = "adsp_ao",
+ .sta_mask = BIT(10),
+ .ctl_offs = 0x35C,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ },
+ .caps = MTK_SCPD_ALWAYS_ON,
+ },
+ [MT8188_POWER_DOMAIN_ADSP_INFRA] = {
+ .name = "adsp_infra",
+ .sta_mask = BIT(9),
+ .ctl_offs = 0x358,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ },
+ .caps = MTK_SCPD_SRAM_ISO,
+ },
+ [MT8188_POWER_DOMAIN_ADSP] = {
+ .name = "adsp",
+ .sta_mask = BIT(8),
+ .ctl_offs = 0x354,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO | MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8188_POWER_DOMAIN_AUDIO] = {
+ .name = "audio",
+ .sta_mask = BIT(6),
+ .ctl_offs = 0x34C,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_ACTIVE_WAKEUP,
+ },
+ [MT8188_POWER_DOMAIN_AUDIO_ASRC] = {
+ .name = "audio_asrc",
+ .sta_mask = BIT(7),
+ .ctl_offs = 0x350,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_VPPSYS0] = {
+ .name = "vppsys0",
+ .sta_mask = BIT(11),
+ .ctl_offs = 0x360,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ },
+ },
+ [MT8188_POWER_DOMAIN_VDOSYS0] = {
+ .name = "vdosys0",
+ .sta_mask = BIT(13),
+ .ctl_offs = 0x368,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_SET,
+ MT8188_TOP_AXI_PROT_EN_CLR,
+ MT8188_TOP_AXI_PROT_EN_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+ },
+ },
+ [MT8188_POWER_DOMAIN_VDOSYS1] = {
+ .name = "vdosys1",
+ .sta_mask = BIT(14),
+ .ctl_offs = 0x36C,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ },
+ [MT8188_POWER_DOMAIN_DP_TX] = {
+ .name = "dp_tx",
+ .sta_mask = BIT(16),
+ .ctl_offs = 0x374,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_EDP_TX] = {
+ .name = "edp_tx",
+ .sta_mask = BIT(17),
+ .ctl_offs = 0x378,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+ MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_VPPSYS1] = {
+ .name = "vppsys1",
+ .sta_mask = BIT(12),
+ .ctl_offs = 0x364,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ },
+ [MT8188_POWER_DOMAIN_WPE] = {
+ .name = "wpe",
+ .sta_mask = BIT(15),
+ .ctl_offs = 0x370,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_VDEC0] = {
+ .name = "vdec0",
+ .sta_mask = BIT(19),
+ .ctl_offs = 0x380,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_VDEC1] = {
+ .name = "vdec1",
+ .sta_mask = BIT(20),
+ .ctl_offs = 0x384,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_VENC] = {
+ .name = "venc",
+ .sta_mask = BIT(22),
+ .ctl_offs = 0x38C,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_IMG_VCORE] = {
+ .name = "vcore",
+ .sta_mask = BIT(28),
+ .ctl_offs = 0x3A4,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
+ },
+ [MT8188_POWER_DOMAIN_IMG_MAIN] = {
+ .name = "img_main",
+ .sta_mask = BIT(29),
+ .ctl_offs = 0x3A8,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_DIP] = {
+ .name = "dip",
+ .sta_mask = BIT(30),
+ .ctl_offs = 0x3AC,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_IPE] = {
+ .name = "ipe",
+ .sta_mask = BIT(31),
+ .ctl_offs = 0x3B0,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_CAM_VCORE] = {
+ .name = "cam_vcore",
+ .sta_mask = BIT(27),
+ .ctl_offs = 0x3A0,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
+ MT8188_TOP_AXI_PROT_EN_1_SET,
+ MT8188_TOP_AXI_PROT_EN_1_CLR,
+ MT8188_TOP_AXI_PROT_EN_1_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
+ MT8188_TOP_AXI_PROT_EN_MM_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_DOMAIN_SUPPLY,
+ },
+ [MT8188_POWER_DOMAIN_CAM_MAIN] = {
+ .name = "cam_main",
+ .sta_mask = BIT(24),
+ .ctl_offs = 0x394,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .bp_infracfg = {
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
+ MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+ MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+ BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
+ MT8188_TOP_AXI_PROT_EN_2_SET,
+ MT8188_TOP_AXI_PROT_EN_2_CLR,
+ MT8188_TOP_AXI_PROT_EN_2_STA),
+ },
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_CAM_SUBA] = {
+ .name = "cam_suba",
+ .sta_mask = BIT(25),
+ .ctl_offs = 0x398,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+ [MT8188_POWER_DOMAIN_CAM_SUBB] = {
+ .name = "cam_subb",
+ .sta_mask = BIT(26),
+ .ctl_offs = 0x39C,
+ .pwr_sta_offs = 0x16C,
+ .pwr_sta2nd_offs = 0x170,
+ .sram_pdn_bits = BIT(8),
+ .sram_pdn_ack_bits = BIT(12),
+ .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
+ },
+};
+
+static const struct scpsys_soc_data mt8188_scpsys_data = {
+ .domains_data = scpsys_domain_data_mt8188,
+ .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188),
+};
+
+#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */
diff --git a/drivers/soc/mediatek/mtk-pm-domains.c b/drivers/soc/mediatek/mtk-pm-domains.c
index 09e3c38b8466..41220e1862b5 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.c
+++ b/drivers/soc/mediatek/mtk-pm-domains.c
@@ -21,6 +21,7 @@
#include "mt8173-pm-domains.h"
#include "mt8183-pm-domains.h"
#include "mt8186-pm-domains.h"
+#include "mt8188-pm-domains.h"
#include "mt8192-pm-domains.h"
#include "mt8195-pm-domains.h"
@@ -579,6 +580,10 @@ static const struct of_device_id scpsys_of_match[] = {
.compatible = "mediatek,mt8186-power-controller",
.data = &mt8186_scpsys_data,
},
+ {
+ .compatible = "mediatek,mt8188-power-controller",
+ .data = &mt8188_scpsys_data,
+ },
{
.compatible = "mediatek,mt8192-power-controller",
.data = &mt8192_scpsys_data,
diff --git a/include/linux/soc/mediatek/infracfg.h b/include/linux/soc/mediatek/infracfg.h
index 50804ac748bd..7d8c067f6f24 100644
--- a/include/linux/soc/mediatek/infracfg.h
+++ b/include/linux/soc/mediatek/infracfg.h
@@ -140,6 +140,127 @@
#define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
#define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
+#define MT8188_TOP_AXI_PROT_EN_SET (0x2A0)
+#define MT8188_TOP_AXI_PROT_EN_CLR (0x2A4)
+#define MT8188_TOP_AXI_PROT_EN_STA (0x228)
+#define MT8188_TOP_AXI_PROT_EN_1_SET (0x2A8)
+#define MT8188_TOP_AXI_PROT_EN_1_CLR (0x2AC)
+#define MT8188_TOP_AXI_PROT_EN_1_STA (0x258)
+#define MT8188_TOP_AXI_PROT_EN_2_SET (0x714)
+#define MT8188_TOP_AXI_PROT_EN_2_CLR (0x718)
+#define MT8188_TOP_AXI_PROT_EN_2_STA (0x724)
+
+#define MT8188_TOP_AXI_PROT_EN_MM_SET (0x2D4)
+#define MT8188_TOP_AXI_PROT_EN_MM_CLR (0x2D8)
+#define MT8188_TOP_AXI_PROT_EN_MM_STA (0x2EC)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_SET (0xDCC)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR (0xDD0)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_STA (0xDD8)
+
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET (0xB84)
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR (0xB88)
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA (0xB90)
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET (0xBCC)
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR (0xBD0)
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA (0xBD8)
+
+#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 (BIT(11))
+#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 (BIT(7))
+#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 (BIT(19))
+#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 (BIT(5))
+#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 (GENMASK(22, 21))
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 (BIT(17))
+
+#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 (BIT(2))
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8) | BIT(18) | BIT(30))
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1 (BIT(24))
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1 (BIT(20))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1 (GENMASK(31, 29))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2 (GENMASK(4, 3) | BIT(28))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMASK(16, 14) | BIT(23) | \
+ BIT(27))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMASK(19, 17) | GENMASK(26, 25))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 (GENMASK(11, 8))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 (GENMASK(22, 21))
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 (BIT(20))
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 (BIT(12))
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 (BIT(24))
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 (BIT(13))
+
+#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 (BIT(10))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 (GENMASK(9, 8))
+#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 (BIT(23))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1) | BIT(4) | BIT(11))
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20))
+#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1 (GENMASK(18, 17) | GENMASK(21, 20))
+#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 (BIT(6))
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 (BIT(21))
+#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1 (GENMASK(31, 30))
+#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2 (BIT(22))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 (BIT(10))
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1 (BIT(23))
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1 (BIT(22))
+
+#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1 (GENMASK(6, 5))
+#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2 (BIT(23))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 (BIT(18))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1 (BIT(23))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2 (BIT(21))
+#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1 (BIT(13))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2 (BIT(13))
+#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1 (BIT(14))
+#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2 (BIT(29))
+#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9) | BIT(11))
+#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 (BIT(26))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3 (BIT(2))
+#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1) | BIT(3))
+#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 (BIT(25))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 (BIT(16))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 (GENMASK(27, 26))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 (GENMASK(25, 24))
+#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2) | BIT(4))
+#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 (BIT(0))
+#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 (BIT(22))
+#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 (BIT(24))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 (BIT(17))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 (GENMASK(31, 30))
+#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2 (BIT(2))
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 (GENMASK(29, 28))
+#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4 (BIT(1))
+
+#define MT8188_SMI_COMMON_CLAMP_EN_STA (0x3C0)
+#define MT8188_SMI_COMMON_CLAMP_EN_SET (0x3C4)
+#define MT8188_SMI_COMMON_CLAMP_EN_CLR (0x3C8)
+
+#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0 (GENMASK(3, 1))
+#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1 (GENMASK(2, 1))
+#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 (BIT(0))
+
+#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 (GENMASK(3, 2))
+#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 (GENMASK(3, 2))
+
+#define MT8188_SMI_LARB10_RESET_ADDR (0xC)
+#define MT8188_SMI_LARB11A_RESET_ADDR (0xC)
+#define MT8188_SMI_LARB11C_RESET_ADDR (0xC)
+#define MT8188_SMI_LARB12_RESET_ADDR (0xC)
+#define MT8188_SMI_LARB11B_RESET_ADDR (0xC)
+#define MT8188_SMI_LARB15_RESET_ADDR (0xC)
+#define MT8188_SMI_LARB16B_RESET_ADDR (0xA0)
+#define MT8188_SMI_LARB17B_RESET_ADDR (0xA0)
+#define MT8188_SMI_LARB16A_RESET_ADDR (0xA0)
+#define MT8188_SMI_LARB17A_RESET_ADDR (0xA0)
+
+#define MT8188_SMI_LARB10_RESET (BIT(0))
+#define MT8188_SMI_LARB11A_RESET (BIT(0))
+#define MT8188_SMI_LARB11C_RESET (BIT(0))
+#define MT8188_SMI_LARB12_RESET (BIT(8))
+#define MT8188_SMI_LARB11B_RESET (BIT(0))
+#define MT8188_SMI_LARB15_RESET (BIT(0))
+#define MT8188_SMI_LARB16B_RESET (BIT(4))
+#define MT8188_SMI_LARB17B_RESET (BIT(4))
+#define MT8188_SMI_LARB16A_RESET (BIT(4))
+#define MT8188_SMI_LARB17A_RESET (BIT(4))
+
#define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
#define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
#define MT8186_TOP_AXI_PROT_EN_STA (0x228)
--
2.18.0
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v1 0/2] Add power domain support for MT8188
2022-09-16 5:52 [PATCH v1 0/2] Add power domain support for MT8188 Garmin.Chang
2022-09-16 5:52 ` [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains Garmin.Chang
2022-09-16 5:52 ` [PATCH v1 2/2] soc: mediatek: pm-domains: Add support for mt8188 Garmin.Chang
@ 2022-09-16 6:22 ` Bo-Chen Chen
2 siblings, 0 replies; 7+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 6:22 UTC (permalink / raw)
To: Garmin.Chang, Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek
On Fri, 2022-09-16 at 13:52 +0800, Garmin.Chang wrote:
> Base on tag: next-20220915, linux-next/master
>
Hello Garmin,
Please add more description for this series.
BRs,
Bo-Chen
> Garmin.Chang (2):
> dt-bindings: power: Add MT8188 power domains
> soc: mediatek: pm-domains: Add support for mt8188
>
> .../power/mediatek,power-controller.yaml | 2 +
> drivers/soc/mediatek/mt8188-pm-domains.h | 623
> ++++++++++++++++++
> drivers/soc/mediatek/mtk-pm-domains.c | 5 +
> .../dt-bindings/power/mediatek,mt8188-power.h | 44 ++
> include/linux/soc/mediatek/infracfg.h | 121 ++++
> 5 files changed, 795 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8188-pm-domains.h
> create mode 100644 include/dt-bindings/power/mediatek,mt8188-power.h
>
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains
2022-09-16 5:52 ` [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains Garmin.Chang
@ 2022-09-16 6:24 ` Bo-Chen Chen
2022-09-18 9:42 ` Krzysztof Kozlowski
1 sibling, 0 replies; 7+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 6:24 UTC (permalink / raw)
To: Garmin.Chang, Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek
On Fri, 2022-09-16 at 13:52 +0800, Garmin.Chang wrote:
> Add power domains dt-bindings for MT8188.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> Change-Id: I62dff8af2bd74d6148712bfaa1caafc0b49e4b0c
Hello Garmin,
please remove change-id.
BRs,
Bo-Chen
> ---
> .../power/mediatek,power-controller.yaml | 2 +
> .../dt-bindings/power/mediatek,mt8188-power.h | 44
> +++++++++++++++++++
> 2 files changed, 46 insertions(+)
> create mode 100644 include/dt-bindings/power/mediatek,mt8188-power.h
>
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-
> controller.yaml
> b/Documentation/devicetree/bindings/power/mediatek,power-
> controller.yaml
> index 605ec7ab5f63..c9acef80f452 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-
> controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-
> controller.yaml
> @@ -28,6 +28,7 @@ properties:
> - mediatek,mt8173-power-controller
> - mediatek,mt8183-power-controller
> - mediatek,mt8186-power-controller
> + - mediatek,mt8188-power-controller
> - mediatek,mt8192-power-controller
> - mediatek,mt8195-power-controller
>
> @@ -84,6 +85,7 @@ $defs:
> "include/dt-bindings/power/mt8167-power.h" - for
> MT8167 type power domain.
> "include/dt-bindings/power/mt8173-power.h" - for
> MT8173 type power domain.
> "include/dt-bindings/power/mt8183-power.h" - for
> MT8183 type power domain.
> + "include/dt-bindings/power/mediatek,mt8188-power.h" -
> for MT8188 type power domain.
> "include/dt-bindings/power/mt8192-power.h" - for
> MT8192 type power domain.
> "include/dt-bindings/power/mt8195-power.h" - for
> MT8195 type power domain.
> maxItems: 1
> diff --git a/include/dt-bindings/power/mediatek,mt8188-power.h
> b/include/dt-bindings/power/mediatek,mt8188-power.h
> new file mode 100644
> index 000000000000..57e75cf3aa2c
> --- /dev/null
> +++ b/include/dt-bindings/power/mediatek,mt8188-power.h
> @@ -0,0 +1,44 @@
> +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Garmin Chang <garmin.chang@mediatek.com>
> + */
> +
> +#ifndef _DT_BINDINGS_POWER_MT8188_POWER_H
> +#define _DT_BINDINGS_POWER_MT8188_POWER_H
> +
> +#define MT8188_POWER_DOMAIN_MFG0 0
> +#define MT8188_POWER_DOMAIN_MFG1 1
> +#define MT8188_POWER_DOMAIN_MFG2 2
> +#define MT8188_POWER_DOMAIN_MFG3 3
> +#define MT8188_POWER_DOMAIN_MFG4 4
> +#define MT8188_POWER_DOMAIN_PEXTP_MAC_P0 5
> +#define MT8188_POWER_DOMAIN_PEXTP_PHY_TOP 6
> +#define MT8188_POWER_DOMAIN_CSIRX_TOP 7
> +#define MT8188_POWER_DOMAIN_ETHER 8
> +#define MT8188_POWER_DOMAIN_HDMI_TX 9
> +#define MT8188_POWER_DOMAIN_ADSP_AO 10
> +#define MT8188_POWER_DOMAIN_ADSP_INFRA 11
> +#define MT8188_POWER_DOMAIN_ADSP 12
> +#define MT8188_POWER_DOMAIN_AUDIO 13
> +#define MT8188_POWER_DOMAIN_AUDIO_ASRC 14
> +#define MT8188_POWER_DOMAIN_VPPSYS0 15
> +#define MT8188_POWER_DOMAIN_VDOSYS0 16
> +#define MT8188_POWER_DOMAIN_VDOSYS1 17
> +#define MT8188_POWER_DOMAIN_DP_TX 18
> +#define MT8188_POWER_DOMAIN_EDP_TX 19
> +#define MT8188_POWER_DOMAIN_VPPSYS1 20
> +#define MT8188_POWER_DOMAIN_WPE 21
> +#define MT8188_POWER_DOMAIN_VDEC0 22
> +#define MT8188_POWER_DOMAIN_VDEC1 23
> +#define MT8188_POWER_DOMAIN_VENC 24
> +#define MT8188_POWER_DOMAIN_IMG_VCORE 25
> +#define MT8188_POWER_DOMAIN_IMG_MAIN 26
> +#define MT8188_POWER_DOMAIN_DIP 27
> +#define MT8188_POWER_DOMAIN_IPE 28
> +#define MT8188_POWER_DOMAIN_CAM_VCORE 29
> +#define MT8188_POWER_DOMAIN_CAM_MAIN 30
> +#define MT8188_POWER_DOMAIN_CAM_SUBA 31
> +#define MT8188_POWER_DOMAIN_CAM_SUBB 32
> +
> +#endif /* _DT_BINDINGS_POWER_MT8188_POWER_H */
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 2/2] soc: mediatek: pm-domains: Add support for mt8188
2022-09-16 5:52 ` [PATCH v1 2/2] soc: mediatek: pm-domains: Add support for mt8188 Garmin.Chang
@ 2022-09-16 6:30 ` Bo-Chen Chen
0 siblings, 0 replies; 7+ messages in thread
From: Bo-Chen Chen @ 2022-09-16 6:30 UTC (permalink / raw)
To: Garmin.Chang, Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek
On Fri, 2022-09-16 at 13:52 +0800, Garmin.Chang wrote:
> Add domain control data including bus protection data size
> change due to more protection steps in mt8188.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> Change-Id: I70ea02e6905b9bfb913123cb00d3b1d9983ef75f
Hello Garmin,
Please remove change-id.
> ---
> drivers/soc/mediatek/mt8188-pm-domains.h | 623
> +++++++++++++++++++++++
> drivers/soc/mediatek/mtk-pm-domains.c | 5 +
> include/linux/soc/mediatek/infracfg.h | 121 +++++
> 3 files changed, 749 insertions(+)
> create mode 100644 drivers/soc/mediatek/mt8188-pm-domains.h
>
> diff --git a/drivers/soc/mediatek/mt8188-pm-domains.h
> b/drivers/soc/mediatek/mt8188-pm-domains.h
> new file mode 100644
> index 000000000000..fc66db60e706
> --- /dev/null
> +++ b/drivers/soc/mediatek/mt8188-pm-domains.h
> @@ -0,0 +1,623 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022 MediaTek Inc.
> + * Author: Garmin Chang <garmin.chang@mediatek.com>
> + */
> +
> +#ifndef __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
> +#define __SOC_MEDIATEK_MT8188_PM_DOMAINS_H
> +
> +#include "mtk-pm-domains.h"
> +#include <dt-bindings/power/mt8188-power.h>
> +
> +/*
> + * MT8188 power domain support
> + */
> +
> +static const struct scpsys_domain_data scpsys_domain_data_mt8188[] =
> {
> + [MT8188_POWER_DOMAIN_MFG0] = {
> + .name = "mfg0",
> + .sta_mask = BIT(1),
> + .ctl_offs = 0x300,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> MTK_SCPD_DOMAIN_SUPPLY,
> + },
> + [MT8188_POWER_DOMAIN_MFG1] = {
> + .name = "mfg1",
> + .sta_mask = BIT(2),
> + .ctl_offs = 0x304,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
> + MT8188_TOP_AXI_PROT_EN_SET,
> + MT8188_TOP_AXI_PROT_EN_CLR,
> + MT8188_TOP_AXI_PROT_EN_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2
> ,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3
> ,
> + MT8188_TOP_AXI_PROT_EN_1_SET,
> + MT8188_TOP_AXI_PROT_EN_1_CLR,
> + MT8188_TOP_AXI_PROT_EN_1_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4
> ,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
> + MT8188_TOP_AXI_PROT_EN_SET,
> + MT8188_TOP_AXI_PROT_EN_CLR,
> + MT8188_TOP_AXI_PROT_EN_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> NR_MFG1_STEP6,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_S
> ET,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_C
> LR,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_S
> TA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_MFG2] = {
> + .name = "mfg2",
> + .sta_mask = BIT(3),
> + .ctl_offs = 0x308,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_MFG3] = {
> + .name = "mfg3",
> + .sta_mask = BIT(4),
> + .ctl_offs = 0x30C,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_MFG4] = {
> + .name = "mfg4",
> + .sta_mask = BIT(5),
> + .ctl_offs = 0x310,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = {
> + .name = "pextp_mac_p0",
> + .sta_mask = BIT(10),
> + .ctl_offs = 0x324,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0
> _STEP1,
> + MT8188_TOP_AXI_PROT_EN_SET,
> + MT8188_TOP_AXI_PROT_EN_CLR,
> + MT8188_TOP_AXI_PROT_EN_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_P
> EXTP_MAC_P0_STEP2,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = {
> + .name = "pextp_phy_top",
> + .sta_mask = BIT(12),
> + .ctl_offs = 0x328,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_CSIRX_TOP] = {
> + .name = "pextp_csirx_top",
> + .sta_mask = BIT(17),
> + .ctl_offs = 0x3C4,
> + .pwr_sta_offs = 0x174,
> + .pwr_sta2nd_offs = 0x178,
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_ETHER] = {
> + .name = "ether",
> + .sta_mask = BIT(1),
> + .ctl_offs = 0x338,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_E
> THER_STEP1,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8188_POWER_DOMAIN_HDMI_TX] = {
> + .name = "hdmi_tx",
> + .sta_mask = BIT(18),
> + .ctl_offs = 0x37C,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_H
> DMI_TX_STEP1,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
> + },
Please take care of the indention.
this should be
BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
MT8188_TOP_AXI_PROT_EN_SET,
MT8188_TOP_AXI_PROT_EN_CLR,
MT8188_TOP_AXI_PROT_EN_STA),
below are the same.
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8188_POWER_DOMAIN_ADSP_AO] = {
> + .name = "adsp_ao",
> + .sta_mask = BIT(10),
> + .ctl_offs = 0x35C,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_ST
> EP1,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_ST
> EP2,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + },
> + .caps = MTK_SCPD_ALWAYS_ON,
> + },
> + [MT8188_POWER_DOMAIN_ADSP_INFRA] = {
> + .name = "adsp_infra",
> + .sta_mask = BIT(9),
> + .ctl_offs = 0x358,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA
> _STEP1,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA
> _STEP2,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + },
> + .caps = MTK_SCPD_SRAM_ISO,
> + },
> + [MT8188_POWER_DOMAIN_ADSP] = {
> + .name = "adsp",
> + .sta_mask = BIT(8),
> + .ctl_offs = 0x354,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1
> ,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2
> ,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF | MTK_SCPD_SRAM_ISO |
> MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8188_POWER_DOMAIN_AUDIO] = {
> + .name = "audio",
> + .sta_mask = BIT(6),
> + .ctl_offs = 0x34C,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP
> 1,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP
> 2,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> MTK_SCPD_ACTIVE_WAKEUP,
> + },
> + [MT8188_POWER_DOMAIN_AUDIO_ASRC] = {
> + .name = "audio_asrc",
> + .sta_mask = BIT(7),
> + .ctl_offs = 0x350,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC
> _STEP1,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC
> _STEP2,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_VPPSYS0] = {
> + .name = "vppsys0",
> + .sta_mask = BIT(11),
> + .ctl_offs = 0x360,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP
> 1,
> + MT8188_TOP_AXI_PROT_EN_SET,
> + MT8188_TOP_AXI_PROT_EN_CLR,
> + MT8188_TOP_AXI_PROT_EN_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0
> _STEP2,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP
> 3,
> + MT8188_TOP_AXI_PROT_EN_SET,
> + MT8188_TOP_AXI_PROT_EN_CLR,
> + MT8188_TOP_AXI_PROT_EN_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0
> _STEP4,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> NR_VPPSYS0_STEP5,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_S
> ET,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_C
> LR,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_S
> TA),
> + },
> + },
> + [MT8188_POWER_DOMAIN_VDOSYS0] = {
> + .name = "vdosys0",
> + .sta_mask = BIT(13),
> + .ctl_offs = 0x368,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_S
> TEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP
> 2,
> + MT8188_TOP_AXI_PROT_EN_SET,
> + MT8188_TOP_AXI_PROT_EN_CLR,
> + MT8188_TOP_AXI_PROT_EN_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VD
> NR_VDOSYS0_STEP3,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_S
> ET,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_C
> LR,
> + MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_S
> TA),
> + },
> + },
> + [MT8188_POWER_DOMAIN_VDOSYS1] = {
> + .name = "vdosys1",
> + .sta_mask = BIT(14),
> + .ctl_offs = 0x36C,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_S
> TEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_S
> TEP2,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1
> _STEP3,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + },
> + [MT8188_POWER_DOMAIN_DP_TX] = {
> + .name = "dp_tx",
> + .sta_mask = BIT(16),
> + .ctl_offs = 0x374,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_D
> P_TX_STEP1,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_EDP_TX] = {
> + .name = "edp_tx",
> + .sta_mask = BIT(17),
> + .ctl_offs = 0x378,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_E
> DP_TX_STEP1,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
> + MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_VPPSYS1] = {
> + .name = "vppsys1",
> + .sta_mask = BIT(12),
> + .ctl_offs = 0x364,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_S
> TEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_S
> TEP2,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1
> _STEP3,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + },
> + [MT8188_POWER_DOMAIN_WPE] = {
> + .name = "wpe",
> + .sta_mask = BIT(15),
> + .ctl_offs = 0x370,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STE
> P1,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STE
> P2,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_VDEC0] = {
> + .name = "vdec0",
> + .sta_mask = BIT(19),
> + .ctl_offs = 0x380,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STE
> P1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_S
> TEP2,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_VDEC1] = {
> + .name = "vdec1",
> + .sta_mask = BIT(20),
> + .ctl_offs = 0x384,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STE
> P1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STE
> P2,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_VENC] = {
> + .name = "venc",
> + .sta_mask = BIT(22),
> + .ctl_offs = 0x38C,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP
> 1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP
> 2,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_ST
> EP3,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_IMG_VCORE] = {
> + .name = "vcore",
> + .sta_mask = BIT(28),
> + .ctl_offs = 0x3A4,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE
> _STEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE
> _STEP2,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCO
> RE_STEP3,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> MTK_SCPD_DOMAIN_SUPPLY,
> + },
> + [MT8188_POWER_DOMAIN_IMG_MAIN] = {
> + .name = "img_main",
> + .sta_mask = BIT(29),
> + .ctl_offs = 0x3A8,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAI
> N_STEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAI
> N_STEP2,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_DIP] = {
> + .name = "dip",
> + .sta_mask = BIT(30),
> + .ctl_offs = 0x3AC,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_IPE] = {
> + .name = "ipe",
> + .sta_mask = BIT(31),
> + .ctl_offs = 0x3B0,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_CAM_VCORE] = {
> + .name = "cam_vcore",
> + .sta_mask = BIT(27),
> + .ctl_offs = 0x3A0,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE
> _STEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_
> STEP2,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_
> STEP3,
> + MT8188_TOP_AXI_PROT_EN_1_SET,
> + MT8188_TOP_AXI_PROT_EN_1_CLR,
> + MT8188_TOP_AXI_PROT_EN_1_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE
> _STEP4,
> + MT8188_TOP_AXI_PROT_EN_MM_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCO
> RE_STEP5,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF |
> MTK_SCPD_DOMAIN_SUPPLY,
> + },
> + [MT8188_POWER_DOMAIN_CAM_MAIN] = {
> + .name = "cam_main",
> + .sta_mask = BIT(24),
> + .ctl_offs = 0x394,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .bp_infracfg = {
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAI
> N_STEP1,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_S
> TEP2,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAI
> N_STEP3,
> + MT8188_TOP_AXI_PROT_EN_MM_2_SET,
> + MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_MM_2_STA),
> + BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_S
> TEP4,
> + MT8188_TOP_AXI_PROT_EN_2_SET,
> + MT8188_TOP_AXI_PROT_EN_2_CLR,
> + MT8188_TOP_AXI_PROT_EN_2_STA),
> + },
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_CAM_SUBA] = {
> + .name = "cam_suba",
> + .sta_mask = BIT(25),
> + .ctl_offs = 0x398,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> + [MT8188_POWER_DOMAIN_CAM_SUBB] = {
> + .name = "cam_subb",
> + .sta_mask = BIT(26),
> + .ctl_offs = 0x39C,
> + .pwr_sta_offs = 0x16C,
> + .pwr_sta2nd_offs = 0x170,
> + .sram_pdn_bits = BIT(8),
> + .sram_pdn_ack_bits = BIT(12),
> + .caps = MTK_SCPD_KEEP_DEFAULT_OFF,
> + },
> +};
> +
> +static const struct scpsys_soc_data mt8188_scpsys_data = {
> + .domains_data = scpsys_domain_data_mt8188,
> + .num_domains = ARRAY_SIZE(scpsys_domain_data_mt8188),
> +};
> +
> +#endif /* __SOC_MEDIATEK_MT8188_PM_DOMAINS_H */
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.c
> b/drivers/soc/mediatek/mtk-pm-domains.c
> index 09e3c38b8466..41220e1862b5 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.c
> +++ b/drivers/soc/mediatek/mtk-pm-domains.c
> @@ -21,6 +21,7 @@
> #include "mt8173-pm-domains.h"
> #include "mt8183-pm-domains.h"
> #include "mt8186-pm-domains.h"
> +#include "mt8188-pm-domains.h"
> #include "mt8192-pm-domains.h"
> #include "mt8195-pm-domains.h"
>
> @@ -579,6 +580,10 @@ static const struct of_device_id
> scpsys_of_match[] = {
> .compatible = "mediatek,mt8186-power-controller",
> .data = &mt8186_scpsys_data,
> },
> + {
> + .compatible = "mediatek,mt8188-power-controller",
> + .data = &mt8188_scpsys_data,
> + },
> {
> .compatible = "mediatek,mt8192-power-controller",
> .data = &mt8192_scpsys_data,
> diff --git a/include/linux/soc/mediatek/infracfg.h
> b/include/linux/soc/mediatek/infracfg.h
> index 50804ac748bd..7d8c067f6f24 100644
> --- a/include/linux/soc/mediatek/infracfg.h
> +++ b/include/linux/soc/mediatek/infracfg.h
> @@ -140,6 +140,127 @@
> #define MT8192_TOP_AXI_PROT_EN_MM_2_MDP_2ND BIT(13)
> #define MT8192_TOP_AXI_PROT_EN_VDNR_CAM BIT(21)
>
> +#define MT8188_TOP_AXI_PROT_EN_SET (0x2A0)
> +#define MT8188_TOP_AXI_PROT_EN_CLR (0x2A4)
> +#define MT8188_TOP_AXI_PROT_EN_STA (0x228)
> +#define MT8188_TOP_AXI_PROT_EN_1_SET (0x2A8)
> +#define MT8188_TOP_AXI_PROT_EN_1_CLR (0x2AC)
> +#define MT8188_TOP_AXI_PROT_EN_1_STA (0x258)
> +#define MT8188_TOP_AXI_PROT_EN_2_SET (0x714)
> +#define MT8188_TOP_AXI_PROT_EN_2_CLR (0x718)
> +#define MT8188_TOP_AXI_PROT_EN_2_STA (0x724)
no need to add parentheses, just
define MT8188_TOP_AXI_PROT_EN_2_STA 0x724
drivers below are the same.
> +
> +#define MT8188_TOP_AXI_PROT_EN_MM_SET
> (0x2D4)
> +#define MT8188_TOP_AXI_PROT_EN_MM_CLR
> (0x2D8)
> +#define MT8188_TOP_AXI_PROT_EN_MM_STA
> (0x2EC)
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_SET
> (0xDCC)
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR
> (0xDD0)
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_STA
> (0xDD8)
> +
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET
> (0xB84)
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR
> (0xB88)
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA
> (0xB90)
> +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET (0xBCC)
> +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR (0xBD0)
> +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA (0xBD8)
> +
> +#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1 (BIT(11
> ))
no need to use (BIT(11)), just BIT(11)
drivers below are the same.
> +#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2 (BIT(7)
> )
> +#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3 (BIT(19
> ))
> +#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4 (BIT(5)
> )
> +#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5 (GENMAS
> K(22, 21))
ditto
> +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6 (BIT(17
> ))
> +
> +#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1 (BIT(2)
> )
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2 (BIT(8)
> | BIT(18) | BIT(30))
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1
> (BIT(24))
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1
> (BIT(20))
> +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1
> (GENMASK(31, 29))
> +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2
> (GENMASK(4, 3) | BIT(28))
> +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1 (GENMAS
> K(16, 14) | BIT(23) | \
> + BIT(27)
> )
> +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2 (GENMAS
> K(19, 17) | GENMASK(26, 25))
> +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1 (GENMAS
> K(11, 8))
> +#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2 (GENMAS
> K(22, 21))
> +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1 (BIT(20
> ))
> +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2 (BIT(12
> ))
> +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1 (BIT(24
> ))
> +#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2 (BIT(13
> ))
> +
> +#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1 (BIT(10
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2 (GENMAS
> K(9, 8))
> +#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3 (BIT(23
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4 (BIT(1)
> | BIT(4) | BIT(11))
> +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5 (BIT(20
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1
> (GENMASK(18, 17) | GENMASK(21, 20))
> +#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2 (BIT(6)
> )
> +#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3 (BIT(21
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1
> (GENMASK(31, 30))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2
> (BIT(22))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3 (BIT(10
> ))
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1
> (BIT(23))
> +#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1
> (BIT(22))
> +
> +#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1
> (GENMASK(6, 5))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2
> (BIT(23))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3 (BIT(18
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1
> (BIT(23))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2
> (BIT(21))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1
> (BIT(13))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2
> (BIT(13))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1
> (BIT(14))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2
> (BIT(29))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1 (BIT(9)
> | BIT(11))
> +#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2 (BIT(26
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3
> (BIT(2))
> +#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1 (BIT(1)
> | BIT(3))
> +#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2 (BIT(25
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3 (BIT(16
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1 (GENMAS
> K(27, 26))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2 (GENMAS
> K(25, 24))
> +#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1 (BIT(2)
> | BIT(4))
> +#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 (BIT(0)
> )
> +#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3 (BIT(22
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4 (BIT(24
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5 (BIT(17
> ))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1 (GENMAS
> K(31, 30))
> +#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2
> (BIT(2))
> +#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3 (GENMAS
> K(29, 28))
> +#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4
> (BIT(1))
> +
> +#define MT8188_SMI_COMMON_CLAMP_EN_STA
> (0x3C0)
> +#define MT8188_SMI_COMMON_CLAMP_EN_SET
> (0x3C4)
> +#define MT8188_SMI_COMMON_CLAMP_EN_CLR
> (0x3C8)
> +
> +#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VDO0
> (GENMASK(3, 1))
> +#define MT8188_SMI_COMMON_SMI_CLAMP_DIP_TO_VPP1
> (GENMASK(2, 1))
> +#define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1
> (BIT(0))
> +
> +#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBA_TO_VPP0 (GENMAS
> K(3, 2))
> +#define MT8188_SMI_COMMON_SMI_CLAMP_CAM_SUBB_TO_VDO0 (GENMAS
> K(3, 2))
> +
> +#define MT8188_SMI_LARB10_RESET_ADDR (0xC)
> +#define MT8188_SMI_LARB11A_RESET_ADDR
> (0xC)
> +#define MT8188_SMI_LARB11C_RESET_ADDR
> (0xC)
> +#define MT8188_SMI_LARB12_RESET_ADDR (0xC)
> +#define MT8188_SMI_LARB11B_RESET_ADDR
> (0xC)
> +#define MT8188_SMI_LARB15_RESET_ADDR (0xC)
> +#define MT8188_SMI_LARB16B_RESET_ADDR
> (0xA0)
> +#define MT8188_SMI_LARB17B_RESET_ADDR
> (0xA0)
> +#define MT8188_SMI_LARB16A_RESET_ADDR
> (0xA0)
> +#define MT8188_SMI_LARB17A_RESET_ADDR
> (0xA0)
> +
> +#define MT8188_SMI_LARB10_RESET
> (BIT(0))
> +#define MT8188_SMI_LARB11A_RESET (BIT(0)
> )
> +#define MT8188_SMI_LARB11C_RESET (BIT(0)
> )
> +#define MT8188_SMI_LARB12_RESET
> (BIT(8))
> +#define MT8188_SMI_LARB11B_RESET (BIT(0)
> )
> +#define MT8188_SMI_LARB15_RESET
> (BIT(0))
> +#define MT8188_SMI_LARB16B_RESET (BIT(4)
> )
> +#define MT8188_SMI_LARB17B_RESET (BIT(4)
> )
> +#define MT8188_SMI_LARB16A_RESET (BIT(4)
> )
> +#define MT8188_SMI_LARB17A_RESET (BIT(4)
> )
> +
> #define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
> #define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
> #define MT8186_TOP_AXI_PROT_EN_STA (0x228)
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains
2022-09-16 5:52 ` [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains Garmin.Chang
2022-09-16 6:24 ` Bo-Chen Chen
@ 2022-09-18 9:42 ` Krzysztof Kozlowski
1 sibling, 0 replies; 7+ messages in thread
From: Krzysztof Kozlowski @ 2022-09-18 9:42 UTC (permalink / raw)
To: Garmin.Chang, Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek
On 16/09/2022 06:52, Garmin.Chang wrote:
> Add power domains dt-bindings for MT8188.
>
> Signed-off-by: Garmin.Chang <Garmin.Chang@mediatek.com>
> Change-Id: I62dff8af2bd74d6148712bfaa1caafc0b49e4b0c
Run chechpatch before sending any patch.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-09-18 9:44 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-09-16 5:52 [PATCH v1 0/2] Add power domain support for MT8188 Garmin.Chang
2022-09-16 5:52 ` [PATCH v1 1/2] dt-bindings: power: Add MT8188 power domains Garmin.Chang
2022-09-16 6:24 ` Bo-Chen Chen
2022-09-18 9:42 ` Krzysztof Kozlowski
2022-09-16 5:52 ` [PATCH v1 2/2] soc: mediatek: pm-domains: Add support for mt8188 Garmin.Chang
2022-09-16 6:30 ` Bo-Chen Chen
2022-09-16 6:22 ` [PATCH v1 0/2] Add power domain support for MT8188 Bo-Chen Chen
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