[PATCH v2 1/3] phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_en

[PATCH v2 1/3] phy: phy-mtk-tphy: keep default value of mcu_bus_ck_gate_en

[Chunfeng Yun]

The default value of mcu_bus_ck_gate_en is 1, if clear it, will
prevent system to enter deep idle mode, so keep its default value
and without affecting PCIe function.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 1e96d07..6073c25 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -688,8 +688,7 @@ static void pcie_phy_instance_power_on(struct mtk_tphy *tphy,
 	u32 tmp;
 
 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLD);
-	tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_MCU_BUS_CK_GATE_EN |
-		P3C_REG_IP_SW_RST);
+	tmp &= ~(P3C_FORCE_IP_SW_RST | P3C_REG_IP_SW_RST);
 	writel(tmp, bank->chip + U3P_U3_CHIP_GPIO_CTLD);
 
 	tmp = readl(bank->chip + U3P_U3_CHIP_GPIO_CTLE);
-- 
1.9.1

[PATCH v2 2/3] phy: phy-mtk-tphy: add configurable parameters for slew rate calibrate

[Chunfeng Yun]

There are two parameters, ref_clk and coefficient, for U2 slew rate
calibrate which may vary on different SoCs, here allow them to be
configurable

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 drivers/phy/mediatek/phy-mtk-tphy.c | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
index 6073c25..38c281b 100644
--- a/drivers/phy/mediatek/phy-mtk-tphy.c
+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
@@ -306,6 +306,8 @@ struct mtk_tphy {
 	const struct mtk_phy_pdata *pdata;
 	struct mtk_phy_instance **phys;
 	int nphys;
+	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
+	int src_coef; /* coefficient for slew rate calibrate */
 };
 
 static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
@@ -360,16 +362,17 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
 	writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
 
 	if (fm_out) {
-		/* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */
-		tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF;
-		tmp /= fm_out;
+		/* ( 1024 / FM_OUT ) x reference clock frequency x coef */
+		tmp = tphy->src_ref_clk * tphy->src_coef;
+		tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
 		calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
 	} else {
 		/* if FM detection fail, set default value */
 		calibration_val = 4;
 	}
-	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n",
-		instance->index, fm_out, calibration_val);
+	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
+		instance->index, fm_out, calibration_val,
+		tphy->src_ref_clk, tphy->src_coef);
 
 	/* set HS slew rate */
 	tmp = readl(com + U3P_USBPHYACR5);
@@ -1041,6 +1044,13 @@ static int mtk_tphy_probe(struct platform_device *pdev)
 		tphy->u3phya_ref = NULL;
 	}
 
+	tphy->src_ref_clk = U3P_REF_CLK;
+	tphy->src_coef = U3P_SLEW_RATE_COEF;
+	/* update parameters of slew rate calibrate if exist */
+	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
+		&tphy->src_ref_clk);
+	device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
+
 	port = 0;
 	for_each_child_of_node(np, child_np) {
 		struct mtk_phy_instance *instance;
-- 
1.9.1

[PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

[Chunfeng Yun]

Add two properties of ref_clk and coefficient used by U2 slew rate
calibrate which may vary on different SoCs

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
---
 Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
index 41e09ed..0d34b2b 100644
--- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
+++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
@@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
  - reg		: offset and length of register shared by multiple ports,
 		  exclude port's private register. It is needed on mt2701
 		  and mt8173, but not on mt2712.
+ - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
+		  calibrate
+ - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
+		  SoC process
 
 Required properties (port (child) node):
 - reg		: address and length of the register set for the port.
-- 
1.9.1

[PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

[Matthias Brugger]

On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> Add two properties of ref_clk and coefficient used by U2 slew rate
> calibrate which may vary on different SoCs
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>

> ---
>  Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> index 41e09ed..0d34b2b 100644
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
>   - reg		: offset and length of register shared by multiple ports,
>  		  exclude port's private register. It is needed on mt2701
>  		  and mt8173, but not on mt2712.
> + - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
> +		  calibrate
> + - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
> +		  SoC process
>  
>  Required properties (port (child) node):
>  - reg		: address and length of the register set for the port.
> 

[PATCH v2 2/3] phy: phy-mtk-tphy: add configurable parameters for slew rate calibrate

[Matthias Brugger]

On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> There are two parameters, ref_clk and coefficient, for U2 slew rate
> calibrate which may vary on different SoCs, here allow them to be
> configurable
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>

Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>


> ---
>  drivers/phy/mediatek/phy-mtk-tphy.c | 20 +++++++++++++++-----
>  1 file changed, 15 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
> index 6073c25..38c281b 100644
> --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> @@ -306,6 +306,8 @@ struct mtk_tphy {
>  	const struct mtk_phy_pdata *pdata;
>  	struct mtk_phy_instance **phys;
>  	int nphys;
> +	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
> +	int src_coef; /* coefficient for slew rate calibrate */
>  };
>  
>  static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
> @@ -360,16 +362,17 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
>  	writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
>  
>  	if (fm_out) {
> -		/* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */
> -		tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF;
> -		tmp /= fm_out;
> +		/* ( 1024 / FM_OUT ) x reference clock frequency x coef */
> +		tmp = tphy->src_ref_clk * tphy->src_coef;
> +		tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
>  		calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
>  	} else {
>  		/* if FM detection fail, set default value */
>  		calibration_val = 4;
>  	}
> -	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n",
> -		instance->index, fm_out, calibration_val);
> +	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
> +		instance->index, fm_out, calibration_val,
> +		tphy->src_ref_clk, tphy->src_coef);
>  
>  	/* set HS slew rate */
>  	tmp = readl(com + U3P_USBPHYACR5);
> @@ -1041,6 +1044,13 @@ static int mtk_tphy_probe(struct platform_device *pdev)
>  		tphy->u3phya_ref = NULL;
>  	}
>  
> +	tphy->src_ref_clk = U3P_REF_CLK;
> +	tphy->src_coef = U3P_SLEW_RATE_COEF;
> +	/* update parameters of slew rate calibrate if exist */
> +	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
> +		&tphy->src_ref_clk);
> +	device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
> +
>  	port = 0;
>  	for_each_child_of_node(np, child_np) {
>  		struct mtk_phy_instance *instance;
> 

[PATCH v2 2/3] phy: phy-mtk-tphy: add configurable parameters for slew rate calibrate

[Chunfeng Yun]

On Wed, 2018-03-14 at 00:21 +0100, Matthias Brugger wrote:
> 
> On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> > There are two parameters, ref_clk and coefficient, for U2 slew rate
> > calibrate which may vary on different SoCs, here allow them to be
> > configurable
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> 
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> 
Thanks
> 
> > ---
> >  drivers/phy/mediatek/phy-mtk-tphy.c | 20 +++++++++++++++-----
> >  1 file changed, 15 insertions(+), 5 deletions(-)
> > 
> > diff --git a/drivers/phy/mediatek/phy-mtk-tphy.c b/drivers/phy/mediatek/phy-mtk-tphy.c
> > index 6073c25..38c281b 100644
> > --- a/drivers/phy/mediatek/phy-mtk-tphy.c
> > +++ b/drivers/phy/mediatek/phy-mtk-tphy.c
> > @@ -306,6 +306,8 @@ struct mtk_tphy {
> >  	const struct mtk_phy_pdata *pdata;
> >  	struct mtk_phy_instance **phys;
> >  	int nphys;
> > +	int src_ref_clk; /* MHZ, reference clock for slew rate calibrate */
> > +	int src_coef; /* coefficient for slew rate calibrate */
> >  };
> >  
> >  static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
> > @@ -360,16 +362,17 @@ static void hs_slew_rate_calibrate(struct mtk_tphy *tphy,
> >  	writel(tmp, fmreg + U3P_U2FREQ_FMMONR1);
> >  
> >  	if (fm_out) {
> > -		/* ( 1024 / FM_OUT ) x reference clock frequency x 0.028 */
> > -		tmp = U3P_FM_DET_CYCLE_CNT * U3P_REF_CLK * U3P_SLEW_RATE_COEF;
> > -		tmp /= fm_out;
> > +		/* ( 1024 / FM_OUT ) x reference clock frequency x coef */
> > +		tmp = tphy->src_ref_clk * tphy->src_coef;
> > +		tmp = (tmp * U3P_FM_DET_CYCLE_CNT) / fm_out;
> >  		calibration_val = DIV_ROUND_CLOSEST(tmp, U3P_SR_COEF_DIVISOR);
> >  	} else {
> >  		/* if FM detection fail, set default value */
> >  		calibration_val = 4;
> >  	}
> > -	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d\n",
> > -		instance->index, fm_out, calibration_val);
> > +	dev_dbg(tphy->dev, "phy:%d, fm_out:%d, calib:%d (clk:%d, coef:%d)\n",
> > +		instance->index, fm_out, calibration_val,
> > +		tphy->src_ref_clk, tphy->src_coef);
> >  
> >  	/* set HS slew rate */
> >  	tmp = readl(com + U3P_USBPHYACR5);
> > @@ -1041,6 +1044,13 @@ static int mtk_tphy_probe(struct platform_device *pdev)
> >  		tphy->u3phya_ref = NULL;
> >  	}
> >  
> > +	tphy->src_ref_clk = U3P_REF_CLK;
> > +	tphy->src_coef = U3P_SLEW_RATE_COEF;
> > +	/* update parameters of slew rate calibrate if exist */
> > +	device_property_read_u32(dev, "mediatek,src-ref-clk-mhz",
> > +		&tphy->src_ref_clk);
> > +	device_property_read_u32(dev, "mediatek,src-coef", &tphy->src_coef);
> > +
> >  	port = 0;
> >  	for_each_child_of_node(np, child_np) {
> >  		struct mtk_phy_instance *instance;
> > 

[PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

[Chunfeng Yun]

On Wed, 2018-03-14 at 00:21 +0100, Matthias Brugger wrote:
> 
> On 03/12/2018 06:25 AM, Chunfeng Yun wrote:
> > Add two properties of ref_clk and coefficient used by U2 slew rate
> > calibrate which may vary on different SoCs
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> 
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> 
Thanks again

> > ---
> >  Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > index 41e09ed..0d34b2b 100644
> > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
> >   - reg		: offset and length of register shared by multiple ports,
> >  		  exclude port's private register. It is needed on mt2701
> >  		  and mt8173, but not on mt2712.
> > + - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
> > +		  calibrate
> > + - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
> > +		  SoC process
> >  
> >  Required properties (port (child) node):
> >  - reg		: address and length of the register set for the port.
> > 

[PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

[Rob Herring]

On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote:
> Add two properties of ref_clk and coefficient used by U2 slew rate
> calibrate which may vary on different SoCs
> 
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
>  Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> index 41e09ed..0d34b2b 100644
> --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
>   - reg		: offset and length of register shared by multiple ports,
>  		  exclude port's private register. It is needed on mt2701
>  		  and mt8173, but not on mt2712.
> + - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
> +		  calibrate
> + - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
> +		  SoC process

What are valid values? This is one cell?

>  
>  Required properties (port (child) node):
>  - reg		: address and length of the register set for the port.
> -- 
> 1.9.1
> 

[PATCH v2 3/3] dt-bindings: phy-mtk-tphy: add properties for U2 slew rate calibrate

[Chunfeng Yun]

On Sun, 2018-03-18 at 07:48 -0500, Rob Herring wrote:
> On Mon, Mar 12, 2018 at 01:25:40PM +0800, Chunfeng Yun wrote:
> > Add two properties of ref_clk and coefficient used by U2 slew rate
> > calibrate which may vary on different SoCs
> > 
> > Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> > ---
> >  Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ++++
> >  1 file changed, 4 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > index 41e09ed..0d34b2b 100644
> > --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt
> > @@ -27,6 +27,10 @@ Optional properties (controller (parent) node):
> >   - reg		: offset and length of register shared by multiple ports,
> >  		  exclude port's private register. It is needed on mt2701
> >  		  and mt8173, but not on mt2712.
> > + - mediatek,src-ref-clk-mhz	: frequency of reference clock for slew rate
> > +		  calibrate
> > + - mediatek,src-coef	: coefficient for slew rate calibrate, depends on
> > +		  SoC process
> 
> What are valid values? This is one cell?
Yes, one cell, integer type. If need, I'll send a new patch

Thanks
> 
> >  
> >  Required properties (port (child) node):
> >  - reg		: address and length of the register set for the port.
> > -- 
> > 1.9.1
> >