* [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform
@ 2021-08-24 10:00 Moudy Ho
2021-08-24 10:00 ` [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP Moudy Ho
` (5 more replies)
0 siblings, 6 replies; 22+ messages in thread
From: Moudy Ho @ 2021-08-24 10:00 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Changes since v6:
- Refactor GCE event to corresponding node.
- Fix dt_binding_check fail.
- Fix compilation errors.
Changes since v5:
- Rebase on v5.14-rc6.
- Move MMSYS/Mutex settings to corresponding driver.
- Revise the software license description and copyright.
- Remove unnecessary enum. or definitions.
- Optimize platform/chip definition conditions.
- Use general printing functions instead of MDP3 private ones.
- Fix compile warning.
Changes since v4:
- Rebase on v5.13-rc1.
- Remove the CMDQ flush flow to match the CMDQ API change.
- Integrate four of MDP's direct-link subcomponents into MDP controller node
from syscon node to avoid illegal clock usage.
- Rewrite dt-binding in a JSON compatible subset of YAML
- Fix a bit of macro argument precedence.
Changes since v3:
- Rebase on v5.9-rc1.
- modify code for review comment from Rob Herring, cancel multiple nodes using
same register base situation.
- control IOMMU port through pm runtime get/put to DMA components' device.
- SCP(VPU) driver revision.
- stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
- add computation of plane address with data_offset.
- fix scale ratio check issue.
- add default v4l2_format setting.
Changes since v2:
- modify code for review comment from Tomasz Figa & Alexandre Courbot
- review comment from Rob Herring will offer code revision in v4, due to
it's related to device node modification, will need to modify code
architecture
Changes since v1:
- modify code for CMDQ v3 API support
- EC ipi cmd migration
- fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
1. out of memory before test complete
Due to capture buffer mmap (refcount + 1) after reqbuf but seems
no corresponding munmap called before device close.
There are total 12XX items(formats) in format test and each format
alloc 8 capture/output buffers.
2. unceasingly captureBufs() (randomly)
Seems the break statement didn't catch the count == 0 situation:
In v4l2-test-buffers.cpp, function: captureBufs()
...
count--;
if (!node->is_m2m && !count)
break;
Log is as attachment
I will paste the test result with problem part in another e-mail
Hi,
This is the first version of RFC patch for Media Data Path 3 (MDP3),
MDP3 is used for scaling and color format conversion.
support using GCE to write register in critical time limitation.
support V4L2 m2m device control.
Moudy Ho (5):
soc: mediatek: mutex: add support for MDP
soc: mediatek: mmsys: Add support for MDP
dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
dts: arm64: mt8183: Add Mediatek MDP3 nodes
media: platform: mtk-mdp3: Add Mediatek MDP3 driver
.../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +
.../bindings/media/mediatek,mdp3-rdma.yaml | 207 +++
.../bindings/media/mediatek,mdp3-rsz.yaml | 65 +
.../bindings/media/mediatek,mdp3-wdma.yaml | 71 +
.../bindings/media/mediatek,mdp3-wrot.yaml | 71 +
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 ++
drivers/media/platform/Kconfig | 19 +
drivers/media/platform/Makefile | 2 +
drivers/media/platform/mtk-mdp3/Makefile | 6 +
.../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
drivers/media/platform/mtk-mdp3/mdp_reg_isp.h | 27 +
.../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
.../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
.../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 280 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 507 +++++++
.../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 46 +
.../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1307 +++++++++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 147 ++
.../media/platform/mtk-mdp3/mtk-mdp3-core.c | 329 +++++
.../media/platform/mtk-mdp3/mtk-mdp3-core.h | 75 +
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 801 ++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 41 +
.../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 746 ++++++++++
.../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 372 +++++
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 312 ++++
.../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 78 +
drivers/soc/mediatek/mt8183-mmsys.h | 235 +++
drivers/soc/mediatek/mtk-mmsys.c | 164 +++
drivers/soc/mediatek/mtk-mmsys.h | 9 +-
drivers/soc/mediatek/mtk-mutex.c | 106 +-
include/linux/soc/mediatek/mtk-mmsys.h | 81 +
include/linux/soc/mediatek/mtk-mutex.h | 8 +
34 files changed, 6495 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP
2021-08-24 10:00 [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
@ 2021-08-24 10:00 ` Moudy Ho
2021-09-07 11:52 ` Matthias Brugger
2021-10-13 13:29 ` AngeloGioacchino Del Regno
2021-08-24 10:00 ` [PATCH v7 2/5] soc: mediatek: mmsys: Add " Moudy Ho
` (4 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Moudy Ho @ 2021-08-24 10:00 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Add functions to support MDP:
1. Get mutex function
2. Enable/disable mutex
3. Enable MDP's modules
4. Write register via CMDQ
Add MDP related settings for 8183 SoC
1. Register settings
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 106 +++++++++++++++++++++++--
include/linux/soc/mediatek/mtk-mutex.h | 8 ++
2 files changed, 108 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..935f2849a094 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -7,9 +7,11 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/regmap.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include <linux/soc/mediatek/mtk-mutex.h>
#define MT2701_MUTEX0_MOD0 0x2c
@@ -107,6 +109,10 @@
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8183_MUTEX_MDP_START 5
+#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
+#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
+
struct mtk_mutex {
int id;
bool claimed;
@@ -123,11 +129,14 @@ enum mtk_mutex_sof_id {
};
struct mtk_mutex_data {
- const unsigned int *mutex_mod;
- const unsigned int *mutex_sof;
- const unsigned int mutex_mod_reg;
- const unsigned int mutex_sof_reg;
- const bool no_clk;
+ const unsigned int *mutex_mod;
+ const unsigned int *mutex_sof;
+ const unsigned int mutex_mod_reg;
+ const unsigned int mutex_sof_reg;
+ const unsigned int *mutex_mdp_offset;
+ const unsigned int mutex_mdp_mod_mask;
+ const unsigned int mutex_mdp_sof_mask;
+ const bool no_clk;
};
struct mtk_mutex_ctx {
@@ -136,6 +145,8 @@ struct mtk_mutex_ctx {
void __iomem *regs;
struct mtk_mutex mutex[10];
const struct mtk_mutex_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
@@ -238,6 +249,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+/* indicate which mutex is used by each pipepline */
+static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
+ [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
+ [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
+ [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
+ [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -272,6 +291,9 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.mutex_sof = mt8183_mutex_sof,
.mutex_mod_reg = MT8183_MUTEX0_MOD0,
.mutex_sof_reg = MT8183_MUTEX0_SOF0,
+ .mutex_mdp_offset = mt8183_mutex_mdp_offset,
+ .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
+ .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
.no_clk = true,
};
@@ -290,6 +312,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
}
EXPORT_SYMBOL_GPL(mtk_mutex_get);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id)
+{
+ struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
+ int i = mtx->data->mutex_mdp_offset[id];
+
+ if (!mtx->mutex[i].claimed) {
+ mtx->mutex[i].claimed = true;
+ return &mtx->mutex[i];
+ }
+
+ return ERR_PTR(-EBUSY);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
+
void mtk_mutex_put(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -369,6 +406,25 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
}
EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
+void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+ unsigned int offset;
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ mod, mtx->data->mutex_mdp_mod_mask);
+
+ offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
+ 0, mtx->data->mutex_mdp_sof_mask);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod);
+
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id)
{
@@ -420,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_enable);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x1, 0x00000001);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
+
void mtk_mutex_disable(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -431,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
}
EXPORT_SYMBOL_GPL(mtk_mutex_disable);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd)
+{
+ struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
+ mutex[mutex->id]);
+
+ WARN_ON(&mtx->mutex[mutex->id] != mutex);
+
+ cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
+ mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
+ 0x0, 0x00000001);
+}
+EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
+
void mtk_mutex_acquire(struct mtk_mutex *mutex)
{
struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
@@ -458,7 +542,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_mutex_ctx *mtx;
- struct resource *regs;
+ struct cmdq_client_reg cmdq_reg;
+ struct resource *regs, addr;
int i;
mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
@@ -479,6 +564,15 @@ static int mtk_mutex_probe(struct platform_device *pdev)
}
}
+ if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
+ mtx->addr = 0L;
+ else
+ mtx->addr = addr.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mtx->subsys_id = cmdq_reg.subsys;
+
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
mtx->regs = devm_ioremap_resource(dev, regs);
if (IS_ERR(mtx->regs)) {
diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
index 6fe4ffbde290..d08b98419dd9 100644
--- a/include/linux/soc/mediatek/mtk-mutex.h
+++ b/include/linux/soc/mediatek/mtk-mutex.h
@@ -11,11 +11,19 @@ struct device;
struct mtk_mutex;
struct mtk_mutex *mtk_mutex_get(struct device *dev);
+struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
+ enum mtk_mdp_pipe_id id);
int mtk_mutex_prepare(struct mtk_mutex *mutex);
void mtk_mutex_add_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
+void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_enable(struct mtk_mutex *mutex);
+void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_disable(struct mtk_mutex *mutex);
+void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
+ struct mmsys_cmdq_cmd *cmd);
void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
enum mtk_ddp_comp_id id);
void mtk_mutex_unprepare(struct mtk_mutex *mutex);
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v7 2/5] soc: mediatek: mmsys: Add support for MDP
2021-08-24 10:00 [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-08-24 10:00 ` [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP Moudy Ho
@ 2021-08-24 10:00 ` Moudy Ho
2021-10-14 15:24 ` Matthias Brugger
2021-08-24 10:00 ` [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
` (3 subsequent siblings)
5 siblings, 1 reply; 22+ messages in thread
From: Moudy Ho @ 2021-08-24 10:00 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Add functions to support MDP:
1. MDP connect/disconnect functions
2. ISP control function
3. Write register via CMDQ
Add MDP related settings for 8183 SoC
1. Register settings
2. MDP route table
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
drivers/soc/mediatek/mt8183-mmsys.h | 235 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 164 +++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.h | 9 +-
include/linux/soc/mediatek/mtk-mmsys.h | 81 +++++++++
4 files changed, 486 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 579dfc8dc8fc..2fa79e745a45 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -12,6 +12,32 @@
#define MT8183_DISP_DPI0_SEL_IN 0xf30
#define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
#define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
+#define MT8183_MDP_ISP_MOUT_EN 0xf80
+#define MT8183_MDP_RDMA0_MOUT_EN 0xf84
+#define MT8183_MDP_PRZ0_MOUT_EN 0xf8c
+#define MT8183_MDP_PRZ1_MOUT_EN 0xf90
+#define MT8183_MDP_COLOR_MOUT_EN 0xf94
+#define MT8183_MDP_IPU_MOUT_EN 0xf98
+#define MT8183_MDP_PATH0_SOUT_SEL 0xfa8
+#define MT8183_MDP_PATH1_SOUT_SEL 0xfac
+#define MT8183_MDP_PRZ0_SEL_IN 0xfc0
+#define MT8183_MDP_PRZ1_SEL_IN 0xfc4
+#define MT8183_MDP_TDSHP_SEL_IN 0xfc8
+#define MT8183_MDP_WROT0_SEL_IN 0xfd0
+#define MT8183_MDP_WDMA_SEL_IN 0xfd4
+#define MT8183_MDP_PATH0_SEL_IN 0xfe0
+#define MT8183_MDP_PATH1_SEL_IN 0xfe4
+#define MT8183_MDP_AAL_MOUT_EN 0xfe8
+#define MT8183_MDP_AAL_SEL_IN 0xfec
+#define MT8183_MDP_CCORR_SEL_IN 0xff0
+#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
+
+#define MT8183_ISP_CTRL_MMSYS_SW0_RST_B 0x140
+#define MT8183_ISP_CTRL_MMSYS_SW1_RST_B 0x144
+#define MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD 0x934
+#define MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD 0x93C
+#define MT8183_ISP_CTRL_ISP_RELAY_CFG_WD 0x994
+#define MT8183_ISP_CTRL_IPU_RELAY_CFG_WD 0x9a0
#define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
#define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
@@ -24,6 +50,55 @@
#define MT8183_DPI0_SEL_IN_RDMA1 0x2
#define MT8183_RDMA0_SOUT_COLOR0 0x1
#define MT8183_RDMA1_SOUT_DSI0 0x1
+#define MT8183_MDP_ISP_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_ISP_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_ISP_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_IPU_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_IPU_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_IPU_MOUT_EN_AAL0 BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_RDMA0_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT BIT(2)
+#define MT8183_MDP_RDMA0_MOUT_EN_AAL0 BIT(3)
+#define MT8183_MDP_AAL_MOUT_EN_CCORR0 BIT(0)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ1 BIT(1)
+#define MT8183_MDP_AAL_MOUT_EN_RSZ0 BIT(2)
+#define MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ0_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_PRZ1_MOUT_EN_TDSHP0 BIT(1)
+#define MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT BIT(2)
+#define MT8183_MDP_PRZ1_MOUT_EN_COLOR0 BIT(4)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT BIT(0)
+#define MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT BIT(1)
+#define MT8183_MDP_AAL_SEL_IN_CAMIN 0
+#define MT8183_MDP_AAL_SEL_IN_RDMA0 1
+#define MT8183_MDP_AAL_SEL_IN_CAMIN2 2
+#define MT8183_MDP_AAL_SEL_IN_CCORR0 3
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN 0
+#define MT8183_MDP_CCORR_SEL_IN_RDMA0 1
+#define MT8183_MDP_CCORR_SEL_IN_CAMIN2 3
+#define MT8183_MDP_CCORR_SEL_IN_AAL0 4
+#define MT8183_MDP_PRZ0_SEL_IN_AAL0 0
+#define MT8183_MDP_PRZ0_SEL_IN_CCORR0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN 0
+#define MT8183_MDP_PRZ1_SEL_IN_RDMA0 1
+#define MT8183_MDP_PRZ1_SEL_IN_CAMIN2 4
+#define MT8183_MDP_PRZ1_SEL_IN_AAL0 5
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ0 0
+#define MT8183_MDP_TDSHP_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_RSZ0 0
+#define MT8183_MDP_PATH0_SEL_IN_RSZ1 1
+#define MT8183_MDP_PATH0_SEL_IN_COLOR0 2
+#define MT8183_MDP_PATH0_SEL_IN_RDMA0 3
+#define MT8183_MDP_PATH1_SEL_IN_RSZ1 0
+#define MT8183_MDP_PATH1_SEL_IN_COLOR0 1
+#define MT8183_MDP_WROT0_SEL_IN_PATH0_OUT 0
+#define MT8183_MDP_WDMA_SEL_IN_PATH1_OUT 0
+#define MT8183_MDP_CCORR_SOUT_SEL_AAL0 0
+#define MT8183_MDP_CCORR_SOUT_SEL_RSZ0 1
+#define MT8183_MDP_PATH0_SOUT_SEL_WROT0 0
+#define MT8183_MDP_PATH1_SOUT_SEL_WDMA 0
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
{
@@ -50,5 +125,165 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
}
};
+static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
+ {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_CCORR0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ1
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_TDSHP0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_COLOR0,
+ MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_COLOR0
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_CCORR0,
+ MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_AAL0
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_CCORR0
+ }, {
+ MDP_COMP_CAMIN, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN2
+ }, {
+ MDP_COMP_AAL0, MDP_COMP_RSZ1,
+ MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_AAL0
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
+ MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
+ MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RDMA0
+ }, {
+ MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_RSZ1
+ }, {
+ MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
+ MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_COLOR0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_WROT0_SEL_IN, MT8183_MDP_WROT0_SEL_IN_PATH0_OUT
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_WDMA_SEL_IN, MT8183_MDP_WDMA_SEL_IN_PATH1_OUT
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_AAL0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_AAL0
+ }, {
+ MDP_COMP_CCORR0, MDP_COMP_RSZ0,
+ MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_RSZ0
+ }, {
+ MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
+ MT8183_MDP_PATH0_SOUT_SEL, MT8183_MDP_PATH0_SOUT_SEL_WROT0
+ }, {
+ MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
+ MT8183_MDP_PATH1_SOUT_SEL, MT8183_MDP_PATH1_SOUT_SEL_WDMA
+ }
+};
+
+static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
+ [ISP_CTRL_MMSYS_SW0_RST_B] = MT8183_ISP_CTRL_MMSYS_SW0_RST_B,
+ [ISP_CTRL_MMSYS_SW1_RST_B] = MT8183_ISP_CTRL_MMSYS_SW1_RST_B,
+ [ISP_CTRL_MDP_ASYNC_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD,
+ [ISP_CTRL_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
+ [ISP_CTRL_ISP_RELAY_CFG_WD] = MT8183_ISP_CTRL_ISP_RELAY_CFG_WD,
+ [ISP_CTRL_IPU_RELAY_CFG_WD] = MT8183_ISP_CTRL_IPU_RELAY_CFG_WD,
+};
+
#endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..c4b99a99ee1e 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -7,8 +7,10 @@
#include <linux/device.h>
#include <linux/io.h>
#include <linux/of_device.h>
+#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/soc/mediatek/mtk-mmsys.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
@@ -50,11 +52,16 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.clk_driver = "clk-mt8183-mm",
.routes = mmsys_mt8183_routing_table,
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
+ .mdp_routes = mmsys_mt8183_mdp_routing_table,
+ .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
+ .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
};
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
+ phys_addr_t addr;
+ u8 subsys_id;
};
void mtk_mmsys_ddp_connect(struct device *dev,
@@ -91,12 +98,160 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
}
EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
+void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(!routes);
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ routes[i].val, 0xFFFFFFFF);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_connect);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
+ int i;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ for (i = 0; i < mmsys->data->mdp_num_routes; i++)
+ if (cur == routes[i].from_comp && next == routes[i].to_comp)
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
+ mmsys->addr + routes[i].addr,
+ 0, 0xFFFFFFFF);
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
+
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Direct link */
+ if (id == MDP_COMP_CAMIN) {
+ /* Reset MDP_DL_ASYNC_TX */
+ /* Bit 3: MDP_DL_ASYNC_TX / MDP_RELAY */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000008);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 3, 0x00000008);
+ }
+
+ /* Reset MDP_DL_ASYNC_RX */
+ /* Bit 10: MDP_DL_ASYNC_RX */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000400);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 10, 0x00000400);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0 << 31, 0x80000000);
+ }
+ }
+
+ if (id == MDP_COMP_CAMIN2) {
+ /* Reset MDP_DL_ASYNC2_TX */
+ /* Bit 4: MDP_DL_ASYNC2_TX / MDP_RELAY2 */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000010);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 4, 0x00000010);
+ }
+
+ /* Reset MDP_DL_ASYNC2_RX */
+ /* Bit 11: MDP_DL_ASYNC2_RX */
+ if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0x0, 0x00000800);
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 1 << 11, 0x00000800);
+ }
+
+ /* Enable sof mode */
+ if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ 0 << 31, 0x80000000);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
+{
+ struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
+ const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
+ u32 reg;
+
+ WARN_ON(mmsys->subsys_id == 0);
+ /* Config for direct link */
+ if (id == MDP_COMP_CAMIN) {
+ if (isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+
+ if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+ if (id == MDP_COMP_CAMIN2) {
+ if (isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD]) {
+ reg = mmsys->addr +
+ isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
+ reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
+ cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
+ (camin_h << 16) + camin_w,
+ 0x3FFF3FFF);
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
+
static int mtk_mmsys_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct platform_device *clks;
struct platform_device *drm;
struct mtk_mmsys *mmsys;
+ struct resource res;
+ struct cmdq_client_reg cmdq_reg;
int ret;
mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -110,6 +265,15 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
return ret;
}
+ if (of_address_to_resource(dev->of_node, 0, &res) < 0)
+ mmsys->addr = 0L;
+ else
+ mmsys->addr = res.start;
+
+ if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
+ dev_info(dev, "cmdq subsys id has not been set\n");
+ mmsys->subsys_id = cmdq_reg.subsys;
+
mmsys->data = of_device_get_match_data(&pdev->dev);
platform_set_drvdata(pdev, mmsys);
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index a760a34e6eca..025d4bc9c8cc 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -74,9 +74,12 @@ struct mtk_mmsys_routes {
};
struct mtk_mmsys_driver_data {
- const char *clk_driver;
- const struct mtk_mmsys_routes *routes;
- const unsigned int num_routes;
+ const char *clk_driver;
+ const struct mtk_mmsys_routes *routes;
+ const unsigned int num_routes;
+ const struct mtk_mmsys_routes *mdp_routes;
+ const unsigned int mdp_num_routes;
+ const unsigned int *mdp_isp_ctrl;
};
/*
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..4eb48d073d2a 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -7,8 +7,14 @@
#define __MTK_MMSYS_H
enum mtk_ddp_comp_id;
+enum mtk_mdp_comp_id;
struct device;
+struct mmsys_cmdq_cmd {
+ struct cmdq_pkt *pkt;
+ s32 *event;
+};
+
enum mtk_ddp_comp_id {
DDP_COMPONENT_AAL0,
DDP_COMPONENT_AAL1,
@@ -42,6 +48,64 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_ID_MAX,
};
+enum mtk_mdp_comp_id {
+ MDP_COMP_NONE = -1, /* Invalid engine */
+
+ /* ISP */
+ MDP_COMP_WPEI = 0,
+ MDP_COMP_WPEO, /* 1 */
+ MDP_COMP_WPEI2, /* 2 */
+ MDP_COMP_WPEO2, /* 3 */
+ MDP_COMP_ISP_IMGI, /* 4 */
+ MDP_COMP_ISP_IMGO, /* 5 */
+ MDP_COMP_ISP_IMG2O, /* 6 */
+
+ /* IPU */
+ MDP_COMP_IPUI, /* 7 */
+ MDP_COMP_IPUO, /* 8 */
+
+ /* MDP */
+ MDP_COMP_CAMIN, /* 9 */
+ MDP_COMP_CAMIN2, /* 10 */
+ MDP_COMP_RDMA0, /* 11 */
+ MDP_COMP_AAL0, /* 12 */
+ MDP_COMP_CCORR0, /* 13 */
+ MDP_COMP_RSZ0, /* 14 */
+ MDP_COMP_RSZ1, /* 15 */
+ MDP_COMP_TDSHP0, /* 16 */
+ MDP_COMP_COLOR0, /* 17 */
+ MDP_COMP_PATH0_SOUT, /* 18 */
+ MDP_COMP_PATH1_SOUT, /* 19 */
+ MDP_COMP_WROT0, /* 20 */
+ MDP_COMP_WDMA, /* 21 */
+
+ /* Dummy Engine */
+ MDP_COMP_RDMA1, /* 22 */
+ MDP_COMP_RSZ2, /* 23 */
+ MDP_COMP_TDSHP1, /* 24 */
+ MDP_COMP_WROT1, /* 25 */
+
+ MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
+};
+
+enum mtk_mdp_pipe_id {
+ MDP_PIPE_RDMA0,
+ MDP_PIPE_IMGI,
+ MDP_PIPE_WPEI,
+ MDP_PIPE_WPEI2,
+ MDP_PIPE_MAX
+};
+
+enum mtk_isp_ctrl {
+ ISP_CTRL_MMSYS_SW0_RST_B,
+ ISP_CTRL_MMSYS_SW1_RST_B,
+ ISP_CTRL_MDP_ASYNC_CFG_WD,
+ ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
+ ISP_CTRL_ISP_RELAY_CFG_WD,
+ ISP_CTRL_IPU_RELAY_CFG_WD,
+ ISP_CTRL_MAX
+};
+
void mtk_mmsys_ddp_connect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
@@ -50,4 +114,21 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
enum mtk_ddp_comp_id cur,
enum mtk_ddp_comp_id next);
+void mtk_mmsys_mdp_connect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
+void mtk_mmsys_mdp_disconnect(struct device *dev,
+ struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id cur,
+ enum mtk_mdp_comp_id next);
+
+void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id);
+
+void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
+ enum mtk_mdp_comp_id id,
+ u32 camin_w, u32 camin_h);
+
#endif /* __MTK_MMSYS_H */
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-24 10:00 [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-08-24 10:00 ` [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP Moudy Ho
2021-08-24 10:00 ` [PATCH v7 2/5] soc: mediatek: mmsys: Add " Moudy Ho
@ 2021-08-24 10:00 ` Moudy Ho
2021-08-24 18:02 ` Rob Herring
2021-09-07 0:11 ` Chun-Kuang Hu
2021-08-24 10:00 ` [PATCH v7 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes Moudy Ho
` (2 subsequent siblings)
5 siblings, 2 replies; 22+ messages in thread
From: Moudy Ho @ 2021-08-24 10:00 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
This patch adds DT binding document for Media Data Path 3 (MDP3)
a unit in multimedia system used for scaling and color format convert.
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
.../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
.../bindings/media/mediatek,mdp3-rdma.yaml | 207 ++++++++++++++++++
.../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
.../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
.../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
5 files changed, 471 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
new file mode 100644
index 000000000000..59fd68b46022
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do color correction with 3X3 matrix.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-ccorr
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_ccorr: mdp3_ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ mediatek,mdp3-id = <0>;
+ reg = <0x1401c000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
new file mode 100644
index 000000000000..b355d7fe791e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
@@ -0,0 +1,207 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do read DMA.
+ RDMA0 is also used to be a controller node containing MMSYS,
+ MUTEX, GCE and SCP settings.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ # controller node
+ - mediatek,mt8183-mdp3
+ - enum:
+ - mediatek,mt8183-mdp3-rdma
+
+ - items:
+ - enum:
+ # read DMA
+ - mediatek,mt8183-mdp3-rdma
+
+ mediatek,scp:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of system control processor (SCP), using
+ the remoteproc & rpmsg framework.
+ $ref: /schemas/remoteproc/mtk,scp.yaml
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ In MDP3, it can allocate multiple identical modules for
+ different data path selection or multi-pipeline execution.
+ This node is used to indicate the ID of each module.
+
+ mdp3-comps:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ items:
+ - enum:
+ # MDP direct-link input path selection, create a
+ # component for path connectedness of HW pipe control
+ - mediatek,mt8183-mdp3-dl1
+ - enum:
+ - mediatek,mt8183-mdp3-dl2
+ - enum:
+ # MDP direct-link output path selection, create a
+ # component for path connectedness of HW pipe control
+ - mediatek,mt8183-mdp3-path1
+ - enum:
+ - mediatek,mt8183-mdp3-path2
+ - enum:
+ # Input DMA of ISP PASS2 (DIP) module for raw image input
+ - mediatek,mt8183-mdp3-imgi
+ - enum:
+ # Output DMA of ISP PASS2 (DIP) module for YUV image output
+ - mediatek,mt8183-mdp3-exto
+
+ mdp3-comp-ids:
+ maxItems: 1
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: |
+ Pipeline ID of MDP direct-link or DIP.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+ maxItems: 6
+
+ iommus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Should point to the respective IOMMU block with master
+ port as argument.
+ $ref: /schemas/iommu/mediatek,iommu.yaml
+
+ mediatek,mmsys:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of mux(multiplexer) controller for HW connections.
+
+ mediatek,mm-mutex:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ maxItems: 1
+ description: |
+ The node of sof(start of frame) signal controller.
+
+ mediatek,mailbox-gce:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ The node of global command engine (GCE), used to read/write
+ registers with critical time limitation.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ mboxes:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ $ref: /schemas/mailbox/mailbox.txt
+
+ gce-subsys:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+if:
+ properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3
+ - enum:
+ - mediatek,mt8183-mdp3-rdma
+
+then:
+ required:
+ - mediatek,scp
+ - mediatek,mmsys
+ - mediatek,mm-mutex
+ - mediatek,mailbox-gce
+ - mboxes
+ - gce-subsys
+
+required:
+ - compatible
+ - mediatek,mdp3-id
+ - reg
+ - clocks
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_rdma0: mdp3_rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
+ "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
+ "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
+ mdp3-comp-ids = <0 1 0 1 0 1>;
+ reg = <0x14001000 0x1000>,
+ <0x14000000 0x1000>,
+ <0x14005000 0x1000>,
+ <0x14006000 0x1000>,
+ <0x15020000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+ <&gce SUBSYS_1502XXXX 0 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>,
+ <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ iommus = <&iommu>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ };
\ No newline at end of file
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
new file mode 100644
index 000000000000..c55a52cd32b7
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Resizer Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to do frame resizing.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-rsz
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ clocks:
+ minItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+
+ mdp3_rsz0: mdp3_rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14003000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3_rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0x14004000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
new file mode 100644
index 000000000000..93e6f331ada8
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wdma
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Should point to the respective IOMMU block with master
+ port as argument.
+ $ref: /schemas/iommu/mediatek,iommu.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wdma: mdp3_wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14006000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu>;
+ };
diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
new file mode 100644
index 000000000000..2993da04c562
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mediatek Media Data Path 3 Device Tree Bindings
+
+maintainers:
+ - Daoyuan Huang <daoyuan.huang@mediatek.com>
+ - Moudy Ho <moudy.ho@mediatek.com>
+
+description: |
+ One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8183-mdp3-wrot
+
+ mediatek,mdp3-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maxItems: 1
+ description: |
+ HW index to distinguish same functionality modules.
+
+ reg:
+ description: |
+ Physical base address and length of the function block
+ register space, the number aligns with the component
+ and its own subcomponent.
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: |
+ sub-system id corresponding to the global command engine (GCE)
+ register address.
+ $ref: /schemas/mailbox/mtk-gce.txt
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 1
+
+ iommus:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: |
+ Should point to the respective IOMMU block with master
+ port as argument.
+ $ref: /schemas/iommu/mediatek,iommu.yaml
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ #include <dt-bindings/gce/mt8183-gce.h>
+ #include <dt-bindings/power/mt8183-power.h>
+ #include <dt-bindings/memory/mt8183-larb-port.h>
+
+ mdp3_wrot0: mdp3_wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0x14005000 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu>;
+ };
--
2.18.0
_______________________________________________
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^ permalink raw reply related [flat|nested] 22+ messages in thread
* [PATCH v7 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes
2021-08-24 10:00 [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
` (2 preceding siblings ...)
2021-08-24 10:00 ` [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
@ 2021-08-24 10:00 ` Moudy Ho
[not found] ` <20210824100027.25989-6-moudy.ho@mediatek.com>
2021-09-03 10:01 ` [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Hans Verkuil
5 siblings, 0 replies; 22+ messages in thread
From: Moudy Ho @ 2021-08-24 10:00 UTC (permalink / raw)
To: moudy.ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Add device nodes for Media Data Path 3 (MDP3) modules.
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 +++++++++++++++++++++++
1 file changed, 110 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index f90df6439c08..067cfb0d6621 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -1232,6 +1232,82 @@
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
};
+ mdp3_rdma0: mdp3_rdma0@14001000 {
+ compatible = "mediatek,mt8183-mdp3",
+ "mediatek,mt8183-mdp3-rdma";
+ mediatek,scp = <&scp>;
+ mediatek,mdp3-id = <0>;
+ mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
+ "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
+ "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
+ mdp3-comp-ids = <0 1 0 1 0 1>;
+ reg = <0 0x14001000 0 0x1000>,
+ <0 0x14000000 0 0x1000>,
+ <0 0x14005000 0 0x1000>,
+ <0 0x14006000 0 0x1000>,
+ <0 0x15020000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
+ <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
+ <&gce SUBSYS_1502XXXX 0 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_RDMA0>,
+ <&mmsys CLK_MM_MDP_RSZ1>,
+ <&mmsys CLK_MM_MDP_DL_TXCK>,
+ <&mmsys CLK_MM_MDP_DL_RX>,
+ <&mmsys CLK_MM_IPU_DL_TXCK>,
+ <&mmsys CLK_MM_IPU_DL_RX>;
+ iommus = <&iommu M4U_PORT_MDP_RDMA0>;
+ mediatek,mmsys = <&mmsys>;
+ mediatek,mm-mutex = <&mutex>;
+ mediatek,mailbox-gce = <&gce>;
+ mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
+ <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
+ gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
+ <&gce 0x14010000 SUBSYS_1401XXXX>,
+ <&gce 0x14020000 SUBSYS_1402XXXX>,
+ <&gce 0x15020000 SUBSYS_1502XXXX>;
+ };
+
+ mdp3_rsz0: mdp3_rsz0@14003000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14003000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ0>;
+ };
+
+ mdp3_rsz1: mdp3_rsz1@14004000 {
+ compatible = "mediatek,mt8183-mdp3-rsz";
+ mediatek,mdp3-id = <1>;
+ reg = <0 0x14004000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_RSZ1>;
+ };
+
+ mdp3_wrot0: mdp3_wrot0@14005000 {
+ compatible = "mediatek,mt8183-mdp3-wrot";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14005000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WROT0>;
+ iommus = <&iommu M4U_PORT_MDP_WROT0>;
+ };
+
+ mdp3_wdma: mdp3_wdma@14006000 {
+ compatible = "mediatek,mt8183-mdp3-wdma";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x14006000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
+ power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ clocks = <&mmsys CLK_MM_MDP_WDMA0>;
+ iommus = <&iommu M4U_PORT_MDP_WDMA0>;
+ };
+
ovl0: ovl@14008000 {
compatible = "mediatek,mt8183-disp-ovl";
reg = <0 0x14008000 0 0x1000>;
@@ -1355,6 +1431,32 @@
reg = <0 0x14016000 0 0x1000>;
interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_LOW>;
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
+ mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
+ <CMDQ_EVENT_MDP_RDMA0_EOF>,
+ <CMDQ_EVENT_MDP_RSZ0_SOF>,
+ <CMDQ_EVENT_MDP_RSZ1_SOF>,
+ <CMDQ_EVENT_MDP_TDSHP_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_SOF>,
+ <CMDQ_EVENT_MDP_WROT0_EOF>,
+ <CMDQ_EVENT_MDP_WDMA0_SOF>,
+ <CMDQ_EVENT_MDP_WDMA0_EOF>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>,
+ <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>,
+ <CMDQ_EVENT_WPE_A_DONE>,
+ <CMDQ_EVENT_SPE_B_DONE>;
};
larb0: larb@14017000 {
@@ -1378,6 +1480,14 @@
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
};
+ mdp3_ccorr: mdp3_ccorr@1401c000 {
+ compatible = "mediatek,mt8183-mdp3-ccorr";
+ mediatek,mdp3-id = <0>;
+ reg = <0 0x1401c000 0 0x1000>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
+ clocks = <&mmsys CLK_MM_MDP_CCORR>;
+ };
+
imgsys: syscon@15020000 {
compatible = "mediatek,mt8183-imgsys", "syscon";
reg = <0 0x15020000 0 0x1000>;
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-24 10:00 ` [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
@ 2021-08-24 18:02 ` Rob Herring
2021-08-30 7:58 ` moudy ho
2021-09-07 0:11 ` Chun-Kuang Hu
1 sibling, 1 reply; 22+ messages in thread
From: Rob Herring @ 2021-08-24 18:02 UTC (permalink / raw)
To: Moudy Ho
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
tfiga, drinkcat, acourbot, pihsun, menghui.lin, sj.huang,
ben.lok, randy.wu, srv_heupstream, hsinyi
On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> This patch adds DT binding document for Media Data Path 3 (MDP3)
> a unit in multimedia system used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> .../bindings/media/mediatek,mdp3-rdma.yaml | 207 ++++++++++++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> 5 files changed, 471 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> new file mode 100644
> index 000000000000..59fd68b46022
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> +
> +maintainers:
> + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> + - Moudy Ho <moudy.ho@mediatek.com>
> +
> +description: |
> + One of Media Data Path 3 (MDP3) components used to do color correction with 3X3 matrix.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-ccorr
> +
> + mediatek,mdp3-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
> + description: |
> + HW index to distinguish same functionality modules.
If we wanted h/w indexes in DT, we'd have a standard property. Why do
you need this?
> +
> + reg:
> + description: |
> + Physical base address and length of the function block
> + register space, the number aligns with the component
> + and its own subcomponent.
Drop and add 'maxItems: 1'
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + sub-system id corresponding to the global command engine (GCE)
You mean 'phandle to GCE and sub-system id'?
> + register address.
> + $ref: /schemas/mailbox/mtk-gce.txt
Kind of looks like jsonschema but in the description and to a .txt
file...
> +
> + clocks:
> + minItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> +
> + mdp3_ccorr: mdp3_ccorr@1401c000 {
> + compatible = "mediatek,mt8183-mdp3-ccorr";
> + mediatek,mdp3-id = <0>;
> + reg = <0x1401c000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> new file mode 100644
> index 000000000000..b355d7fe791e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> @@ -0,0 +1,207 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Media Data Path 3 Device Tree Bindings
> +
> +maintainers:
> + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> + - Moudy Ho <moudy.ho@mediatek.com>
> +
> +description: |
> + One of Media Data Path 3 (MDP3) components used to do read DMA.
> + RDMA0 is also used to be a controller node containing MMSYS,
> + MUTEX, GCE and SCP settings.
> +
> +properties:
> + compatible:
> + oneOf:
> + - items:
> + - enum:
Should be indented 2 more spaces. Install yamllint and check with 'make
dt_binding_check'.
> + # controller node
> + - mediatek,mt8183-mdp3
And then 2 more here.
> + - enum:
> + - mediatek,mt8183-mdp3-rdma
> +
> + - items:
> + - enum:
> + # read DMA
> + - mediatek,mt8183-mdp3-rdma
> +
> + mediatek,scp:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of system control processor (SCP), using
> + the remoteproc & rpmsg framework.
> + $ref: /schemas/remoteproc/mtk,scp.yaml
> +
> + mediatek,mdp3-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
> + description: |
> + In MDP3, it can allocate multiple identical modules for
> + different data path selection or multi-pipeline execution.
> + This node is used to indicate the ID of each module.
> +
> + mdp3-comps:
> + $ref: /schemas/types.yaml#/definitions/string-array
> + items:
> + - enum:
And this is 2 too many spaces...
> + # MDP direct-link input path selection, create a
> + # component for path connectedness of HW pipe control
> + - mediatek,mt8183-mdp3-dl1
> + - enum:
> + - mediatek,mt8183-mdp3-dl2
> + - enum:
> + # MDP direct-link output path selection, create a
> + # component for path connectedness of HW pipe control
> + - mediatek,mt8183-mdp3-path1
> + - enum:
> + - mediatek,mt8183-mdp3-path2
> + - enum:
> + # Input DMA of ISP PASS2 (DIP) module for raw image input
> + - mediatek,mt8183-mdp3-imgi
> + - enum:
> + # Output DMA of ISP PASS2 (DIP) module for YUV image output
> + - mediatek,mt8183-mdp3-exto
> +
> + mdp3-comp-ids:
> + maxItems: 1
> + $ref: /schemas/types.yaml#/definitions/uint32-array
If only a single item, then it's a 'uint32' not an array.
> + description: |
> + Pipeline ID of MDP direct-link or DIP.
> +
> + reg:
> + description: |
> + Physical base address and length of the function block
> + register space, the number aligns with the component
> + and its own subcomponent.
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + sub-system id corresponding to the global command engine (GCE)
> + register address.
> + $ref: /schemas/mailbox/mtk-gce.txt
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + minItems: 1
> + maxItems: 6
Need to define what they are.
> +
> + iommus:
> + $ref: /schemas/types.yaml#/definitions/phandle
iommus already has a type definition.
> + description: |
> + Should point to the respective IOMMU block with master
> + port as argument.
> + $ref: /schemas/iommu/mediatek,iommu.yaml
No. Drop (the whole description because you don't need generic
descriptions for common properties).
What's needed is how many entries (maxItems: 1).
> +
> + mediatek,mmsys:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of mux(multiplexer) controller for HW connections.
> +
> + mediatek,mm-mutex:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + maxItems: 1
> + description: |
> + The node of sof(start of frame) signal controller.
> +
> + mediatek,mailbox-gce:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: |
> + The node of global command engine (GCE), used to read/write
> + registers with critical time limitation.
> + $ref: /schemas/mailbox/mtk-gce.txt
> +
> + mboxes:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + $ref: /schemas/mailbox/mailbox.txt
> +
> + gce-subsys:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + sub-system id corresponding to the global command engine (GCE)
> + register address.
> + $ref: /schemas/mailbox/mtk-gce.txt
> +
> +if:
> + properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3
> + - enum:
> + - mediatek,mt8183-mdp3-rdma
Normally, you want to use 'contains' for if/then schemas:
compatible:
contains:
const: mediatek,mt8183-mdp3
> +
> +then:
> + required:
> + - mediatek,scp
> + - mediatek,mmsys
> + - mediatek,mm-mutex
> + - mediatek,mailbox-gce
> + - mboxes
> + - gce-subsys
> +
> +required:
> + - compatible
> + - mediatek,mdp3-id
> + - reg
> + - clocks
> + - mediatek,gce-client-reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> + #include <dt-bindings/power/mt8183-power.h>
> + #include <dt-bindings/memory/mt8183-larb-port.h>
> +
> + mdp3_rdma0: mdp3_rdma0@14001000 {
> + compatible = "mediatek,mt8183-mdp3",
> + "mediatek,mt8183-mdp3-rdma";
> + mediatek,scp = <&scp>;
> + mediatek,mdp3-id = <0>;
> + mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-mdp3-dl2",
> + "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-mdp3-path2",
> + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto";
> + mdp3-comp-ids = <0 1 0 1 0 1>;
> + reg = <0x14001000 0x1000>,
> + <0x14000000 0x1000>,
> + <0x14005000 0x1000>,
> + <0x14006000 0x1000>,
> + <0x15020000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>,
> + <&gce SUBSYS_1400XXXX 0 0x1000>,
> + <&gce SUBSYS_1400XXXX 0x5000 0x1000>,
> + <&gce SUBSYS_1400XXXX 0x6000 0x1000>,
> + <&gce SUBSYS_1502XXXX 0 0x1000>;
> + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> + <&mmsys CLK_MM_MDP_RSZ1>,
> + <&mmsys CLK_MM_MDP_DL_TXCK>,
> + <&mmsys CLK_MM_MDP_DL_RX>,
> + <&mmsys CLK_MM_IPU_DL_TXCK>,
> + <&mmsys CLK_MM_IPU_DL_RX>;
> + iommus = <&iommu>;
> + mediatek,mmsys = <&mmsys>;
> + mediatek,mm-mutex = <&mutex>;
> + mediatek,mailbox-gce = <&gce>;
> + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
> + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
> + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> + <&gce 0x14010000 SUBSYS_1401XXXX>,
> + <&gce 0x14020000 SUBSYS_1402XXXX>,
> + <&gce 0x15020000 SUBSYS_1502XXXX>;
> + };
> \ No newline at end of file
Fix this.
Similar comments on the rest.
Rob
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-24 18:02 ` Rob Herring
@ 2021-08-30 7:58 ` moudy ho
2021-08-30 15:05 ` Rob Herring
0 siblings, 1 reply; 22+ messages in thread
From: moudy ho @ 2021-08-30 7:58 UTC (permalink / raw)
To: Rob Herring
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart, linux-media,
devicetree, linux-arm-kernel, linux-mediatek, linux-kernel,
tfiga, drinkcat, acourbot, pihsun, menghui.lin, sj.huang,
ben.lok, randy.wu, srv_heupstream, hsinyi
On Tue, 2021-08-24 at 13:02 -0500, Rob Herring wrote:
> On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> > This patch adds DT binding document for Media Data Path 3 (MDP3)
> > a unit in multimedia system used for scaling and color format
> > convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > ++++++++++++++++++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > 5 files changed, 471 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > ccorr.yaml
> > new file mode 100644
> > index 000000000000..59fd68b46022
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > ccorr.yaml
> > @@ -0,0 +1,57 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipusfH8hi$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> >
> > +
> > +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> > +
> > +maintainers:
> > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > + - Moudy Ho <moudy.ho@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to do color
> > correction with 3X3 matrix.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-ccorr
> > +
> > + mediatek,mdp3-id:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + maxItems: 1
> > + description: |
> > + HW index to distinguish same functionality modules.
>
> If we wanted h/w indexes in DT, we'd have a standard property. Why
> do
> you need this?
>
I'm sorry not quite sure what HW indexes means (something like
aliases?)
It was originally used to mark multiple identical modules in the MDP
data path algorithm, so that appropriate paths can be dynamically
dispatched.
> > +
> > + reg:
> > + description: |
> > + Physical base address and length of the function block
> > + register space, the number aligns with the component
> > + and its own subcomponent.
>
> Drop and add 'maxItems: 1'
>
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + sub-system id corresponding to the global command engine
> > (GCE)
>
> You mean 'phandle to GCE and sub-system id'?
Yes.
>
> > + register address.
> > + $ref: /schemas/mailbox/mtk-gce.txt
>
> Kind of looks like jsonschema but in the description and to a .txt
> file...
>
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_ccorr: mdp3_ccorr@1401c000 {
> > + compatible = "mediatek,mt8183-mdp3-ccorr";
> > + mediatek,mdp3-id = <0>;
> > + reg = <0x1401c000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> > + };
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > new file mode 100644
> > index 000000000000..b355d7fe791e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > rdma.yaml
> > @@ -0,0 +1,207 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajips2k1HT2$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> >
> > +
> > +title: Mediatek Media Data Path 3 Device Tree Bindings
> > +
> > +maintainers:
> > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > + - Moudy Ho <moudy.ho@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to do read DMA.
> > + RDMA0 is also used to be a controller node containing MMSYS,
> > + MUTEX, GCE and SCP settings.
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
>
> Should be indented 2 more spaces. Install yamllint and check with
> 'make
> dt_binding_check'.
>
> > + # controller node
> > + - mediatek,mt8183-mdp3
>
> And then 2 more here.
>
> > + - enum:
> > + - mediatek,mt8183-mdp3-rdma
> > +
> > + - items:
> > + - enum:
> > + # read DMA
> > + - mediatek,mt8183-mdp3-rdma
> > +
> > + mediatek,scp:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + maxItems: 1
> > + description: |
> > + The node of system control processor (SCP), using
> > + the remoteproc & rpmsg framework.
> > + $ref: /schemas/remoteproc/mtk,scp.yaml
> > +
> > + mediatek,mdp3-id:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + maxItems: 1
> > + description: |
> > + In MDP3, it can allocate multiple identical modules for
> > + different data path selection or multi-pipeline execution.
> > + This node is used to indicate the ID of each module.
> > +
> > + mdp3-comps:
> > + $ref: /schemas/types.yaml#/definitions/string-array
> > + items:
> > + - enum:
>
> And this is 2 too many spaces...
>
> > + # MDP direct-link input path selection, create a
> > + # component for path connectedness of HW pipe control
> > + - mediatek,mt8183-mdp3-dl1
> > + - enum:
> > + - mediatek,mt8183-mdp3-dl2
> > + - enum:
> > + # MDP direct-link output path selection, create a
> > + # component for path connectedness of HW pipe control
> > + - mediatek,mt8183-mdp3-path1
> > + - enum:
> > + - mediatek,mt8183-mdp3-path2
> > + - enum:
> > + # Input DMA of ISP PASS2 (DIP) module for raw image
> > input
> > + - mediatek,mt8183-mdp3-imgi
> > + - enum:
> > + # Output DMA of ISP PASS2 (DIP) module for YUV image
> > output
> > + - mediatek,mt8183-mdp3-exto
> > +
> > + mdp3-comp-ids:
> > + maxItems: 1
> > + $ref: /schemas/types.yaml#/definitions/uint32-array
>
> If only a single item, then it's a 'uint32' not an array.
Only one in other module, but multiple in RDMA0 for subcomponents.
>
> > + description: |
> > + Pipeline ID of MDP direct-link or DIP.
> > +
> > + reg:
> > + description: |
> > + Physical base address and length of the function block
> > + register space, the number aligns with the component
> > + and its own subcomponent.
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + sub-system id corresponding to the global command engine
> > (GCE)
> > + register address.
> > + $ref: /schemas/mailbox/mtk-gce.txt
> > +
> > + power-domains:
> > + maxItems: 1
> > +
> > + clocks:
> > + minItems: 1
> > + maxItems: 6
>
> Need to define what they are.
>
> > +
> > + iommus:
> > + $ref: /schemas/types.yaml#/definitions/phandle
>
> iommus already has a type definition.
>
> > + description: |
> > + Should point to the respective IOMMU block with master
> > + port as argument.
> > + $ref: /schemas/iommu/mediatek,iommu.yaml
>
> No. Drop (the whole description because you don't need generic
> descriptions for common properties).
>
> What's needed is how many entries (maxItems: 1).
>
> > +
> > + mediatek,mmsys:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + maxItems: 1
> > + description: |
> > + The node of mux(multiplexer) controller for HW connections.
> > +
> > + mediatek,mm-mutex:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + maxItems: 1
> > + description: |
> > + The node of sof(start of frame) signal controller.
> > +
> > + mediatek,mailbox-gce:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: |
> > + The node of global command engine (GCE), used to read/write
> > + registers with critical time limitation.
> > + $ref: /schemas/mailbox/mtk-gce.txt
> > +
> > + mboxes:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + $ref: /schemas/mailbox/mailbox.txt
> > +
> > + gce-subsys:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + sub-system id corresponding to the global command engine
> > (GCE)
> > + register address.
> > + $ref: /schemas/mailbox/mtk-gce.txt
> > +
> > +if:
> > + properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3
> > + - enum:
> > + - mediatek,mt8183-mdp3-rdma
>
> Normally, you want to use 'contains' for if/then schemas:
>
> compatible:
> contains:
> const: mediatek,mt8183-mdp3
>
> > +
> > +then:
> > + required:
> > + - mediatek,scp
> > + - mediatek,mmsys
> > + - mediatek,mm-mutex
> > + - mediatek,mailbox-gce
> > + - mboxes
> > + - gce-subsys
> > +
> > +required:
> > + - compatible
> > + - mediatek,mdp3-id
> > + - reg
> > + - clocks
> > + - mediatek,gce-client-reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > + #include <dt-bindings/power/mt8183-power.h>
> > + #include <dt-bindings/memory/mt8183-larb-port.h>
> > +
> > + mdp3_rdma0: mdp3_rdma0@14001000 {
> > + compatible = "mediatek,mt8183-mdp3",
> > + "mediatek,mt8183-mdp3-rdma";
> > + mediatek,scp = <&scp>;
> > + mediatek,mdp3-id = <0>;
> > + mdp3-comps = "mediatek,mt8183-mdp3-dl1", "mediatek,mt8183-
> > mdp3-dl2",
> > + "mediatek,mt8183-mdp3-path1", "mediatek,mt8183-
> > mdp3-path2",
> > + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-
> > mdp3-exto";
> > + mdp3-comp-ids = <0 1 0 1 0 1>;
> > + reg = <0x14001000 0x1000>,
> > + <0x14000000 0x1000>,
> > + <0x14005000 0x1000>,
> > + <0x14006000 0x1000>,
> > + <0x15020000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000
> > 0x1000>,
> > + <&gce SUBSYS_1400XXXX 0 0x1000>,
> > + <&gce SUBSYS_1400XXXX 0x5000
> > 0x1000>,
> > + <&gce SUBSYS_1400XXXX 0x6000
> > 0x1000>,
> > + <&gce SUBSYS_1502XXXX 0 0x1000>;
> > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
> > + clocks = <&mmsys CLK_MM_MDP_RDMA0>,
> > + <&mmsys CLK_MM_MDP_RSZ1>,
> > + <&mmsys CLK_MM_MDP_DL_TXCK>,
> > + <&mmsys CLK_MM_MDP_DL_RX>,
> > + <&mmsys CLK_MM_IPU_DL_TXCK>,
> > + <&mmsys CLK_MM_IPU_DL_RX>;
> > + iommus = <&iommu>;
> > + mediatek,mmsys = <&mmsys>;
> > + mediatek,mm-mutex = <&mutex>;
> > + mediatek,mailbox-gce = <&gce>;
> > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>,
> > + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>,
> > + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>,
> > + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>;
> > + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>,
> > + <&gce 0x14010000 SUBSYS_1401XXXX>,
> > + <&gce 0x14020000 SUBSYS_1402XXXX>,
> > + <&gce 0x15020000 SUBSYS_1502XXXX>;
> > + };
> > \ No newline at end of file
>
> Fix this.
>
> Similar comments on the rest.
>
> Rob
Thanks for the suggestion, the remaining will be corrected in the
further.
Moudy Ho
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-30 7:58 ` moudy ho
@ 2021-08-30 15:05 ` Rob Herring
2021-09-01 8:14 ` moudy ho
2021-09-02 23:32 ` Chun-Kuang Hu
0 siblings, 2 replies; 22+ messages in thread
From: Rob Herring @ 2021-08-30 15:05 UTC (permalink / raw)
To: moudy ho
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, devicetree, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang, ben.lok, randy.wu, srv_heupstream,
Hsin-Yi Wang
On Mon, Aug 30, 2021 at 2:58 AM moudy ho <moudy.ho@mediatek.com> wrote:
>
> On Tue, 2021-08-24 at 13:02 -0500, Rob Herring wrote:
> > On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> > > This patch adds DT binding document for Media Data Path 3 (MDP3)
> > > a unit in multimedia system used for scaling and color format
> > > convert.
> > >
> > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > > ---
> > > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > > ++++++++++++++++++
> > > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > > 5 files changed, 471 insertions(+)
> > > create mode 100644
> > > Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> > > create mode 100644
> > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > > create mode 100644
> > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > > create mode 100644
> > > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > > create mode 100644
> > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > ccorr.yaml
> > > new file mode 100644
> > > index 000000000000..59fd68b46022
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > ccorr.yaml
> > > @@ -0,0 +1,57 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id:
> > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipusfH8hi$
> > >
> > > +$schema:
> > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> > >
> > > +
> > > +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> > > +
> > > +maintainers:
> > > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > > + - Moudy Ho <moudy.ho@mediatek.com>
> > > +
> > > +description: |
> > > + One of Media Data Path 3 (MDP3) components used to do color
> > > correction with 3X3 matrix.
> > > +
> > > +properties:
> > > + compatible:
> > > + items:
> > > + - enum:
> > > + - mediatek,mt8183-mdp3-ccorr
> > > +
> > > + mediatek,mdp3-id:
> > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > + maxItems: 1
> > > + description: |
> > > + HW index to distinguish same functionality modules.
> >
> > If we wanted h/w indexes in DT, we'd have a standard property. Why
> > do
> > you need this?
> >
> I'm sorry not quite sure what HW indexes means (something like
> aliases?)
It means whatever you said in your description.
And no, I'm not suggesting you use aliases.
> It was originally used to mark multiple identical modules in the MDP
> data path algorithm, so that appropriate paths can be dynamically
> dispatched.
If they are identical, then why do you need to distinguish them in DT?
If there's some difference you need to know about such as connections
to other blocks, then describe that. Another common example is needing
to know what bits/registers to access in a syscon phandle. For that,
make the register offset or bits be args to the phandle property.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-30 15:05 ` Rob Herring
@ 2021-09-01 8:14 ` moudy ho
2021-09-01 10:16 ` Chen-Yu Tsai
2021-09-02 23:32 ` Chun-Kuang Hu
1 sibling, 1 reply; 22+ messages in thread
From: moudy ho @ 2021-09-01 8:14 UTC (permalink / raw)
To: Rob Herring
Cc: Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, devicetree, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang, ben.lok, randy.wu, srv_heupstream,
Hsin-Yi Wang
On Mon, 2021-08-30 at 10:05 -0500, Rob Herring wrote:
> On Mon, Aug 30, 2021 at 2:58 AM moudy ho <moudy.ho@mediatek.com>
> wrote:
> >
> > On Tue, 2021-08-24 at 13:02 -0500, Rob Herring wrote:
> > > On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> > > > This patch adds DT binding document for Media Data Path 3
> > > > (MDP3)
> > > > a unit in multimedia system used for scaling and color format
> > > > convert.
> > > >
> > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > > > ---
> > > > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > > > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > > > ++++++++++++++++++
> > > > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > > > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > > > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > > > 5 files changed, 471 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > > >
> > > > diff --git
> > > > a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml
> > > > b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml
> > > > new file mode 100644
> > > > index 000000000000..59fd68b46022
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml
> > > > @@ -0,0 +1,57 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id:
> > > >
https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipusfH8hi$
> > > >
> > > > +$schema:
> > > >
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> > > >
> > > > +
> > > > +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> > > > +
> > > > +maintainers:
> > > > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > > > + - Moudy Ho <moudy.ho@mediatek.com>
> > > > +
> > > > +description: |
> > > > + One of Media Data Path 3 (MDP3) components used to do color
> > > > correction with 3X3 matrix.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - mediatek,mt8183-mdp3-ccorr
> > > > +
> > > > + mediatek,mdp3-id:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > + maxItems: 1
> > > > + description: |
> > > > + HW index to distinguish same functionality modules.
> > >
> > > If we wanted h/w indexes in DT, we'd have a standard property.
> > > Why
> > > do
> > > you need this?
> > >
> >
> > I'm sorry not quite sure what HW indexes means (something like
> > aliases?)
>
> It means whatever you said in your description.
>
> And no, I'm not suggesting you use aliases.
Sorry for the inaccuracy described here, the comment i mentioned before
should be "standard property" instead of "HW index".
> > It was originally used to mark multiple identical modules in the
> > MDP
> > data path algorithm, so that appropriate paths can be dynamically
> > dispatched.
>
> If they are identical, then why do you need to distinguish them in
> DT?
> If there's some difference you need to know about such as connections
> to other blocks, then describe that. Another common example is
> needing
> to know what bits/registers to access in a syscon phandle. For that,
> make the register offset or bits be args to the phandle property.
>
> Rob
Integrating the previous discussion, maybe I can revise the description
to the following:
description: |
There may be multiple blocks with the same function but different
addresses in MDP3. In order to distinguish the connection with
other blocks, a unique ID is needed to dynamically use one or
more identical blocks to implement multiple pipelines.
Moudy
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-09-01 8:14 ` moudy ho
@ 2021-09-01 10:16 ` Chen-Yu Tsai
2021-09-03 7:15 ` moudy ho
0 siblings, 1 reply; 22+ messages in thread
From: Chen-Yu Tsai @ 2021-09-01 10:16 UTC (permalink / raw)
To: moudy ho
Cc: Rob Herring, Mauro Carvalho Chehab, Matthias Brugger,
Hans Verkuil, Jernej Skrabec, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, Devicetree List, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang, ben.lok, Randy Wu, srv_heupstream,
Hsin-Yi Wang
On Wed, Sep 1, 2021 at 5:04 PM moudy ho <moudy.ho@mediatek.com> wrote:
>
> On Mon, 2021-08-30 at 10:05 -0500, Rob Herring wrote:
> > On Mon, Aug 30, 2021 at 2:58 AM moudy ho <moudy.ho@mediatek.com>
> > wrote:
> > >
> > > On Tue, 2021-08-24 at 13:02 -0500, Rob Herring wrote:
> > > > On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> > > > > This patch adds DT binding document for Media Data Path 3
> > > > > (MDP3)
> > > > > a unit in multimedia system used for scaling and color format
> > > > > convert.
> > > > >
> > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > > > > ---
> > > > > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > > > > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > > > > ++++++++++++++++++
> > > > > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > > > > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > > > > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > > > > 5 files changed, 471 insertions(+)
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > ccorr.yaml
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > > > > create mode 100644
> > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > > > >
> > > > > diff --git
> > > > > a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > ccorr.yaml
> > > > > b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > ccorr.yaml
> > > > > new file mode 100644
> > > > > index 000000000000..59fd68b46022
> > > > > --- /dev/null
> > > > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > ccorr.yaml
> > > > > @@ -0,0 +1,57 @@
> > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > +%YAML 1.2
> > > > > +---
> > > > > +$id:
> > > > >
> https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipusfH8hi$
> > > > >
> > > > > +$schema:
> > > > >
> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> > > > >
> > > > > +
> > > > > +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> > > > > +
> > > > > +maintainers:
> > > > > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > > > > + - Moudy Ho <moudy.ho@mediatek.com>
> > > > > +
> > > > > +description: |
> > > > > + One of Media Data Path 3 (MDP3) components used to do color
> > > > > correction with 3X3 matrix.
> > > > > +
> > > > > +properties:
> > > > > + compatible:
> > > > > + items:
> > > > > + - enum:
> > > > > + - mediatek,mt8183-mdp3-ccorr
> > > > > +
> > > > > + mediatek,mdp3-id:
> > > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > > + maxItems: 1
> > > > > + description: |
> > > > > + HW index to distinguish same functionality modules.
> > > >
> > > > If we wanted h/w indexes in DT, we'd have a standard property.
> > > > Why
> > > > do
> > > > you need this?
> > > >
> > >
> > > I'm sorry not quite sure what HW indexes means (something like
> > > aliases?)
> >
> > It means whatever you said in your description.
> >
> > And no, I'm not suggesting you use aliases.
>
> Sorry for the inaccuracy described here, the comment i mentioned before
> should be "standard property" instead of "HW index".
>
> > > It was originally used to mark multiple identical modules in the
> > > MDP
> > > data path algorithm, so that appropriate paths can be dynamically
> > > dispatched.
> >
> > If they are identical, then why do you need to distinguish them in
> > DT?
> > If there's some difference you need to know about such as connections
> > to other blocks, then describe that. Another common example is
> > needing
> > to know what bits/registers to access in a syscon phandle. For that,
> > make the register offset or bits be args to the phandle property.
> >
> > Rob
>
> Integrating the previous discussion, maybe I can revise the description
> to the following:
> description: |
> There may be multiple blocks with the same function but different
> addresses in MDP3. In order to distinguish the connection with
> other blocks, a unique ID is needed to dynamically use one or
> more identical blocks to implement multiple pipelines.
With display pipelines it is common to describe the pipeline with an OF
graph. With the pipeline drawn out, you also get ways to derive identifiers
for otherwise identical blocks, such as from port IDs.
See Documentation/devicetree/bindings/display/allwinner,sun4i-a10-display-engine.yaml
and arch/arm/boot/dts/sun9i-a80.dtsi for such an example.
ChenYu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-30 15:05 ` Rob Herring
2021-09-01 8:14 ` moudy ho
@ 2021-09-02 23:32 ` Chun-Kuang Hu
1 sibling, 0 replies; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-09-02 23:32 UTC (permalink / raw)
To: Rob Herring
Cc: moudy ho, Mauro Carvalho Chehab, Matthias Brugger, Hans Verkuil,
Jernej Skrabec, Maoguang Meng, daoyuan huang, Ping-Hsun Wu,
Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, DTML, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang, ben.lok, randy.wu, srv_heupstream,
Hsin-Yi Wang
Hi, Rob:
Rob Herring <robh@kernel.org> 於 2021年8月30日 週一 下午11:06寫道：
>
> On Mon, Aug 30, 2021 at 2:58 AM moudy ho <moudy.ho@mediatek.com> wrote:
> >
> > On Tue, 2021-08-24 at 13:02 -0500, Rob Herring wrote:
> > > On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> > > > This patch adds DT binding document for Media Data Path 3 (MDP3)
> > > > a unit in multimedia system used for scaling and color format
> > > > convert.
> > > >
> > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > > > ---
> > > > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > > > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > > > ++++++++++++++++++
> > > > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > > > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > > > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > > > 5 files changed, 471 insertions(+)
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > > > create mode 100644
> > > > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml
> > > > new file mode 100644
> > > > index 000000000000..59fd68b46022
> > > > --- /dev/null
> > > > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > ccorr.yaml
> > > > @@ -0,0 +1,57 @@
> > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > +%YAML 1.2
> > > > +---
> > > > +$id:
> > > > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipusfH8hi$
> > > >
> > > > +$schema:
> > > > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> > > >
> > > > +
> > > > +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> > > > +
> > > > +maintainers:
> > > > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > > > + - Moudy Ho <moudy.ho@mediatek.com>
> > > > +
> > > > +description: |
> > > > + One of Media Data Path 3 (MDP3) components used to do color
> > > > correction with 3X3 matrix.
> > > > +
> > > > +properties:
> > > > + compatible:
> > > > + items:
> > > > + - enum:
> > > > + - mediatek,mt8183-mdp3-ccorr
> > > > +
> > > > + mediatek,mdp3-id:
> > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > + maxItems: 1
> > > > + description: |
> > > > + HW index to distinguish same functionality modules.
> > >
> > > If we wanted h/w indexes in DT, we'd have a standard property. Why
> > > do
> > > you need this?
> > >
> > I'm sorry not quite sure what HW indexes means (something like
> > aliases?)
>
> It means whatever you said in your description.
>
> And no, I'm not suggesting you use aliases.
Because mediatek drm driver has the same problem with mdp driver, and
it has already use the aliases [1]. No matter what is the conclusion
for mdp driver, I think mediatek drm driver should align to this
conclusion. If the conclusion is to remove aliases, should I modify
the dts which has already upstreamed? Should mediatek drm driver be
backward-compatible with down stream dts which use aliases?
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/mediatek/mt8173.dtsi?h=v5.14
Regards,
Chun-Kuang.
>
> > It was originally used to mark multiple identical modules in the MDP
> > data path algorithm, so that appropriate paths can be dynamically
> > dispatched.
>
> If they are identical, then why do you need to distinguish them in DT?
> If there's some difference you need to know about such as connections
> to other blocks, then describe that. Another common example is needing
> to know what bits/registers to access in a syscon phandle. For that,
> make the register offset or bits be args to the phandle property.
>
> Rob
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-09-01 10:16 ` Chen-Yu Tsai
@ 2021-09-03 7:15 ` moudy ho
0 siblings, 0 replies; 22+ messages in thread
From: moudy ho @ 2021-09-03 7:15 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Rob Herring, Mauro Carvalho Chehab, Matthias Brugger,
Hans Verkuil, Jernej Skrabec, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, Devicetree List, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang, ben.lok, Randy Wu, srv_heupstream,
Hsin-Yi Wang
On Wed, 2021-09-01 at 18:16 +0800, Chen-Yu Tsai wrote:
> On Wed, Sep 1, 2021 at 5:04 PM moudy ho <moudy.ho@mediatek.com>
> wrote:
> >
> > On Mon, 2021-08-30 at 10:05 -0500, Rob Herring wrote:
> > > On Mon, Aug 30, 2021 at 2:58 AM moudy ho <moudy.ho@mediatek.com>
> > > wrote:
> > > >
> > > > On Tue, 2021-08-24 at 13:02 -0500, Rob Herring wrote:
> > > > > On Tue, Aug 24, 2021 at 06:00:25PM +0800, Moudy Ho wrote:
> > > > > > This patch adds DT binding document for Media Data Path 3
> > > > > > (MDP3)
> > > > > > a unit in multimedia system used for scaling and color
> > > > > > format
> > > > > > convert.
> > > > > >
> > > > > > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > > > > > ---
> > > > > > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > > > > > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > > > > > ++++++++++++++++++
> > > > > > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > > > > > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > > > > > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > > > > > 5 files changed, 471 insertions(+)
> > > > > > create mode 100644
> > > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > ccorr.yaml
> > > > > > create mode 100644
> > > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > rdma.yaml
> > > > > > create mode 100644
> > > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > rsz.yaml
> > > > > > create mode 100644
> > > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > wdma.yaml
> > > > > > create mode 100644
> > > > > > Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > wrot.yaml
> > > > > >
> > > > > > diff --git
> > > > > > a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > ccorr.yaml
> > > > > > b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > ccorr.yaml
> > > > > > new file mode 100644
> > > > > > index 000000000000..59fd68b46022
> > > > > > --- /dev/null
> > > > > > +++
> > > > > > b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > > > > > ccorr.yaml
> > > > > > @@ -0,0 +1,57 @@
> > > > > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > > > > +%YAML 1.2
> > > > > > +---
> > > > > > +$id:
> > > > > >
> >
> >
https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipusfH8hi$
> > > > > >
> > > > > > +$schema:
> > > > > >
> >
> >
https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!1C0ChLqzi7Zq8D2d4_S4IqCEei4GXdgy3_VCQg8MdsJP7n8TlxbGyajipi-OInix$
> > > > > >
> > > > > > +
> > > > > > +title: Mediatek Media Data Path 3 CCORR Device Tree
> > > > > > Bindings
> > > > > > +
> > > > > > +maintainers:
> > > > > > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > > > > > + - Moudy Ho <moudy.ho@mediatek.com>
> > > > > > +
> > > > > > +description: |
> > > > > > + One of Media Data Path 3 (MDP3) components used to do
> > > > > > color
> > > > > > correction with 3X3 matrix.
> > > > > > +
> > > > > > +properties:
> > > > > > + compatible:
> > > > > > + items:
> > > > > > + - enum:
> > > > > > + - mediatek,mt8183-mdp3-ccorr
> > > > > > +
> > > > > > + mediatek,mdp3-id:
> > > > > > + $ref: /schemas/types.yaml#/definitions/uint32
> > > > > > + maxItems: 1
> > > > > > + description: |
> > > > > > + HW index to distinguish same functionality modules.
> > > > >
> > > > > If we wanted h/w indexes in DT, we'd have a standard
> > > > > property.
> > > > > Why
> > > > > do
> > > > > you need this?
> > > > >
> > > >
> > > > I'm sorry not quite sure what HW indexes means (something like
> > > > aliases?)
> > >
> > > It means whatever you said in your description.
> > >
> > > And no, I'm not suggesting you use aliases.
> >
> > Sorry for the inaccuracy described here, the comment i mentioned
> > before
> > should be "standard property" instead of "HW index".
> >
> > > > It was originally used to mark multiple identical modules in
> > > > the
> > > > MDP
> > > > data path algorithm, so that appropriate paths can be
> > > > dynamically
> > > > dispatched.
> > >
> > > If they are identical, then why do you need to distinguish them
> > > in
> > > DT?
> > > If there's some difference you need to know about such as
> > > connections
> > > to other blocks, then describe that. Another common example is
> > > needing
> > > to know what bits/registers to access in a syscon phandle. For
> > > that,
> > > make the register offset or bits be args to the phandle property.
> > >
> > > Rob
> >
> > Integrating the previous discussion, maybe I can revise the
> > description
> > to the following:
> > description: |
> > There may be multiple blocks with the same function but
> > different
> > addresses in MDP3. In order to distinguish the connection
> > with
> > other blocks, a unique ID is needed to dynamically use one or
> > more identical blocks to implement multiple pipelines.
>
> With display pipelines it is common to describe the pipeline with an
> OF
> graph. With the pipeline drawn out, you also get ways to derive
> identifiers
> for otherwise identical blocks, such as from port IDs.
>
> See Documentation/devicetree/bindings/display/allwinner,sun4i-a10-
> display-engine.yaml
> and arch/arm/boot/dts/sun9i-a80.dtsi for such an example.
>
>
> ChenYu
From the MDP routing table defined in mt8183-mmsys.h
([v7,2/5] soc: mediatek: mmsys: Add support for MDP),
It can be seen that each component has its own independent
one-to-many mapping table, and its next-level receiver may
have its own multiple inputs and is difficult to briefly
describe these relationships.
In addition, due to hardware limitations, RSZ0 (for example)
cannot be completely regarded as RSZ1 in mmsys, and must be
regarded as an independent entity, an example mentioned
in line #67 from mtk-mdp3-cmdq.c
([v7,5/5] media: platform: mtk-mdp3: Add Mediatek MDP3 driver).
Moudy
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 5/5] media: platform: mtk-mdp3: Add Mediatek MDP3 driver
[not found] ` <20210824100027.25989-6-moudy.ho@mediatek.com>
@ 2021-09-03 9:48 ` Hans Verkuil
0 siblings, 0 replies; 22+ messages in thread
From: Hans Verkuil @ 2021-09-03 9:48 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
On 24/08/2021 12:00, Moudy Ho wrote:
> This patch adds driver for Mediatek's Media Data Path ver.3 (MDP3).
> It provides the following functions:
> color transform, format conversion, resize, crop, rotate, flip
> and additional image quality enhancement.
>
> The MDP3 driver is mainly used for Google Chromebook products to
> import the new architecture to set the HW settings as shown below:
> User -> V4L2 framework
> -> MDP3 driver -> SCP (setting calculations)
> -> MDP3 driver -> CMDQ (GCE driver) -> HW
>
> Each modules' related operation control is sited in mtk-mdp3-comp.c
> Each modules' register table is defined in file with "mdp_reg_" prefix
> GCE related API, operation control sited in mtk-mdp3-cmdq.c
> V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
> Probe, power, suspend/resume, system level functions are defined in
> mtk-mdp3-core.c
>
> Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
> Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> Depend on:
> [1] https://patchwork.kernel.org/project/linux-mediatek/patch/20190906115513.159705-9-acourbot@chromium.org/
> [2] https://patchwork.kernel.org/project/linux-mediatek/patch/20190906115513.159705-10-acourbot@chromium.org/
> ---
> drivers/media/platform/Kconfig | 19 +
> drivers/media/platform/Makefile | 2 +
> drivers/media/platform/mtk-mdp3/Makefile | 6 +
> .../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
> drivers/media/platform/mtk-mdp3/mdp_reg_isp.h | 27 +
> .../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
> drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
> .../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
> .../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
> drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 280 ++++
> .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 507 +++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 46 +
> .../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1307 +++++++++++++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 147 ++
> .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 329 +++++
> .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 75 +
> .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 801 ++++++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 41 +
> .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 746 ++++++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 372 +++++
> .../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 312 ++++
> .../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 78 +
> 22 files changed, 5320 insertions(+)
> create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
>
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 157c924686e4..b7f331dbe1b5 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -299,6 +299,25 @@ config VIDEO_MEDIATEK_MDP
> To compile this driver as a module, choose M here: the
> module will be called mtk-mdp.
>
> +config VIDEO_MEDIATEK_MDP3
> + tristate "Mediatek MDP v3 driver"
> + depends on MTK_IOMMU
This should probably be:
depends on MTK_IOMMU || COMPILE_TEST
> + depends on VIDEO_DEV && VIDEO_V4L2
> + depends on ARCH_MEDIATEK || COMPILE_TEST
> + depends on HAS_DMA
> + select VIDEOBUF2_DMA_CONTIG
> + select V4L2_MEM2MEM_DEV
> + select VIDEO_MEDIATEK_VPU
> + select MTK_CMDQ
> + select MTK_SCP
> + default n
> + help
> + It is a v4l2 driver and present in Mediatek MT8183 SoC.
> + The driver supports for scaling and color space conversion.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called mtk-mdp3.
> +
> config VIDEO_MEDIATEK_VCODEC
> tristate "Mediatek Video Codec driver"
> depends on MTK_IOMMU || COMPILE_TEST
Regards,
Hans
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform
2021-08-24 10:00 [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
` (4 preceding siblings ...)
[not found] ` <20210824100027.25989-6-moudy.ho@mediatek.com>
@ 2021-09-03 10:01 ` Hans Verkuil
2021-10-14 8:43 ` moudy ho
5 siblings, 1 reply; 22+ messages in thread
From: Hans Verkuil @ 2021-09-03 10:01 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Hi Moudy,
Can you provide the 'v4l2-compliance -s' output?
Make sure to compile v4l2-compliance from the latest code base:
https://git.linuxtv.org/v4l-utils.git/
Compiling on x86_64 (so using COMPILE_TEST) fails:
LD .tmp_vmlinux.kallsyms1
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-core.o: in function `mdp_probe':
mtk-mdp3-core.c:(.text+0x415): undefined reference to `mtk_mutex_mdp_get'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.o: in function `config_camin_subfrm':
mtk-mdp3-comp.c:(.text+0x9b): undefined reference to `mtk_mmsys_mdp_camin_ctrl'
ld: mtk-mdp3-comp.c:(.text+0xbc): undefined reference to `mtk_mmsys_mdp_camin_ctrl'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.o: in function `mdp_component_deinit':
mtk-mdp3-comp.c:(.text+0x2707): undefined reference to `mtk_mutex_put'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.o: in function `init_isp.cold':
mtk-mdp3-comp.c:(.text.unlikely+0x4f): undefined reference to `mtk_mmsys_mdp_isp_ctrl'
ld: mtk-mdp3-comp.c:(.text.unlikely+0x7a): undefined reference to `mtk_mmsys_mdp_isp_ctrl'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_auto_release_work':
mtk-mdp3-cmdq.c:(.text+0x13): undefined reference to `mtk_mutex_unprepare'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_path_subfrm_require':
mtk-mdp3-cmdq.c:(.text+0x45e): undefined reference to `mtk_mutex_add_mdp_mod'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_path_subfrm_run.isra.0':
mtk-mdp3-cmdq.c:(.text+0x78b): undefined reference to `mtk_mutex_enable_by_cmdq'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_path_config_subfrm':
mtk-mdp3-cmdq.c:(.text+0xa0d): undefined reference to `mtk_mmsys_mdp_connect'
ld: mtk-mdp3-cmdq.c:(.text+0xd08): undefined reference to `mtk_mmsys_mdp_disconnect'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_cmdq_send':
(.text+0x1358): undefined reference to `mtk_mutex_prepare'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_handle_cmdq_callback.cold':
mtk-mdp3-cmdq.c:(.text.unlikely+0x34): undefined reference to `mtk_mutex_unprepare'
ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function `mdp_cmdq_send.cold':
mtk-mdp3-cmdq.c:(.text.unlikely+0xe3): undefined reference to `mtk_mutex_unprepare'
make: *** [Makefile:1177: vmlinux] Error 1
I also get compile warnings:
drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c: In function ‘mdp_sub_comps_create’:
drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c:1151:29: warning: implicit conversion from ‘enum mtk_mdp_comp_id’ to ‘enum mdp_comp_type’ [-Wenum-conversion]
1151 | enum mdp_comp_type type = MDP_COMP_NONE;
| ^~~~~~~~~~~~~
drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c: In function ‘mdp_component_init’:
drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c:1217:6: warning: unused variable ‘i’ [-Wunused-variable]
1217 | int i, ret;
| ^
drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c: In function ‘mdp_cmdq_send’:
drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c:489:1: warning: the frame size of 1312 bytes is larger than 1024 bytes [-Wframe-larger-than=]
489 | }
| ^
Regards,
Hans
On 24/08/2021 12:00, Moudy Ho wrote:
> Changes since v6:
> - Refactor GCE event to corresponding node.
> - Fix dt_binding_check fail.
> - Fix compilation errors.
>
> Changes since v5:
> - Rebase on v5.14-rc6.
> - Move MMSYS/Mutex settings to corresponding driver.
> - Revise the software license description and copyright.
> - Remove unnecessary enum. or definitions.
> - Optimize platform/chip definition conditions.
> - Use general printing functions instead of MDP3 private ones.
> - Fix compile warning.
>
> Changes since v4:
> - Rebase on v5.13-rc1.
> - Remove the CMDQ flush flow to match the CMDQ API change.
> - Integrate four of MDP's direct-link subcomponents into MDP controller node
> from syscon node to avoid illegal clock usage.
> - Rewrite dt-binding in a JSON compatible subset of YAML
> - Fix a bit of macro argument precedence.
>
> Changes since v3:
> - Rebase on v5.9-rc1.
> - modify code for review comment from Rob Herring, cancel multiple nodes using
> same register base situation.
> - control IOMMU port through pm runtime get/put to DMA components' device.
> - SCP(VPU) driver revision.
> - stop queuing jobs(remove flush_workqueue()) after mdp_m2m_release().
> - add computation of plane address with data_offset.
> - fix scale ratio check issue.
> - add default v4l2_format setting.
>
> Changes since v2:
> - modify code for review comment from Tomasz Figa & Alexandre Courbot
> - review comment from Rob Herring will offer code revision in v4, due to
> it's related to device node modification, will need to modify code
> architecture
>
> Changes since v1:
> - modify code for CMDQ v3 API support
> - EC ipi cmd migration
> - fix compliance test fail item (m2m cmd with -f) due to there is two problem in runing all format(-f) cmd:
> 1. out of memory before test complete
> Due to capture buffer mmap (refcount + 1) after reqbuf but seems
> no corresponding munmap called before device close.
> There are total 12XX items(formats) in format test and each format
> alloc 8 capture/output buffers.
> 2. unceasingly captureBufs() (randomly)
> Seems the break statement didn't catch the count == 0 situation:
> In v4l2-test-buffers.cpp, function: captureBufs()
> ...
> count--;
> if (!node->is_m2m && !count)
> break;
> Log is as attachment
>
> I will paste the test result with problem part in another e-mail
>
> Hi,
>
> This is the first version of RFC patch for Media Data Path 3 (MDP3),
> MDP3 is used for scaling and color format conversion.
> support using GCE to write register in critical time limitation.
> support V4L2 m2m device control.
>
> Moudy Ho (5):
> soc: mediatek: mutex: add support for MDP
> soc: mediatek: mmsys: Add support for MDP
> dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
> dts: arm64: mt8183: Add Mediatek MDP3 nodes
> media: platform: mtk-mdp3: Add Mediatek MDP3 driver
>
> .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +
> .../bindings/media/mediatek,mdp3-rdma.yaml | 207 +++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 65 +
> .../bindings/media/mediatek,mdp3-wdma.yaml | 71 +
> .../bindings/media/mediatek,mdp3-wrot.yaml | 71 +
> arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 ++
> drivers/media/platform/Kconfig | 19 +
> drivers/media/platform/Makefile | 2 +
> drivers/media/platform/mtk-mdp3/Makefile | 6 +
> .../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
> drivers/media/platform/mtk-mdp3/mdp_reg_isp.h | 27 +
> .../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
> drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
> .../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
> .../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
> drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 280 ++++
> .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 507 +++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 46 +
> .../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1307 +++++++++++++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 147 ++
> .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 329 +++++
> .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 75 +
> .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 801 ++++++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 41 +
> .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 746 ++++++++++
> .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 372 +++++
> .../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 312 ++++
> .../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 78 +
> drivers/soc/mediatek/mt8183-mmsys.h | 235 +++
> drivers/soc/mediatek/mtk-mmsys.c | 164 +++
> drivers/soc/mediatek/mtk-mmsys.h | 9 +-
> drivers/soc/mediatek/mtk-mutex.c | 106 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 81 +
> include/linux/soc/mediatek/mtk-mutex.h | 8 +
> 34 files changed, 6495 insertions(+), 9 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
> create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-08-24 10:00 ` [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
2021-08-24 18:02 ` Rob Herring
@ 2021-09-07 0:11 ` Chun-Kuang Hu
2021-09-10 2:29 ` moudy ho
1 sibling, 1 reply; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-09-07 0:11 UTC (permalink / raw)
To: Moudy Ho
Cc: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang (黃信璋),
ben.lok, randy.wu, srv_heupstream, Hsin-Yi Wang
Hi, Moudy:
Moudy Ho <moudy.ho@mediatek.com> 於 2021年8月24日 週二 下午6:02寫道：
>
> This patch adds DT binding document for Media Data Path 3 (MDP3)
> a unit in multimedia system used for scaling and color format convert.
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> .../bindings/media/mediatek,mdp3-rdma.yaml | 207 ++++++++++++++++++
> .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> 5 files changed, 471 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
I've compared ccorr driver in display [1] and ccorr in mdp [2], both
are similar. So I would like both binding document are placed
together. In display folder? In mdp folder? In SoC folder? I've no
idea which one is better. At lease put together.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c?h=v5.14
[2] https://patchwork.kernel.org/project/linux-mediatek/patch/20210824100027.25989-6-moudy.ho@mediatek.com/
Regards,
Chun-Kuang.
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
>
> diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> new file mode 100644
> index 000000000000..59fd68b46022
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> +
> +maintainers:
> + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> + - Moudy Ho <moudy.ho@mediatek.com>
> +
> +description: |
> + One of Media Data Path 3 (MDP3) components used to do color correction with 3X3 matrix.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8183-mdp3-ccorr
> +
> + mediatek,mdp3-id:
> + $ref: /schemas/types.yaml#/definitions/uint32
> + maxItems: 1
> + description: |
> + HW index to distinguish same functionality modules.
> +
> + reg:
> + description: |
> + Physical base address and length of the function block
> + register space, the number aligns with the component
> + and its own subcomponent.
> +
> + mediatek,gce-client-reg:
> + $ref: /schemas/types.yaml#/definitions/phandle-array
> + description: |
> + sub-system id corresponding to the global command engine (GCE)
> + register address.
> + $ref: /schemas/mailbox/mtk-gce.txt
> +
> + clocks:
> + minItems: 1
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8183-clk.h>
> + #include <dt-bindings/gce/mt8183-gce.h>
> +
> + mdp3_ccorr: mdp3_ccorr@1401c000 {
> + compatible = "mediatek,mt8183-mdp3-ccorr";
> + mediatek,mdp3-id = <0>;
> + reg = <0x1401c000 0x1000>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>;
> + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> + };
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP
2021-08-24 10:00 ` [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP Moudy Ho
@ 2021-09-07 11:52 ` Matthias Brugger
2021-09-17 1:23 ` moudy ho
2021-10-13 13:29 ` AngeloGioacchino Del Regno
1 sibling, 1 reply; 22+ messages in thread
From: Matthias Brugger @ 2021-09-07 11:52 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Hans Verkuil,
Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
On 24/08/2021 12:00, Moudy Ho wrote:
> Add functions to support MDP:
> 1. Get mutex function
> 2. Enable/disable mutex
> 3. Enable MDP's modules
> 4. Write register via CMDQ
>
> Add MDP related settings for 8183 SoC
> 1. Register settings
>
Please write some good commit message.
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 106 +++++++++++++++++++++++--
> include/linux/soc/mediatek/mtk-mutex.h | 8 ++
> 2 files changed, 108 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..935f2849a094 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -7,9 +7,11 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> #include <linux/soc/mediatek/mtk-mutex.h>
>
> #define MT2701_MUTEX0_MOD0 0x2c
> @@ -107,6 +109,10 @@
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>
> +#define MT8183_MUTEX_MDP_START 5
> +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
> +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -123,11 +129,14 @@ enum mtk_mutex_sof_id {
> };
>
> struct mtk_mutex_data {
> - const unsigned int *mutex_mod;
> - const unsigned int *mutex_sof;
> - const unsigned int mutex_mod_reg;
> - const unsigned int mutex_sof_reg;
> - const bool no_clk;
> + const unsigned int *mutex_mod;
> + const unsigned int *mutex_sof;
> + const unsigned int mutex_mod_reg;
> + const unsigned int mutex_sof_reg;
> + const unsigned int *mutex_mdp_offset;
> + const unsigned int mutex_mdp_mod_mask;
> + const unsigned int mutex_mdp_sof_mask;
> + const bool no_clk;
Not needed, please drop.
> };
>
> struct mtk_mutex_ctx {
> @@ -136,6 +145,8 @@ struct mtk_mutex_ctx {
> void __iomem *regs;
> struct mtk_mutex mutex[10];
> const struct mtk_mutex_data *data;
> + phys_addr_t addr;
> + u8 subsys_id;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -238,6 +249,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +/* indicate which mutex is used by each pipepline */
> +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
Does this code even compile?
There is some basic rules for patches, for example that they have to compile,
don't break anything etc.
Please read the documentation and stick to it, before submitting patches:
https://www.kernel.org/doc/html/latest/process/submitting-patches.html
Regards,
Matthias
> + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -272,6 +291,9 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .mutex_sof = mt8183_mutex_sof,
> .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .mutex_mdp_offset = mt8183_mutex_mdp_offset,
> + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> };
>
> @@ -290,6 +312,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get);
>
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id)
> +{
> + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> + int i = mtx->data->mutex_mdp_offset[id];
> +
> + if (!mtx->mutex[i].claimed) {
> + mtx->mutex[i].claimed = true;
> + return &mtx->mutex[i];
> + }
> +
> + return ERR_PTR(-EBUSY);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> +
> void mtk_mutex_put(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -369,6 +406,25 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
>
> +void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> + unsigned int offset;
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
> + mod, mtx->data->mutex_mdp_mod_mask);
> +
> + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
> + 0, mtx->data->mutex_mdp_sof_mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod);
> +
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id)
> {
> @@ -420,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_enable);
>
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x1, 0x00000001);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> +
> void mtk_mutex_disable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -431,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_disable);
>
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x0, 0x00000001);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> +
> void mtk_mutex_acquire(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -458,7 +542,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct mtk_mutex_ctx *mtx;
> - struct resource *regs;
> + struct cmdq_client_reg cmdq_reg;
> + struct resource *regs, addr;
> int i;
>
> mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> @@ -479,6 +564,15 @@ static int mtk_mutex_probe(struct platform_device *pdev)
> }
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> + mtx->addr = 0L;
> + else
> + mtx->addr = addr.start;
> +
> + if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
> + dev_info(dev, "cmdq subsys id has not been set\n");
> + mtx->subsys_id = cmdq_reg.subsys;
> +
> regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> mtx->regs = devm_ioremap_resource(dev, regs);
> if (IS_ERR(mtx->regs)) {
> diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h
> index 6fe4ffbde290..d08b98419dd9 100644
> --- a/include/linux/soc/mediatek/mtk-mutex.h
> +++ b/include/linux/soc/mediatek/mtk-mutex.h
> @@ -11,11 +11,19 @@ struct device;
> struct mtk_mutex;
>
> struct mtk_mutex *mtk_mutex_get(struct device *dev);
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id);
> int mtk_mutex_prepare(struct mtk_mutex *mutex);
> void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> +void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_enable(struct mtk_mutex *mutex);
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_disable(struct mtk_mutex *mutex);
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd);
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id);
> void mtk_mutex_unprepare(struct mtk_mutex *mutex);
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
2021-09-07 0:11 ` Chun-Kuang Hu
@ 2021-09-10 2:29 ` moudy ho
0 siblings, 0 replies; 22+ messages in thread
From: moudy ho @ 2021-09-10 2:29 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec, Maoguang Meng, daoyuan huang,
Ping-Hsun Wu, Geert Uytterhoeven, Rob Landley, Laurent Pinchart,
Linux Media Mailing List, DTML, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Tomasz Figa, Nicolas Boichat, Alexandre Courbot, Pi-Hsun Shih,
menghui.lin, Sj Huang (黃信璋),
ben.lok, randy.wu, srv_heupstream, Hsin-Yi Wang
On Tue, 2021-09-07 at 08:11 +0800, Chun-Kuang Hu wrote:
> Hi, Moudy:
>
> Moudy Ho <moudy.ho@mediatek.com> 於 2021年8月24日 週二 下午6:02寫道：
> >
> > This patch adds DT binding document for Media Data Path 3 (MDP3)
> > a unit in multimedia system used for scaling and color format
> > convert.
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +++++
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 207
> > ++++++++++++++++++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 ++++++
> > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 ++++++
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 ++++++
> > 5 files changed, 471 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
>
> I've compared ccorr driver in display [1] and ccorr in mdp [2], both
> are similar. So I would like both binding document are placed
> together. In display folder? In mdp folder? In SoC folder? I've no
> idea which one is better. At lease put together.
>
> [1]
> https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/gpu/drm/mediatek/mtk_disp_ccorr.c?h=v5.14__;!!CTRNKA9wMg0ARbw!xOYd8SaiDSRvJBgpaQpLzMxqPOAstMX7cGXkhEnuYa1Wb3EMiiElNEPeycP_k2IQ$
>
> [2]
> https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/patch/20210824100027.25989-6-moudy.ho@mediatek.com/__;!!CTRNKA9wMg0ARbw!xOYd8SaiDSRvJBgpaQpLzMxqPOAstMX7cGXkhEnuYa1Wb3EMiiElNEPeyTwjz4UU$
>
>
> Regards,
> Chun-Kuang.
Hi Chun-Kuang,
Thank you for your recommendation.
I will integrate the same component binding files in MDP and DISP, and
place them in the folder same with MMSYS instead.
(
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
)
The first version of RDMA, CCORR, AAL, COLOR and WDMA will be provided
by MDP and then DISP add it own property later.
Thanks & Regards,
Moudy Ho
>
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > ccorr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > ccorr.yaml
> > new file mode 100644
> > index 000000000000..59fd68b46022
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-
> > ccorr.yaml
> > @@ -0,0 +1,57 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/media/mediatek,mdp3-ccorr.yaml*__;Iw!!CTRNKA9wMg0ARbw!xOYd8SaiDSRvJBgpaQpLzMxqPOAstMX7cGXkhEnuYa1Wb3EMiiElNEPeyW4MmXUY$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!xOYd8SaiDSRvJBgpaQpLzMxqPOAstMX7cGXkhEnuYa1Wb3EMiiElNEPeydwX0gSy$
> >
> > +
> > +title: Mediatek Media Data Path 3 CCORR Device Tree Bindings
> > +
> > +maintainers:
> > + - Daoyuan Huang <daoyuan.huang@mediatek.com>
> > + - Moudy Ho <moudy.ho@mediatek.com>
> > +
> > +description: |
> > + One of Media Data Path 3 (MDP3) components used to do color
> > correction with 3X3 matrix.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8183-mdp3-ccorr
> > +
> > + mediatek,mdp3-id:
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + maxItems: 1
> > + description: |
> > + HW index to distinguish same functionality modules.
> > +
> > + reg:
> > + description: |
> > + Physical base address and length of the function block
> > + register space, the number aligns with the component
> > + and its own subcomponent.
> > +
> > + mediatek,gce-client-reg:
> > + $ref: /schemas/types.yaml#/definitions/phandle-array
> > + description: |
> > + sub-system id corresponding to the global command engine
> > (GCE)
> > + register address.
> > + $ref: /schemas/mailbox/mtk-gce.txt
> > +
> > + clocks:
> > + minItems: 1
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8183-clk.h>
> > + #include <dt-bindings/gce/mt8183-gce.h>
> > +
> > + mdp3_ccorr: mdp3_ccorr@1401c000 {
> > + compatible = "mediatek,mt8183-mdp3-ccorr";
> > + mediatek,mdp3-id = <0>;
> > + reg = <0x1401c000 0x1000>;
> > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000
> > 0x1000>;
> > + clocks = <&mmsys CLK_MM_MDP_CCORR>;
> > + };
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP
2021-09-07 11:52 ` Matthias Brugger
@ 2021-09-17 1:23 ` moudy ho
0 siblings, 0 replies; 22+ messages in thread
From: moudy ho @ 2021-09-17 1:23 UTC (permalink / raw)
To: Matthias Brugger, Mauro Carvalho Chehab, Rob Herring,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
On Tue, 2021-09-07 at 13:52 +0200, Matthias Brugger wrote:
>
> On 24/08/2021 12:00, Moudy Ho wrote:
> > Add functions to support MDP:
> > 1. Get mutex function
> > 2. Enable/disable mutex
> > 3. Enable MDP's modules
> > 4. Write register via CMDQ
> >
> > Add MDP related settings for 8183 SoC
> > 1. Register settings
> >
>
> Please write some good commit message.
>
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > drivers/soc/mediatek/mtk-mutex.c | 106
> > +++++++++++++++++++++++--
> > include/linux/soc/mediatek/mtk-mutex.h | 8 ++
> > 2 files changed, 108 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-mutex.c
> > b/drivers/soc/mediatek/mtk-mutex.c
> > index 2e4bcc300576..935f2849a094 100644
> > --- a/drivers/soc/mediatek/mtk-mutex.c
> > +++ b/drivers/soc/mediatek/mtk-mutex.c
> > @@ -7,9 +7,11 @@
> > #include <linux/iopoll.h>
> > #include <linux/module.h>
> > #include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > #include <linux/platform_device.h>
> > #include <linux/regmap.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > #include <linux/soc/mediatek/mtk-mutex.h>
> >
> > #define MT2701_MUTEX0_MOD0 0x2c
> > @@ -107,6 +109,10 @@
> > #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_S
> > OF_DSI0 << 6)
> > #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_S
> > OF_DPI0 << 6)
> >
> > +#define MT8183_MUTEX_MDP_START 5
> > +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
> > +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
> > +
> > struct mtk_mutex {
> > int id;
> > bool claimed;
> > @@ -123,11 +129,14 @@ enum mtk_mutex_sof_id {
> > };
> >
> > struct mtk_mutex_data {
> > - const unsigned int *mutex_mod;
> > - const unsigned int *mutex_sof;
> > - const unsigned int mutex_mod_reg;
> > - const unsigned int mutex_sof_reg;
> > - const bool no_clk;
> > + const unsigned int *mutex_mod;
> > + const unsigned int *mutex_sof;
> > + const unsigned int mutex_mod_reg;
> > + const unsigned int mutex_sof_reg;
> > + const unsigned int *mutex_mdp_offset;
> > + const unsigned int mutex_mdp_mod_mask;
> > + const unsigned int mutex_mdp_sof_mask;
> > + const bool no_clk;
>
> Not needed, please drop.
>
> > };
> >
> > struct mtk_mutex_ctx {
> > @@ -136,6 +145,8 @@ struct mtk_mutex_ctx {
> > void __iomem *regs;
> > struct mtk_mutex mutex[10];
> > const struct mtk_mutex_data *data;
> > + phys_addr_t addr;
> > + u8 subsys_id;
> > };
> >
> > static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX]
> > = {
> > @@ -238,6 +249,14 @@ static const unsigned int
> > mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> > [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 |
> > MT8183_MUTEX_EOF_DPI0,
> > };
> >
> > +/* indicate which mutex is used by each pipepline */
> > +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] =
> > {
>
> Does this code even compile?
> There is some basic rules for patches, for example that they have to
> compile,
> don't break anything etc.
> Please read the documentation and stick to it, before submitting
> patches:
>
https://urldefense.com/v3/__https://www.kernel.org/doc/html/latest/process/submitting-patches.html__;!!CTRNKA9wMg0ARbw!ydpwywaE1_wrjDqXOQ2N-a98Tw2kejngWaJOgZAWmh-y8tBOW0M_BRXfuhKHSZQ9$
>
>
> Regards,
> Matthias
Hi Matthias,
I shouldn't have applied patches directly after chip compatibility
testing in internal codebase that it had to resolve some conflict and
been recorded automatically by GIT.
Sorry for the inconvenience, those redundant codes that cause
compilation errors will be removed and confirmed in future versions.
Thanks & Regards,
Moudy Ho
>
> > + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> > + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> > + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> > + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> > +};
> > +
> > static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> > .mutex_mod = mt2701_mutex_mod,
> > .mutex_sof = mt2712_mutex_sof,
> > @@ -272,6 +291,9 @@ static const struct mtk_mutex_data
> > mt8183_mutex_driver_data = {
> > .mutex_sof = mt8183_mutex_sof,
> > .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> > .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> > + .mutex_mdp_offset = mt8183_mutex_mdp_offset,
> > + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> > + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> > .no_clk = true,
> > };
> >
> > @@ -290,6 +312,21 @@ struct mtk_mutex *mtk_mutex_get(struct device
> > *dev)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_get);
> >
> > +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> > + enum mtk_mdp_pipe_id id)
> > +{
> > + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> > + int i = mtx->data->mutex_mdp_offset[id];
> > +
> > + if (!mtx->mutex[i].claimed) {
> > + mtx->mutex[i].claimed = true;
> > + return &mtx->mutex[i];
> > + }
> > +
> > + return ERR_PTR(-EBUSY);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> > +
> > void mtk_mutex_put(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -369,6 +406,25 @@ void mtk_mutex_add_comp(struct mtk_mutex
> > *mutex,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
> >
> > +void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
> > + struct mmsys_cmdq_cmd *cmd)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > + unsigned int offset;
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex-
> > >id);
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr +
> > offset,
> > + mod, mtx->data->mutex_mdp_mod_mask);
> > +
> > + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex-
> > >id);
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr +
> > offset,
> > + 0, mtx->data->mutex_mdp_sof_mask);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod);
> > +
> > void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id)
> > {
> > @@ -420,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_enable);
> >
> > +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> > + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> > + 0x1, 0x00000001);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> > +
> > void mtk_mutex_disable(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -431,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex
> > *mutex)
> > }
> > EXPORT_SYMBOL_GPL(mtk_mutex_disable);
> >
> > +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd)
> > +{
> > + struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > + mutex[mutex->id]);
> > +
> > + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> > +
> > + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> > + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> > + 0x0, 0x00000001);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> > +
> > void mtk_mutex_acquire(struct mtk_mutex *mutex)
> > {
> > struct mtk_mutex_ctx *mtx = container_of(mutex, struct
> > mtk_mutex_ctx,
> > @@ -458,7 +542,8 @@ static int mtk_mutex_probe(struct
> > platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > struct mtk_mutex_ctx *mtx;
> > - struct resource *regs;
> > + struct cmdq_client_reg cmdq_reg;
> > + struct resource *regs, addr;
> > int i;
> >
> > mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> > @@ -479,6 +564,15 @@ static int mtk_mutex_probe(struct
> > platform_device *pdev)
> > }
> > }
> >
> > + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> > + mtx->addr = 0L;
> > + else
> > + mtx->addr = addr.start;
> > +
> > + if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
> > + dev_info(dev, "cmdq subsys id has not been set\n");
> > + mtx->subsys_id = cmdq_reg.subsys;
> > +
> > regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > mtx->regs = devm_ioremap_resource(dev, regs);
> > if (IS_ERR(mtx->regs)) {
> > diff --git a/include/linux/soc/mediatek/mtk-mutex.h
> > b/include/linux/soc/mediatek/mtk-mutex.h
> > index 6fe4ffbde290..d08b98419dd9 100644
> > --- a/include/linux/soc/mediatek/mtk-mutex.h
> > +++ b/include/linux/soc/mediatek/mtk-mutex.h
> > @@ -11,11 +11,19 @@ struct device;
> > struct mtk_mutex;
> >
> > struct mtk_mutex *mtk_mutex_get(struct device *dev);
> > +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> > + enum mtk_mdp_pipe_id id);
> > int mtk_mutex_prepare(struct mtk_mutex *mutex);
> > void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > +void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_enable(struct mtk_mutex *mutex);
> > +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_disable(struct mtk_mutex *mutex);
> > +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> > + struct mmsys_cmdq_cmd *cmd);
> > void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> > enum mtk_ddp_comp_id id);
> > void mtk_mutex_unprepare(struct mtk_mutex *mutex);
> >
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP
2021-08-24 10:00 ` [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP Moudy Ho
2021-09-07 11:52 ` Matthias Brugger
@ 2021-10-13 13:29 ` AngeloGioacchino Del Regno
1 sibling, 0 replies; 22+ messages in thread
From: AngeloGioacchino Del Regno @ 2021-10-13 13:29 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Matthias Brugger,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi, benjamin.gaignard
Hello Moudy,
thanks for the patch! Though, there are a few things to improve.
> Add functions to support MDP:
> 1. Get mutex function
> 2. Enable/disable mutex
> 3. Enable MDP's modules
> 4. Write register via CMDQ
>
> Add MDP related settings for 8183 SoC
> 1. Register settings
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mutex.c | 106 +++++++++++++++++++++++--
> include/linux/soc/mediatek/mtk-mutex.h | 8 ++
> 2 files changed, 108 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
> index 2e4bcc300576..935f2849a094 100644
> --- a/drivers/soc/mediatek/mtk-mutex.c
> +++ b/drivers/soc/mediatek/mtk-mutex.c
> @@ -7,9 +7,11 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> #include <linux/soc/mediatek/mtk-mutex.h>
>
> #define MT2701_MUTEX0_MOD0 0x2c
> @@ -107,6 +109,10 @@
> #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
> #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
>
> +#define MT8183_MUTEX_MDP_START 5
> +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF
> +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007
> +
> struct mtk_mutex {
> int id;
> bool claimed;
> @@ -123,11 +129,14 @@ enum mtk_mutex_sof_id {
> };
>
> struct mtk_mutex_data {
> - const unsigned int *mutex_mod;
> - const unsigned int *mutex_sof;
> - const unsigned int mutex_mod_reg;
> - const unsigned int mutex_sof_reg;
> - const bool no_clk;
> + const unsigned int *mutex_mod;
> + const unsigned int *mutex_sof;
> + const unsigned int mutex_mod_reg;
> + const unsigned int mutex_sof_reg;
> + const unsigned int *mutex_mdp_offset;
> + const unsigned int mutex_mdp_mod_mask;
> + const unsigned int mutex_mdp_sof_mask;
> + const bool no_clk;
As a rule of thumb, if you're changing any formatting, not only you should have
a good reason, but also it's something that shall be done in a different commit,
so, one for functional changes, one for cosmetic changes (not necessarily in this
order).
This will make it easier for everyone to review your patches.
> };
>
> struct mtk_mutex_ctx {
> @@ -136,6 +145,8 @@ struct mtk_mutex_ctx {
> void __iomem *regs;
> struct mtk_mutex mutex[10];
> const struct mtk_mutex_data *data;
> + phys_addr_t addr;
> + u8 subsys_id;
> };
>
> static const unsigned int mt2701_mutex_mod[DDP_COMPONENT_ID_MAX] = {
> @@ -238,6 +249,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
> [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
> };
>
> +/* indicate which mutex is used by each pipepline */
> +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = {
> + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START,
> + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1,
> + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2,
> + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3
> +};
> +
> static const struct mtk_mutex_data mt2701_mutex_driver_data = {
> .mutex_mod = mt2701_mutex_mod,
> .mutex_sof = mt2712_mutex_sof,
> @@ -272,6 +291,9 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
> .mutex_sof = mt8183_mutex_sof,
> .mutex_mod_reg = MT8183_MUTEX0_MOD0,
> .mutex_sof_reg = MT8183_MUTEX0_SOF0,
> + .mutex_mdp_offset = mt8183_mutex_mdp_offset,
> + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK,
> + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK,
> .no_clk = true,
> };
>
> @@ -290,6 +312,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_get);
>
> +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev,
> + enum mtk_mdp_pipe_id id)
> +{
> + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
> + int i = mtx->data->mutex_mdp_offset[id];
> +
> + if (!mtx->mutex[i].claimed) {
I'm not sure that tracking the usage of this mutex here is the right thing
to do: from what I understand, this is being acquired by the MDP driver, at
mdp_probe(), and only once... so this check may be mostly useless, if not
in order to avoid possible race conditions due to really bad code.
Can anyone else give an opinion on that?
> + mtx->mutex[i].claimed = true;
> + return &mtx->mutex[i];
> + }
> +
> + return ERR_PTR(-EBUSY);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get);
> +
> void mtk_mutex_put(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -369,6 +406,25 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_add_comp);
>
> +void mtk_mutex_add_mdp_mod(struct mtk_mutex *mutex, u32 mod,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> + unsigned int offset;
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg, mutex->id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
> + mod, mtx->data->mutex_mdp_mod_mask);
> +
Calls to this function makes this driver to depend on CONFIG_MTK_CMDQ.
Failing to meet this requirement will make the build to fail with:
drivers/soc/mediatek/mtk-mutex.c:545: undefined reference to `cmdq_pkt_write_mask'
> + offset = DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg, mutex->id);
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id, mtx->addr + offset,
> + 0, mtx->data->mutex_mdp_sof_mask);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_add_mdp_mod);
> +
> void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
> enum mtk_ddp_comp_id id)
> {
> @@ -420,6 +476,20 @@ void mtk_mutex_enable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_enable);
>
> +void mtk_mutex_enable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x1, 0x00000001);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_enable_by_cmdq);
> +
> void mtk_mutex_disable(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -431,6 +501,20 @@ void mtk_mutex_disable(struct mtk_mutex *mutex)
> }
> EXPORT_SYMBOL_GPL(mtk_mutex_disable);
>
> +void mtk_mutex_disable_by_cmdq(struct mtk_mutex *mutex,
> + struct mmsys_cmdq_cmd *cmd)
> +{
> + struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> + mutex[mutex->id]);
> +
> + WARN_ON(&mtx->mutex[mutex->id] != mutex);
> +
> + cmdq_pkt_write_mask(cmd->pkt, mtx->subsys_id,
> + mtx->addr + DISP_REG_MUTEX_EN(mutex->id),
> + 0x0, 0x00000001);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mutex_disable_by_cmdq);
> +
> void mtk_mutex_acquire(struct mtk_mutex *mutex)
> {
> struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx,
> @@ -458,7 +542,8 @@ static int mtk_mutex_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct mtk_mutex_ctx *mtx;
> - struct resource *regs;
> + struct cmdq_client_reg cmdq_reg;
> + struct resource *regs, addr;
> int i;
>
> mtx = devm_kzalloc(dev, sizeof(*mtx), GFP_KERNEL);
> @@ -479,6 +564,15 @@ static int mtk_mutex_probe(struct platform_device *pdev)
> }
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &addr) < 0)
> + mtx->addr = 0L;
> + else
> + mtx->addr = addr.start;
> +
> + if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
... And it's the same here:
drivers/soc/mediatek/mtk-mutex.c:605: undefined reference to `cmdq_dev_get_client_reg'
Please add the required dependency/select in Kconfig.
Regards,
- Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform
2021-09-03 10:01 ` [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Hans Verkuil
@ 2021-10-14 8:43 ` moudy ho
0 siblings, 0 replies; 22+ messages in thread
From: moudy ho @ 2021-10-14 8:43 UTC (permalink / raw)
To: Hans Verkuil, Mauro Carvalho Chehab, Rob Herring,
Matthias Brugger, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
Hi Hans,
Thank you for your kind guidance, it is really helpful for us to
comprehend V4L2 framework.
After modifying the settings you mentioned, the V4L2-Compliance test
results all passed and listed below.
All these changes will be integrated into the next version.
localhost ~ # v4l2-compliance -d 11
v4l2-compliance SHA: not available
, 32 bits, 32-bit time_t
Compliance test for mtk-mdp3 device /dev/video11:
Driver Info:
Driver name : mtk-mdp3
Card type : 14001000.mdp3_rdma0
Bus info : platform:mtk-mdp3
Driver version : 5.10.66
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video11 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
test invalid ioctls: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 4 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Total for mtk-mdp3 device /dev/video11: 45, Succeeded: 45, Failed: 0,
Warnings: 0
localhost ~ # v4l2-compliance -d 11 -s 1
v4l2-compliance SHA: not available
, 32 bits, 32-bit time_t
Compliance test for mtk-mdp3 device /dev/video11:
Driver Info:
Driver name : mtk-mdp3
Card type : 14001000.mdp3_rdma0
Bus info : platform:mtk-mdp3
Driver version : 5.10.66
Capabilities : 0x84204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Device Capabilities
Device Caps : 0x04204000
Video Memory-to-Memory Multiplanar
Streaming
Extended Pix Format
Required ioctls:
test VIDIOC_QUERYCAP: OK
Allow for multiple opens:
test second /dev/video11 open: OK
test VIDIOC_QUERYCAP: OK
test VIDIOC_G/S_PRIORITY: OK
test for unlimited opens: OK
test invalid ioctls: OK
Debug ioctls:
test VIDIOC_DBG_G/S_REGISTER: OK (Not Supported)
test VIDIOC_LOG_STATUS: OK (Not Supported)
Input ioctls:
test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
test VIDIOC_ENUMAUDIO: OK (Not Supported)
test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
test VIDIOC_G/S_AUDIO: OK (Not Supported)
Inputs: 0 Audio Inputs: 0 Tuners: 0
Output ioctls:
test VIDIOC_G/S_MODULATOR: OK (Not Supported)
test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
test VIDIOC_ENUMAUDOUT: OK (Not Supported)
test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
test VIDIOC_G/S_AUDOUT: OK (Not Supported)
Outputs: 0 Audio Outputs: 0 Modulators: 0
Input/Output configuration ioctls:
test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
test VIDIOC_G/S_EDID: OK (Not Supported)
Control ioctls:
test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
test VIDIOC_QUERYCTRL: OK
test VIDIOC_G/S_CTRL: OK
test VIDIOC_G/S/TRY_EXT_CTRLS: OK
test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
Standard Controls: 4 Private Controls: 0
Format ioctls:
test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK
test VIDIOC_G/S_PARM: OK (Not Supported)
test VIDIOC_G_FBUF: OK (Not Supported)
test VIDIOC_G_FMT: OK
test VIDIOC_TRY_FMT: OK
test VIDIOC_S_FMT: OK
test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
test Cropping: OK
test Composing: OK
test Scaling: OK
Codec ioctls:
test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
test VIDIOC_G_ENC_INDEX: OK (Not Supported)
test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)
Buffer ioctls:
test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK
test VIDIOC_EXPBUF: OK
test Requests: OK (Not Supported)
Test input 0:
Streaming ioctls:
test read/write: OK (Not Supported)
test blocking wait: OK
Video Capture Multiplanar: Captured 1 buffers
test MMAP (no poll): OK
Video Capture Multiplanar: Captured 1 buffers
test MMAP (select): OK
Video Capture Multiplanar: Captured 1 buffers
test MMAP (epoll): OK
test USERPTR (no poll): OK (Not Supported)
test USERPTR (select): OK (Not Supported)
test DMABUF: Cannot test, specify --expbuf-device
Total for mtk-mdp3 device /dev/video11: 52, Succeeded: 52, Failed: 0,
Warnings: 0
Thanks & Regards,
Moudy Ho
On Fri, 2021-09-03 at 12:01 +0200, Hans Verkuil wrote:
> Hi Moudy,
>
> Can you provide the 'v4l2-compliance -s' output?
>
> Make sure to compile v4l2-compliance from the latest code base:
>
https://urldefense.com/v3/__https://git.linuxtv.org/v4l-utils.git/__;!!CTRNKA9wMg0ARbw!2QmkFhMoYBCR4MC5d_l8b7zvdEdwkfd6826nOY6WAHQChU4rMl8P9UtO6Z8ZrcPD$
>
>
> Compiling on x86_64 (so using COMPILE_TEST) fails:
>
> LD .tmp_vmlinux.kallsyms1
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-core.o: in function
> `mdp_probe':
> mtk-mdp3-core.c:(.text+0x415): undefined reference to
> `mtk_mutex_mdp_get'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.o: in function
> `config_camin_subfrm':
> mtk-mdp3-comp.c:(.text+0x9b): undefined reference to
> `mtk_mmsys_mdp_camin_ctrl'
> ld: mtk-mdp3-comp.c:(.text+0xbc): undefined reference to
> `mtk_mmsys_mdp_camin_ctrl'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.o: in function
> `mdp_component_deinit':
> mtk-mdp3-comp.c:(.text+0x2707): undefined reference to
> `mtk_mutex_put'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.o: in function
> `init_isp.cold':
> mtk-mdp3-comp.c:(.text.unlikely+0x4f): undefined reference to
> `mtk_mmsys_mdp_isp_ctrl'
> ld: mtk-mdp3-comp.c:(.text.unlikely+0x7a): undefined reference to
> `mtk_mmsys_mdp_isp_ctrl'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_auto_release_work':
> mtk-mdp3-cmdq.c:(.text+0x13): undefined reference to
> `mtk_mutex_unprepare'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_path_subfrm_require':
> mtk-mdp3-cmdq.c:(.text+0x45e): undefined reference to
> `mtk_mutex_add_mdp_mod'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_path_subfrm_run.isra.0':
> mtk-mdp3-cmdq.c:(.text+0x78b): undefined reference to
> `mtk_mutex_enable_by_cmdq'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_path_config_subfrm':
> mtk-mdp3-cmdq.c:(.text+0xa0d): undefined reference to
> `mtk_mmsys_mdp_connect'
> ld: mtk-mdp3-cmdq.c:(.text+0xd08): undefined reference to
> `mtk_mmsys_mdp_disconnect'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_cmdq_send':
> (.text+0x1358): undefined reference to `mtk_mutex_prepare'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_handle_cmdq_callback.cold':
> mtk-mdp3-cmdq.c:(.text.unlikely+0x34): undefined reference to
> `mtk_mutex_unprepare'
> ld: drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.o: in function
> `mdp_cmdq_send.cold':
> mtk-mdp3-cmdq.c:(.text.unlikely+0xe3): undefined reference to
> `mtk_mutex_unprepare'
> make: *** [Makefile:1177: vmlinux] Error 1
>
> I also get compile warnings:
>
> drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c: In function
> ‘mdp_sub_comps_create’:
> drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c:1151:29: warning:
> implicit conversion from ‘enum mtk_mdp_comp_id’ to ‘enum
> mdp_comp_type’ [-Wenum-conversion]
> 1151 | enum mdp_comp_type type = MDP_COMP_NONE;
> | ^~~~~~~~~~~~~
> drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c: In function
> ‘mdp_component_init’:
> drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c:1217:6: warning:
> unused variable ‘i’ [-Wunused-variable]
> 1217 | int i, ret;
> | ^
> drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c: In function
> ‘mdp_cmdq_send’:
> drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c:489:1: warning: the
> frame size of 1312 bytes is larger than 1024 bytes [-Wframe-larger-
> than=]
> 489 | }
> | ^
>
> Regards,
>
> Hans
>
> On 24/08/2021 12:00, Moudy Ho wrote:
> > Changes since v6:
> > - Refactor GCE event to corresponding node.
> > - Fix dt_binding_check fail.
> > - Fix compilation errors.
> >
> > Changes since v5:
> > - Rebase on v5.14-rc6.
> > - Move MMSYS/Mutex settings to corresponding driver.
> > - Revise the software license description and copyright.
> > - Remove unnecessary enum. or definitions.
> > - Optimize platform/chip definition conditions.
> > - Use general printing functions instead of MDP3 private ones.
> > - Fix compile warning.
> >
> > Changes since v4:
> > - Rebase on v5.13-rc1.
> > - Remove the CMDQ flush flow to match the CMDQ API change.
> > - Integrate four of MDP's direct-link subcomponents into MDP
> > controller node
> > from syscon node to avoid illegal clock usage.
> > - Rewrite dt-binding in a JSON compatible subset of YAML
> > - Fix a bit of macro argument precedence.
> >
> > Changes since v3:
> > - Rebase on v5.9-rc1.
> > - modify code for review comment from Rob Herring, cancel multiple
> > nodes using
> > same register base situation.
> > - control IOMMU port through pm runtime get/put to DMA components'
> > device.
> > - SCP(VPU) driver revision.
> > - stop queuing jobs(remove flush_workqueue()) after
> > mdp_m2m_release().
> > - add computation of plane address with data_offset.
> > - fix scale ratio check issue.
> > - add default v4l2_format setting.
> >
> > Changes since v2:
> > - modify code for review comment from Tomasz Figa & Alexandre
> > Courbot
> > - review comment from Rob Herring will offer code revision in v4,
> > due to
> > it's related to device node modification, will need to modify
> > code
> > architecture
> >
> > Changes since v1:
> > - modify code for CMDQ v3 API support
> > - EC ipi cmd migration
> > - fix compliance test fail item (m2m cmd with -f) due to there is
> > two problem in runing all format(-f) cmd:
> > 1. out of memory before test complete
> > Due to capture buffer mmap (refcount + 1) after reqbuf but
> > seems
> > no corresponding munmap called before device close.
> > There are total 12XX items(formats) in format test and each
> > format
> > alloc 8 capture/output buffers.
> > 2. unceasingly captureBufs() (randomly)
> > Seems the break statement didn't catch the count == 0
> > situation:
> > In v4l2-test-buffers.cpp, function: captureBufs()
> > ...
> > count--;
> > if (!node->is_m2m && !count)
> > break;
> > Log is as attachment
> >
> > I will paste the test result with problem part in another e-mail
> >
> > Hi,
> >
> > This is the first version of RFC patch for Media Data Path 3
> > (MDP3),
> > MDP3 is used for scaling and color format conversion.
> > support using GCE to write register in critical time limitation.
> > support V4L2 m2m device control.
> >
> > Moudy Ho (5):
> > soc: mediatek: mutex: add support for MDP
> > soc: mediatek: mmsys: Add support for MDP
> > dt-binding: mt8183: Add Mediatek MDP3 dt-bindings
> > dts: arm64: mt8183: Add Mediatek MDP3 nodes
> > media: platform: mtk-mdp3: Add Mediatek MDP3 driver
> >
> > .../bindings/media/mediatek,mdp3-ccorr.yaml | 57 +
> > .../bindings/media/mediatek,mdp3-rdma.yaml | 207 +++
> > .../bindings/media/mediatek,mdp3-rsz.yaml | 65 +
> > .../bindings/media/mediatek,mdp3-wdma.yaml | 71 +
> > .../bindings/media/mediatek,mdp3-wrot.yaml | 71 +
> > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 110 ++
> > drivers/media/platform/Kconfig | 19 +
> > drivers/media/platform/Makefile | 2 +
> > drivers/media/platform/mtk-mdp3/Makefile | 6 +
> > .../media/platform/mtk-mdp3/mdp_reg_ccorr.h | 19 +
> > drivers/media/platform/mtk-mdp3/mdp_reg_isp.h | 27 +
> > .../media/platform/mtk-mdp3/mdp_reg_rdma.h | 65 +
> > drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h | 39 +
> > .../media/platform/mtk-mdp3/mdp_reg_wdma.h | 47 +
> > .../media/platform/mtk-mdp3/mdp_reg_wrot.h | 55 +
> > drivers/media/platform/mtk-mdp3/mtk-img-ipi.h | 280 ++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.c | 507 +++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-cmdq.h | 46 +
> > .../media/platform/mtk-mdp3/mtk-mdp3-comp.c | 1307
> > +++++++++++++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-comp.h | 147 ++
> > .../media/platform/mtk-mdp3/mtk-mdp3-core.c | 329 +++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-core.h | 75 +
> > .../media/platform/mtk-mdp3/mtk-mdp3-m2m.c | 801 ++++++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-m2m.h | 41 +
> > .../media/platform/mtk-mdp3/mtk-mdp3-regs.c | 746 ++++++++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-regs.h | 372 +++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-vpu.c | 312 ++++
> > .../media/platform/mtk-mdp3/mtk-mdp3-vpu.h | 78 +
> > drivers/soc/mediatek/mt8183-mmsys.h | 235 +++
> > drivers/soc/mediatek/mtk-mmsys.c | 164 +++
> > drivers/soc/mediatek/mtk-mmsys.h | 9 +-
> > drivers/soc/mediatek/mtk-mutex.c | 106 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 81 +
> > include/linux/soc/mediatek/mtk-mutex.h | 8 +
> > 34 files changed, 6495 insertions(+), 9 deletions(-)
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-ccorr.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wdma.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml
> > create mode 100644 drivers/media/platform/mtk-mdp3/Makefile
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_ccorr.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_isp.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rdma.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_rsz.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wdma.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mdp_reg_wrot.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-img-ipi.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-cmdq.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-comp.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-core.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-m2m.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-regs.h
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.c
> > create mode 100644 drivers/media/platform/mtk-mdp3/mtk-mdp3-vpu.h
> >
>
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 2/5] soc: mediatek: mmsys: Add support for MDP
2021-08-24 10:00 ` [PATCH v7 2/5] soc: mediatek: mmsys: Add " Moudy Ho
@ 2021-10-14 15:24 ` Matthias Brugger
2021-10-15 12:22 ` moudy ho
0 siblings, 1 reply; 22+ messages in thread
From: Matthias Brugger @ 2021-10-14 15:24 UTC (permalink / raw)
To: Moudy Ho, Mauro Carvalho Chehab, Rob Herring, Hans Verkuil,
Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
On 24/08/2021 12:00, Moudy Ho wrote:
> Add functions to support MDP:
> 1. MDP connect/disconnect functions
> 2. ISP control function
> 3. Write register via CMDQ
Sounds like three patches instead of one.
>
> Add MDP related settings for 8183 SoC
> 1. Register settings
> 2. MDP route table
>
> Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> ---
> drivers/soc/mediatek/mt8183-mmsys.h | 235 +++++++++++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.c | 164 +++++++++++++++++
> drivers/soc/mediatek/mtk-mmsys.h | 9 +-
> include/linux/soc/mediatek/mtk-mmsys.h | 81 +++++++++
> 4 files changed, 486 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
> index 579dfc8dc8fc..2fa79e745a45 100644
> --- a/drivers/soc/mediatek/mt8183-mmsys.h
> +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> @@ -12,6 +12,32 @@
> #define MT8183_DISP_DPI0_SEL_IN 0xf30
> #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
> +#define MT8183_MDP_ISP_MOUT_EN 0xf80
> +#define MT8183_MDP_RDMA0_MOUT_EN 0xf84
> +#define MT8183_MDP_PRZ0_MOUT_EN 0xf8c
> +#define MT8183_MDP_PRZ1_MOUT_EN 0xf90
> +#define MT8183_MDP_COLOR_MOUT_EN 0xf94
> +#define MT8183_MDP_IPU_MOUT_EN 0xf98
> +#define MT8183_MDP_PATH0_SOUT_SEL 0xfa8
> +#define MT8183_MDP_PATH1_SOUT_SEL 0xfac
> +#define MT8183_MDP_PRZ0_SEL_IN 0xfc0
> +#define MT8183_MDP_PRZ1_SEL_IN 0xfc4
> +#define MT8183_MDP_TDSHP_SEL_IN 0xfc8
> +#define MT8183_MDP_WROT0_SEL_IN 0xfd0
> +#define MT8183_MDP_WDMA_SEL_IN 0xfd4
> +#define MT8183_MDP_PATH0_SEL_IN 0xfe0
> +#define MT8183_MDP_PATH1_SEL_IN 0xfe4
> +#define MT8183_MDP_AAL_MOUT_EN 0xfe8
> +#define MT8183_MDP_AAL_SEL_IN 0xfec
> +#define MT8183_MDP_CCORR_SEL_IN 0xff0
> +#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
> +
> +#define MT8183_ISP_CTRL_MMSYS_SW0_RST_B 0x140
> +#define MT8183_ISP_CTRL_MMSYS_SW1_RST_B 0x144
> +#define MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD 0x934
> +#define MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD 0x93C
> +#define MT8183_ISP_CTRL_ISP_RELAY_CFG_WD 0x994
> +#define MT8183_ISP_CTRL_IPU_RELAY_CFG_WD 0x9a0
>
> #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> @@ -24,6 +50,55 @@
> #define MT8183_DPI0_SEL_IN_RDMA1 0x2
> #define MT8183_RDMA0_SOUT_COLOR0 0x1
> #define MT8183_RDMA1_SOUT_DSI0 0x1
> +#define MT8183_MDP_ISP_MOUT_EN_CCORR0 BIT(0)
> +#define MT8183_MDP_ISP_MOUT_EN_RSZ1 BIT(1)
> +#define MT8183_MDP_ISP_MOUT_EN_AAL0 BIT(2)
> +#define MT8183_MDP_IPU_MOUT_EN_CCORR0 BIT(0)
> +#define MT8183_MDP_IPU_MOUT_EN_RSZ1 BIT(1)
> +#define MT8183_MDP_IPU_MOUT_EN_AAL0 BIT(2)
> +#define MT8183_MDP_RDMA0_MOUT_EN_CCORR0 BIT(0)
> +#define MT8183_MDP_RDMA0_MOUT_EN_RSZ1 BIT(1)
> +#define MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT BIT(2)
> +#define MT8183_MDP_RDMA0_MOUT_EN_AAL0 BIT(3)
> +#define MT8183_MDP_AAL_MOUT_EN_CCORR0 BIT(0)
> +#define MT8183_MDP_AAL_MOUT_EN_RSZ1 BIT(1)
> +#define MT8183_MDP_AAL_MOUT_EN_RSZ0 BIT(2)
> +#define MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT BIT(0)
> +#define MT8183_MDP_PRZ0_MOUT_EN_TDSHP0 BIT(1)
> +#define MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT BIT(0)
> +#define MT8183_MDP_PRZ1_MOUT_EN_TDSHP0 BIT(1)
> +#define MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT BIT(2)
> +#define MT8183_MDP_PRZ1_MOUT_EN_COLOR0 BIT(4)
> +#define MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT BIT(0)
> +#define MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT BIT(1)
> +#define MT8183_MDP_AAL_SEL_IN_CAMIN 0
> +#define MT8183_MDP_AAL_SEL_IN_RDMA0 1
> +#define MT8183_MDP_AAL_SEL_IN_CAMIN2 2
> +#define MT8183_MDP_AAL_SEL_IN_CCORR0 3
> +#define MT8183_MDP_CCORR_SEL_IN_CAMIN 0
> +#define MT8183_MDP_CCORR_SEL_IN_RDMA0 1
> +#define MT8183_MDP_CCORR_SEL_IN_CAMIN2 3
> +#define MT8183_MDP_CCORR_SEL_IN_AAL0 4
> +#define MT8183_MDP_PRZ0_SEL_IN_AAL0 0
> +#define MT8183_MDP_PRZ0_SEL_IN_CCORR0 1
> +#define MT8183_MDP_PRZ1_SEL_IN_CAMIN 0
> +#define MT8183_MDP_PRZ1_SEL_IN_RDMA0 1
> +#define MT8183_MDP_PRZ1_SEL_IN_CAMIN2 4
> +#define MT8183_MDP_PRZ1_SEL_IN_AAL0 5
> +#define MT8183_MDP_TDSHP_SEL_IN_RSZ0 0
> +#define MT8183_MDP_TDSHP_SEL_IN_RSZ1 1
> +#define MT8183_MDP_PATH0_SEL_IN_RSZ0 0
> +#define MT8183_MDP_PATH0_SEL_IN_RSZ1 1
> +#define MT8183_MDP_PATH0_SEL_IN_COLOR0 2
> +#define MT8183_MDP_PATH0_SEL_IN_RDMA0 3
> +#define MT8183_MDP_PATH1_SEL_IN_RSZ1 0
> +#define MT8183_MDP_PATH1_SEL_IN_COLOR0 1
> +#define MT8183_MDP_WROT0_SEL_IN_PATH0_OUT 0
> +#define MT8183_MDP_WDMA_SEL_IN_PATH1_OUT 0
> +#define MT8183_MDP_CCORR_SOUT_SEL_AAL0 0
> +#define MT8183_MDP_CCORR_SOUT_SEL_RSZ0 1
> +#define MT8183_MDP_PATH0_SOUT_SEL_WROT0 0
> +#define MT8183_MDP_PATH1_SOUT_SEL_WDMA 0
>
> static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> {
> @@ -50,5 +125,165 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
> }
> };
>
> +static const struct mtk_mmsys_routes mmsys_mt8183_mdp_routing_table[] = {
> + {
> + MDP_COMP_CAMIN, MDP_COMP_CCORR0,
> + MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_CCORR0
> + }, {
> + MDP_COMP_CAMIN, MDP_COMP_RSZ1,
> + MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_RSZ1
> + }, {
> + MDP_COMP_CAMIN, MDP_COMP_AAL0,
> + MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_AAL0
> + }, {
> + MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
> + MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_CCORR0
> + }, {
> + MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
> + MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_RSZ1
> + }, {
> + MDP_COMP_CAMIN2, MDP_COMP_AAL0,
> + MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_AAL0
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_CCORR0,
> + MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_CCORR0
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_RSZ1,
> + MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_RSZ1
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_AAL0,
> + MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_AAL0
> + }, {
> + MDP_COMP_AAL0, MDP_COMP_CCORR0,
> + MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_CCORR0
> + }, {
> + MDP_COMP_AAL0, MDP_COMP_RSZ1,
> + MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ1
> + }, {
> + MDP_COMP_AAL0, MDP_COMP_RSZ0,
> + MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ0
> + }, {
> + MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT
> + }, {
> + MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
> + MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_TDSHP0
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
> + MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_TDSHP0
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
> + MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_COLOR0,
> + MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_COLOR0
> + }, {
> + MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT
> + }, {
> + MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
> + MT8183_MDP_COLOR_MOUT_EN, MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT
> + }, {
> + MDP_COMP_CAMIN, MDP_COMP_AAL0,
> + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_AAL0,
> + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_RDMA0
> + }, {
> + MDP_COMP_CAMIN2, MDP_COMP_AAL0,
> + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN2
> + }, {
> + MDP_COMP_CCORR0, MDP_COMP_AAL0,
> + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CCORR0
> + }, {
> + MDP_COMP_CAMIN, MDP_COMP_CCORR0,
> + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_CCORR0,
> + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_RDMA0
> + }, {
> + MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
> + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN2
> + }, {
> + MDP_COMP_AAL0, MDP_COMP_CCORR0,
> + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_AAL0
> + }, {
> + MDP_COMP_AAL0, MDP_COMP_RSZ0,
> + MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_AAL0
> + }, {
> + MDP_COMP_CCORR0, MDP_COMP_RSZ0,
> + MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_CCORR0
> + }, {
> + MDP_COMP_CAMIN, MDP_COMP_RSZ1,
> + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_RSZ1,
> + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_RDMA0
> + }, {
> + MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
> + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN2
> + }, {
> + MDP_COMP_AAL0, MDP_COMP_RSZ1,
> + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_AAL0
> + }, {
> + MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
> + MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ0
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
> + MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ1
> + }, {
> + MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ0
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ1
> + }, {
> + MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_COLOR0
> + }, {
> + MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
> + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RDMA0
> + }, {
> + MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
> + MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_RSZ1
> + }, {
> + MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
> + MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_COLOR0
> + }, {
> + MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
> + MT8183_MDP_WROT0_SEL_IN, MT8183_MDP_WROT0_SEL_IN_PATH0_OUT
> + }, {
> + MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
> + MT8183_MDP_WDMA_SEL_IN, MT8183_MDP_WDMA_SEL_IN_PATH1_OUT
> + }, {
> + MDP_COMP_CCORR0, MDP_COMP_AAL0,
> + MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_AAL0
> + }, {
> + MDP_COMP_CCORR0, MDP_COMP_RSZ0,
> + MT8183_MDP_CCORR_SOUT_SEL, MT8183_MDP_CCORR_SOUT_SEL_RSZ0
> + }, {
> + MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
> + MT8183_MDP_PATH0_SOUT_SEL, MT8183_MDP_PATH0_SOUT_SEL_WROT0
> + }, {
> + MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
> + MT8183_MDP_PATH1_SOUT_SEL, MT8183_MDP_PATH1_SOUT_SEL_WDMA
> + }
> +};
> +
> +static const unsigned int mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> + [ISP_CTRL_MMSYS_SW0_RST_B] = MT8183_ISP_CTRL_MMSYS_SW0_RST_B,
> + [ISP_CTRL_MMSYS_SW1_RST_B] = MT8183_ISP_CTRL_MMSYS_SW1_RST_B,
> + [ISP_CTRL_MDP_ASYNC_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD,
> + [ISP_CTRL_MDP_ASYNC_IPU_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
> + [ISP_CTRL_ISP_RELAY_CFG_WD] = MT8183_ISP_CTRL_ISP_RELAY_CFG_WD,
> + [ISP_CTRL_IPU_RELAY_CFG_WD] = MT8183_ISP_CTRL_IPU_RELAY_CFG_WD,
> +};
> +
> #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 080660ef11bf..c4b99a99ee1e 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -7,8 +7,10 @@
> #include <linux/device.h>
> #include <linux/io.h>
> #include <linux/of_device.h>
> +#include <linux/of_address.h>
> #include <linux/platform_device.h>
> #include <linux/soc/mediatek/mtk-mmsys.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk-mmsys.h"
> #include "mt8167-mmsys.h"
> @@ -50,11 +52,16 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .clk_driver = "clk-mt8183-mm",
> .routes = mmsys_mt8183_routing_table,
> .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> + .mdp_routes = mmsys_mt8183_mdp_routing_table,
> + .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
> + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> };
>
> struct mtk_mmsys {
> void __iomem *regs;
> const struct mtk_mmsys_driver_data *data;
> + phys_addr_t addr;
> + u8 subsys_id;
> };
>
> void mtk_mmsys_ddp_connect(struct device *dev,
> @@ -91,12 +98,160 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_mdp_connect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id cur,
> + enum mtk_mdp_comp_id next)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
> + int i;
> +
> + WARN_ON(!routes);
> + WARN_ON(mmsys->subsys_id == 0);
> + for (i = 0; i < mmsys->data->mdp_num_routes; i++)
> + if (cur == routes[i].from_comp && next == routes[i].to_comp)
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> + mmsys->addr + routes[i].addr,
> + routes[i].val, 0xFFFFFFFF);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_connect);
I wonder if we are going the wrong path with mmsys. It seems to me that we are
adding random export symbols. I suppose the don't want to use syscon/regmap
because we want to define the routing tables in the mmsys driver, as they are
part of the mmsys HW, correct?
Regards,
Matthias
> +
> +void mtk_mmsys_mdp_disconnect(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id cur,
> + enum mtk_mdp_comp_id next)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const struct mtk_mmsys_routes *routes = mmsys->data->mdp_routes;
> + int i;
> +
> + WARN_ON(mmsys->subsys_id == 0);
> + for (i = 0; i < mmsys->data->mdp_num_routes; i++)
> + if (cur == routes[i].from_comp && next == routes[i].to_comp)
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> + mmsys->addr + routes[i].addr,
> + 0, 0xFFFFFFFF);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
> +
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + WARN_ON(mmsys->subsys_id == 0);
> + /* Direct link */
> + if (id == MDP_COMP_CAMIN) {
> + /* Reset MDP_DL_ASYNC_TX */
> + /* Bit 3: MDP_DL_ASYNC_TX / MDP_RELAY */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000008);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 3, 0x00000008);
> + }
> +
> + /* Reset MDP_DL_ASYNC_RX */
> + /* Bit 10: MDP_DL_ASYNC_RX */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000400);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 10, 0x00000400);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0 << 31, 0x80000000);
> + }
> + }
> +
> + if (id == MDP_COMP_CAMIN2) {
> + /* Reset MDP_DL_ASYNC2_TX */
> + /* Bit 4: MDP_DL_ASYNC2_TX / MDP_RELAY2 */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000010);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 4, 0x00000010);
> + }
> +
> + /* Reset MDP_DL_ASYNC2_RX */
> + /* Bit 11: MDP_DL_ASYNC2_RX */
> + if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0x0, 0x00000800);
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 1 << 11, 0x00000800);
> + }
> +
> + /* Enable sof mode */
> + if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + 0 << 31, 0x80000000);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id, u32 camin_w, u32 camin_h)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> + u32 reg;
> +
> + WARN_ON(mmsys->subsys_id == 0);
> + /* Config for direct link */
> + if (id == MDP_COMP_CAMIN) {
> + if (isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> +
> + if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> + if (id == MDP_COMP_CAMIN2) {
> + if (isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD]) {
> + reg = mmsys->addr +
> + isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
> + reg = mmsys->addr + isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
> + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id, reg,
> + (camin_h << 16) + camin_w,
> + 0x3FFF3FFF);
> + }
> + }
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> +
> static int mtk_mmsys_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> struct platform_device *clks;
> struct platform_device *drm;
> struct mtk_mmsys *mmsys;
> + struct resource res;
> + struct cmdq_client_reg cmdq_reg;
> int ret;
>
> mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> @@ -110,6 +265,15 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
> return ret;
> }
>
> + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> + mmsys->addr = 0L;
> + else
> + mmsys->addr = res.start;
> +
> + if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
> + dev_info(dev, "cmdq subsys id has not been set\n");
> + mmsys->subsys_id = cmdq_reg.subsys;
> +
> mmsys->data = of_device_get_match_data(&pdev->dev);
> platform_set_drvdata(pdev, mmsys);
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
> index a760a34e6eca..025d4bc9c8cc 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.h
> +++ b/drivers/soc/mediatek/mtk-mmsys.h
> @@ -74,9 +74,12 @@ struct mtk_mmsys_routes {
> };
>
> struct mtk_mmsys_driver_data {
> - const char *clk_driver;
> - const struct mtk_mmsys_routes *routes;
> - const unsigned int num_routes;
> + const char *clk_driver;
> + const struct mtk_mmsys_routes *routes;
> + const unsigned int num_routes;
> + const struct mtk_mmsys_routes *mdp_routes;
> + const unsigned int mdp_num_routes;
> + const unsigned int *mdp_isp_ctrl;
Style changes in seperate patch please.
> };
>
> /*
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 2228bf6133da..4eb48d073d2a 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -7,8 +7,14 @@
> #define __MTK_MMSYS_H
>
> enum mtk_ddp_comp_id;
> +enum mtk_mdp_comp_id;
> struct device;
>
> +struct mmsys_cmdq_cmd {
> + struct cmdq_pkt *pkt;
> + s32 *event;
> +};
> +
> enum mtk_ddp_comp_id {
> DDP_COMPONENT_AAL0,
> DDP_COMPONENT_AAL1,
> @@ -42,6 +48,64 @@ enum mtk_ddp_comp_id {
> DDP_COMPONENT_ID_MAX,
> };
>
> +enum mtk_mdp_comp_id {
> + MDP_COMP_NONE = -1, /* Invalid engine */
> +
> + /* ISP */
> + MDP_COMP_WPEI = 0,
> + MDP_COMP_WPEO, /* 1 */
> + MDP_COMP_WPEI2, /* 2 */
> + MDP_COMP_WPEO2, /* 3 */
> + MDP_COMP_ISP_IMGI, /* 4 */
> + MDP_COMP_ISP_IMGO, /* 5 */
> + MDP_COMP_ISP_IMG2O, /* 6 */
> +
> + /* IPU */
> + MDP_COMP_IPUI, /* 7 */
> + MDP_COMP_IPUO, /* 8 */
> +
> + /* MDP */
> + MDP_COMP_CAMIN, /* 9 */
> + MDP_COMP_CAMIN2, /* 10 */
> + MDP_COMP_RDMA0, /* 11 */
> + MDP_COMP_AAL0, /* 12 */
> + MDP_COMP_CCORR0, /* 13 */
> + MDP_COMP_RSZ0, /* 14 */
> + MDP_COMP_RSZ1, /* 15 */
> + MDP_COMP_TDSHP0, /* 16 */
> + MDP_COMP_COLOR0, /* 17 */
> + MDP_COMP_PATH0_SOUT, /* 18 */
> + MDP_COMP_PATH1_SOUT, /* 19 */
> + MDP_COMP_WROT0, /* 20 */
> + MDP_COMP_WDMA, /* 21 */
> +
> + /* Dummy Engine */
> + MDP_COMP_RDMA1, /* 22 */
> + MDP_COMP_RSZ2, /* 23 */
> + MDP_COMP_TDSHP1, /* 24 */
> + MDP_COMP_WROT1, /* 25 */
> +
> + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> +};
> +
> +enum mtk_mdp_pipe_id {
> + MDP_PIPE_RDMA0,
> + MDP_PIPE_IMGI,
> + MDP_PIPE_WPEI,
> + MDP_PIPE_WPEI2,
> + MDP_PIPE_MAX
> +};
> +
> +enum mtk_isp_ctrl {
> + ISP_CTRL_MMSYS_SW0_RST_B,
> + ISP_CTRL_MMSYS_SW1_RST_B,
> + ISP_CTRL_MDP_ASYNC_CFG_WD,
> + ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
> + ISP_CTRL_ISP_RELAY_CFG_WD,
> + ISP_CTRL_IPU_RELAY_CFG_WD,
> + ISP_CTRL_MAX
> +};
> +
> void mtk_mmsys_ddp_connect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
> @@ -50,4 +114,21 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> +void mtk_mmsys_mdp_connect(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id cur,
> + enum mtk_mdp_comp_id next);
> +
> +void mtk_mmsys_mdp_disconnect(struct device *dev,
> + struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id cur,
> + enum mtk_mdp_comp_id next);
> +
> +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id);
> +
> +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct mmsys_cmdq_cmd *cmd,
> + enum mtk_mdp_comp_id id,
> + u32 camin_w, u32 camin_h);
> +
> #endif /* __MTK_MMSYS_H */
>
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^ permalink raw reply [flat|nested] 22+ messages in thread
* Re: [PATCH v7 2/5] soc: mediatek: mmsys: Add support for MDP
2021-10-14 15:24 ` Matthias Brugger
@ 2021-10-15 12:22 ` moudy ho
0 siblings, 0 replies; 22+ messages in thread
From: moudy ho @ 2021-10-15 12:22 UTC (permalink / raw)
To: Matthias Brugger, Mauro Carvalho Chehab, Rob Herring,
Hans Verkuil, Jernej Skrabec
Cc: Maoguang Meng, daoyuan huang, Ping-Hsun Wu, Geert Uytterhoeven,
Rob Landley, Laurent Pinchart, linux-media, devicetree,
linux-arm-kernel, linux-mediatek, linux-kernel, tfiga, drinkcat,
acourbot, pihsun, menghui.lin, sj.huang, ben.lok, randy.wu,
srv_heupstream, hsinyi
On Thu, 2021-10-14 at 17:24 +0200, Matthias Brugger wrote:
>
> On 24/08/2021 12:00, Moudy Ho wrote:
> > Add functions to support MDP:
> > 1. MDP connect/disconnect functions
> > 2. ISP control function
> > 3. Write register via CMDQ
>
> Sounds like three patches instead of one.
>
> >
> > Add MDP related settings for 8183 SoC
> > 1. Register settings
> > 2. MDP route table
> >
> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
> > ---
> > drivers/soc/mediatek/mt8183-mmsys.h | 235
> > +++++++++++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.c | 164 +++++++++++++++++
> > drivers/soc/mediatek/mtk-mmsys.h | 9 +-
> > include/linux/soc/mediatek/mtk-mmsys.h | 81 +++++++++
> > 4 files changed, 486 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/soc/mediatek/mt8183-mmsys.h
> > b/drivers/soc/mediatek/mt8183-mmsys.h
> > index 579dfc8dc8fc..2fa79e745a45 100644
> > --- a/drivers/soc/mediatek/mt8183-mmsys.h
> > +++ b/drivers/soc/mediatek/mt8183-mmsys.h
> > @@ -12,6 +12,32 @@
> > #define MT8183_DISP_DPI0_SEL_IN 0xf30
> > #define MT8183_DISP_RDMA0_SOUT_SEL_IN 0xf50
> > #define MT8183_DISP_RDMA1_SOUT_SEL_IN 0xf54
> > +#define MT8183_MDP_ISP_MOUT_EN 0xf80
> > +#define MT8183_MDP_RDMA0_MOUT_EN 0xf84
> > +#define MT8183_MDP_PRZ0_MOUT_EN 0xf8c
> > +#define MT8183_MDP_PRZ1_MOUT_EN 0xf90
> > +#define MT8183_MDP_COLOR_MOUT_EN 0xf94
> > +#define MT8183_MDP_IPU_MOUT_EN 0xf98
> > +#define MT8183_MDP_PATH0_SOUT_SEL 0xfa8
> > +#define MT8183_MDP_PATH1_SOUT_SEL 0xfac
> > +#define MT8183_MDP_PRZ0_SEL_IN 0xfc0
> > +#define MT8183_MDP_PRZ1_SEL_IN 0xfc4
> > +#define MT8183_MDP_TDSHP_SEL_IN 0xfc8
> > +#define MT8183_MDP_WROT0_SEL_IN 0xfd0
> > +#define MT8183_MDP_WDMA_SEL_IN 0xfd4
> > +#define MT8183_MDP_PATH0_SEL_IN 0xfe0
> > +#define MT8183_MDP_PATH1_SEL_IN 0xfe4
> > +#define MT8183_MDP_AAL_MOUT_EN 0xfe8
> > +#define MT8183_MDP_AAL_SEL_IN 0xfec
> > +#define MT8183_MDP_CCORR_SEL_IN 0xff0
> > +#define MT8183_MDP_CCORR_SOUT_SEL 0xff4
> > +
> > +#define MT8183_ISP_CTRL_MMSYS_SW0_RST_B 0x140
> > +#define MT8183_ISP_CTRL_MMSYS_SW1_RST_B 0x144
> > +#define MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD 0x934
> > +#define MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD 0x93C
> > +#define MT8183_ISP_CTRL_ISP_RELAY_CFG_WD 0x994
> > +#define MT8183_ISP_CTRL_IPU_RELAY_CFG_WD 0x9a0
> >
> > #define MT8183_OVL0_MOUT_EN_OVL0_2L BIT(4)
> > #define MT8183_OVL0_2L_MOUT_EN_DISP_PATH0 BIT(0)
> > @@ -24,6 +50,55 @@
> > #define MT8183_DPI0_SEL_IN_RDMA1 0x2
> > #define MT8183_RDMA0_SOUT_COLOR0 0x1
> > #define MT8183_RDMA1_SOUT_DSI0 0x1
> > +#define MT8183_MDP_ISP_MOUT_EN_CCORR0 BIT(0)
> > +#define MT8183_MDP_ISP_MOUT_EN_RSZ1 BIT(1)
> > +#define MT8183_MDP_ISP_MOUT_EN_AAL0 BIT(2)
> > +#define MT8183_MDP_IPU_MOUT_EN_CCORR0 BIT(0)
> > +#define MT8183_MDP_IPU_MOUT_EN_RSZ1 BIT(1)
> > +#define MT8183_MDP_IPU_MOUT_EN_AAL0 BIT(2)
> > +#define MT8183_MDP_RDMA0_MOUT_EN_CCORR0 BIT(0)
> > +#define MT8183_MDP_RDMA0_MOUT_EN_RSZ1 BIT(1)
> > +#define MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT BIT(2)
> > +#define MT8183_MDP_RDMA0_MOUT_EN_AAL0 BIT(3)
> > +#define MT8183_MDP_AAL_MOUT_EN_CCORR0 BIT(0)
> > +#define MT8183_MDP_AAL_MOUT_EN_RSZ1 BIT(1)
> > +#define MT8183_MDP_AAL_MOUT_EN_RSZ0 BIT(2)
> > +#define MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT BIT(0)
> > +#define MT8183_MDP_PRZ0_MOUT_EN_TDSHP0 BIT(1)
> > +#define MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT BIT(0)
> > +#define MT8183_MDP_PRZ1_MOUT_EN_TDSHP0 BIT(1)
> > +#define MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT BIT(2)
> > +#define MT8183_MDP_PRZ1_MOUT_EN_COLOR0 BIT(4)
> > +#define MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT BIT(0)
> > +#define MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT BIT(1)
> > +#define MT8183_MDP_AAL_SEL_IN_CAMIN 0
> > +#define MT8183_MDP_AAL_SEL_IN_RDMA0 1
> > +#define MT8183_MDP_AAL_SEL_IN_CAMIN2 2
> > +#define MT8183_MDP_AAL_SEL_IN_CCORR0 3
> > +#define MT8183_MDP_CCORR_SEL_IN_CAMIN 0
> > +#define MT8183_MDP_CCORR_SEL_IN_RDMA0 1
> > +#define MT8183_MDP_CCORR_SEL_IN_CAMIN2 3
> > +#define MT8183_MDP_CCORR_SEL_IN_AAL0 4
> > +#define MT8183_MDP_PRZ0_SEL_IN_AAL0 0
> > +#define MT8183_MDP_PRZ0_SEL_IN_CCORR0 1
> > +#define MT8183_MDP_PRZ1_SEL_IN_CAMIN 0
> > +#define MT8183_MDP_PRZ1_SEL_IN_RDMA0 1
> > +#define MT8183_MDP_PRZ1_SEL_IN_CAMIN2 4
> > +#define MT8183_MDP_PRZ1_SEL_IN_AAL0 5
> > +#define MT8183_MDP_TDSHP_SEL_IN_RSZ0 0
> > +#define MT8183_MDP_TDSHP_SEL_IN_RSZ1 1
> > +#define MT8183_MDP_PATH0_SEL_IN_RSZ0 0
> > +#define MT8183_MDP_PATH0_SEL_IN_RSZ1 1
> > +#define MT8183_MDP_PATH0_SEL_IN_COLOR0 2
> > +#define MT8183_MDP_PATH0_SEL_IN_RDMA0 3
> > +#define MT8183_MDP_PATH1_SEL_IN_RSZ1 0
> > +#define MT8183_MDP_PATH1_SEL_IN_COLOR0 1
> > +#define MT8183_MDP_WROT0_SEL_IN_PATH0_OUT 0
> > +#define MT8183_MDP_WDMA_SEL_IN_PATH1_OUT 0
> > +#define MT8183_MDP_CCORR_SOUT_SEL_AAL0 0
> > +#define MT8183_MDP_CCORR_SOUT_SEL_RSZ0 1
> > +#define MT8183_MDP_PATH0_SOUT_SEL_WROT0 0
> > +#define MT8183_MDP_PATH1_SOUT_SEL_WDMA 0
> >
> > static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[]
> > = {
> > {
> > @@ -50,5 +125,165 @@ static const struct mtk_mmsys_routes
> > mmsys_mt8183_routing_table[] = {
> > }
> > };
> >
> > +static const struct mtk_mmsys_routes
> > mmsys_mt8183_mdp_routing_table[] = {
> > + {
> > + MDP_COMP_CAMIN, MDP_COMP_CCORR0,
> > + MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_CCORR0
> > + }, {
> > + MDP_COMP_CAMIN, MDP_COMP_RSZ1,
> > + MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_RSZ1
> > + }, {
> > + MDP_COMP_CAMIN, MDP_COMP_AAL0,
> > + MT8183_MDP_ISP_MOUT_EN, MT8183_MDP_ISP_MOUT_EN_AAL0
> > + }, {
> > + MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
> > + MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_CCORR0
> > + }, {
> > + MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
> > + MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_RSZ1
> > + }, {
> > + MDP_COMP_CAMIN2, MDP_COMP_AAL0,
> > + MT8183_MDP_IPU_MOUT_EN, MT8183_MDP_IPU_MOUT_EN_AAL0
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_CCORR0,
> > + MT8183_MDP_RDMA0_MOUT_EN,
> > MT8183_MDP_RDMA0_MOUT_EN_CCORR0
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_RSZ1,
> > + MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_RSZ1
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_RDMA0_MOUT_EN,
> > MT8183_MDP_RDMA0_MOUT_EN_PATH0_OUT
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_AAL0,
> > + MT8183_MDP_RDMA0_MOUT_EN, MT8183_MDP_RDMA0_MOUT_EN_AAL0
> > + }, {
> > + MDP_COMP_AAL0, MDP_COMP_CCORR0,
> > + MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_CCORR0
> > + }, {
> > + MDP_COMP_AAL0, MDP_COMP_RSZ1,
> > + MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ1
> > + }, {
> > + MDP_COMP_AAL0, MDP_COMP_RSZ0,
> > + MT8183_MDP_AAL_MOUT_EN, MT8183_MDP_AAL_MOUT_EN_RSZ0
> > + }, {
> > + MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_PRZ0_MOUT_EN,
> > MT8183_MDP_PRZ0_MOUT_EN_PATH0_OUT
> > + }, {
> > + MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
> > + MT8183_MDP_PRZ0_MOUT_EN, MT8183_MDP_PRZ0_MOUT_EN_TDSHP0
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_PRZ1_MOUT_EN,
> > MT8183_MDP_PRZ1_MOUT_EN_PATH0_OUT
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
> > + MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_TDSHP0
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
> > + MT8183_MDP_PRZ1_MOUT_EN,
> > MT8183_MDP_PRZ1_MOUT_EN_PATH1_OUT
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_COLOR0,
> > + MT8183_MDP_PRZ1_MOUT_EN, MT8183_MDP_PRZ1_MOUT_EN_COLOR0
> > + }, {
> > + MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_COLOR_MOUT_EN,
> > MT8183_MDP_COLOR_MOUT_EN_PATH0_OUT
> > + }, {
> > + MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
> > + MT8183_MDP_COLOR_MOUT_EN,
> > MT8183_MDP_COLOR_MOUT_EN_PATH1_OUT
> > + }, {
> > + MDP_COMP_CAMIN, MDP_COMP_AAL0,
> > + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_AAL0,
> > + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_RDMA0
> > + }, {
> > + MDP_COMP_CAMIN2, MDP_COMP_AAL0,
> > + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CAMIN2
> > + }, {
> > + MDP_COMP_CCORR0, MDP_COMP_AAL0,
> > + MT8183_MDP_AAL_SEL_IN, MT8183_MDP_AAL_SEL_IN_CCORR0
> > + }, {
> > + MDP_COMP_CAMIN, MDP_COMP_CCORR0,
> > + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_CCORR0,
> > + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_RDMA0
> > + }, {
> > + MDP_COMP_CAMIN2, MDP_COMP_CCORR0,
> > + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_CAMIN2
> > + }, {
> > + MDP_COMP_AAL0, MDP_COMP_CCORR0,
> > + MT8183_MDP_CCORR_SEL_IN, MT8183_MDP_CCORR_SEL_IN_AAL0
> > + }, {
> > + MDP_COMP_AAL0, MDP_COMP_RSZ0,
> > + MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_AAL0
> > + }, {
> > + MDP_COMP_CCORR0, MDP_COMP_RSZ0,
> > + MT8183_MDP_PRZ0_SEL_IN, MT8183_MDP_PRZ0_SEL_IN_CCORR0
> > + }, {
> > + MDP_COMP_CAMIN, MDP_COMP_RSZ1,
> > + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_RSZ1,
> > + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_RDMA0
> > + }, {
> > + MDP_COMP_CAMIN2, MDP_COMP_RSZ1,
> > + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_CAMIN2
> > + }, {
> > + MDP_COMP_AAL0, MDP_COMP_RSZ1,
> > + MT8183_MDP_PRZ1_SEL_IN, MT8183_MDP_PRZ1_SEL_IN_AAL0
> > + }, {
> > + MDP_COMP_RSZ0, MDP_COMP_TDSHP0,
> > + MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ0
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_TDSHP0,
> > + MT8183_MDP_TDSHP_SEL_IN, MT8183_MDP_TDSHP_SEL_IN_RSZ1
> > + }, {
> > + MDP_COMP_RSZ0, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ0
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RSZ1
> > + }, {
> > + MDP_COMP_COLOR0, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_COLOR0
> > + }, {
> > + MDP_COMP_RDMA0, MDP_COMP_PATH0_SOUT,
> > + MT8183_MDP_PATH0_SEL_IN, MT8183_MDP_PATH0_SEL_IN_RDMA0
> > + }, {
> > + MDP_COMP_RSZ1, MDP_COMP_PATH1_SOUT,
> > + MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_RSZ1
> > + }, {
> > + MDP_COMP_COLOR0, MDP_COMP_PATH1_SOUT,
> > + MT8183_MDP_PATH1_SEL_IN, MT8183_MDP_PATH1_SEL_IN_COLOR0
> > + }, {
> > + MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
> > + MT8183_MDP_WROT0_SEL_IN,
> > MT8183_MDP_WROT0_SEL_IN_PATH0_OUT
> > + }, {
> > + MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
> > + MT8183_MDP_WDMA_SEL_IN,
> > MT8183_MDP_WDMA_SEL_IN_PATH1_OUT
> > + }, {
> > + MDP_COMP_CCORR0, MDP_COMP_AAL0,
> > + MT8183_MDP_CCORR_SOUT_SEL,
> > MT8183_MDP_CCORR_SOUT_SEL_AAL0
> > + }, {
> > + MDP_COMP_CCORR0, MDP_COMP_RSZ0,
> > + MT8183_MDP_CCORR_SOUT_SEL,
> > MT8183_MDP_CCORR_SOUT_SEL_RSZ0
> > + }, {
> > + MDP_COMP_PATH0_SOUT, MDP_COMP_WROT0,
> > + MT8183_MDP_PATH0_SOUT_SEL,
> > MT8183_MDP_PATH0_SOUT_SEL_WROT0
> > + }, {
> > + MDP_COMP_PATH1_SOUT, MDP_COMP_WDMA,
> > + MT8183_MDP_PATH1_SOUT_SEL,
> > MT8183_MDP_PATH1_SOUT_SEL_WDMA
> > + }
> > +};
> > +
> > +static const unsigned int
> > mmsys_mt8183_mdp_isp_ctrl_table[ISP_CTRL_MAX] = {
> > + [ISP_CTRL_MMSYS_SW0_RST_B] = MT8183_ISP_CTRL_MMSYS_SW0_RST_B,
> > + [ISP_CTRL_MMSYS_SW1_RST_B] = MT8183_ISP_CTRL_MMSYS_SW1_RST_B,
> > + [ISP_CTRL_MDP_ASYNC_CFG_WD] = MT8183_ISP_CTRL_MDP_ASYNC_CFG_WD,
> > + [ISP_CTRL_MDP_ASYNC_IPU_CFG_WD] =
> > MT8183_ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
> > + [ISP_CTRL_ISP_RELAY_CFG_WD] = MT8183_ISP_CTRL_ISP_RELAY_CFG_WD,
> > + [ISP_CTRL_IPU_RELAY_CFG_WD] = MT8183_ISP_CTRL_IPU_RELAY_CFG_WD,
> > +};
> > +
> > #endif /* __SOC_MEDIATEK_MT8183_MMSYS_H */
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> > b/drivers/soc/mediatek/mtk-mmsys.c
> > index 080660ef11bf..c4b99a99ee1e 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -7,8 +7,10 @@
> > #include <linux/device.h>
> > #include <linux/io.h>
> > #include <linux/of_device.h>
> > +#include <linux/of_address.h>
> > #include <linux/platform_device.h>
> > #include <linux/soc/mediatek/mtk-mmsys.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> >
> > #include "mtk-mmsys.h"
> > #include "mt8167-mmsys.h"
> > @@ -50,11 +52,16 @@ static const struct mtk_mmsys_driver_data
> > mt8183_mmsys_driver_data = {
> > .clk_driver = "clk-mt8183-mm",
> > .routes = mmsys_mt8183_routing_table,
> > .num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
> > + .mdp_routes = mmsys_mt8183_mdp_routing_table,
> > + .mdp_num_routes = ARRAY_SIZE(mmsys_mt8183_mdp_routing_table),
> > + .mdp_isp_ctrl = mmsys_mt8183_mdp_isp_ctrl_table,
> > };
> >
> > struct mtk_mmsys {
> > void __iomem *regs;
> > const struct mtk_mmsys_driver_data *data;
> > + phys_addr_t addr;
> > + u8 subsys_id;
> > };
> >
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > @@ -91,12 +98,160 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > }
> > EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
> >
> > +void mtk_mmsys_mdp_connect(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id cur,
> > + enum mtk_mdp_comp_id next)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_routes *routes = mmsys->data-
> > >mdp_routes;
> > + int i;
> > +
> > + WARN_ON(!routes);
> > + WARN_ON(mmsys->subsys_id == 0);
> > + for (i = 0; i < mmsys->data->mdp_num_routes; i++)
> > + if (cur == routes[i].from_comp && next ==
> > routes[i].to_comp)
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > + mmsys->addr +
> > routes[i].addr,
> > + routes[i].val, 0xFFFFFFFF);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_connect);
Hi Matthias,
Thank you for your suggestion.
Does this mean that we should use regmap to cover the various uses of
MDP and DRM instead of adding new independent interfaces like the
current one?
If so, I will make corresponding changes in the next version with DRM
owner.
>
> I wonder if we are going the wrong path with mmsys. It seems to me
> that we are
> adding random export symbols. I suppose the don't want to use
> syscon/regmap
> because we want to define the routing tables in the mmsys driver, as
> they are
> part of the mmsys HW, correct?
>
> Regards,
> Matthias
>
>
> > +
> > +void mtk_mmsys_mdp_disconnect(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id cur,
> > + enum mtk_mdp_comp_id next)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const struct mtk_mmsys_routes *routes = mmsys->data-
> > >mdp_routes;
> > + int i;
> > +
> > + WARN_ON(mmsys->subsys_id == 0);
> > + for (i = 0; i < mmsys->data->mdp_num_routes; i++)
> > + if (cur == routes[i].from_comp && next ==
> > routes[i].to_comp)
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > + mmsys->addr +
> > routes[i].addr,
> > + 0, 0xFFFFFFFF);
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_disconnect);
> > +
> > +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> > + u32 reg;
> > +
> > + WARN_ON(mmsys->subsys_id == 0);
> > + /* Direct link */
> > + if (id == MDP_COMP_CAMIN) {
> > + /* Reset MDP_DL_ASYNC_TX */
> > + /* Bit 3: MDP_DL_ASYNC_TX / MDP_RELAY */
> > + if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 0x0, 0x00000008);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 1 << 3, 0x00000008);
> > + }
> > +
> > + /* Reset MDP_DL_ASYNC_RX */
> > + /* Bit 10: MDP_DL_ASYNC_RX */
> > + if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 0x0, 0x00000400);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 1 << 10, 0x00000400);
> > + }
> > +
> > + /* Enable sof mode */
> > + if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 0 << 31, 0x80000000);
> > + }
> > + }
> > +
> > + if (id == MDP_COMP_CAMIN2) {
> > + /* Reset MDP_DL_ASYNC2_TX */
> > + /* Bit 4: MDP_DL_ASYNC2_TX / MDP_RELAY2 */
> > + if (isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_MMSYS_SW0_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 0x0, 0x00000010);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 1 << 4, 0x00000010);
> > + }
> > +
> > + /* Reset MDP_DL_ASYNC2_RX */
> > + /* Bit 11: MDP_DL_ASYNC2_RX */
> > + if (isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_MMSYS_SW1_RST_B];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 0x0, 0x00000800);
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 1 << 11, 0x00000800);
> > + }
> > +
> > + /* Enable sof mode */
> > + if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + 0 << 31, 0x80000000);
> > + }
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_isp_ctrl);
> > +
> > +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id, u32 camin_w, u32
> > camin_h)
> > +{
> > + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> > + const unsigned int *isp_ctrl = mmsys->data->mdp_isp_ctrl;
> > + u32 reg;
> > +
> > + WARN_ON(mmsys->subsys_id == 0);
> > + /* Config for direct link */
> > + if (id == MDP_COMP_CAMIN) {
> > + if (isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_MDP_ASYNC_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > +
> > + if (isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_ISP_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + }
> > + if (id == MDP_COMP_CAMIN2) {
> > + if (isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD]) {
> > + reg = mmsys->addr +
> > + isp_ctrl[ISP_CTRL_MDP_ASYNC_IPU_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + if (isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD]) {
> > + reg = mmsys->addr +
> > isp_ctrl[ISP_CTRL_IPU_RELAY_CFG_WD];
> > + cmdq_pkt_write_mask(cmd->pkt, mmsys->subsys_id,
> > reg,
> > + (camin_h << 16) + camin_w,
> > + 0x3FFF3FFF);
> > + }
> > + }
> > +}
> > +EXPORT_SYMBOL_GPL(mtk_mmsys_mdp_camin_ctrl);
> > +
> > static int mtk_mmsys_probe(struct platform_device *pdev)
> > {
> > struct device *dev = &pdev->dev;
> > struct platform_device *clks;
> > struct platform_device *drm;
> > struct mtk_mmsys *mmsys;
> > + struct resource res;
> > + struct cmdq_client_reg cmdq_reg;
> > int ret;
> >
> > mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> > @@ -110,6 +265,15 @@ static int mtk_mmsys_probe(struct
> > platform_device *pdev)
> > return ret;
> > }
> >
> > + if (of_address_to_resource(dev->of_node, 0, &res) < 0)
> > + mmsys->addr = 0L;
> > + else
> > + mmsys->addr = res.start;
> > +
> > + if (cmdq_dev_get_client_reg(dev, &cmdq_reg, 0) != 0)
> > + dev_info(dev, "cmdq subsys id has not been set\n");
> > + mmsys->subsys_id = cmdq_reg.subsys;
> > +
> > mmsys->data = of_device_get_match_data(&pdev->dev);
> > platform_set_drvdata(pdev, mmsys);
> >
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.h
> > b/drivers/soc/mediatek/mtk-mmsys.h
> > index a760a34e6eca..025d4bc9c8cc 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.h
> > +++ b/drivers/soc/mediatek/mtk-mmsys.h
> > @@ -74,9 +74,12 @@ struct mtk_mmsys_routes {
> > };
> >
> > struct mtk_mmsys_driver_data {
> > - const char *clk_driver;
> > - const struct mtk_mmsys_routes *routes;
> > - const unsigned int num_routes;
> > + const char *clk_driver;
> > + const struct mtk_mmsys_routes *routes;
> > + const unsigned int num_routes;
> > + const struct mtk_mmsys_routes *mdp_routes;
> > + const unsigned int mdp_num_routes;
> > + const unsigned int *mdp_isp_ctrl;
>
> Style changes in seperate patch please.
>
> > };
> >
> > /*
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> > b/include/linux/soc/mediatek/mtk-mmsys.h
> > index 2228bf6133da..4eb48d073d2a 100644
> > --- a/include/linux/soc/mediatek/mtk-mmsys.h
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -7,8 +7,14 @@
> > #define __MTK_MMSYS_H
> >
> > enum mtk_ddp_comp_id;
> > +enum mtk_mdp_comp_id;
> > struct device;
> >
> > +struct mmsys_cmdq_cmd {
> > + struct cmdq_pkt *pkt;
> > + s32 *event;
> > +};
> > +
> > enum mtk_ddp_comp_id {
> > DDP_COMPONENT_AAL0,
> > DDP_COMPONENT_AAL1,
> > @@ -42,6 +48,64 @@ enum mtk_ddp_comp_id {
> > DDP_COMPONENT_ID_MAX,
> > };
> >
> > +enum mtk_mdp_comp_id {
> > + MDP_COMP_NONE = -1, /* Invalid engine */
> > +
> > + /* ISP */
> > + MDP_COMP_WPEI = 0,
> > + MDP_COMP_WPEO, /* 1 */
> > + MDP_COMP_WPEI2, /* 2 */
> > + MDP_COMP_WPEO2, /* 3 */
> > + MDP_COMP_ISP_IMGI, /* 4 */
> > + MDP_COMP_ISP_IMGO, /* 5 */
> > + MDP_COMP_ISP_IMG2O, /* 6 */
> > +
> > + /* IPU */
> > + MDP_COMP_IPUI, /* 7 */
> > + MDP_COMP_IPUO, /* 8 */
> > +
> > + /* MDP */
> > + MDP_COMP_CAMIN, /* 9 */
> > + MDP_COMP_CAMIN2, /* 10 */
> > + MDP_COMP_RDMA0, /* 11 */
> > + MDP_COMP_AAL0, /* 12 */
> > + MDP_COMP_CCORR0, /* 13 */
> > + MDP_COMP_RSZ0, /* 14 */
> > + MDP_COMP_RSZ1, /* 15 */
> > + MDP_COMP_TDSHP0, /* 16 */
> > + MDP_COMP_COLOR0, /* 17 */
> > + MDP_COMP_PATH0_SOUT, /* 18 */
> > + MDP_COMP_PATH1_SOUT, /* 19 */
> > + MDP_COMP_WROT0, /* 20 */
> > + MDP_COMP_WDMA, /* 21 */
> > +
> > + /* Dummy Engine */
> > + MDP_COMP_RDMA1, /* 22 */
> > + MDP_COMP_RSZ2, /* 23 */
> > + MDP_COMP_TDSHP1, /* 24 */
> > + MDP_COMP_WROT1, /* 25 */
> > +
> > + MDP_MAX_COMP_COUNT /* ALWAYS keep at the end */
> > +};
> > +
> > +enum mtk_mdp_pipe_id {
> > + MDP_PIPE_RDMA0,
> > + MDP_PIPE_IMGI,
> > + MDP_PIPE_WPEI,
> > + MDP_PIPE_WPEI2,
> > + MDP_PIPE_MAX
> > +};
> > +
> > +enum mtk_isp_ctrl {
> > + ISP_CTRL_MMSYS_SW0_RST_B,
> > + ISP_CTRL_MMSYS_SW1_RST_B,
> > + ISP_CTRL_MDP_ASYNC_CFG_WD,
> > + ISP_CTRL_MDP_ASYNC_IPU_CFG_WD,
> > + ISP_CTRL_ISP_RELAY_CFG_WD,
> > + ISP_CTRL_IPU_RELAY_CFG_WD,
> > + ISP_CTRL_MAX
> > +};
> > +
> > void mtk_mmsys_ddp_connect(struct device *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> > @@ -50,4 +114,21 @@ void mtk_mmsys_ddp_disconnect(struct device
> > *dev,
> > enum mtk_ddp_comp_id cur,
> > enum mtk_ddp_comp_id next);
> >
> > +void mtk_mmsys_mdp_connect(struct device *dev,
> > + struct mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id cur,
> > + enum mtk_mdp_comp_id next);
> > +
> > +void mtk_mmsys_mdp_disconnect(struct device *dev,
> > + struct mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id cur,
> > + enum mtk_mdp_comp_id next);
> > +
> > +void mtk_mmsys_mdp_isp_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id);
> > +
> > +void mtk_mmsys_mdp_camin_ctrl(struct device *dev, struct
> > mmsys_cmdq_cmd *cmd,
> > + enum mtk_mdp_comp_id id,
> > + u32 camin_w, u32 camin_h);
> > +
> > #endif /* __MTK_MMSYS_H */
> >
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^ permalink raw reply [flat|nested] 22+ messages in thread
end of thread, other threads:[~2021-10-15 12:24 UTC | newest]
Thread overview: 22+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-08-24 10:00 [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Moudy Ho
2021-08-24 10:00 ` [PATCH v7 1/5] soc: mediatek: mutex: add support for MDP Moudy Ho
2021-09-07 11:52 ` Matthias Brugger
2021-09-17 1:23 ` moudy ho
2021-10-13 13:29 ` AngeloGioacchino Del Regno
2021-08-24 10:00 ` [PATCH v7 2/5] soc: mediatek: mmsys: Add " Moudy Ho
2021-10-14 15:24 ` Matthias Brugger
2021-10-15 12:22 ` moudy ho
2021-08-24 10:00 ` [PATCH v7 3/5] dt-binding: mt8183: Add Mediatek MDP3 dt-bindings Moudy Ho
2021-08-24 18:02 ` Rob Herring
2021-08-30 7:58 ` moudy ho
2021-08-30 15:05 ` Rob Herring
2021-09-01 8:14 ` moudy ho
2021-09-01 10:16 ` Chen-Yu Tsai
2021-09-03 7:15 ` moudy ho
2021-09-02 23:32 ` Chun-Kuang Hu
2021-09-07 0:11 ` Chun-Kuang Hu
2021-09-10 2:29 ` moudy ho
2021-08-24 10:00 ` [PATCH v7 4/5] dts: arm64: mt8183: Add Mediatek MDP3 nodes Moudy Ho
[not found] ` <20210824100027.25989-6-moudy.ho@mediatek.com>
2021-09-03 9:48 ` [PATCH v7 5/5] media: platform: mtk-mdp3: Add Mediatek MDP3 driver Hans Verkuil
2021-09-03 10:01 ` [PATCH v7 0/5] media: mediatek: support mdp3 on mt8183 platform Hans Verkuil
2021-10-14 8:43 ` moudy ho
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