* [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
[not found] <CGME20180307164708epcas1p27e6599e85617f559c5c4c8eb92a70a47@epcas1p2.samsung.com>
@ 2018-03-07 16:46 ` Sylwester Nawrocki
[not found] ` <CGME20180307164733epcas1p3695c022315be8d2839ac9e88016e3a76@epcas1p3.samsung.com>
2018-03-08 2:25 ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Chanwoo Choi
0 siblings, 2 replies; 6+ messages in thread
From: Sylwester Nawrocki @ 2018-03-07 16:46 UTC (permalink / raw)
To: linux-arm-kernel
This allows changing the EPLL output frequency through the audio subsystem
clock tree leaf clocks. This change is needed to support audio on the HDMI
interface on Peach-Pi(t) Chromebook.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 8c050ff63536..1f204ba37f0f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
mout_group5_5800_p, SRC_TOP7, 16, 2),
- MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
+ MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
+ CLK_SET_RATE_PARENT, 0),
MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
};
--
2.14.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table
[not found] ` <CGME20180307164733epcas1p3695c022315be8d2839ac9e88016e3a76@epcas1p3.samsung.com>
@ 2018-03-07 16:46 ` Sylwester Nawrocki
2018-03-08 1:55 ` Chanwoo Choi
0 siblings, 1 reply; 6+ messages in thread
From: Sylwester Nawrocki @ 2018-03-07 16:46 UTC (permalink / raw)
To: linux-arm-kernel
Adding these EPLL output frequency entries allows to support all required
audio sample rates on the CODEC and the HDMI interface on Peach-Pit
Chromebook.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 1f204ba37f0f..f2607cb97a97 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
+ PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
+ PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
+ PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
};
--
2.14.2
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table
2018-03-07 16:46 ` [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table Sylwester Nawrocki
@ 2018-03-08 1:55 ` Chanwoo Choi
2018-03-12 10:31 ` Sylwester Nawrocki
0 siblings, 1 reply; 6+ messages in thread
From: Chanwoo Choi @ 2018-03-08 1:55 UTC (permalink / raw)
To: linux-arm-kernel
On 2018? 03? 08? 01:46, Sylwester Nawrocki wrote:
> Adding these EPLL output frequency entries allows to support all required
> audio sample rates on the CODEC and the HDMI interface on Peach-Pit
> Chromebook.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 1f204ba37f0f..f2607cb97a97 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
> PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
> PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
> PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
> + PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
> + PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
> PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
> PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
> + PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
> PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
> };
>
>
Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
2018-03-07 16:46 ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Sylwester Nawrocki
[not found] ` <CGME20180307164733epcas1p3695c022315be8d2839ac9e88016e3a76@epcas1p3.samsung.com>
@ 2018-03-08 2:25 ` Chanwoo Choi
2018-03-12 10:29 ` Sylwester Nawrocki
1 sibling, 1 reply; 6+ messages in thread
From: Chanwoo Choi @ 2018-03-08 2:25 UTC (permalink / raw)
To: linux-arm-kernel
Hi Sylwester,
On 2018? 03? 08? 01:46, Sylwester Nawrocki wrote:
> This allows changing the EPLL output frequency through the audio subsystem
> clock tree leaf clocks. This change is needed to support audio on the HDMI
> interface on Peach-Pi(t) Chromebook.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 8c050ff63536..1f204ba37f0f 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>
> MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
> mout_group5_5800_p, SRC_TOP7, 16, 2),
> - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
> + MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
> + CLK_SET_RATE_PARENT, 0),
>
> MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
> };
>
Looks good to me.
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
--
Best Regards,
Chanwoo Choi
Samsung Electronics
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk
2018-03-08 2:25 ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Chanwoo Choi
@ 2018-03-12 10:29 ` Sylwester Nawrocki
0 siblings, 0 replies; 6+ messages in thread
From: Sylwester Nawrocki @ 2018-03-12 10:29 UTC (permalink / raw)
To: linux-arm-kernel
On 03/08/2018 03:25 AM, Chanwoo Choi wrote:
> On 2018? 03? 08? 01:46, Sylwester Nawrocki wrote:
>> This allows changing the EPLL output frequency through the audio subsystem
>> clock tree leaf clocks. This change is needed to support audio on the HDMI
>> interface on Peach-Pi(t) Chromebook.
>>
>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> ---
>> drivers/clk/samsung/clk-exynos5420.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 8c050ff63536..1f204ba37f0f 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -621,7 +621,8 @@ static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
>>
>> MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
>> mout_group5_5800_p, SRC_TOP7, 16, 2),
>> - MUX(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2),
>> + MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
>> + CLK_SET_RATE_PARENT, 0),
>>
>> MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
>> };
>>
> Looks good to me.
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks for your review, patch applied to the clk/samsung tree.
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table
2018-03-08 1:55 ` Chanwoo Choi
@ 2018-03-12 10:31 ` Sylwester Nawrocki
0 siblings, 0 replies; 6+ messages in thread
From: Sylwester Nawrocki @ 2018-03-12 10:31 UTC (permalink / raw)
To: linux-arm-kernel
On 03/08/2018 02:55 AM, Chanwoo Choi wrote:
> On 2018? 03? 08? 01:46, Sylwester Nawrocki wrote:
>> Adding these EPLL output frequency entries allows to support all required
>> audio sample rates on the CODEC and the HDMI interface on Peach-Pit
>> Chromebook.
>>
>> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
>> ---
>> drivers/clk/samsung/clk-exynos5420.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 1f204ba37f0f..f2607cb97a97 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -1360,8 +1360,11 @@ static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
>> PLL_36XX_RATE(180633609U, 301, 5, 3, 3671),
>> PLL_36XX_RATE(131072006U, 131, 3, 3, 4719),
>> PLL_36XX_RATE(100000000U, 200, 3, 4, 0),
>> + PLL_36XX_RATE( 73728000U, 98, 2, 4, 19923),
>> + PLL_36XX_RATE( 67737602U, 90, 2, 4, 20762),
>> PLL_36XX_RATE( 65536003U, 131, 3, 4, 4719),
>> PLL_36XX_RATE( 49152000U, 197, 3, 5, -25690),
>> + PLL_36XX_RATE( 45158401U, 90, 3, 4, 20762),
>> PLL_36XX_RATE( 32768001U, 131, 3, 5, 4719),
>> };
>>
>>
> Looks good to me.
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Thanks for your review, patch applied to the clk/samsung tree.
--
Regards,
Sylwester
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-03-12 10:31 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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[not found] <CGME20180307164708epcas1p27e6599e85617f559c5c4c8eb92a70a47@epcas1p2.samsung.com>
2018-03-07 16:46 ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Sylwester Nawrocki
[not found] ` <CGME20180307164733epcas1p3695c022315be8d2839ac9e88016e3a76@epcas1p3.samsung.com>
2018-03-07 16:46 ` [PATCH] clk: samsung: exynos5420: Add more entries to EPLL rate table Sylwester Nawrocki
2018-03-08 1:55 ` Chanwoo Choi
2018-03-12 10:31 ` Sylwester Nawrocki
2018-03-08 2:25 ` [PATCH] clk: samsung: exynos5420: Add CLK_SET_RATE_PARENT flag to mout_mau_epll_clk Chanwoo Choi
2018-03-12 10:29 ` Sylwester Nawrocki
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