Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / Atom feed
* [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing
@ 2020-03-11 16:53 Enric Balletbo i Serra
  2020-03-11 16:53 ` [PATCH v12 1/5] drm/mediatek: Omit warning on probe defers Enric Balletbo i Serra
                   ` (4 more replies)
  0 siblings, 5 replies; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:53 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, James Liao,
	dri-devel, Richard Fontana, Collabora Kernel ML, linux-clk,
	Nicolas Boichat, Weiyi Lu, Krzysztof Kozlowski, wens,
	Allison Randal, mtk01761, Owen Chen, linux-media, devicetree,
	frank-w, Seiya Wang, sean.wang, Houlong Wei, linux-mediatek,
	hsinyi, Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Fabien Parent,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg

Dear all,

These patches are intended to solve an old standing issue on some
Mediatek devices (mt8173, mt2701 and mt2712 are affected by this issue).

Up to now both drivers, clock and drm are probed with the same device tree
compatible. But only the first driver gets probed, which in effect breaks
graphics on those devices.

The MMSYS (Multimedia subsystem) in Mediatek SoCs has some registers to
control clock gates (which is used in the clk driver) and some registers
to set the routing and enable the differnet blocks of the display
and MDP (Media Data Path) subsystem. On this series the clk driver is
not a pure clock controller but a system controller that can provide
access to the shared registers between the different drivers that need
it (mediatek-drm and mediatek-mdp). Hence the MMSYS clk driver was moved
to drivers/soc/mediatek and is the entry point (parent) which will trigger
the probe of the corresponding mediatek-drm driver.

**IMPORTANT** This series only fixes the issue on mt8173 to make it
simple and as is the only platform I can test. Similar changes should be
applied for mt2701 and mt2712 to have display working.

These patches apply on top of linux-next.

For reference, here are the links to the old discussions:
* v11: https://patchwork.kernel.org/project/linux-mediatek/list/?series=249871
* v10: https://patchwork.kernel.org/project/linux-mediatek/list/?series=248505
* v9: https://patchwork.kernel.org/project/linux-clk/list/?series=247591
* v8: https://patchwork.kernel.org/project/linux-mediatek/list/?series=244891
* v7: https://patchwork.kernel.org/project/linux-mediatek/list/?series=241217
* v6: https://patchwork.kernel.org/project/linux-mediatek/list/?series=213219
* v5: https://patchwork.kernel.org/project/linux-mediatek/list/?series=44063
* v4:
  * https://patchwork.kernel.org/patch/10530871/
  * https://patchwork.kernel.org/patch/10530883/
  * https://patchwork.kernel.org/patch/10530885/
  * https://patchwork.kernel.org/patch/10530911/
  * https://patchwork.kernel.org/patch/10530913/
* v3:
  * https://patchwork.kernel.org/patch/10367857/
  * https://patchwork.kernel.org/patch/10367861/
  * https://patchwork.kernel.org/patch/10367877/
  * https://patchwork.kernel.org/patch/10367875/
  * https://patchwork.kernel.org/patch/10367885/
  * https://patchwork.kernel.org/patch/10367883/
  * https://patchwork.kernel.org/patch/10367889/
  * https://patchwork.kernel.org/patch/10367907/
  * https://patchwork.kernel.org/patch/10367909/
  * https://patchwork.kernel.org/patch/10367905/
* v2: No relevant discussion, see v3
* v1:
  * https://patchwork.kernel.org/patch/10016497/
  * https://patchwork.kernel.org/patch/10016499/
  * https://patchwork.kernel.org/patch/10016505/
  * https://patchwork.kernel.org/patch/10016507/

Best regards,
 Enric

Changes in v12:
- Leave the clocks part in drivers/clk (clk-mt8173-mm)
- Instantiate the clock driver from the mtk-mmsys driver.
- Add default config option to not break anything.
- Removed the Reviewed-by CK tag as changed the organization.

Changes in v10:
- Update the binding documentation for the mmsys system controller.
- Renamed to be generic mtk-mmsys
- Add driver data support to be able to support diferent SoCs
- Select CONFIG_MTK_MMSYS (CK)
- Pass device pointer of mmsys device instead of config regs (CK)
- Match driver data to get display routing.

Changes in v9:
- Move mmsys to drivers/soc/mediatek (CK)
- Introduced a new patch to move routing control into mmsys driver.
- Removed the patch to use regmap as is not needed anymore.
- Do not move the display routing from the drm driver (CK)

Changes in v8:
- Be a builtin_platform_driver like other mediatek mmsys drivers.
- New patch introduced in this series.

Changes in v7:
- Free clk_data->clks as well
- Get rid of private data structure

Enric Balletbo i Serra (3):
  dt-bindings: mediatek: Update mmsys binding to reflect it is a system
    controller
  soc / drm: mediatek: Move routing control to mmsys device
  soc / drm: mediatek: Fix mediatek-drm device probing

Matthias Brugger (2):
  drm/mediatek: Omit warning on probe defers
  clk / soc: mediatek: Move mt8173 MMSYS to platform driver

 .../bindings/arm/mediatek/mediatek,mmsys.txt  |   7 +-
 drivers/clk/mediatek/Kconfig                  |   7 +
 drivers/clk/mediatek/Makefile                 |   1 +
 drivers/clk/mediatek/clk-mt8173-mm.c          | 146 ++++++++
 drivers/clk/mediatek/clk-mt8173.c             | 104 ------
 drivers/gpu/drm/mediatek/Kconfig              |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_color.c     |   5 +-
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c       |   5 +-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   5 +-
 drivers/gpu/drm/mediatek/mtk_dpi.c            |  12 +-
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c       |  19 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c        | 259 +-------------
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h        |   7 -
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        |  45 +--
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   2 +-
 drivers/gpu/drm/mediatek/mtk_dsi.c            |   8 +-
 drivers/gpu/drm/mediatek/mtk_hdmi.c           |   4 +-
 drivers/soc/mediatek/Kconfig                  |   8 +
 drivers/soc/mediatek/Makefile                 |   1 +
 drivers/soc/mediatek/mtk-mmsys.c              | 335 ++++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h        |  20 ++
 21 files changed, 590 insertions(+), 411 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt8173-mm.c
 create mode 100644 drivers/soc/mediatek/mtk-mmsys.c
 create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h

-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH v12 1/5] drm/mediatek: Omit warning on probe defers
  2020-03-11 16:53 [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing Enric Balletbo i Serra
@ 2020-03-11 16:53 ` Enric Balletbo i Serra
  2020-03-11 16:53 ` [PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller Enric Balletbo i Serra
                   ` (3 subsequent siblings)
  4 siblings, 0 replies; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:53 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, dri-devel,
	Richard Fontana, Collabora Kernel ML, linux-clk, Weiyi Lu, wens,
	Allison Randal, mtk01761, linux-media, devicetree, frank-w,
	Seiya Wang, sean.wang, Houlong Wei, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Greg Kroah-Hartman, rdunlap,
	linux-kernel, Daniel Vetter, matthias.bgg

From: Matthias Brugger <mbrugger@suse.com>

It can happen that the mmsys clock drivers aren't probed before the
platform driver gets invoked. The platform driver used to print a warning
that the driver failed to get the clocks. Omit this error on
the defered probe path.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---

Changes in v12: None
Changes in v10: None
Changes in v9: None
Changes in v8: None
Changes in v7: None

 drivers/gpu/drm/mediatek/mtk_disp_color.c |  5 ++++-
 drivers/gpu/drm/mediatek/mtk_disp_ovl.c   |  5 ++++-
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c  |  5 ++++-
 drivers/gpu/drm/mediatek/mtk_dpi.c        | 12 +++++++++---
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c    |  3 ++-
 drivers/gpu/drm/mediatek/mtk_dsi.c        |  8 ++++++--
 drivers/gpu/drm/mediatek/mtk_hdmi.c       |  4 +++-
 7 files changed, 32 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_color.c b/drivers/gpu/drm/mediatek/mtk_disp_color.c
index 6fb0d6983a4a..3ae9c810845b 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_color.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_color.c
@@ -119,7 +119,10 @@ static int mtk_disp_color_probe(struct platform_device *pdev)
 	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
 				&mtk_disp_color_funcs);
 	if (ret) {
-		dev_err(dev, "Failed to initialize component: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to initialize component: %d\n",
+				ret);
+
 		return ret;
 	}
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
index 891d80c73e04..28651bc579bc 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c
@@ -386,7 +386,10 @@ static int mtk_disp_ovl_probe(struct platform_device *pdev)
 	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
 				&mtk_disp_ovl_funcs);
 	if (ret) {
-		dev_err(dev, "Failed to initialize component: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to initialize component: %d\n",
+				ret);
+
 		return ret;
 	}
 
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 0cb848d64206..e04319fedf46 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -294,7 +294,10 @@ static int mtk_disp_rdma_probe(struct platform_device *pdev)
 	ret = mtk_ddp_comp_init(dev, dev->of_node, &priv->ddp_comp, comp_id,
 				&mtk_disp_rdma_funcs);
 	if (ret) {
-		dev_err(dev, "Failed to initialize component: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to initialize component: %d\n",
+				ret);
+
 		return ret;
 	}
 
diff --git a/drivers/gpu/drm/mediatek/mtk_dpi.c b/drivers/gpu/drm/mediatek/mtk_dpi.c
index 01fa8b8d763d..1b219edef541 100644
--- a/drivers/gpu/drm/mediatek/mtk_dpi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dpi.c
@@ -701,21 +701,27 @@ static int mtk_dpi_probe(struct platform_device *pdev)
 	dpi->engine_clk = devm_clk_get(dev, "engine");
 	if (IS_ERR(dpi->engine_clk)) {
 		ret = PTR_ERR(dpi->engine_clk);
-		dev_err(dev, "Failed to get engine clock: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to get engine clock: %d\n", ret);
+
 		return ret;
 	}
 
 	dpi->pixel_clk = devm_clk_get(dev, "pixel");
 	if (IS_ERR(dpi->pixel_clk)) {
 		ret = PTR_ERR(dpi->pixel_clk);
-		dev_err(dev, "Failed to get pixel clock: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to get pixel clock: %d\n", ret);
+
 		return ret;
 	}
 
 	dpi->tvd_clk = devm_clk_get(dev, "pll");
 	if (IS_ERR(dpi->tvd_clk)) {
 		ret = PTR_ERR(dpi->tvd_clk);
-		dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to get tvdpll clock: %d\n", ret);
+
 		return ret;
 	}
 
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 13035c906035..b885f60f474c 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -628,7 +628,8 @@ static int mtk_ddp_probe(struct platform_device *pdev)
 	if (!ddp->data->no_clk) {
 		ddp->clk = devm_clk_get(dev, NULL);
 		if (IS_ERR(ddp->clk)) {
-			dev_err(dev, "Failed to get clock\n");
+			if (PTR_ERR(ddp->clk) != -EPROBE_DEFER)
+				dev_err(dev, "Failed to get clock\n");
 			return PTR_ERR(ddp->clk);
 		}
 	}
diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c
index 5fa1073cf26b..a45ed0270531 100644
--- a/drivers/gpu/drm/mediatek/mtk_dsi.c
+++ b/drivers/gpu/drm/mediatek/mtk_dsi.c
@@ -1194,14 +1194,18 @@ static int mtk_dsi_probe(struct platform_device *pdev)
 	dsi->engine_clk = devm_clk_get(dev, "engine");
 	if (IS_ERR(dsi->engine_clk)) {
 		ret = PTR_ERR(dsi->engine_clk);
-		dev_err(dev, "Failed to get engine clock: %d\n", ret);
+
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to get engine clock: %d\n", ret);
 		goto err_unregister_host;
 	}
 
 	dsi->digital_clk = devm_clk_get(dev, "digital");
 	if (IS_ERR(dsi->digital_clk)) {
 		ret = PTR_ERR(dsi->digital_clk);
-		dev_err(dev, "Failed to get digital clock: %d\n", ret);
+
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to get digital clock: %d\n", ret);
 		goto err_unregister_host;
 	}
 
diff --git a/drivers/gpu/drm/mediatek/mtk_hdmi.c b/drivers/gpu/drm/mediatek/mtk_hdmi.c
index 5e4a4dbda443..69c6a146c561 100644
--- a/drivers/gpu/drm/mediatek/mtk_hdmi.c
+++ b/drivers/gpu/drm/mediatek/mtk_hdmi.c
@@ -1451,7 +1451,9 @@ static int mtk_hdmi_dt_parse_pdata(struct mtk_hdmi *hdmi,
 
 	ret = mtk_hdmi_get_all_clk(hdmi, np);
 	if (ret) {
-		dev_err(dev, "Failed to get clocks: %d\n", ret);
+		if (ret != -EPROBE_DEFER)
+			dev_err(dev, "Failed to get clocks: %d\n", ret);
+
 		return ret;
 	}
 
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller
  2020-03-11 16:53 [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing Enric Balletbo i Serra
  2020-03-11 16:53 ` [PATCH v12 1/5] drm/mediatek: Omit warning on probe defers Enric Balletbo i Serra
@ 2020-03-11 16:53 ` Enric Balletbo i Serra
  2020-03-12 15:22   ` Rob Herring
  2020-03-11 16:53 ` [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver Enric Balletbo i Serra
                   ` (2 subsequent siblings)
  4 siblings, 1 reply; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:53 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, dri-devel,
	Richard Fontana, Collabora Kernel ML, linux-clk, Weiyi Lu, wens,
	Allison Randal, mtk01761, linux-media, devicetree, frank-w,
	Seiya Wang, sean.wang, Houlong Wei, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Greg Kroah-Hartman, rdunlap,
	linux-kernel, Daniel Vetter, matthias.bgg

The mmsys system controller is not only a pure clock controller, so
update the binding documentation to reflect that apart from providing
clocks, it also provides routing and miscellaneous control registers.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---

Changes in v12: None
Changes in v10:
- Update the binding documentation for the mmsys system controller.

Changes in v9: None
Changes in v8: None
Changes in v7: None

 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt    | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
index 301eefbe1618..8d6a9d98e7a6 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
@@ -1,7 +1,8 @@
 Mediatek mmsys controller
 ============================
 
-The Mediatek mmsys controller provides various clocks to the system.
+The Mediatek mmsys system controller provides clock control, routing control,
+and miscellaneous control in mmsys partition.
 
 Required Properties:
 
@@ -15,13 +16,13 @@ Required Properties:
 	- "mediatek,mt8183-mmsys", "syscon"
 - #clock-cells: Must be 1
 
-The mmsys controller uses the common clk binding from
+For the clock control, the mmsys controller uses the common clk binding from
 Documentation/devicetree/bindings/clock/clock-bindings.txt
 The available clocks are defined in dt-bindings/clock/mt*-clk.h.
 
 Example:
 
-mmsys: clock-controller@14000000 {
+mmsys: syscon@14000000 {
 	compatible = "mediatek,mt8173-mmsys", "syscon";
 	reg = <0 0x14000000 0 0x1000>;
 	#clock-cells = <1>;
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver
  2020-03-11 16:53 [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing Enric Balletbo i Serra
  2020-03-11 16:53 ` [PATCH v12 1/5] drm/mediatek: Omit warning on probe defers Enric Balletbo i Serra
  2020-03-11 16:53 ` [PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller Enric Balletbo i Serra
@ 2020-03-11 16:53 ` Enric Balletbo i Serra
  2020-03-11 16:58   ` Enric Balletbo i Serra
       [not found]   ` <158474603935.125146.14986079780178656133@swboyd.mtv.corp.google.com>
  2020-03-11 16:53 ` [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device Enric Balletbo i Serra
  2020-03-11 16:53 ` [PATCH v12 5/5] soc / drm: mediatek: Fix mediatek-drm device probing Enric Balletbo i Serra
  4 siblings, 2 replies; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:53 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, James Liao,
	dri-devel, Richard Fontana, Collabora Kernel ML, linux-clk,
	Nicolas Boichat, Weiyi Lu, Krzysztof Kozlowski, wens,
	Allison Randal, mtk01761, Owen Chen, linux-media, devicetree,
	frank-w, Seiya Wang, sean.wang, Houlong Wei, linux-mediatek,
	hsinyi, Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Fabien Parent,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg

From: Matthias Brugger <mbrugger@suse.com>

There is no strong reason for this to use CLK_OF_DECLARE instead of
being a platform driver. Plus, MMSYS provides clocks but also a shared
register space for the mediatek-drm and the mediatek-mdp
driver. So move the MMSYS clocks to a new platform driver and also
create a new MMSYS platform driver in drivers/soc/mediatek that
instantiates the clock driver.

Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---

Changes in v12:
- Leave the clocks part in drivers/clk (clk-mt8173-mm)
- Instantiate the clock driver from the mtk-mmsys driver.
- Add default config option to not break anything.
- Removed the Reviewed-by CK tag as changed the organization.

Changes in v10:
- Renamed to be generic mtk-mmsys
- Add driver data support to be able to support diferent SoCs

Changes in v9:
- Move mmsys to drivers/soc/mediatek (CK)

Changes in v8:
- Be a builtin_platform_driver like other mediatek mmsys drivers.

Changes in v7:
- Free clk_data->clks as well
- Get rid of private data structure

 drivers/clk/mediatek/Kconfig         |   7 ++
 drivers/clk/mediatek/Makefile        |   1 +
 drivers/clk/mediatek/clk-mt8173-mm.c | 146 +++++++++++++++++++++++++++
 drivers/clk/mediatek/clk-mt8173.c    | 104 -------------------
 drivers/soc/mediatek/Kconfig         |   8 ++
 drivers/soc/mediatek/Makefile        |   1 +
 drivers/soc/mediatek/mtk-mmsys.c     |  50 +++++++++
 7 files changed, 213 insertions(+), 104 deletions(-)
 create mode 100644 drivers/clk/mediatek/clk-mt8173-mm.c
 create mode 100644 drivers/soc/mediatek/mtk-mmsys.c

diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
index ea3c70d1307e..9e28db8125cd 100644
--- a/drivers/clk/mediatek/Kconfig
+++ b/drivers/clk/mediatek/Kconfig
@@ -274,6 +274,13 @@ config COMMON_CLK_MT8173
 	---help---
 	  This driver supports MediaTek MT8173 clocks.
 
+config COMMON_CLK_MT8173_MMSYS
+	bool "Clock driver for MediaTek MT8173 mmsys"
+	depends on COMMON_CLK_MT8173
+	default COMMON_CLK_MT8173
+	help
+	  This driver supports MediaTek MT8173 mmsys clocks.
+
 config COMMON_CLK_MT8183
 	bool "Clock driver for MediaTek MT8183"
 	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index 8cdb76a5cd71..bb0536942075 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
 obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
 obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
 obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
+obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
 obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
 obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
 obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c
new file mode 100644
index 000000000000..36fa20be77b6
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt8173-mm.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include "clk-gate.h"
+#include "clk-mtk.h"
+
+#include <dt-bindings/clock/mt8173-clk.h>
+
+static const struct mtk_gate_regs mm0_cg_regs = {
+	.set_ofs = 0x0104,
+	.clr_ofs = 0x0108,
+	.sta_ofs = 0x0100,
+};
+
+static const struct mtk_gate_regs mm1_cg_regs = {
+	.set_ofs = 0x0114,
+	.clr_ofs = 0x0118,
+	.sta_ofs = 0x0110,
+};
+
+#define GATE_MM0(_id, _name, _parent, _shift) {			\
+		.id = _id,					\
+		.name = _name,					\
+		.parent_name = _parent,				\
+		.regs = &mm0_cg_regs,				\
+		.shift = _shift,				\
+		.ops = &mtk_clk_gate_ops_setclr,		\
+	}
+
+#define GATE_MM1(_id, _name, _parent, _shift) {			\
+		.id = _id,					\
+		.name = _name,					\
+		.parent_name = _parent,				\
+		.regs = &mm1_cg_regs,				\
+		.shift = _shift,				\
+		.ops = &mtk_clk_gate_ops_setclr,		\
+	}
+
+static const struct mtk_gate mt8173_mm_clks[] = {
+	/* MM0 */
+	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
+	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
+	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
+	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
+	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
+	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
+	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
+	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
+	GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
+	GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
+	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
+	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
+	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
+	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
+	GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
+	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
+	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
+	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
+	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
+	GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
+	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
+	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
+	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
+	GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
+	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
+	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
+	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
+	GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
+	GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
+	GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
+	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
+	/* MM1 */
+	GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
+	GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
+	GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
+	GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
+	GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
+	GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
+	GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
+	GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
+	GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
+	GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
+	GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
+	GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
+	GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
+	GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
+	GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
+	GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
+	GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
+	GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
+	GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
+	GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
+	GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
+};
+
+struct clk_mt8173_mm_driver_data {
+	const struct mtk_gate *gates_clk;
+	int gates_num;
+};
+
+static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data = {
+	.gates_clk = mt8173_mm_clks,
+	.gates_num = ARRAY_SIZE(mt8173_mm_clks),
+};
+
+static int clk_mt8173_mm_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = dev->parent->of_node;
+	const struct clk_mt8173_mm_driver_data *data;
+	struct clk_onecell_data *clk_data;
+	int ret;
+
+	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+	if (!clk_data)
+		return -ENOMEM;
+
+	data = &mt8173_mmsys_driver_data;
+
+	ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
+				     clk_data);
+	if (ret)
+		return ret;
+
+	ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static struct platform_driver clk_mt8173_mm_drv = {
+	.driver = {
+		.name = "clk-mt8173-mm",
+	},
+	.probe = clk_mt8173_mm_probe,
+};
+
+builtin_platform_driver(clk_mt8173_mm_drv);
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 537a7f49b0f7..8f898ac476c0 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -753,93 +753,6 @@ static const struct mtk_gate img_clks[] __initconst = {
 	GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
 };
 
-static const struct mtk_gate_regs mm0_cg_regs __initconst = {
-	.set_ofs = 0x0104,
-	.clr_ofs = 0x0108,
-	.sta_ofs = 0x0100,
-};
-
-static const struct mtk_gate_regs mm1_cg_regs __initconst = {
-	.set_ofs = 0x0114,
-	.clr_ofs = 0x0118,
-	.sta_ofs = 0x0110,
-};
-
-#define GATE_MM0(_id, _name, _parent, _shift) {			\
-		.id = _id,					\
-		.name = _name,					\
-		.parent_name = _parent,				\
-		.regs = &mm0_cg_regs,				\
-		.shift = _shift,				\
-		.ops = &mtk_clk_gate_ops_setclr,		\
-	}
-
-#define GATE_MM1(_id, _name, _parent, _shift) {			\
-		.id = _id,					\
-		.name = _name,					\
-		.parent_name = _parent,				\
-		.regs = &mm1_cg_regs,				\
-		.shift = _shift,				\
-		.ops = &mtk_clk_gate_ops_setclr,		\
-	}
-
-static const struct mtk_gate mm_clks[] __initconst = {
-	/* MM0 */
-	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
-	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
-	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
-	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
-	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
-	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
-	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
-	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
-	GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
-	GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
-	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
-	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
-	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
-	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
-	GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
-	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
-	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
-	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
-	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
-	GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
-	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
-	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
-	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
-	GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
-	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
-	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
-	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
-	GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
-	GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
-	GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
-	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
-	/* MM1 */
-	GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
-	GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
-	GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
-	GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
-	GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
-	GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
-	GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
-	GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
-	GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
-	GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
-	GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
-	GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
-	GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
-	GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
-	GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
-	GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
-	GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
-	GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
-	GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
-	GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
-	GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
-};
-
 static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
 	.set_ofs = 0x0000,
 	.clr_ofs = 0x0004,
@@ -1144,23 +1057,6 @@ static void __init mtk_imgsys_init(struct device_node *node)
 }
 CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
 
-static void __init mtk_mmsys_init(struct device_node *node)
-{
-	struct clk_onecell_data *clk_data;
-	int r;
-
-	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
-
-	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
-						clk_data);
-
-	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
-	if (r)
-		pr_err("%s(): could not register clock provider: %d\n",
-			__func__, r);
-}
-CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
-
 static void __init mtk_vdecsys_init(struct device_node *node)
 {
 	struct clk_onecell_data *clk_data;
diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
index 2114b563478c..e84513318725 100644
--- a/drivers/soc/mediatek/Kconfig
+++ b/drivers/soc/mediatek/Kconfig
@@ -44,4 +44,12 @@ config MTK_SCPSYS
 	  Say yes here to add support for the MediaTek SCPSYS power domain
 	  driver.
 
+config MTK_MMSYS
+	bool "MediaTek MMSYS Support"
+	depends on COMMON_CLK_MT8173_MMSYS
+	default COMMON_CLK_MT8173_MMSYS
+	help
+	  Say yes here to add support for the MediaTek Multimedia
+	  Subsystem (MMSYS).
+
 endmenu
diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
index b01733074ad6..01f9f873634a 100644
--- a/drivers/soc/mediatek/Makefile
+++ b/drivers/soc/mediatek/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
 obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
 obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
 obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
+obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
new file mode 100644
index 000000000000..dbdfedd302fa
--- /dev/null
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2014 MediaTek Inc.
+ * Author: James Liao <jamesjj.liao@mediatek.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+struct mtk_mmsys_driver_data {
+	const char *clk_driver;
+};
+
+static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
+	.clk_driver = "clk-mt8173-mm",
+};
+
+static int mtk_mmsys_probe(struct platform_device *pdev)
+{
+	const struct mtk_mmsys_driver_data *data;
+	struct platform_device *clks;
+
+	data = of_device_get_match_data(&pdev->dev);
+
+	clks = platform_device_register_data(&pdev->dev, data->clk_driver,
+					     PLATFORM_DEVID_AUTO, NULL, 0);
+	if (IS_ERR(clks))
+		return PTR_ERR(clks);
+
+	return 0;
+}
+
+static const struct of_device_id of_match_mtk_mmsys[] = {
+	{
+		.compatible = "mediatek,mt8173-mmsys",
+		.data = &mt8173_mmsys_driver_data,
+	},
+	{ }
+};
+
+static struct platform_driver mtk_mmsys_drv = {
+	.driver = {
+		.name = "mtk-mmsys",
+		.of_match_table = of_match_mtk_mmsys,
+	},
+	.probe = mtk_mmsys_probe,
+};
+
+builtin_platform_driver(mtk_mmsys_drv);
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-11 16:53 [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing Enric Balletbo i Serra
                   ` (2 preceding siblings ...)
  2020-03-11 16:53 ` [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver Enric Balletbo i Serra
@ 2020-03-11 16:53 ` Enric Balletbo i Serra
  2020-03-25 16:16   ` Matthias Brugger
  2020-03-11 16:53 ` [PATCH v12 5/5] soc / drm: mediatek: Fix mediatek-drm device probing Enric Balletbo i Serra
  4 siblings, 1 reply; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:53 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, dri-devel,
	Richard Fontana, Collabora Kernel ML, linux-clk, Weiyi Lu, wens,
	Allison Randal, mtk01761, linux-media, devicetree, frank-w,
	Seiya Wang, sean.wang, Houlong Wei, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Greg Kroah-Hartman, rdunlap,
	linux-kernel, Daniel Vetter, matthias.bgg

Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
Those functions will allow DRM driver and others to control the data
path routing.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
---

Changes in v12: None
Changes in v10:
- Select CONFIG_MTK_MMSYS (CK)
- Pass device pointer of mmsys device instead of config regs (CK)

Changes in v9:
- Introduced a new patch to move routing control into mmsys driver.
- Removed the patch to use regmap as is not needed anymore.

Changes in v8: None
Changes in v7: None

 drivers/gpu/drm/mediatek/Kconfig        |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
 drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
 drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
 drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
 drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
 include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
 8 files changed, 316 insertions(+), 282 deletions(-)
 create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h

diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
index fa5ffc4fe823..c420f5a3d33b 100644
--- a/drivers/gpu/drm/mediatek/Kconfig
+++ b/drivers/gpu/drm/mediatek/Kconfig
@@ -11,6 +11,7 @@ config DRM_MEDIATEK
 	select DRM_MIPI_DSI
 	select DRM_PANEL
 	select MEMORY
+	select MTK_MMSYS
 	select MTK_SMI
 	select VIDEOMODE_HELPERS
 	help
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
index 0e05683d7b53..579a5a5d4472 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
@@ -6,6 +6,7 @@
 #include <linux/clk.h>
 #include <linux/pm_runtime.h>
 #include <linux/soc/mediatek/mtk-cmdq.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
 
 #include <asm/barrier.h>
 #include <soc/mediatek/smi.h>
@@ -28,7 +29,7 @@
  * @enabled: records whether crtc_enable succeeded
  * @planes: array of 4 drm_plane structures, one for each overlay plane
  * @pending_planes: whether any plane has pending changes to be applied
- * @config_regs: memory mapped mmsys configuration register space
+ * @mmsys_dev: pointer to the mmsys device for configuration registers
  * @mutex: handle to one of the ten disp_mutex streams
  * @ddp_comp_nr: number of components in ddp_comp
  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
@@ -50,7 +51,7 @@ struct mtk_drm_crtc {
 	u32				cmdq_event;
 #endif
 
-	void __iomem			*config_regs;
+	struct device			*mmsys_dev;
 	struct mtk_disp_mutex		*mutex;
 	unsigned int			ddp_comp_nr;
 	struct mtk_ddp_comp		**ddp_comp;
@@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
 	}
 
 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
-		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
-					 mtk_crtc->ddp_comp[i]->id,
-					 mtk_crtc->ddp_comp[i + 1]->id);
+		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
+				      mtk_crtc->ddp_comp[i]->id,
+				      mtk_crtc->ddp_comp[i + 1]->id);
 		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
 					mtk_crtc->ddp_comp[i]->id);
 	}
@@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
 					   mtk_crtc->ddp_comp[i]->id);
 	mtk_disp_mutex_disable(mtk_crtc->mutex);
 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
-		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
-					      mtk_crtc->ddp_comp[i]->id,
-					      mtk_crtc->ddp_comp[i + 1]->id);
+		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
+					 mtk_crtc->ddp_comp[i]->id,
+					 mtk_crtc->ddp_comp[i + 1]->id);
 		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
 					   mtk_crtc->ddp_comp[i]->id);
 	}
@@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
 	if (!mtk_crtc)
 		return -ENOMEM;
 
-	mtk_crtc->config_regs = priv->config_regs;
+	mtk_crtc->mmsys_dev = priv->mmsys_dev;
 	mtk_crtc->ddp_comp_nr = path_len;
 	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
 						sizeof(*mtk_crtc->ddp_comp),
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index b885f60f474c..014c1bbe1df2 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -13,26 +13,6 @@
 #include "mtk_drm_ddp.h"
 #include "mtk_drm_ddp_comp.h"
 
-#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
-#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
-#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
-#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
-#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
-#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
-#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
-#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
-#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
-#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
-#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
-#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
-#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
-#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
-
-#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
-#define DISP_REG_CONFIG_OUT_SEL			0x04c
-#define DISP_REG_CONFIG_DSI_SEL			0x050
-#define DISP_REG_CONFIG_DPI_SEL			0x064
-
 #define MT2701_DISP_MUTEX0_MOD0			0x2c
 #define MT2701_DISP_MUTEX0_SOF0			0x30
 
@@ -94,48 +74,6 @@
 #define MUTEX_SOF_DSI2			5
 #define MUTEX_SOF_DSI3			6
 
-#define OVL0_MOUT_EN_COLOR0		0x1
-#define OD_MOUT_EN_RDMA0		0x1
-#define OD1_MOUT_EN_RDMA1		BIT(16)
-#define UFOE_MOUT_EN_DSI0		0x1
-#define COLOR0_SEL_IN_OVL0		0x1
-#define OVL1_MOUT_EN_COLOR1		0x1
-#define GAMMA_MOUT_EN_RDMA1		0x1
-#define RDMA0_SOUT_DPI0			0x2
-#define RDMA0_SOUT_DPI1			0x3
-#define RDMA0_SOUT_DSI1			0x1
-#define RDMA0_SOUT_DSI2			0x4
-#define RDMA0_SOUT_DSI3			0x5
-#define RDMA1_SOUT_DPI0			0x2
-#define RDMA1_SOUT_DPI1			0x3
-#define RDMA1_SOUT_DSI1			0x1
-#define RDMA1_SOUT_DSI2			0x4
-#define RDMA1_SOUT_DSI3			0x5
-#define RDMA2_SOUT_DPI0			0x2
-#define RDMA2_SOUT_DPI1			0x3
-#define RDMA2_SOUT_DSI1			0x1
-#define RDMA2_SOUT_DSI2			0x4
-#define RDMA2_SOUT_DSI3			0x5
-#define DPI0_SEL_IN_RDMA1		0x1
-#define DPI0_SEL_IN_RDMA2		0x3
-#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
-#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
-#define DSI0_SEL_IN_RDMA1		0x1
-#define DSI0_SEL_IN_RDMA2		0x4
-#define DSI1_SEL_IN_RDMA1		0x1
-#define DSI1_SEL_IN_RDMA2		0x4
-#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
-#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
-#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
-#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
-#define COLOR1_SEL_IN_OVL1		0x1
-
-#define OVL_MOUT_EN_RDMA		0x1
-#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
-#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
-#define DSI_SEL_IN_BLS			0x0
-#define DPI_SEL_IN_BLS			0x0
-#define DSI_SEL_IN_RDMA			0x1
 
 struct mtk_disp_mutex {
 	int id;
@@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
 	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
 };
 
-static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
-				    enum mtk_ddp_comp_id next,
-				    unsigned int *addr)
-{
-	unsigned int value;
-
-	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
-		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
-		value = OVL0_MOUT_EN_COLOR0;
-	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
-		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
-		value = OVL_MOUT_EN_RDMA;
-	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
-		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
-		value = OD_MOUT_EN_RDMA0;
-	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
-		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
-		value = UFOE_MOUT_EN_DSI0;
-	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
-		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
-		value = OVL1_MOUT_EN_COLOR1;
-	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
-		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
-		value = GAMMA_MOUT_EN_RDMA1;
-	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
-		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
-		value = OD1_MOUT_EN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
-		value = RDMA0_SOUT_DPI0;
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
-		value = RDMA0_SOUT_DPI1;
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
-		value = RDMA0_SOUT_DSI1;
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
-		value = RDMA0_SOUT_DSI2;
-	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
-		value = RDMA0_SOUT_DSI3;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
-		value = RDMA1_SOUT_DSI1;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
-		value = RDMA1_SOUT_DSI2;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
-		value = RDMA1_SOUT_DSI3;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
-		value = RDMA1_SOUT_DPI0;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
-		value = RDMA1_SOUT_DPI1;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
-		value = RDMA2_SOUT_DPI0;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
-		value = RDMA2_SOUT_DPI1;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
-		value = RDMA2_SOUT_DSI1;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
-		value = RDMA2_SOUT_DSI2;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
-		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
-		value = RDMA2_SOUT_DSI3;
-	} else {
-		value = 0;
-	}
-
-	return value;
-}
-
-static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
-				   enum mtk_ddp_comp_id next,
-				   unsigned int *addr)
-{
-	unsigned int value;
-
-	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
-		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
-		value = COLOR0_SEL_IN_OVL0;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
-		value = DPI0_SEL_IN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
-		value = DPI1_SEL_IN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
-		value = DSI0_SEL_IN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
-		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
-		value = DSI1_SEL_IN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
-		value = DSI2_SEL_IN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
-		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
-		value = DSI3_SEL_IN_RDMA1;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
-		value = DPI0_SEL_IN_RDMA2;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
-		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
-		value = DPI1_SEL_IN_RDMA2;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
-		value = DSI0_SEL_IN_RDMA2;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
-		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
-		value = DSI1_SEL_IN_RDMA2;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
-		value = DSI2_SEL_IN_RDMA2;
-	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
-		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
-		value = DSI3_SEL_IN_RDMA2;
-	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
-		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
-		value = COLOR1_SEL_IN_OVL1;
-	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
-		*addr = DISP_REG_CONFIG_DSI_SEL;
-		value = DSI_SEL_IN_BLS;
-	} else {
-		value = 0;
-	}
-
-	return value;
-}
-
-static void mtk_ddp_sout_sel(void __iomem *config_regs,
-			     enum mtk_ddp_comp_id cur,
-			     enum mtk_ddp_comp_id next)
-{
-	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
-		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
-			       config_regs + DISP_REG_CONFIG_OUT_SEL);
-	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
-		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
-			       config_regs + DISP_REG_CONFIG_OUT_SEL);
-		writel_relaxed(DSI_SEL_IN_RDMA,
-			       config_regs + DISP_REG_CONFIG_DSI_SEL);
-		writel_relaxed(DPI_SEL_IN_BLS,
-			       config_regs + DISP_REG_CONFIG_DPI_SEL);
-	}
-}
-
-void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
-			      enum mtk_ddp_comp_id cur,
-			      enum mtk_ddp_comp_id next)
-{
-	unsigned int addr, value, reg;
-
-	value = mtk_ddp_mout_en(cur, next, &addr);
-	if (value) {
-		reg = readl_relaxed(config_regs + addr) | value;
-		writel_relaxed(reg, config_regs + addr);
-	}
-
-	mtk_ddp_sout_sel(config_regs, cur, next);
-
-	value = mtk_ddp_sel_in(cur, next, &addr);
-	if (value) {
-		reg = readl_relaxed(config_regs + addr) | value;
-		writel_relaxed(reg, config_regs + addr);
-	}
-}
-
-void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
-				   enum mtk_ddp_comp_id cur,
-				   enum mtk_ddp_comp_id next)
-{
-	unsigned int addr, value, reg;
-
-	value = mtk_ddp_mout_en(cur, next, &addr);
-	if (value) {
-		reg = readl_relaxed(config_regs + addr) & ~value;
-		writel_relaxed(reg, config_regs + addr);
-	}
-
-	value = mtk_ddp_sel_in(cur, next, &addr);
-	if (value) {
-		reg = readl_relaxed(config_regs + addr) & ~value;
-		writel_relaxed(reg, config_regs + addr);
-	}
-}
-
 struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
 {
 	struct mtk_ddp *ddp = dev_get_drvdata(dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
index 827be424a148..6b691a57be4a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
@@ -12,13 +12,6 @@ struct regmap;
 struct device;
 struct mtk_disp_mutex;
 
-void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
-			      enum mtk_ddp_comp_id cur,
-			      enum mtk_ddp_comp_id next);
-void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
-				   enum mtk_ddp_comp_id cur,
-				   enum mtk_ddp_comp_id next);
-
 struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
 int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
 void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 8e2d3cb62ad5..208f9c5256ef 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -10,6 +10,7 @@
 #include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/pm_runtime.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
 #include <linux/dma-mapping.h>
 
 #include <drm/drm_atomic.h>
@@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct mtk_drm_private *private;
-	struct resource *mem;
 	struct device_node *node;
 	struct component_match *match = NULL;
 	int ret;
@@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		return -ENOMEM;
 
 	private->data = of_device_get_match_data(dev);
-
-	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-	private->config_regs = devm_ioremap_resource(dev, mem);
-	if (IS_ERR(private->config_regs)) {
-		ret = PTR_ERR(private->config_regs);
-		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
-			ret);
-		return ret;
+	private->mmsys_dev = dev->parent;
+	if (!private->mmsys_dev) {
+		dev_err(dev, "Failed to get MMSYS device\n");
+		return -ENODEV;
 	}
 
 	/* Iterate over sibling DISP function blocks */
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 17bc99b9f5d4..b5be63e53176 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -39,7 +39,7 @@ struct mtk_drm_private {
 
 	struct device_node *mutex_node;
 	struct device *mutex_dev;
-	void __iomem *config_regs;
+	struct device *mmsys_dev;
 	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
 	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
 	const struct mtk_mmsys_driver_data *data;
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index dbdfedd302fa..4b286b525cd3 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -5,8 +5,76 @@
  */
 
 #include <linux/clk-provider.h>
+#include <linux/device.h>
 #include <linux/of_device.h>
 #include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-mmsys.h>
+
+#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
+#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
+
+#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
+#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
+#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
+#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
+#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
+#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
+#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
+#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
+#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
+#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
+#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
+#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
+#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
+#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
+
+#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
+#define DISP_REG_CONFIG_OUT_SEL			0x04c
+#define DISP_REG_CONFIG_DSI_SEL			0x050
+#define DISP_REG_CONFIG_DPI_SEL			0x064
+
+#define OVL0_MOUT_EN_COLOR0			0x1
+#define OD_MOUT_EN_RDMA0			0x1
+#define OD1_MOUT_EN_RDMA1			BIT(16)
+#define UFOE_MOUT_EN_DSI0			0x1
+#define COLOR0_SEL_IN_OVL0			0x1
+#define OVL1_MOUT_EN_COLOR1			0x1
+#define GAMMA_MOUT_EN_RDMA1			0x1
+#define RDMA0_SOUT_DPI0				0x2
+#define RDMA0_SOUT_DPI1				0x3
+#define RDMA0_SOUT_DSI1				0x1
+#define RDMA0_SOUT_DSI2				0x4
+#define RDMA0_SOUT_DSI3				0x5
+#define RDMA1_SOUT_DPI0				0x2
+#define RDMA1_SOUT_DPI1				0x3
+#define RDMA1_SOUT_DSI1				0x1
+#define RDMA1_SOUT_DSI2				0x4
+#define RDMA1_SOUT_DSI3				0x5
+#define RDMA2_SOUT_DPI0				0x2
+#define RDMA2_SOUT_DPI1				0x3
+#define RDMA2_SOUT_DSI1				0x1
+#define RDMA2_SOUT_DSI2				0x4
+#define RDMA2_SOUT_DSI3				0x5
+#define DPI0_SEL_IN_RDMA1			0x1
+#define DPI0_SEL_IN_RDMA2			0x3
+#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
+#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
+#define DSI0_SEL_IN_RDMA1			0x1
+#define DSI0_SEL_IN_RDMA2			0x4
+#define DSI1_SEL_IN_RDMA1			0x1
+#define DSI1_SEL_IN_RDMA2			0x4
+#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
+#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
+#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
+#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
+#define COLOR1_SEL_IN_OVL1			0x1
+
+#define OVL_MOUT_EN_RDMA			0x1
+#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
+#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
+#define DSI_SEL_IN_BLS				0x0
+#define DPI_SEL_IN_BLS				0x0
+#define DSI_SEL_IN_RDMA				0x1
 
 struct mtk_mmsys_driver_data {
 	const char *clk_driver;
@@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 };
 
+static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
+					  enum mtk_ddp_comp_id next,
+					  unsigned int *addr)
+{
+	unsigned int value;
+
+	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
+		value = OVL0_MOUT_EN_COLOR0;
+	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
+		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
+		value = OVL_MOUT_EN_RDMA;
+	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
+		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+		value = OD_MOUT_EN_RDMA0;
+	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
+		value = UFOE_MOUT_EN_DSI0;
+	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
+		value = OVL1_MOUT_EN_COLOR1;
+	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
+		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
+		value = GAMMA_MOUT_EN_RDMA1;
+	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
+		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
+		value = OD1_MOUT_EN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DPI0;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DPI1;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DSI1;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DSI2;
+	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+		value = RDMA0_SOUT_DSI3;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+		value = RDMA1_SOUT_DSI1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+		value = RDMA1_SOUT_DSI2;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+		value = RDMA1_SOUT_DSI3;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+		value = RDMA1_SOUT_DPI0;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+		value = RDMA1_SOUT_DPI1;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+		value = RDMA2_SOUT_DPI0;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+		value = RDMA2_SOUT_DPI1;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+		value = RDMA2_SOUT_DSI1;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+		value = RDMA2_SOUT_DSI2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+		value = RDMA2_SOUT_DSI3;
+	} else {
+		value = 0;
+	}
+
+	return value;
+}
+
+static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
+					 enum mtk_ddp_comp_id next,
+					 unsigned int *addr)
+{
+	unsigned int value;
+
+	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
+		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
+		value = COLOR0_SEL_IN_OVL0;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
+		value = DPI0_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
+		value = DPI1_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI0_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+		value = DSI1_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI2_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+		value = DSI3_SEL_IN_RDMA1;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
+		value = DPI0_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
+		value = DPI1_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI0_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
+		value = DSI1_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI2_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
+		value = DSI3_SEL_IN_RDMA2;
+	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
+		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
+		value = COLOR1_SEL_IN_OVL1;
+	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+		*addr = DISP_REG_CONFIG_DSI_SEL;
+		value = DSI_SEL_IN_BLS;
+	} else {
+		value = 0;
+	}
+
+	return value;
+}
+
+static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
+				   enum mtk_ddp_comp_id cur,
+				   enum mtk_ddp_comp_id next)
+{
+	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
+		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
+			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
+		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
+			       config_regs + DISP_REG_CONFIG_OUT_SEL);
+		writel_relaxed(DSI_SEL_IN_RDMA,
+			       config_regs + DISP_REG_CONFIG_DSI_SEL);
+		writel_relaxed(DPI_SEL_IN_BLS,
+			       config_regs + DISP_REG_CONFIG_DPI_SEL);
+	}
+}
+
+void mtk_mmsys_ddp_connect(struct device *dev,
+			   enum mtk_ddp_comp_id cur,
+			   enum mtk_ddp_comp_id next)
+{
+	void __iomem *config_regs = dev_get_drvdata(dev);
+	unsigned int addr, value, reg;
+
+	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+	if (value) {
+		reg = readl_relaxed(config_regs + addr) | value;
+		writel_relaxed(reg, config_regs + addr);
+	}
+
+	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
+
+	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+	if (value) {
+		reg = readl_relaxed(config_regs + addr) | value;
+		writel_relaxed(reg, config_regs + addr);
+	}
+}
+
+void mtk_mmsys_ddp_disconnect(struct device *dev,
+			      enum mtk_ddp_comp_id cur,
+			      enum mtk_ddp_comp_id next)
+{
+	void __iomem *config_regs = dev_get_drvdata(dev);
+	unsigned int addr, value, reg;
+
+	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
+	if (value) {
+		reg = readl_relaxed(config_regs + addr) & ~value;
+		writel_relaxed(reg, config_regs + addr);
+	}
+
+	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
+	if (value) {
+		reg = readl_relaxed(config_regs + addr) & ~value;
+		writel_relaxed(reg, config_regs + addr);
+	}
+}
+
 static int mtk_mmsys_probe(struct platform_device *pdev)
 {
 	const struct mtk_mmsys_driver_data *data;
+	struct device *dev = &pdev->dev;
 	struct platform_device *clks;
+	void __iomem *config_regs;
+	struct resource *mem;
+	int ret;
+
+	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	config_regs = devm_ioremap_resource(dev, mem);
+	if (IS_ERR(config_regs)) {
+		ret = PTR_ERR(config_regs);
+		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
+			ret);
+		return ret;
+	}
+
+	platform_set_drvdata(pdev, config_regs);
 
 	data = of_device_get_match_data(&pdev->dev);
 
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
new file mode 100644
index 000000000000..7bab5d9a3d31
--- /dev/null
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2015 MediaTek Inc.
+ */
+
+#ifndef __MTK_MMSYS_H
+#define __MTK_MMSYS_H
+
+enum mtk_ddp_comp_id;
+struct device;
+
+void mtk_mmsys_ddp_connect(struct device *dev,
+			   enum mtk_ddp_comp_id cur,
+			   enum mtk_ddp_comp_id next);
+
+void mtk_mmsys_ddp_disconnect(struct device *dev,
+			      enum mtk_ddp_comp_id cur,
+			      enum mtk_ddp_comp_id next);
+
+#endif /* __MTK_MMSYS_H */
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* [PATCH v12 5/5] soc / drm: mediatek: Fix mediatek-drm device probing
  2020-03-11 16:53 [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing Enric Balletbo i Serra
                   ` (3 preceding siblings ...)
  2020-03-11 16:53 ` [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device Enric Balletbo i Serra
@ 2020-03-11 16:53 ` Enric Balletbo i Serra
  4 siblings, 0 replies; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:53 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, dri-devel,
	Richard Fontana, Collabora Kernel ML, linux-clk, Weiyi Lu, wens,
	Allison Randal, mtk01761, linux-media, devicetree, frank-w,
	Seiya Wang, sean.wang, Houlong Wei, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Greg Kroah-Hartman, rdunlap,
	linux-kernel, Daniel Vetter, matthias.bgg

In the actual implementation the same compatible string
"mediatek,<chip>-mmsys" is used to bind the clock drivers
(drivers/soc/mediatek) as well as to the gpu driver
(drivers/gpu/drm/mediatek/mtk_drm_drv.c). This ends with the problem
that the only probed driver is the clock driver and there is no display
at all.

In any case having the same compatible string for two drivers is not
correct and should be fixed. To fix this, and maintain backward
compatibility, we can consider that the mmsys driver is the top-level
entry point for the multimedia subsystem, so is not a pure clock
controller but a system controller, and the drm driver is instantiated
by that MMSYS driver.

Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Acked-by: CK Hu <ck.hu@mediatek.com>
---

Changes in v12: None
Changes in v10:
- Match driver data to get display routing.

Changes in v9:
- Do not move the display routing from the drm driver (CK)

Changes in v8:
- New patch introduced in this series.

Changes in v7: None

 drivers/gpu/drm/mediatek/mtk_drm_drv.c | 31 ++++++++++++++++----------
 drivers/soc/mediatek/mtk-mmsys.c       |  6 +++++
 2 files changed, 25 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 208f9c5256ef..bb26e346750a 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -422,9 +422,21 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	{ }
 };
 
+static const struct of_device_id mtk_drm_of_ids[] = {
+	{ .compatible = "mediatek,mt2701-mmsys",
+	  .data = &mt2701_mmsys_driver_data},
+	{ .compatible = "mediatek,mt2712-mmsys",
+	  .data = &mt2712_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8173-mmsys",
+	  .data = &mt8173_mmsys_driver_data},
+	{ }
+};
+
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	struct device_node *phandle = dev->parent->of_node;
+	const struct of_device_id *of_id;
 	struct mtk_drm_private *private;
 	struct device_node *node;
 	struct component_match *match = NULL;
@@ -442,8 +454,14 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
+	of_id = of_match_node(mtk_drm_of_ids, phandle);
+	if (!of_id)
+		return -ENODEV;
+
+	private->data = of_id->data;
+
 	/* Iterate over sibling DISP function blocks */
-	for_each_child_of_node(dev->of_node->parent, node) {
+	for_each_child_of_node(phandle->parent, node) {
 		const struct of_device_id *of_id;
 		enum mtk_ddp_comp_type comp_type;
 		int comp_id;
@@ -575,22 +593,11 @@ static int mtk_drm_sys_resume(struct device *dev)
 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend,
 			 mtk_drm_sys_resume);
 
-static const struct of_device_id mtk_drm_of_ids[] = {
-	{ .compatible = "mediatek,mt2701-mmsys",
-	  .data = &mt2701_mmsys_driver_data},
-	{ .compatible = "mediatek,mt2712-mmsys",
-	  .data = &mt2712_mmsys_driver_data},
-	{ .compatible = "mediatek,mt8173-mmsys",
-	  .data = &mt8173_mmsys_driver_data},
-	{ }
-};
-
 static struct platform_driver mtk_drm_platform_driver = {
 	.probe	= mtk_drm_probe,
 	.remove	= mtk_drm_remove,
 	.driver	= {
 		.name	= "mediatek-drm",
-		.of_match_table = mtk_drm_of_ids,
 		.pm     = &mtk_drm_pm_ops,
 	},
 };
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4b286b525cd3..32a92ec447c5 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -285,6 +285,7 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	const struct mtk_mmsys_driver_data *data;
 	struct device *dev = &pdev->dev;
 	struct platform_device *clks;
+	struct platform_device *drm;
 	void __iomem *config_regs;
 	struct resource *mem;
 	int ret;
@@ -307,6 +308,11 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	if (IS_ERR(clks))
 		return PTR_ERR(clks);
 
+	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
+					    PLATFORM_DEVID_AUTO, NULL, 0);
+	if (IS_ERR(drm))
+		return PTR_ERR(drm);
+
 	return 0;
 }
 
-- 
2.25.1


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver
  2020-03-11 16:53 ` [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver Enric Balletbo i Serra
@ 2020-03-11 16:58   ` Enric Balletbo i Serra
       [not found]   ` <158474603935.125146.14986079780178656133@swboyd.mtv.corp.google.com>
  1 sibling, 0 replies; 16+ messages in thread
From: Enric Balletbo i Serra @ 2020-03-11 16:58 UTC (permalink / raw)
  To: robh+dt, mark.rutland, ck.hu, p.zabel, airlied, mturquette,
	sboyd, ulrich.hecht+renesas, laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, James Liao,
	dri-devel, Richard Fontana, Collabora Kernel ML, linux-clk,
	Nicolas Boichat, Weiyi Lu, Krzysztof Kozlowski, wens,
	Allison Randal, mtk01761, Owen Chen, linux-media, devicetree,
	frank-w, Seiya Wang, sean.wang, Houlong Wei, linux-mediatek,
	hsinyi, Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Matthias Brugger, Fabien Parent,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg



On 11/3/20 17:53, Enric Balletbo i Serra wrote:
> From: Matthias Brugger <mbrugger@suse.com>
> 
> There is no strong reason for this to use CLK_OF_DECLARE instead of
> being a platform driver. Plus, MMSYS provides clocks but also a shared
> register space for the mediatek-drm and the mediatek-mdp
> driver. So move the MMSYS clocks to a new platform driver and also
> create a new MMSYS platform driver in drivers/soc/mediatek that
> instantiates the clock driver.
> 
> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> 
> Changes in v12:
> - Leave the clocks part in drivers/clk (clk-mt8173-mm)
> - Instantiate the clock driver from the mtk-mmsys driver.
> - Add default config option to not break anything.
> - Removed the Reviewed-by CK tag as changed the organization.
> 
> Changes in v10:
> - Renamed to be generic mtk-mmsys
> - Add driver data support to be able to support diferent SoCs
> 
> Changes in v9:
> - Move mmsys to drivers/soc/mediatek (CK)
> 
> Changes in v8:
> - Be a builtin_platform_driver like other mediatek mmsys drivers.
> 
> Changes in v7:
> - Free clk_data->clks as well
> - Get rid of private data structure
> 
>  drivers/clk/mediatek/Kconfig         |   7 ++
>  drivers/clk/mediatek/Makefile        |   1 +
>  drivers/clk/mediatek/clk-mt8173-mm.c | 146 +++++++++++++++++++++++++++
>  drivers/clk/mediatek/clk-mt8173.c    | 104 -------------------

Quoting Matthias to continue the discussion here:

"I'm not sure we really need that. We can just convert the mmsys clock bits in
clk-mt8173.c to a platform driver with no need put them in a seperate file.
If you think a seperate file is worth doing, I think the approach is to put the
driver in a seperate file first and in a following patch change it to a platform
driver."

"Anyway its Stephen to make the decision. If he thinks things are fine like
this, I'm happy to take the patch through my tree"


>  drivers/soc/mediatek/Kconfig         |   8 ++
>  drivers/soc/mediatek/Makefile        |   1 +
>  drivers/soc/mediatek/mtk-mmsys.c     |  50 +++++++++
>  7 files changed, 213 insertions(+), 104 deletions(-)
>  create mode 100644 drivers/clk/mediatek/clk-mt8173-mm.c
>  create mode 100644 drivers/soc/mediatek/mtk-mmsys.c
> 
> diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> index ea3c70d1307e..9e28db8125cd 100644
> --- a/drivers/clk/mediatek/Kconfig
> +++ b/drivers/clk/mediatek/Kconfig
> @@ -274,6 +274,13 @@ config COMMON_CLK_MT8173
>  	---help---
>  	  This driver supports MediaTek MT8173 clocks.
>  
> +config COMMON_CLK_MT8173_MMSYS
> +	bool "Clock driver for MediaTek MT8173 mmsys"
> +	depends on COMMON_CLK_MT8173
> +	default COMMON_CLK_MT8173
> +	help
> +	  This driver supports MediaTek MT8173 mmsys clocks.
> +
>  config COMMON_CLK_MT8183
>  	bool "Clock driver for MediaTek MT8183"
>  	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index 8cdb76a5cd71..bb0536942075 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -41,6 +41,7 @@ obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o
>  obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o
>  obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135.o
>  obj-$(CONFIG_COMMON_CLK_MT8173) += clk-mt8173.o
> +obj-$(CONFIG_COMMON_CLK_MT8173_MMSYS) += clk-mt8173-mm.o
>  obj-$(CONFIG_COMMON_CLK_MT8183) += clk-mt8183.o
>  obj-$(CONFIG_COMMON_CLK_MT8183_AUDIOSYS) += clk-mt8183-audio.o
>  obj-$(CONFIG_COMMON_CLK_MT8183_CAMSYS) += clk-mt8183-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8173-mm.c b/drivers/clk/mediatek/clk-mt8173-mm.c
> new file mode 100644
> index 000000000000..36fa20be77b6
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8173-mm.c
> @@ -0,0 +1,146 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: James Liao <jamesjj.liao@mediatek.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +#include <dt-bindings/clock/mt8173-clk.h>
> +
> +static const struct mtk_gate_regs mm0_cg_regs = {
> +	.set_ofs = 0x0104,
> +	.clr_ofs = 0x0108,
> +	.sta_ofs = 0x0100,
> +};
> +
> +static const struct mtk_gate_regs mm1_cg_regs = {
> +	.set_ofs = 0x0114,
> +	.clr_ofs = 0x0118,
> +	.sta_ofs = 0x0110,
> +};
> +
> +#define GATE_MM0(_id, _name, _parent, _shift) {			\
> +		.id = _id,					\
> +		.name = _name,					\
> +		.parent_name = _parent,				\
> +		.regs = &mm0_cg_regs,				\
> +		.shift = _shift,				\
> +		.ops = &mtk_clk_gate_ops_setclr,		\
> +	}
> +
> +#define GATE_MM1(_id, _name, _parent, _shift) {			\
> +		.id = _id,					\
> +		.name = _name,					\
> +		.parent_name = _parent,				\
> +		.regs = &mm1_cg_regs,				\
> +		.shift = _shift,				\
> +		.ops = &mtk_clk_gate_ops_setclr,		\
> +	}
> +
> +static const struct mtk_gate mt8173_mm_clks[] = {
> +	/* MM0 */
> +	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
> +	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
> +	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
> +	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
> +	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
> +	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
> +	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
> +	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
> +	GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
> +	GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
> +	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
> +	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
> +	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
> +	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
> +	GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
> +	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
> +	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
> +	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
> +	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
> +	GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
> +	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
> +	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
> +	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
> +	GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
> +	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
> +	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
> +	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
> +	GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
> +	GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
> +	GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
> +	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
> +	/* MM1 */
> +	GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
> +	GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
> +	GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
> +	GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
> +	GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
> +	GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
> +	GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
> +	GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
> +	GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
> +	GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
> +	GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
> +	GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
> +	GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
> +	GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
> +	GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
> +	GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
> +	GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
> +	GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
> +	GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
> +	GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
> +	GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
> +};
> +
> +struct clk_mt8173_mm_driver_data {
> +	const struct mtk_gate *gates_clk;
> +	int gates_num;
> +};
> +
> +static const struct clk_mt8173_mm_driver_data mt8173_mmsys_driver_data = {
> +	.gates_clk = mt8173_mm_clks,
> +	.gates_num = ARRAY_SIZE(mt8173_mm_clks),
> +};
> +
> +static int clk_mt8173_mm_probe(struct platform_device *pdev)
> +{
> +	struct device *dev = &pdev->dev;
> +	struct device_node *node = dev->parent->of_node;
> +	const struct clk_mt8173_mm_driver_data *data;
> +	struct clk_onecell_data *clk_data;
> +	int ret;
> +
> +	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
> +	if (!clk_data)
> +		return -ENOMEM;
> +
> +	data = &mt8173_mmsys_driver_data;
> +
> +	ret = mtk_clk_register_gates(node, data->gates_clk, data->gates_num,
> +				     clk_data);
> +	if (ret)
> +		return ret;
> +
> +	ret = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> +	if (ret)
> +		return ret;
> +
> +	return 0;
> +}
> +
> +static struct platform_driver clk_mt8173_mm_drv = {
> +	.driver = {
> +		.name = "clk-mt8173-mm",
> +	},
> +	.probe = clk_mt8173_mm_probe,
> +};
> +
> +builtin_platform_driver(clk_mt8173_mm_drv);
> diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
> index 537a7f49b0f7..8f898ac476c0 100644
> --- a/drivers/clk/mediatek/clk-mt8173.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -753,93 +753,6 @@ static const struct mtk_gate img_clks[] __initconst = {
>  	GATE_IMG(CLK_IMG_FD, "img_fd", "mm_sel", 11),
>  };
>  
> -static const struct mtk_gate_regs mm0_cg_regs __initconst = {
> -	.set_ofs = 0x0104,
> -	.clr_ofs = 0x0108,
> -	.sta_ofs = 0x0100,
> -};
> -
> -static const struct mtk_gate_regs mm1_cg_regs __initconst = {
> -	.set_ofs = 0x0114,
> -	.clr_ofs = 0x0118,
> -	.sta_ofs = 0x0110,
> -};
> -
> -#define GATE_MM0(_id, _name, _parent, _shift) {			\
> -		.id = _id,					\
> -		.name = _name,					\
> -		.parent_name = _parent,				\
> -		.regs = &mm0_cg_regs,				\
> -		.shift = _shift,				\
> -		.ops = &mtk_clk_gate_ops_setclr,		\
> -	}
> -
> -#define GATE_MM1(_id, _name, _parent, _shift) {			\
> -		.id = _id,					\
> -		.name = _name,					\
> -		.parent_name = _parent,				\
> -		.regs = &mm1_cg_regs,				\
> -		.shift = _shift,				\
> -		.ops = &mtk_clk_gate_ops_setclr,		\
> -	}
> -
> -static const struct mtk_gate mm_clks[] __initconst = {
> -	/* MM0 */
> -	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),
> -	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
> -	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 2),
> -	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 3),
> -	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 4),
> -	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 5),
> -	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 6),
> -	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 7),
> -	GATE_MM0(CLK_MM_MDP_TDSHP0, "mm_mdp_tdshp0", "mm_sel", 8),
> -	GATE_MM0(CLK_MM_MDP_TDSHP1, "mm_mdp_tdshp1", "mm_sel", 9),
> -	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),
> -	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),
> -	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),
> -	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),
> -	GATE_MM0(CLK_MM_MUTEX_32K, "mm_mutex_32k", "rtc_sel", 15),
> -	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 16),
> -	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 17),
> -	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 18),
> -	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 19),
> -	GATE_MM0(CLK_MM_DISP_RDMA2, "mm_disp_rdma2", "mm_sel", 20),
> -	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),
> -	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),
> -	GATE_MM0(CLK_MM_DISP_COLOR0, "mm_disp_color0", "mm_sel", 23),
> -	GATE_MM0(CLK_MM_DISP_COLOR1, "mm_disp_color1", "mm_sel", 24),
> -	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),
> -	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),
> -	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 27),
> -	GATE_MM0(CLK_MM_DISP_SPLIT0, "mm_disp_split0", "mm_sel", 28),
> -	GATE_MM0(CLK_MM_DISP_SPLIT1, "mm_disp_split1", "mm_sel", 29),
> -	GATE_MM0(CLK_MM_DISP_MERGE, "mm_disp_merge", "mm_sel", 30),
> -	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 31),
> -	/* MM1 */
> -	GATE_MM1(CLK_MM_DISP_PWM0MM, "mm_disp_pwm0mm", "mm_sel", 0),
> -	GATE_MM1(CLK_MM_DISP_PWM026M, "mm_disp_pwm026m", "pwm_sel", 1),
> -	GATE_MM1(CLK_MM_DISP_PWM1MM, "mm_disp_pwm1mm", "mm_sel", 2),
> -	GATE_MM1(CLK_MM_DISP_PWM126M, "mm_disp_pwm126m", "pwm_sel", 3),
> -	GATE_MM1(CLK_MM_DSI0_ENGINE, "mm_dsi0_engine", "mm_sel", 4),
> -	GATE_MM1(CLK_MM_DSI0_DIGITAL, "mm_dsi0_digital", "dsi0_dig", 5),
> -	GATE_MM1(CLK_MM_DSI1_ENGINE, "mm_dsi1_engine", "mm_sel", 6),
> -	GATE_MM1(CLK_MM_DSI1_DIGITAL, "mm_dsi1_digital", "dsi1_dig", 7),
> -	GATE_MM1(CLK_MM_DPI_PIXEL, "mm_dpi_pixel", "dpi0_sel", 8),
> -	GATE_MM1(CLK_MM_DPI_ENGINE, "mm_dpi_engine", "mm_sel", 9),
> -	GATE_MM1(CLK_MM_DPI1_PIXEL, "mm_dpi1_pixel", "lvds_pxl", 10),
> -	GATE_MM1(CLK_MM_DPI1_ENGINE, "mm_dpi1_engine", "mm_sel", 11),
> -	GATE_MM1(CLK_MM_HDMI_PIXEL, "mm_hdmi_pixel", "dpi0_sel", 12),
> -	GATE_MM1(CLK_MM_HDMI_PLLCK, "mm_hdmi_pllck", "hdmi_sel", 13),
> -	GATE_MM1(CLK_MM_HDMI_AUDIO, "mm_hdmi_audio", "apll1", 14),
> -	GATE_MM1(CLK_MM_HDMI_SPDIF, "mm_hdmi_spdif", "apll2", 15),
> -	GATE_MM1(CLK_MM_LVDS_PIXEL, "mm_lvds_pixel", "lvds_pxl", 16),
> -	GATE_MM1(CLK_MM_LVDS_CTS, "mm_lvds_cts", "lvds_cts", 17),
> -	GATE_MM1(CLK_MM_SMI_LARB4, "mm_smi_larb4", "mm_sel", 18),
> -	GATE_MM1(CLK_MM_HDMI_HDCP, "mm_hdmi_hdcp", "hdcp_sel", 19),
> -	GATE_MM1(CLK_MM_HDMI_HDCP24M, "mm_hdmi_hdcp24m", "hdcp_24m_sel", 20),
> -};
> -
>  static const struct mtk_gate_regs vdec0_cg_regs __initconst = {
>  	.set_ofs = 0x0000,
>  	.clr_ofs = 0x0004,
> @@ -1144,23 +1057,6 @@ static void __init mtk_imgsys_init(struct device_node *node)
>  }
>  CLK_OF_DECLARE(mtk_imgsys, "mediatek,mt8173-imgsys", mtk_imgsys_init);
>  
> -static void __init mtk_mmsys_init(struct device_node *node)
> -{
> -	struct clk_onecell_data *clk_data;
> -	int r;
> -
> -	clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
> -
> -	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
> -						clk_data);
> -
> -	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> -	if (r)
> -		pr_err("%s(): could not register clock provider: %d\n",
> -			__func__, r);
> -}
> -CLK_OF_DECLARE(mtk_mmsys, "mediatek,mt8173-mmsys", mtk_mmsys_init);
> -
>  static void __init mtk_vdecsys_init(struct device_node *node)
>  {
>  	struct clk_onecell_data *clk_data;
> diff --git a/drivers/soc/mediatek/Kconfig b/drivers/soc/mediatek/Kconfig
> index 2114b563478c..e84513318725 100644
> --- a/drivers/soc/mediatek/Kconfig
> +++ b/drivers/soc/mediatek/Kconfig
> @@ -44,4 +44,12 @@ config MTK_SCPSYS
>  	  Say yes here to add support for the MediaTek SCPSYS power domain
>  	  driver.
>  
> +config MTK_MMSYS
> +	bool "MediaTek MMSYS Support"
> +	depends on COMMON_CLK_MT8173_MMSYS
> +	default COMMON_CLK_MT8173_MMSYS
> +	help
> +	  Say yes here to add support for the MediaTek Multimedia
> +	  Subsystem (MMSYS).
> +
>  endmenu
> diff --git a/drivers/soc/mediatek/Makefile b/drivers/soc/mediatek/Makefile
> index b01733074ad6..01f9f873634a 100644
> --- a/drivers/soc/mediatek/Makefile
> +++ b/drivers/soc/mediatek/Makefile
> @@ -3,3 +3,4 @@ obj-$(CONFIG_MTK_CMDQ) += mtk-cmdq-helper.o
>  obj-$(CONFIG_MTK_INFRACFG) += mtk-infracfg.o
>  obj-$(CONFIG_MTK_PMIC_WRAP) += mtk-pmic-wrap.o
>  obj-$(CONFIG_MTK_SCPSYS) += mtk-scpsys.o
> +obj-$(CONFIG_MTK_MMSYS) += mtk-mmsys.o
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> new file mode 100644
> index 000000000000..dbdfedd302fa
> --- /dev/null
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -0,0 +1,50 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2014 MediaTek Inc.
> + * Author: James Liao <jamesjj.liao@mediatek.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +
> +struct mtk_mmsys_driver_data {
> +	const char *clk_driver;
> +};
> +
> +static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> +	.clk_driver = "clk-mt8173-mm",
> +};
> +
> +static int mtk_mmsys_probe(struct platform_device *pdev)
> +{
> +	const struct mtk_mmsys_driver_data *data;
> +	struct platform_device *clks;
> +
> +	data = of_device_get_match_data(&pdev->dev);
> +
> +	clks = platform_device_register_data(&pdev->dev, data->clk_driver,
> +					     PLATFORM_DEVID_AUTO, NULL, 0);
> +	if (IS_ERR(clks))
> +		return PTR_ERR(clks);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id of_match_mtk_mmsys[] = {
> +	{
> +		.compatible = "mediatek,mt8173-mmsys",
> +		.data = &mt8173_mmsys_driver_data,
> +	},
> +	{ }
> +};
> +
> +static struct platform_driver mtk_mmsys_drv = {
> +	.driver = {
> +		.name = "mtk-mmsys",
> +		.of_match_table = of_match_mtk_mmsys,
> +	},
> +	.probe = mtk_mmsys_probe,
> +};
> +
> +builtin_platform_driver(mtk_mmsys_drv);
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller
  2020-03-11 16:53 ` [PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller Enric Balletbo i Serra
@ 2020-03-12 15:22   ` Rob Herring
  0 siblings, 0 replies; 16+ messages in thread
From: Rob Herring @ 2020-03-12 15:22 UTC (permalink / raw)
  To: Enric Balletbo i Serra
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, linux-arm-kernel, ck.hu, mtk01761,
	linux-media, devicetree, Daniel Vetter, frank-w, Seiya Wang,
	sean.wang, Houlong Wei, linux-mediatek, hsinyi, Matthias Brugger,
	Thomas Gleixner, Mauro Carvalho Chehab, Allison Randal,
	Matthias Brugger, sboyd, Greg Kroah-Hartman, rdunlap,
	linux-kernel, p.zabel, matthias.bgg

On Wed, Mar 11, 2020 at 05:53:19PM +0100, Enric Balletbo i Serra wrote:
> The mmsys system controller is not only a pure clock controller, so
> update the binding documentation to reflect that apart from providing
> clocks, it also provides routing and miscellaneous control registers.
> 
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> ---
> 
> Changes in v12: None
> Changes in v10:
> - Update the binding documentation for the mmsys system controller.
> 
> Changes in v9: None
> Changes in v8: None
> Changes in v7: None
> 
>  .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt    | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)

Reviewed-by: Rob Herring <robh@kernel.org>

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver
       [not found]   ` <158474603935.125146.14986079780178656133@swboyd.mtv.corp.google.com>
@ 2020-03-25 15:36     ` Chun-Kuang Hu
  0 siblings, 0 replies; 16+ messages in thread
From: Chun-Kuang Hu @ 2020-03-25 15:36 UTC (permalink / raw)
  To: Stephen Boyd
  Cc: Mark Rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	David Airlie, mturquette, DRI Development, Fabien Parent,
	Laurent Pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	hat.com, linux-clk, Nicolas Boichat, Weiyi Lu,
	Krzysztof Kozlowski, wens, linux-arm-kernel, CK Hu, mtk01761,
	Owen Chen, linux-media, devicetree, frank-w, Seiya Wang,
	sean.wang, Houlong Wei, Enric Balletbo i Serra, Rob Herring,
	linux-mediatek, hsinyi, Matthias Brugger, Thomas Gleixner,
	Mauro Carvalho Chehab, Allison Randal, Matthias Brugger,
	Greg Kroah-Hartman, rdunlap, linux-kernel, p.zabel, matthias.bgg,
	James Liao

Stephen Boyd <sboyd@kernel.org> 於 2020年3月21日 週六 上午7:14寫道:
>
> Quoting Enric Balletbo i Serra (2020-03-11 09:53:20)
> > From: Matthias Brugger <mbrugger@suse.com>
> >
> > There is no strong reason for this to use CLK_OF_DECLARE instead of
> > being a platform driver. Plus, MMSYS provides clocks but also a shared
> > register space for the mediatek-drm and the mediatek-mdp
> > driver. So move the MMSYS clocks to a new platform driver and also
> > create a new MMSYS platform driver in drivers/soc/mediatek that
> > instantiates the clock driver.
> >
> > Signed-off-by: Matthias Brugger <mbrugger@suse.com>
> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > ---
>
> Reviewed-by: Stephen Boyd <sboyd@kernel.org>
>
> Unless you want me to pick this up by itself?

I would like Matthias to pick up this series together.

> _______________________________________________
> dri-devel mailing list
> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-11 16:53 ` [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device Enric Balletbo i Serra
@ 2020-03-25 16:16   ` Matthias Brugger
  2020-03-25 23:05     ` CK Hu
  0 siblings, 1 reply; 16+ messages in thread
From: Matthias Brugger @ 2020-03-25 16:16 UTC (permalink / raw)
  To: Enric Balletbo i Serra, robh+dt, mark.rutland, ck.hu, p.zabel,
	airlied, mturquette, sboyd, ulrich.hecht+renesas,
	laurent.pinchart
  Cc: Kate Stewart, Andrew-CT Chen, Minghsiu Tsai, dri-devel,
	Richard Fontana, Collabora Kernel ML, linux-clk, Weiyi Lu, wens,
	Allison Randal, mtk01761, linux-media, devicetree, frank-w,
	Seiya Wang, sean.wang, Houlong Wei, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	linux-arm-kernel, Greg Kroah-Hartman, rdunlap, linux-kernel,
	Daniel Vetter, matthias.bgg



On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> Those functions will allow DRM driver and others to control the data
> path routing.
> 
> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Acked-by: CK Hu <ck.hu@mediatek.com>

This patch does not apply against v5.6-rc1.
Please rebase as this is a quite big patch and it won't be easy to do that by hand.

Regards,
Matthias

> ---
> 
> Changes in v12: None
> Changes in v10:
> - Select CONFIG_MTK_MMSYS (CK)
> - Pass device pointer of mmsys device instead of config regs (CK)
> 
> Changes in v9:
> - Introduced a new patch to move routing control into mmsys driver.
> - Removed the patch to use regmap as is not needed anymore.
> 
> Changes in v8: None
> Changes in v7: None
> 
>  drivers/gpu/drm/mediatek/Kconfig        |   1 +
>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
>  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
>  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
>  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
>  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
>  8 files changed, 316 insertions(+), 282 deletions(-)
>  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
> 
> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> index fa5ffc4fe823..c420f5a3d33b 100644
> --- a/drivers/gpu/drm/mediatek/Kconfig
> +++ b/drivers/gpu/drm/mediatek/Kconfig
> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
>  	select DRM_MIPI_DSI
>  	select DRM_PANEL
>  	select MEMORY
> +	select MTK_MMSYS
>  	select MTK_SMI
>  	select VIDEOMODE_HELPERS
>  	help
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 0e05683d7b53..579a5a5d4472 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -6,6 +6,7 @@
>  #include <linux/clk.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/soc/mediatek/mtk-cmdq.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
>  
>  #include <asm/barrier.h>
>  #include <soc/mediatek/smi.h>
> @@ -28,7 +29,7 @@
>   * @enabled: records whether crtc_enable succeeded
>   * @planes: array of 4 drm_plane structures, one for each overlay plane
>   * @pending_planes: whether any plane has pending changes to be applied
> - * @config_regs: memory mapped mmsys configuration register space
> + * @mmsys_dev: pointer to the mmsys device for configuration registers
>   * @mutex: handle to one of the ten disp_mutex streams
>   * @ddp_comp_nr: number of components in ddp_comp
>   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
>  	u32				cmdq_event;
>  #endif
>  
> -	void __iomem			*config_regs;
> +	struct device			*mmsys_dev;
>  	struct mtk_disp_mutex		*mutex;
>  	unsigned int			ddp_comp_nr;
>  	struct mtk_ddp_comp		**ddp_comp;
> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
>  	}
>  
>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> -					 mtk_crtc->ddp_comp[i]->id,
> -					 mtk_crtc->ddp_comp[i + 1]->id);
> +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> +				      mtk_crtc->ddp_comp[i]->id,
> +				      mtk_crtc->ddp_comp[i + 1]->id);
>  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
>  					mtk_crtc->ddp_comp[i]->id);
>  	}
> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
>  					   mtk_crtc->ddp_comp[i]->id);
>  	mtk_disp_mutex_disable(mtk_crtc->mutex);
>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
> -					      mtk_crtc->ddp_comp[i]->id,
> -					      mtk_crtc->ddp_comp[i + 1]->id);
> +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
> +					 mtk_crtc->ddp_comp[i]->id,
> +					 mtk_crtc->ddp_comp[i + 1]->id);
>  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
>  					   mtk_crtc->ddp_comp[i]->id);
>  	}
> @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>  	if (!mtk_crtc)
>  		return -ENOMEM;
>  
> -	mtk_crtc->config_regs = priv->config_regs;
> +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
>  	mtk_crtc->ddp_comp_nr = path_len;
>  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
>  						sizeof(*mtk_crtc->ddp_comp),
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> index b885f60f474c..014c1bbe1df2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> @@ -13,26 +13,6 @@
>  #include "mtk_drm_ddp.h"
>  #include "mtk_drm_ddp_comp.h"
>  
> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> -
> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> -#define DISP_REG_CONFIG_OUT_SEL			0x04c
> -#define DISP_REG_CONFIG_DSI_SEL			0x050
> -#define DISP_REG_CONFIG_DPI_SEL			0x064
> -
>  #define MT2701_DISP_MUTEX0_MOD0			0x2c
>  #define MT2701_DISP_MUTEX0_SOF0			0x30
>  
> @@ -94,48 +74,6 @@
>  #define MUTEX_SOF_DSI2			5
>  #define MUTEX_SOF_DSI3			6
>  
> -#define OVL0_MOUT_EN_COLOR0		0x1
> -#define OD_MOUT_EN_RDMA0		0x1
> -#define OD1_MOUT_EN_RDMA1		BIT(16)
> -#define UFOE_MOUT_EN_DSI0		0x1
> -#define COLOR0_SEL_IN_OVL0		0x1
> -#define OVL1_MOUT_EN_COLOR1		0x1
> -#define GAMMA_MOUT_EN_RDMA1		0x1
> -#define RDMA0_SOUT_DPI0			0x2
> -#define RDMA0_SOUT_DPI1			0x3
> -#define RDMA0_SOUT_DSI1			0x1
> -#define RDMA0_SOUT_DSI2			0x4
> -#define RDMA0_SOUT_DSI3			0x5
> -#define RDMA1_SOUT_DPI0			0x2
> -#define RDMA1_SOUT_DPI1			0x3
> -#define RDMA1_SOUT_DSI1			0x1
> -#define RDMA1_SOUT_DSI2			0x4
> -#define RDMA1_SOUT_DSI3			0x5
> -#define RDMA2_SOUT_DPI0			0x2
> -#define RDMA2_SOUT_DPI1			0x3
> -#define RDMA2_SOUT_DSI1			0x1
> -#define RDMA2_SOUT_DSI2			0x4
> -#define RDMA2_SOUT_DSI3			0x5
> -#define DPI0_SEL_IN_RDMA1		0x1
> -#define DPI0_SEL_IN_RDMA2		0x3
> -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> -#define DSI0_SEL_IN_RDMA1		0x1
> -#define DSI0_SEL_IN_RDMA2		0x4
> -#define DSI1_SEL_IN_RDMA1		0x1
> -#define DSI1_SEL_IN_RDMA2		0x4
> -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
> -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
> -#define COLOR1_SEL_IN_OVL1		0x1
> -
> -#define OVL_MOUT_EN_RDMA		0x1
> -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
> -#define DSI_SEL_IN_BLS			0x0
> -#define DPI_SEL_IN_BLS			0x0
> -#define DSI_SEL_IN_RDMA			0x1
>  
>  struct mtk_disp_mutex {
>  	int id;
> @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
>  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
>  };
>  
> -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> -				    enum mtk_ddp_comp_id next,
> -				    unsigned int *addr)
> -{
> -	unsigned int value;
> -
> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> -		value = OVL0_MOUT_EN_COLOR0;
> -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> -		value = OVL_MOUT_EN_RDMA;
> -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> -		value = OD_MOUT_EN_RDMA0;
> -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> -		value = UFOE_MOUT_EN_DSI0;
> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> -		value = OVL1_MOUT_EN_COLOR1;
> -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> -		value = GAMMA_MOUT_EN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> -		value = OD1_MOUT_EN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> -		value = RDMA0_SOUT_DPI0;
> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> -		value = RDMA0_SOUT_DPI1;
> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> -		value = RDMA0_SOUT_DSI1;
> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> -		value = RDMA0_SOUT_DSI2;
> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> -		value = RDMA0_SOUT_DSI3;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> -		value = RDMA1_SOUT_DSI1;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> -		value = RDMA1_SOUT_DSI2;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> -		value = RDMA1_SOUT_DSI3;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> -		value = RDMA1_SOUT_DPI0;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> -		value = RDMA1_SOUT_DPI1;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> -		value = RDMA2_SOUT_DPI0;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> -		value = RDMA2_SOUT_DPI1;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> -		value = RDMA2_SOUT_DSI1;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> -		value = RDMA2_SOUT_DSI2;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> -		value = RDMA2_SOUT_DSI3;
> -	} else {
> -		value = 0;
> -	}
> -
> -	return value;
> -}
> -
> -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> -				   enum mtk_ddp_comp_id next,
> -				   unsigned int *addr)
> -{
> -	unsigned int value;
> -
> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> -		value = COLOR0_SEL_IN_OVL0;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> -		value = DPI0_SEL_IN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> -		value = DPI1_SEL_IN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> -		value = DSI0_SEL_IN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> -		value = DSI1_SEL_IN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> -		value = DSI2_SEL_IN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> -		value = DSI3_SEL_IN_RDMA1;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> -		value = DPI0_SEL_IN_RDMA2;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> -		value = DPI1_SEL_IN_RDMA2;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> -		value = DSI0_SEL_IN_RDMA2;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> -		value = DSI1_SEL_IN_RDMA2;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> -		value = DSI2_SEL_IN_RDMA2;
> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> -		value = DSI3_SEL_IN_RDMA2;
> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> -		value = COLOR1_SEL_IN_OVL1;
> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> -		*addr = DISP_REG_CONFIG_DSI_SEL;
> -		value = DSI_SEL_IN_BLS;
> -	} else {
> -		value = 0;
> -	}
> -
> -	return value;
> -}
> -
> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
> -			     enum mtk_ddp_comp_id cur,
> -			     enum mtk_ddp_comp_id next)
> -{
> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> -		writel_relaxed(DSI_SEL_IN_RDMA,
> -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> -		writel_relaxed(DPI_SEL_IN_BLS,
> -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> -	}
> -}
> -
> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> -			      enum mtk_ddp_comp_id cur,
> -			      enum mtk_ddp_comp_id next)
> -{
> -	unsigned int addr, value, reg;
> -
> -	value = mtk_ddp_mout_en(cur, next, &addr);
> -	if (value) {
> -		reg = readl_relaxed(config_regs + addr) | value;
> -		writel_relaxed(reg, config_regs + addr);
> -	}
> -
> -	mtk_ddp_sout_sel(config_regs, cur, next);
> -
> -	value = mtk_ddp_sel_in(cur, next, &addr);
> -	if (value) {
> -		reg = readl_relaxed(config_regs + addr) | value;
> -		writel_relaxed(reg, config_regs + addr);
> -	}
> -}
> -
> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> -				   enum mtk_ddp_comp_id cur,
> -				   enum mtk_ddp_comp_id next)
> -{
> -	unsigned int addr, value, reg;
> -
> -	value = mtk_ddp_mout_en(cur, next, &addr);
> -	if (value) {
> -		reg = readl_relaxed(config_regs + addr) & ~value;
> -		writel_relaxed(reg, config_regs + addr);
> -	}
> -
> -	value = mtk_ddp_sel_in(cur, next, &addr);
> -	if (value) {
> -		reg = readl_relaxed(config_regs + addr) & ~value;
> -		writel_relaxed(reg, config_regs + addr);
> -	}
> -}
> -
>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
>  {
>  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> index 827be424a148..6b691a57be4a 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> @@ -12,13 +12,6 @@ struct regmap;
>  struct device;
>  struct mtk_disp_mutex;
>  
> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> -			      enum mtk_ddp_comp_id cur,
> -			      enum mtk_ddp_comp_id next);
> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> -				   enum mtk_ddp_comp_id cur,
> -				   enum mtk_ddp_comp_id next);
> -
>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
>  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 8e2d3cb62ad5..208f9c5256ef 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -10,6 +10,7 @@
>  #include <linux/of_address.h>
>  #include <linux/of_platform.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
>  #include <linux/dma-mapping.h>
>  
>  #include <drm/drm_atomic.h>
> @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  {
>  	struct device *dev = &pdev->dev;
>  	struct mtk_drm_private *private;
> -	struct resource *mem;
>  	struct device_node *node;
>  	struct component_match *match = NULL;
>  	int ret;
> @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
>  		return -ENOMEM;
>  
>  	private->data = of_device_get_match_data(dev);
> -
> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> -	private->config_regs = devm_ioremap_resource(dev, mem);
> -	if (IS_ERR(private->config_regs)) {
> -		ret = PTR_ERR(private->config_regs);
> -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> -			ret);
> -		return ret;
> +	private->mmsys_dev = dev->parent;
> +	if (!private->mmsys_dev) {
> +		dev_err(dev, "Failed to get MMSYS device\n");
> +		return -ENODEV;
>  	}
>  
>  	/* Iterate over sibling DISP function blocks */
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 17bc99b9f5d4..b5be63e53176 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -39,7 +39,7 @@ struct mtk_drm_private {
>  
>  	struct device_node *mutex_node;
>  	struct device *mutex_dev;
> -	void __iomem *config_regs;
> +	struct device *mmsys_dev;
>  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
>  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
>  	const struct mtk_mmsys_driver_data *data;
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index dbdfedd302fa..4b286b525cd3 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -5,8 +5,76 @@
>   */
>  
>  #include <linux/clk-provider.h>
> +#include <linux/device.h>
>  #include <linux/of_device.h>
>  #include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-mmsys.h>
> +
> +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
> +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
> +
> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> +
> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> +#define DISP_REG_CONFIG_OUT_SEL			0x04c
> +#define DISP_REG_CONFIG_DSI_SEL			0x050
> +#define DISP_REG_CONFIG_DPI_SEL			0x064
> +
> +#define OVL0_MOUT_EN_COLOR0			0x1
> +#define OD_MOUT_EN_RDMA0			0x1
> +#define OD1_MOUT_EN_RDMA1			BIT(16)
> +#define UFOE_MOUT_EN_DSI0			0x1
> +#define COLOR0_SEL_IN_OVL0			0x1
> +#define OVL1_MOUT_EN_COLOR1			0x1
> +#define GAMMA_MOUT_EN_RDMA1			0x1
> +#define RDMA0_SOUT_DPI0				0x2
> +#define RDMA0_SOUT_DPI1				0x3
> +#define RDMA0_SOUT_DSI1				0x1
> +#define RDMA0_SOUT_DSI2				0x4
> +#define RDMA0_SOUT_DSI3				0x5
> +#define RDMA1_SOUT_DPI0				0x2
> +#define RDMA1_SOUT_DPI1				0x3
> +#define RDMA1_SOUT_DSI1				0x1
> +#define RDMA1_SOUT_DSI2				0x4
> +#define RDMA1_SOUT_DSI3				0x5
> +#define RDMA2_SOUT_DPI0				0x2
> +#define RDMA2_SOUT_DPI1				0x3
> +#define RDMA2_SOUT_DSI1				0x1
> +#define RDMA2_SOUT_DSI2				0x4
> +#define RDMA2_SOUT_DSI3				0x5
> +#define DPI0_SEL_IN_RDMA1			0x1
> +#define DPI0_SEL_IN_RDMA2			0x3
> +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
> +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
> +#define DSI0_SEL_IN_RDMA1			0x1
> +#define DSI0_SEL_IN_RDMA2			0x4
> +#define DSI1_SEL_IN_RDMA1			0x1
> +#define DSI1_SEL_IN_RDMA2			0x4
> +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
> +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
> +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
> +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
> +#define COLOR1_SEL_IN_OVL1			0x1
> +
> +#define OVL_MOUT_EN_RDMA			0x1
> +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
> +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
> +#define DSI_SEL_IN_BLS				0x0
> +#define DPI_SEL_IN_BLS				0x0
> +#define DSI_SEL_IN_RDMA				0x1
>  
>  struct mtk_mmsys_driver_data {
>  	const char *clk_driver;
> @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>  	.clk_driver = "clk-mt8173-mm",
>  };
>  
> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> +					  enum mtk_ddp_comp_id next,
> +					  unsigned int *addr)
> +{
> +	unsigned int value;
> +
> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> +		value = OVL0_MOUT_EN_COLOR0;
> +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> +		value = OVL_MOUT_EN_RDMA;
> +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> +		value = OD_MOUT_EN_RDMA0;
> +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> +		value = UFOE_MOUT_EN_DSI0;
> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> +		value = OVL1_MOUT_EN_COLOR1;
> +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> +		value = GAMMA_MOUT_EN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> +		value = OD1_MOUT_EN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> +		value = RDMA0_SOUT_DPI0;
> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> +		value = RDMA0_SOUT_DPI1;
> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> +		value = RDMA0_SOUT_DSI1;
> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> +		value = RDMA0_SOUT_DSI2;
> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> +		value = RDMA0_SOUT_DSI3;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> +		value = RDMA1_SOUT_DSI1;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> +		value = RDMA1_SOUT_DSI2;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> +		value = RDMA1_SOUT_DSI3;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> +		value = RDMA1_SOUT_DPI0;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> +		value = RDMA1_SOUT_DPI1;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> +		value = RDMA2_SOUT_DPI0;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> +		value = RDMA2_SOUT_DPI1;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> +		value = RDMA2_SOUT_DSI1;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> +		value = RDMA2_SOUT_DSI2;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> +		value = RDMA2_SOUT_DSI3;
> +	} else {
> +		value = 0;
> +	}
> +
> +	return value;
> +}
> +
> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> +					 enum mtk_ddp_comp_id next,
> +					 unsigned int *addr)
> +{
> +	unsigned int value;
> +
> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> +		value = COLOR0_SEL_IN_OVL0;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> +		value = DPI0_SEL_IN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> +		value = DPI1_SEL_IN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> +		value = DSI0_SEL_IN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> +		value = DSI1_SEL_IN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> +		value = DSI2_SEL_IN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> +		value = DSI3_SEL_IN_RDMA1;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> +		value = DPI0_SEL_IN_RDMA2;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> +		value = DPI1_SEL_IN_RDMA2;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> +		value = DSI0_SEL_IN_RDMA2;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> +		value = DSI1_SEL_IN_RDMA2;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> +		value = DSI2_SEL_IN_RDMA2;
> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> +		value = DSI3_SEL_IN_RDMA2;
> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> +		value = COLOR1_SEL_IN_OVL1;
> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> +		*addr = DISP_REG_CONFIG_DSI_SEL;
> +		value = DSI_SEL_IN_BLS;
> +	} else {
> +		value = 0;
> +	}
> +
> +	return value;
> +}
> +
> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> +				   enum mtk_ddp_comp_id cur,
> +				   enum mtk_ddp_comp_id next)
> +{
> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +		writel_relaxed(DSI_SEL_IN_RDMA,
> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> +		writel_relaxed(DPI_SEL_IN_BLS,
> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> +	}
> +}
> +
> +void mtk_mmsys_ddp_connect(struct device *dev,
> +			   enum mtk_ddp_comp_id cur,
> +			   enum mtk_ddp_comp_id next)
> +{
> +	void __iomem *config_regs = dev_get_drvdata(dev);
> +	unsigned int addr, value, reg;
> +
> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> +	if (value) {
> +		reg = readl_relaxed(config_regs + addr) | value;
> +		writel_relaxed(reg, config_regs + addr);
> +	}
> +
> +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> +
> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> +	if (value) {
> +		reg = readl_relaxed(config_regs + addr) | value;
> +		writel_relaxed(reg, config_regs + addr);
> +	}
> +}
> +
> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> +			      enum mtk_ddp_comp_id cur,
> +			      enum mtk_ddp_comp_id next)
> +{
> +	void __iomem *config_regs = dev_get_drvdata(dev);
> +	unsigned int addr, value, reg;
> +
> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> +	if (value) {
> +		reg = readl_relaxed(config_regs + addr) & ~value;
> +		writel_relaxed(reg, config_regs + addr);
> +	}
> +
> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> +	if (value) {
> +		reg = readl_relaxed(config_regs + addr) & ~value;
> +		writel_relaxed(reg, config_regs + addr);
> +	}
> +}
> +
>  static int mtk_mmsys_probe(struct platform_device *pdev)
>  {
>  	const struct mtk_mmsys_driver_data *data;
> +	struct device *dev = &pdev->dev;
>  	struct platform_device *clks;
> +	void __iomem *config_regs;
> +	struct resource *mem;
> +	int ret;
> +
> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +	config_regs = devm_ioremap_resource(dev, mem);
> +	if (IS_ERR(config_regs)) {
> +		ret = PTR_ERR(config_regs);
> +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> +			ret);
> +		return ret;
> +	}
> +
> +	platform_set_drvdata(pdev, config_regs);
>  
>  	data = of_device_get_match_data(&pdev->dev);
>  
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> new file mode 100644
> index 000000000000..7bab5d9a3d31
> --- /dev/null
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -0,0 +1,20 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2015 MediaTek Inc.
> + */
> +
> +#ifndef __MTK_MMSYS_H
> +#define __MTK_MMSYS_H
> +
> +enum mtk_ddp_comp_id;
> +struct device;
> +
> +void mtk_mmsys_ddp_connect(struct device *dev,
> +			   enum mtk_ddp_comp_id cur,
> +			   enum mtk_ddp_comp_id next);
> +
> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> +			      enum mtk_ddp_comp_id cur,
> +			      enum mtk_ddp_comp_id next);
> +
> +#endif /* __MTK_MMSYS_H */
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-25 16:16   ` Matthias Brugger
@ 2020-03-25 23:05     ` CK Hu
  2020-03-26 11:54       ` Matthias Brugger
  2020-03-27 17:04       ` Matthias Brugger
  0 siblings, 2 replies; 16+ messages in thread
From: CK Hu @ 2020-03-25 23:05 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, linux-arm-kernel, mtk01761,
	linux-media, devicetree, Daniel Vetter, frank-w, Seiya Wang,
	sean.wang, Houlong Wei, robh+dt, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	Allison Randal, sboyd, Greg Kroah-Hartman, rdunlap, linux-kernel,
	p.zabel, matthias.bgg, Enric Balletbo i Serra

Hi, Matthias:

On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
> 
> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
> > Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> > replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> > Those functions will allow DRM driver and others to control the data
> > path routing.
> > 
> > Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> > Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> > Reviewed-by: CK Hu <ck.hu@mediatek.com>
> > Acked-by: CK Hu <ck.hu@mediatek.com>
> 
> This patch does not apply against v5.6-rc1.
> Please rebase as this is a quite big patch and it won't be easy to do that by hand.

I think this patch depends on [1] which has been acked by me and I have
not picked it. The simple way is that you pick [1] first and then pick
this series.

[1] 
https://patchwork.kernel.org/patch/11406227/

Regards,
CK

> 
> Regards,
> Matthias
> 
> > ---
> > 
> > Changes in v12: None
> > Changes in v10:
> > - Select CONFIG_MTK_MMSYS (CK)
> > - Pass device pointer of mmsys device instead of config regs (CK)
> > 
> > Changes in v9:
> > - Introduced a new patch to move routing control into mmsys driver.
> > - Removed the patch to use regmap as is not needed anymore.
> > 
> > Changes in v8: None
> > Changes in v7: None
> > 
> >  drivers/gpu/drm/mediatek/Kconfig        |   1 +
> >  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
> >  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
> >  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
> >  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
> >  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
> >  8 files changed, 316 insertions(+), 282 deletions(-)
> >  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
> > 
> > diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> > index fa5ffc4fe823..c420f5a3d33b 100644
> > --- a/drivers/gpu/drm/mediatek/Kconfig
> > +++ b/drivers/gpu/drm/mediatek/Kconfig
> > @@ -11,6 +11,7 @@ config DRM_MEDIATEK
> >  	select DRM_MIPI_DSI
> >  	select DRM_PANEL
> >  	select MEMORY
> > +	select MTK_MMSYS
> >  	select MTK_SMI
> >  	select VIDEOMODE_HELPERS
> >  	help
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > index 0e05683d7b53..579a5a5d4472 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> > @@ -6,6 +6,7 @@
> >  #include <linux/clk.h>
> >  #include <linux/pm_runtime.h>
> >  #include <linux/soc/mediatek/mtk-cmdq.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> >  
> >  #include <asm/barrier.h>
> >  #include <soc/mediatek/smi.h>
> > @@ -28,7 +29,7 @@
> >   * @enabled: records whether crtc_enable succeeded
> >   * @planes: array of 4 drm_plane structures, one for each overlay plane
> >   * @pending_planes: whether any plane has pending changes to be applied
> > - * @config_regs: memory mapped mmsys configuration register space
> > + * @mmsys_dev: pointer to the mmsys device for configuration registers
> >   * @mutex: handle to one of the ten disp_mutex streams
> >   * @ddp_comp_nr: number of components in ddp_comp
> >   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
> > @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
> >  	u32				cmdq_event;
> >  #endif
> >  
> > -	void __iomem			*config_regs;
> > +	struct device			*mmsys_dev;
> >  	struct mtk_disp_mutex		*mutex;
> >  	unsigned int			ddp_comp_nr;
> >  	struct mtk_ddp_comp		**ddp_comp;
> > @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> >  	}
> >  
> >  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> > -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> > -					 mtk_crtc->ddp_comp[i]->id,
> > -					 mtk_crtc->ddp_comp[i + 1]->id);
> > +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> > +				      mtk_crtc->ddp_comp[i]->id,
> > +				      mtk_crtc->ddp_comp[i + 1]->id);
> >  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
> >  					mtk_crtc->ddp_comp[i]->id);
> >  	}
> > @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
> >  					   mtk_crtc->ddp_comp[i]->id);
> >  	mtk_disp_mutex_disable(mtk_crtc->mutex);
> >  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> > -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
> > -					      mtk_crtc->ddp_comp[i]->id,
> > -					      mtk_crtc->ddp_comp[i + 1]->id);
> > +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
> > +					 mtk_crtc->ddp_comp[i]->id,
> > +					 mtk_crtc->ddp_comp[i + 1]->id);
> >  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
> >  					   mtk_crtc->ddp_comp[i]->id);
> >  	}
> > @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >  	if (!mtk_crtc)
> >  		return -ENOMEM;
> >  
> > -	mtk_crtc->config_regs = priv->config_regs;
> > +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
> >  	mtk_crtc->ddp_comp_nr = path_len;
> >  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
> >  						sizeof(*mtk_crtc->ddp_comp),
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > index b885f60f474c..014c1bbe1df2 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> > @@ -13,26 +13,6 @@
> >  #include "mtk_drm_ddp.h"
> >  #include "mtk_drm_ddp_comp.h"
> >  
> > -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> > -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> > -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> > -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> > -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> > -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> > -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> > -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> > -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> > -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> > -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> > -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> > -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> > -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> > -
> > -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> > -#define DISP_REG_CONFIG_OUT_SEL			0x04c
> > -#define DISP_REG_CONFIG_DSI_SEL			0x050
> > -#define DISP_REG_CONFIG_DPI_SEL			0x064
> > -
> >  #define MT2701_DISP_MUTEX0_MOD0			0x2c
> >  #define MT2701_DISP_MUTEX0_SOF0			0x30
> >  
> > @@ -94,48 +74,6 @@
> >  #define MUTEX_SOF_DSI2			5
> >  #define MUTEX_SOF_DSI3			6
> >  
> > -#define OVL0_MOUT_EN_COLOR0		0x1
> > -#define OD_MOUT_EN_RDMA0		0x1
> > -#define OD1_MOUT_EN_RDMA1		BIT(16)
> > -#define UFOE_MOUT_EN_DSI0		0x1
> > -#define COLOR0_SEL_IN_OVL0		0x1
> > -#define OVL1_MOUT_EN_COLOR1		0x1
> > -#define GAMMA_MOUT_EN_RDMA1		0x1
> > -#define RDMA0_SOUT_DPI0			0x2
> > -#define RDMA0_SOUT_DPI1			0x3
> > -#define RDMA0_SOUT_DSI1			0x1
> > -#define RDMA0_SOUT_DSI2			0x4
> > -#define RDMA0_SOUT_DSI3			0x5
> > -#define RDMA1_SOUT_DPI0			0x2
> > -#define RDMA1_SOUT_DPI1			0x3
> > -#define RDMA1_SOUT_DSI1			0x1
> > -#define RDMA1_SOUT_DSI2			0x4
> > -#define RDMA1_SOUT_DSI3			0x5
> > -#define RDMA2_SOUT_DPI0			0x2
> > -#define RDMA2_SOUT_DPI1			0x3
> > -#define RDMA2_SOUT_DSI1			0x1
> > -#define RDMA2_SOUT_DSI2			0x4
> > -#define RDMA2_SOUT_DSI3			0x5
> > -#define DPI0_SEL_IN_RDMA1		0x1
> > -#define DPI0_SEL_IN_RDMA2		0x3
> > -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> > -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> > -#define DSI0_SEL_IN_RDMA1		0x1
> > -#define DSI0_SEL_IN_RDMA2		0x4
> > -#define DSI1_SEL_IN_RDMA1		0x1
> > -#define DSI1_SEL_IN_RDMA2		0x4
> > -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> > -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
> > -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> > -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
> > -#define COLOR1_SEL_IN_OVL1		0x1
> > -
> > -#define OVL_MOUT_EN_RDMA		0x1
> > -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> > -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
> > -#define DSI_SEL_IN_BLS			0x0
> > -#define DPI_SEL_IN_BLS			0x0
> > -#define DSI_SEL_IN_RDMA			0x1
> >  
> >  struct mtk_disp_mutex {
> >  	int id;
> > @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> >  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> >  };
> >  
> > -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > -				    enum mtk_ddp_comp_id next,
> > -				    unsigned int *addr)
> > -{
> > -	unsigned int value;
> > -
> > -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > -		value = OVL0_MOUT_EN_COLOR0;
> > -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > -		value = OVL_MOUT_EN_RDMA;
> > -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > -		value = OD_MOUT_EN_RDMA0;
> > -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > -		value = UFOE_MOUT_EN_DSI0;
> > -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > -		value = OVL1_MOUT_EN_COLOR1;
> > -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > -		value = GAMMA_MOUT_EN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > -		value = OD1_MOUT_EN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > -		value = RDMA0_SOUT_DPI0;
> > -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > -		value = RDMA0_SOUT_DPI1;
> > -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > -		value = RDMA0_SOUT_DSI1;
> > -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > -		value = RDMA0_SOUT_DSI2;
> > -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > -		value = RDMA0_SOUT_DSI3;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > -		value = RDMA1_SOUT_DSI1;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > -		value = RDMA1_SOUT_DSI2;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > -		value = RDMA1_SOUT_DSI3;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > -		value = RDMA1_SOUT_DPI0;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > -		value = RDMA1_SOUT_DPI1;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > -		value = RDMA2_SOUT_DPI0;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > -		value = RDMA2_SOUT_DPI1;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > -		value = RDMA2_SOUT_DSI1;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > -		value = RDMA2_SOUT_DSI2;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > -		value = RDMA2_SOUT_DSI3;
> > -	} else {
> > -		value = 0;
> > -	}
> > -
> > -	return value;
> > -}
> > -
> > -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > -				   enum mtk_ddp_comp_id next,
> > -				   unsigned int *addr)
> > -{
> > -	unsigned int value;
> > -
> > -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > -		value = COLOR0_SEL_IN_OVL0;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > -		value = DPI0_SEL_IN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > -		value = DPI1_SEL_IN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > -		value = DSI0_SEL_IN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > -		value = DSI1_SEL_IN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > -		value = DSI2_SEL_IN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > -		value = DSI3_SEL_IN_RDMA1;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > -		value = DPI0_SEL_IN_RDMA2;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > -		value = DPI1_SEL_IN_RDMA2;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > -		value = DSI0_SEL_IN_RDMA2;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > -		value = DSI1_SEL_IN_RDMA2;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > -		value = DSI2_SEL_IN_RDMA2;
> > -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > -		value = DSI3_SEL_IN_RDMA2;
> > -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > -		value = COLOR1_SEL_IN_OVL1;
> > -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > -		*addr = DISP_REG_CONFIG_DSI_SEL;
> > -		value = DSI_SEL_IN_BLS;
> > -	} else {
> > -		value = 0;
> > -	}
> > -
> > -	return value;
> > -}
> > -
> > -static void mtk_ddp_sout_sel(void __iomem *config_regs,
> > -			     enum mtk_ddp_comp_id cur,
> > -			     enum mtk_ddp_comp_id next)
> > -{
> > -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> > -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> > -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> > -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> > -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> > -		writel_relaxed(DSI_SEL_IN_RDMA,
> > -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> > -		writel_relaxed(DPI_SEL_IN_BLS,
> > -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> > -	}
> > -}
> > -
> > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> > -			      enum mtk_ddp_comp_id cur,
> > -			      enum mtk_ddp_comp_id next)
> > -{
> > -	unsigned int addr, value, reg;
> > -
> > -	value = mtk_ddp_mout_en(cur, next, &addr);
> > -	if (value) {
> > -		reg = readl_relaxed(config_regs + addr) | value;
> > -		writel_relaxed(reg, config_regs + addr);
> > -	}
> > -
> > -	mtk_ddp_sout_sel(config_regs, cur, next);
> > -
> > -	value = mtk_ddp_sel_in(cur, next, &addr);
> > -	if (value) {
> > -		reg = readl_relaxed(config_regs + addr) | value;
> > -		writel_relaxed(reg, config_regs + addr);
> > -	}
> > -}
> > -
> > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> > -				   enum mtk_ddp_comp_id cur,
> > -				   enum mtk_ddp_comp_id next)
> > -{
> > -	unsigned int addr, value, reg;
> > -
> > -	value = mtk_ddp_mout_en(cur, next, &addr);
> > -	if (value) {
> > -		reg = readl_relaxed(config_regs + addr) & ~value;
> > -		writel_relaxed(reg, config_regs + addr);
> > -	}
> > -
> > -	value = mtk_ddp_sel_in(cur, next, &addr);
> > -	if (value) {
> > -		reg = readl_relaxed(config_regs + addr) & ~value;
> > -		writel_relaxed(reg, config_regs + addr);
> > -	}
> > -}
> > -
> >  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
> >  {
> >  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> > index 827be424a148..6b691a57be4a 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> > @@ -12,13 +12,6 @@ struct regmap;
> >  struct device;
> >  struct mtk_disp_mutex;
> >  
> > -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> > -			      enum mtk_ddp_comp_id cur,
> > -			      enum mtk_ddp_comp_id next);
> > -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> > -				   enum mtk_ddp_comp_id cur,
> > -				   enum mtk_ddp_comp_id next);
> > -
> >  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
> >  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
> >  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 8e2d3cb62ad5..208f9c5256ef 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -10,6 +10,7 @@
> >  #include <linux/of_address.h>
> >  #include <linux/of_platform.h>
> >  #include <linux/pm_runtime.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> >  #include <linux/dma-mapping.h>
> >  
> >  #include <drm/drm_atomic.h>
> > @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  {
> >  	struct device *dev = &pdev->dev;
> >  	struct mtk_drm_private *private;
> > -	struct resource *mem;
> >  	struct device_node *node;
> >  	struct component_match *match = NULL;
> >  	int ret;
> > @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >  		return -ENOMEM;
> >  
> >  	private->data = of_device_get_match_data(dev);
> > -
> > -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > -	private->config_regs = devm_ioremap_resource(dev, mem);
> > -	if (IS_ERR(private->config_regs)) {
> > -		ret = PTR_ERR(private->config_regs);
> > -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> > -			ret);
> > -		return ret;
> > +	private->mmsys_dev = dev->parent;
> > +	if (!private->mmsys_dev) {
> > +		dev_err(dev, "Failed to get MMSYS device\n");
> > +		return -ENODEV;
> >  	}
> >  
> >  	/* Iterate over sibling DISP function blocks */
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 17bc99b9f5d4..b5be63e53176 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -39,7 +39,7 @@ struct mtk_drm_private {
> >  
> >  	struct device_node *mutex_node;
> >  	struct device *mutex_dev;
> > -	void __iomem *config_regs;
> > +	struct device *mmsys_dev;
> >  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
> >  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
> >  	const struct mtk_mmsys_driver_data *data;
> > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> > index dbdfedd302fa..4b286b525cd3 100644
> > --- a/drivers/soc/mediatek/mtk-mmsys.c
> > +++ b/drivers/soc/mediatek/mtk-mmsys.c
> > @@ -5,8 +5,76 @@
> >   */
> >  
> >  #include <linux/clk-provider.h>
> > +#include <linux/device.h>
> >  #include <linux/of_device.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-mmsys.h>
> > +
> > +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
> > +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> > +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> > +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> > +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> > +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> > +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> > +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> > +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> > +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> > +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> > +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> > +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> > +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> > +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> > +
> > +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> > +#define DISP_REG_CONFIG_OUT_SEL			0x04c
> > +#define DISP_REG_CONFIG_DSI_SEL			0x050
> > +#define DISP_REG_CONFIG_DPI_SEL			0x064
> > +
> > +#define OVL0_MOUT_EN_COLOR0			0x1
> > +#define OD_MOUT_EN_RDMA0			0x1
> > +#define OD1_MOUT_EN_RDMA1			BIT(16)
> > +#define UFOE_MOUT_EN_DSI0			0x1
> > +#define COLOR0_SEL_IN_OVL0			0x1
> > +#define OVL1_MOUT_EN_COLOR1			0x1
> > +#define GAMMA_MOUT_EN_RDMA1			0x1
> > +#define RDMA0_SOUT_DPI0				0x2
> > +#define RDMA0_SOUT_DPI1				0x3
> > +#define RDMA0_SOUT_DSI1				0x1
> > +#define RDMA0_SOUT_DSI2				0x4
> > +#define RDMA0_SOUT_DSI3				0x5
> > +#define RDMA1_SOUT_DPI0				0x2
> > +#define RDMA1_SOUT_DPI1				0x3
> > +#define RDMA1_SOUT_DSI1				0x1
> > +#define RDMA1_SOUT_DSI2				0x4
> > +#define RDMA1_SOUT_DSI3				0x5
> > +#define RDMA2_SOUT_DPI0				0x2
> > +#define RDMA2_SOUT_DPI1				0x3
> > +#define RDMA2_SOUT_DSI1				0x1
> > +#define RDMA2_SOUT_DSI2				0x4
> > +#define RDMA2_SOUT_DSI3				0x5
> > +#define DPI0_SEL_IN_RDMA1			0x1
> > +#define DPI0_SEL_IN_RDMA2			0x3
> > +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
> > +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
> > +#define DSI0_SEL_IN_RDMA1			0x1
> > +#define DSI0_SEL_IN_RDMA2			0x4
> > +#define DSI1_SEL_IN_RDMA1			0x1
> > +#define DSI1_SEL_IN_RDMA2			0x4
> > +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
> > +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
> > +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
> > +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
> > +#define COLOR1_SEL_IN_OVL1			0x1
> > +
> > +#define OVL_MOUT_EN_RDMA			0x1
> > +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
> > +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
> > +#define DSI_SEL_IN_BLS				0x0
> > +#define DPI_SEL_IN_BLS				0x0
> > +#define DSI_SEL_IN_RDMA				0x1
> >  
> >  struct mtk_mmsys_driver_data {
> >  	const char *clk_driver;
> > @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> >  	.clk_driver = "clk-mt8173-mm",
> >  };
> >  
> > +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> > +					  enum mtk_ddp_comp_id next,
> > +					  unsigned int *addr)
> > +{
> > +	unsigned int value;
> > +
> > +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> > +		value = OVL0_MOUT_EN_COLOR0;
> > +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> > +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> > +		value = OVL_MOUT_EN_RDMA;
> > +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> > +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > +		value = OD_MOUT_EN_RDMA0;
> > +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> > +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> > +		value = UFOE_MOUT_EN_DSI0;
> > +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> > +		value = OVL1_MOUT_EN_COLOR1;
> > +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> > +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> > +		value = GAMMA_MOUT_EN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> > +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> > +		value = OD1_MOUT_EN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +		value = RDMA0_SOUT_DPI0;
> > +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +		value = RDMA0_SOUT_DPI1;
> > +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +		value = RDMA0_SOUT_DSI1;
> > +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +		value = RDMA0_SOUT_DSI2;
> > +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> > +		value = RDMA0_SOUT_DSI3;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > +		value = RDMA1_SOUT_DSI1;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > +		value = RDMA1_SOUT_DSI2;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > +		value = RDMA1_SOUT_DSI3;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > +		value = RDMA1_SOUT_DPI0;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> > +		value = RDMA1_SOUT_DPI1;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > +		value = RDMA2_SOUT_DPI0;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > +		value = RDMA2_SOUT_DPI1;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > +		value = RDMA2_SOUT_DSI1;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > +		value = RDMA2_SOUT_DSI2;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> > +		value = RDMA2_SOUT_DSI3;
> > +	} else {
> > +		value = 0;
> > +	}
> > +
> > +	return value;
> > +}
> > +
> > +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> > +					 enum mtk_ddp_comp_id next,
> > +					 unsigned int *addr)
> > +{
> > +	unsigned int value;
> > +
> > +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> > +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> > +		value = COLOR0_SEL_IN_OVL0;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > +		value = DPI0_SEL_IN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > +		value = DPI1_SEL_IN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> > +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > +		value = DSI0_SEL_IN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> > +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > +		value = DSI1_SEL_IN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> > +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > +		value = DSI2_SEL_IN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> > +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > +		value = DSI3_SEL_IN_RDMA1;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > +		value = DPI0_SEL_IN_RDMA2;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> > +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> > +		value = DPI1_SEL_IN_RDMA2;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> > +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > +		value = DSI0_SEL_IN_RDMA2;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> > +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> > +		value = DSI1_SEL_IN_RDMA2;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> > +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > +		value = DSI2_SEL_IN_RDMA2;
> > +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> > +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> > +		value = DSI3_SEL_IN_RDMA2;
> > +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> > +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> > +		value = COLOR1_SEL_IN_OVL1;
> > +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > +		*addr = DISP_REG_CONFIG_DSI_SEL;
> > +		value = DSI_SEL_IN_BLS;
> > +	} else {
> > +		value = 0;
> > +	}
> > +
> > +	return value;
> > +}
> > +
> > +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> > +				   enum mtk_ddp_comp_id cur,
> > +				   enum mtk_ddp_comp_id next)
> > +{
> > +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> > +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> > +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> > +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> > +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> > +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> > +		writel_relaxed(DSI_SEL_IN_RDMA,
> > +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> > +		writel_relaxed(DPI_SEL_IN_BLS,
> > +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> > +	}
> > +}
> > +
> > +void mtk_mmsys_ddp_connect(struct device *dev,
> > +			   enum mtk_ddp_comp_id cur,
> > +			   enum mtk_ddp_comp_id next)
> > +{
> > +	void __iomem *config_regs = dev_get_drvdata(dev);
> > +	unsigned int addr, value, reg;
> > +
> > +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > +	if (value) {
> > +		reg = readl_relaxed(config_regs + addr) | value;
> > +		writel_relaxed(reg, config_regs + addr);
> > +	}
> > +
> > +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> > +
> > +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > +	if (value) {
> > +		reg = readl_relaxed(config_regs + addr) | value;
> > +		writel_relaxed(reg, config_regs + addr);
> > +	}
> > +}
> > +
> > +void mtk_mmsys_ddp_disconnect(struct device *dev,
> > +			      enum mtk_ddp_comp_id cur,
> > +			      enum mtk_ddp_comp_id next)
> > +{
> > +	void __iomem *config_regs = dev_get_drvdata(dev);
> > +	unsigned int addr, value, reg;
> > +
> > +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> > +	if (value) {
> > +		reg = readl_relaxed(config_regs + addr) & ~value;
> > +		writel_relaxed(reg, config_regs + addr);
> > +	}
> > +
> > +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> > +	if (value) {
> > +		reg = readl_relaxed(config_regs + addr) & ~value;
> > +		writel_relaxed(reg, config_regs + addr);
> > +	}
> > +}
> > +
> >  static int mtk_mmsys_probe(struct platform_device *pdev)
> >  {
> >  	const struct mtk_mmsys_driver_data *data;
> > +	struct device *dev = &pdev->dev;
> >  	struct platform_device *clks;
> > +	void __iomem *config_regs;
> > +	struct resource *mem;
> > +	int ret;
> > +
> > +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > +	config_regs = devm_ioremap_resource(dev, mem);
> > +	if (IS_ERR(config_regs)) {
> > +		ret = PTR_ERR(config_regs);
> > +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> > +			ret);
> > +		return ret;
> > +	}
> > +
> > +	platform_set_drvdata(pdev, config_regs);
> >  
> >  	data = of_device_get_match_data(&pdev->dev);
> >  
> > diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> > new file mode 100644
> > index 000000000000..7bab5d9a3d31
> > --- /dev/null
> > +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> > @@ -0,0 +1,20 @@
> > +/* SPDX-License-Identifier: GPL-2.0-only */
> > +/*
> > + * Copyright (c) 2015 MediaTek Inc.
> > + */
> > +
> > +#ifndef __MTK_MMSYS_H
> > +#define __MTK_MMSYS_H
> > +
> > +enum mtk_ddp_comp_id;
> > +struct device;
> > +
> > +void mtk_mmsys_ddp_connect(struct device *dev,
> > +			   enum mtk_ddp_comp_id cur,
> > +			   enum mtk_ddp_comp_id next);
> > +
> > +void mtk_mmsys_ddp_disconnect(struct device *dev,
> > +			      enum mtk_ddp_comp_id cur,
> > +			      enum mtk_ddp_comp_id next);
> > +
> > +#endif /* __MTK_MMSYS_H */
> > 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-25 23:05     ` CK Hu
@ 2020-03-26 11:54       ` Matthias Brugger
  2020-03-26 14:51         ` CK Hu
  2020-03-27 17:04       ` Matthias Brugger
  1 sibling, 1 reply; 16+ messages in thread
From: Matthias Brugger @ 2020-03-26 11:54 UTC (permalink / raw)
  To: CK Hu
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, linux-arm-kernel, mtk01761,
	linux-media, devicetree, Daniel Vetter, frank-w, Seiya Wang,
	sean.wang, Houlong Wei, robh+dt, linux-mediatek, hsinyi,
	Matthias Brugger, Thomas Gleixner, Mauro Carvalho Chehab,
	Allison Randal, sboyd, Greg Kroah-Hartman, rdunlap, linux-kernel,
	p.zabel, matthias.bgg, Enric Balletbo i Serra

Hi CK,

On 26/03/2020 00:05, CK Hu wrote:
> Hi, Matthias:
> 
> On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
>>
>> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
>>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
>>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
>>> Those functions will allow DRM driver and others to control the data
>>> path routing.
>>>
>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
>>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>>> Acked-by: CK Hu <ck.hu@mediatek.com>
>>
>> This patch does not apply against v5.6-rc1.
>> Please rebase as this is a quite big patch and it won't be easy to do that by hand.
> 
> I think this patch depends on [1] which has been acked by me and I have
> not picked it. The simple way is that you pick [1] first and then pick
> this series.
> 
> [1] 
> https://patchwork.kernel.org/patch/11406227/
> 

You would need to provide a stable tag for me that I can merge into my tree. You
can also try to merge my for-next [1] which has the newest version from Enric.
If you see any merge conflict, then we have to do something about it :)

Regards,
Matthias

[1]
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next

> Regards,
> CK
> 
>>
>> Regards,
>> Matthias
>>
>>> ---
>>>
>>> Changes in v12: None
>>> Changes in v10:
>>> - Select CONFIG_MTK_MMSYS (CK)
>>> - Pass device pointer of mmsys device instead of config regs (CK)
>>>
>>> Changes in v9:
>>> - Introduced a new patch to move routing control into mmsys driver.
>>> - Removed the patch to use regmap as is not needed anymore.
>>>
>>> Changes in v8: None
>>> Changes in v7: None
>>>
>>>  drivers/gpu/drm/mediatek/Kconfig        |   1 +
>>>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
>>>  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
>>>  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
>>>  8 files changed, 316 insertions(+), 282 deletions(-)
>>>  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
>>> index fa5ffc4fe823..c420f5a3d33b 100644
>>> --- a/drivers/gpu/drm/mediatek/Kconfig
>>> +++ b/drivers/gpu/drm/mediatek/Kconfig
>>> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
>>>  	select DRM_MIPI_DSI
>>>  	select DRM_PANEL
>>>  	select MEMORY
>>> +	select MTK_MMSYS
>>>  	select MTK_SMI
>>>  	select VIDEOMODE_HELPERS
>>>  	help
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> index 0e05683d7b53..579a5a5d4472 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> @@ -6,6 +6,7 @@
>>>  #include <linux/clk.h>
>>>  #include <linux/pm_runtime.h>
>>>  #include <linux/soc/mediatek/mtk-cmdq.h>
>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>  
>>>  #include <asm/barrier.h>
>>>  #include <soc/mediatek/smi.h>
>>> @@ -28,7 +29,7 @@
>>>   * @enabled: records whether crtc_enable succeeded
>>>   * @planes: array of 4 drm_plane structures, one for each overlay plane
>>>   * @pending_planes: whether any plane has pending changes to be applied
>>> - * @config_regs: memory mapped mmsys configuration register space
>>> + * @mmsys_dev: pointer to the mmsys device for configuration registers
>>>   * @mutex: handle to one of the ten disp_mutex streams
>>>   * @ddp_comp_nr: number of components in ddp_comp
>>>   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
>>> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
>>>  	u32				cmdq_event;
>>>  #endif
>>>  
>>> -	void __iomem			*config_regs;
>>> +	struct device			*mmsys_dev;
>>>  	struct mtk_disp_mutex		*mutex;
>>>  	unsigned int			ddp_comp_nr;
>>>  	struct mtk_ddp_comp		**ddp_comp;
>>> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
>>>  	}
>>>  
>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
>>> -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
>>> -					 mtk_crtc->ddp_comp[i]->id,
>>> -					 mtk_crtc->ddp_comp[i + 1]->id);
>>> +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
>>> +				      mtk_crtc->ddp_comp[i]->id,
>>> +				      mtk_crtc->ddp_comp[i + 1]->id);
>>>  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
>>>  					mtk_crtc->ddp_comp[i]->id);
>>>  	}
>>> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
>>>  					   mtk_crtc->ddp_comp[i]->id);
>>>  	mtk_disp_mutex_disable(mtk_crtc->mutex);
>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
>>> -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
>>> -					      mtk_crtc->ddp_comp[i]->id,
>>> -					      mtk_crtc->ddp_comp[i + 1]->id);
>>> +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
>>> +					 mtk_crtc->ddp_comp[i]->id,
>>> +					 mtk_crtc->ddp_comp[i + 1]->id);
>>>  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
>>>  					   mtk_crtc->ddp_comp[i]->id);
>>>  	}
>>> @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>>>  	if (!mtk_crtc)
>>>  		return -ENOMEM;
>>>  
>>> -	mtk_crtc->config_regs = priv->config_regs;
>>> +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
>>>  	mtk_crtc->ddp_comp_nr = path_len;
>>>  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
>>>  						sizeof(*mtk_crtc->ddp_comp),
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>> index b885f60f474c..014c1bbe1df2 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>> @@ -13,26 +13,6 @@
>>>  #include "mtk_drm_ddp.h"
>>>  #include "mtk_drm_ddp_comp.h"
>>>  
>>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
>>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
>>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
>>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
>>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
>>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
>>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
>>> -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
>>> -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
>>> -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
>>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
>>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
>>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
>>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
>>> -
>>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>>> -#define DISP_REG_CONFIG_OUT_SEL			0x04c
>>> -#define DISP_REG_CONFIG_DSI_SEL			0x050
>>> -#define DISP_REG_CONFIG_DPI_SEL			0x064
>>> -
>>>  #define MT2701_DISP_MUTEX0_MOD0			0x2c
>>>  #define MT2701_DISP_MUTEX0_SOF0			0x30
>>>  
>>> @@ -94,48 +74,6 @@
>>>  #define MUTEX_SOF_DSI2			5
>>>  #define MUTEX_SOF_DSI3			6
>>>  
>>> -#define OVL0_MOUT_EN_COLOR0		0x1
>>> -#define OD_MOUT_EN_RDMA0		0x1
>>> -#define OD1_MOUT_EN_RDMA1		BIT(16)
>>> -#define UFOE_MOUT_EN_DSI0		0x1
>>> -#define COLOR0_SEL_IN_OVL0		0x1
>>> -#define OVL1_MOUT_EN_COLOR1		0x1
>>> -#define GAMMA_MOUT_EN_RDMA1		0x1
>>> -#define RDMA0_SOUT_DPI0			0x2
>>> -#define RDMA0_SOUT_DPI1			0x3
>>> -#define RDMA0_SOUT_DSI1			0x1
>>> -#define RDMA0_SOUT_DSI2			0x4
>>> -#define RDMA0_SOUT_DSI3			0x5
>>> -#define RDMA1_SOUT_DPI0			0x2
>>> -#define RDMA1_SOUT_DPI1			0x3
>>> -#define RDMA1_SOUT_DSI1			0x1
>>> -#define RDMA1_SOUT_DSI2			0x4
>>> -#define RDMA1_SOUT_DSI3			0x5
>>> -#define RDMA2_SOUT_DPI0			0x2
>>> -#define RDMA2_SOUT_DPI1			0x3
>>> -#define RDMA2_SOUT_DSI1			0x1
>>> -#define RDMA2_SOUT_DSI2			0x4
>>> -#define RDMA2_SOUT_DSI3			0x5
>>> -#define DPI0_SEL_IN_RDMA1		0x1
>>> -#define DPI0_SEL_IN_RDMA2		0x3
>>> -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
>>> -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
>>> -#define DSI0_SEL_IN_RDMA1		0x1
>>> -#define DSI0_SEL_IN_RDMA2		0x4
>>> -#define DSI1_SEL_IN_RDMA1		0x1
>>> -#define DSI1_SEL_IN_RDMA2		0x4
>>> -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
>>> -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
>>> -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
>>> -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
>>> -#define COLOR1_SEL_IN_OVL1		0x1
>>> -
>>> -#define OVL_MOUT_EN_RDMA		0x1
>>> -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
>>> -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
>>> -#define DSI_SEL_IN_BLS			0x0
>>> -#define DPI_SEL_IN_BLS			0x0
>>> -#define DSI_SEL_IN_RDMA			0x1
>>>  
>>>  struct mtk_disp_mutex {
>>>  	int id;
>>> @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
>>>  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
>>>  };
>>>  
>>> -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> -				    enum mtk_ddp_comp_id next,
>>> -				    unsigned int *addr)
>>> -{
>>> -	unsigned int value;
>>> -
>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> -		value = OVL0_MOUT_EN_COLOR0;
>>> -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> -		value = OVL_MOUT_EN_RDMA;
>>> -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> -		value = OD_MOUT_EN_RDMA0;
>>> -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> -		value = UFOE_MOUT_EN_DSI0;
>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> -		value = OVL1_MOUT_EN_COLOR1;
>>> -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> -		value = GAMMA_MOUT_EN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> -		value = OD1_MOUT_EN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DPI0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DPI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DSI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DSI2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DSI3;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DSI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DSI2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DSI3;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DPI0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DPI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DPI0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DPI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DSI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DSI2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DSI3;
>>> -	} else {
>>> -		value = 0;
>>> -	}
>>> -
>>> -	return value;
>>> -}
>>> -
>>> -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> -				   enum mtk_ddp_comp_id next,
>>> -				   unsigned int *addr)
>>> -{
>>> -	unsigned int value;
>>> -
>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> -		value = COLOR0_SEL_IN_OVL0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI0_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI1_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI0_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> -		value = DSI1_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI2_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> -		value = DSI3_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI0_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI1_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI0_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> -		value = DSI1_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI2_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI3_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> -		value = COLOR1_SEL_IN_OVL1;
>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DSI_SEL;
>>> -		value = DSI_SEL_IN_BLS;
>>> -	} else {
>>> -		value = 0;
>>> -	}
>>> -
>>> -	return value;
>>> -}
>>> -
>>> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
>>> -			     enum mtk_ddp_comp_id cur,
>>> -			     enum mtk_ddp_comp_id next)
>>> -{
>>> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>>> -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> -		writel_relaxed(DSI_SEL_IN_RDMA,
>>> -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
>>> -		writel_relaxed(DPI_SEL_IN_BLS,
>>> -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
>>> -	}
>>> -}
>>> -
>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
>>> -			      enum mtk_ddp_comp_id cur,
>>> -			      enum mtk_ddp_comp_id next)
>>> -{
>>> -	unsigned int addr, value, reg;
>>> -
>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) | value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -
>>> -	mtk_ddp_sout_sel(config_regs, cur, next);
>>> -
>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) | value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -}
>>> -
>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
>>> -				   enum mtk_ddp_comp_id cur,
>>> -				   enum mtk_ddp_comp_id next)
>>> -{
>>> -	unsigned int addr, value, reg;
>>> -
>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -
>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -}
>>> -
>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
>>>  {
>>>  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>> index 827be424a148..6b691a57be4a 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>> @@ -12,13 +12,6 @@ struct regmap;
>>>  struct device;
>>>  struct mtk_disp_mutex;
>>>  
>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
>>> -			      enum mtk_ddp_comp_id cur,
>>> -			      enum mtk_ddp_comp_id next);
>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
>>> -				   enum mtk_ddp_comp_id cur,
>>> -				   enum mtk_ddp_comp_id next);
>>> -
>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
>>>  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
>>>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>> index 8e2d3cb62ad5..208f9c5256ef 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>> @@ -10,6 +10,7 @@
>>>  #include <linux/of_address.h>
>>>  #include <linux/of_platform.h>
>>>  #include <linux/pm_runtime.h>
>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>  #include <linux/dma-mapping.h>
>>>  
>>>  #include <drm/drm_atomic.h>
>>> @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
>>>  {
>>>  	struct device *dev = &pdev->dev;
>>>  	struct mtk_drm_private *private;
>>> -	struct resource *mem;
>>>  	struct device_node *node;
>>>  	struct component_match *match = NULL;
>>>  	int ret;
>>> @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
>>>  		return -ENOMEM;
>>>  
>>>  	private->data = of_device_get_match_data(dev);
>>> -
>>> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> -	private->config_regs = devm_ioremap_resource(dev, mem);
>>> -	if (IS_ERR(private->config_regs)) {
>>> -		ret = PTR_ERR(private->config_regs);
>>> -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
>>> -			ret);
>>> -		return ret;
>>> +	private->mmsys_dev = dev->parent;
>>> +	if (!private->mmsys_dev) {
>>> +		dev_err(dev, "Failed to get MMSYS device\n");
>>> +		return -ENODEV;
>>>  	}
>>>  
>>>  	/* Iterate over sibling DISP function blocks */
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>> index 17bc99b9f5d4..b5be63e53176 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>> @@ -39,7 +39,7 @@ struct mtk_drm_private {
>>>  
>>>  	struct device_node *mutex_node;
>>>  	struct device *mutex_dev;
>>> -	void __iomem *config_regs;
>>> +	struct device *mmsys_dev;
>>>  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
>>>  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
>>>  	const struct mtk_mmsys_driver_data *data;
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>>> index dbdfedd302fa..4b286b525cd3 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -5,8 +5,76 @@
>>>   */
>>>  
>>>  #include <linux/clk-provider.h>
>>> +#include <linux/device.h>
>>>  #include <linux/of_device.h>
>>>  #include <linux/platform_device.h>
>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>> +
>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
>>> +
>>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
>>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
>>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
>>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
>>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
>>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
>>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
>>> +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
>>> +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
>>> +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
>>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
>>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
>>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
>>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
>>> +
>>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>>> +#define DISP_REG_CONFIG_OUT_SEL			0x04c
>>> +#define DISP_REG_CONFIG_DSI_SEL			0x050
>>> +#define DISP_REG_CONFIG_DPI_SEL			0x064
>>> +
>>> +#define OVL0_MOUT_EN_COLOR0			0x1
>>> +#define OD_MOUT_EN_RDMA0			0x1
>>> +#define OD1_MOUT_EN_RDMA1			BIT(16)
>>> +#define UFOE_MOUT_EN_DSI0			0x1
>>> +#define COLOR0_SEL_IN_OVL0			0x1
>>> +#define OVL1_MOUT_EN_COLOR1			0x1
>>> +#define GAMMA_MOUT_EN_RDMA1			0x1
>>> +#define RDMA0_SOUT_DPI0				0x2
>>> +#define RDMA0_SOUT_DPI1				0x3
>>> +#define RDMA0_SOUT_DSI1				0x1
>>> +#define RDMA0_SOUT_DSI2				0x4
>>> +#define RDMA0_SOUT_DSI3				0x5
>>> +#define RDMA1_SOUT_DPI0				0x2
>>> +#define RDMA1_SOUT_DPI1				0x3
>>> +#define RDMA1_SOUT_DSI1				0x1
>>> +#define RDMA1_SOUT_DSI2				0x4
>>> +#define RDMA1_SOUT_DSI3				0x5
>>> +#define RDMA2_SOUT_DPI0				0x2
>>> +#define RDMA2_SOUT_DPI1				0x3
>>> +#define RDMA2_SOUT_DSI1				0x1
>>> +#define RDMA2_SOUT_DSI2				0x4
>>> +#define RDMA2_SOUT_DSI3				0x5
>>> +#define DPI0_SEL_IN_RDMA1			0x1
>>> +#define DPI0_SEL_IN_RDMA2			0x3
>>> +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
>>> +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
>>> +#define DSI0_SEL_IN_RDMA1			0x1
>>> +#define DSI0_SEL_IN_RDMA2			0x4
>>> +#define DSI1_SEL_IN_RDMA1			0x1
>>> +#define DSI1_SEL_IN_RDMA2			0x4
>>> +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
>>> +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
>>> +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
>>> +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
>>> +#define COLOR1_SEL_IN_OVL1			0x1
>>> +
>>> +#define OVL_MOUT_EN_RDMA			0x1
>>> +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
>>> +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
>>> +#define DSI_SEL_IN_BLS				0x0
>>> +#define DPI_SEL_IN_BLS				0x0
>>> +#define DSI_SEL_IN_RDMA				0x1
>>>  
>>>  struct mtk_mmsys_driver_data {
>>>  	const char *clk_driver;
>>> @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>>>  	.clk_driver = "clk-mt8173-mm",
>>>  };
>>>  
>>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> +					  enum mtk_ddp_comp_id next,
>>> +					  unsigned int *addr)
>>> +{
>>> +	unsigned int value;
>>> +
>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> +		value = OVL0_MOUT_EN_COLOR0;
>>> +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> +		value = OVL_MOUT_EN_RDMA;
>>> +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> +		value = OD_MOUT_EN_RDMA0;
>>> +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> +		value = UFOE_MOUT_EN_DSI0;
>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> +		value = OVL1_MOUT_EN_COLOR1;
>>> +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> +		value = GAMMA_MOUT_EN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> +		value = OD1_MOUT_EN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DPI0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DPI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DSI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DSI2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DSI3;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DSI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DSI2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DSI3;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DPI0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DPI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DPI0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DPI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DSI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DSI2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DSI3;
>>> +	} else {
>>> +		value = 0;
>>> +	}
>>> +
>>> +	return value;
>>> +}
>>> +
>>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> +					 enum mtk_ddp_comp_id next,
>>> +					 unsigned int *addr)
>>> +{
>>> +	unsigned int value;
>>> +
>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> +		value = COLOR0_SEL_IN_OVL0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI0_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI1_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI0_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> +		value = DSI1_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI2_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> +		value = DSI3_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI0_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI1_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI0_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> +		value = DSI1_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI2_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI3_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> +		value = COLOR1_SEL_IN_OVL1;
>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DSI_SEL;
>>> +		value = DSI_SEL_IN_BLS;
>>> +	} else {
>>> +		value = 0;
>>> +	}
>>> +
>>> +	return value;
>>> +}
>>> +
>>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>> +				   enum mtk_ddp_comp_id cur,
>>> +				   enum mtk_ddp_comp_id next)
>>> +{
>>> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>>> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> +		writel_relaxed(DSI_SEL_IN_RDMA,
>>> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
>>> +		writel_relaxed(DPI_SEL_IN_BLS,
>>> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
>>> +	}
>>> +}
>>> +
>>> +void mtk_mmsys_ddp_connect(struct device *dev,
>>> +			   enum mtk_ddp_comp_id cur,
>>> +			   enum mtk_ddp_comp_id next)
>>> +{
>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
>>> +	unsigned int addr, value, reg;
>>> +
>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) | value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +
>>> +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>>> +
>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) | value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +}
>>> +
>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> +			      enum mtk_ddp_comp_id cur,
>>> +			      enum mtk_ddp_comp_id next)
>>> +{
>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
>>> +	unsigned int addr, value, reg;
>>> +
>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +
>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +}
>>> +
>>>  static int mtk_mmsys_probe(struct platform_device *pdev)
>>>  {
>>>  	const struct mtk_mmsys_driver_data *data;
>>> +	struct device *dev = &pdev->dev;
>>>  	struct platform_device *clks;
>>> +	void __iomem *config_regs;
>>> +	struct resource *mem;
>>> +	int ret;
>>> +
>>> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +	config_regs = devm_ioremap_resource(dev, mem);
>>> +	if (IS_ERR(config_regs)) {
>>> +		ret = PTR_ERR(config_regs);
>>> +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
>>> +			ret);
>>> +		return ret;
>>> +	}
>>> +
>>> +	platform_set_drvdata(pdev, config_regs);
>>>  
>>>  	data = of_device_get_match_data(&pdev->dev);
>>>  
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> new file mode 100644
>>> index 000000000000..7bab5d9a3d31
>>> --- /dev/null
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -0,0 +1,20 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>> +/*
>>> + * Copyright (c) 2015 MediaTek Inc.
>>> + */
>>> +
>>> +#ifndef __MTK_MMSYS_H
>>> +#define __MTK_MMSYS_H
>>> +
>>> +enum mtk_ddp_comp_id;
>>> +struct device;
>>> +
>>> +void mtk_mmsys_ddp_connect(struct device *dev,
>>> +			   enum mtk_ddp_comp_id cur,
>>> +			   enum mtk_ddp_comp_id next);
>>> +
>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> +			      enum mtk_ddp_comp_id cur,
>>> +			      enum mtk_ddp_comp_id next);
>>> +
>>> +#endif /* __MTK_MMSYS_H */
>>>
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-26 11:54       ` Matthias Brugger
@ 2020-03-26 14:51         ` CK Hu
  2020-03-26 15:45           ` Matthias Brugger
  0 siblings, 1 reply; 16+ messages in thread
From: CK Hu @ 2020-03-26 14:51 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, Allison Randal, mtk01761, linux-media,
	devicetree, p.zabel, frank-w, Seiya Wang, sean.wang, Houlong Wei,
	robh+dt, linux-mediatek, hsinyi, Matthias Brugger,
	Thomas Gleixner, Mauro Carvalho Chehab, linux-arm-kernel, sboyd,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg, Enric Balletbo i Serra

Hi, Matthias:

On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote:
> Hi CK,
> 
> On 26/03/2020 00:05, CK Hu wrote:
> > Hi, Matthias:
> > 
> > On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
> >>
> >> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
> >>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> >>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> >>> Those functions will allow DRM driver and others to control the data
> >>> path routing.
> >>>
> >>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> >>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> >>> Acked-by: CK Hu <ck.hu@mediatek.com>
> >>
> >> This patch does not apply against v5.6-rc1.
> >> Please rebase as this is a quite big patch and it won't be easy to do that by hand.
> > 
> > I think this patch depends on [1] which has been acked by me and I have
> > not picked it. The simple way is that you pick [1] first and then pick
> > this series.
> > 
> > [1] 
> > https://patchwork.kernel.org/patch/11406227/
> > 
> 
> You would need to provide a stable tag for me that I can merge into my tree. You
> can also try to merge my for-next [1] which has the newest version from Enric.
> If you see any merge conflict, then we have to do something about it :)
> 
> Regards,
> Matthias
> 
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> 

You have applied this series, so I would not apply other patches which
would conflict with this series. After this series land on main stream
(wish it happen in this merge window), I would rebase other patch on
main stream.

Regards,
CK

> > Regards,
> > CK
> > 
> >>
> >> Regards,
> >> Matthias
> >>
> >>> ---
> >>>
> >>> Changes in v12: None
> >>> Changes in v10:
> >>> - Select CONFIG_MTK_MMSYS (CK)
> >>> - Pass device pointer of mmsys device instead of config regs (CK)
> >>>
> >>> Changes in v9:
> >>> - Introduced a new patch to move routing control into mmsys driver.
> >>> - Removed the patch to use regmap as is not needed anymore.
> >>>
> >>> Changes in v8: None
> >>> Changes in v7: None
> >>>
> >>>  drivers/gpu/drm/mediatek/Kconfig        |   1 +
> >>>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
> >>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
> >>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
> >>>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
> >>>  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
> >>>  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
> >>>  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
> >>>  8 files changed, 316 insertions(+), 282 deletions(-)
> >>>  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
> >>>
> >>> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> >>> index fa5ffc4fe823..c420f5a3d33b 100644
> >>> --- a/drivers/gpu/drm/mediatek/Kconfig
> >>> +++ b/drivers/gpu/drm/mediatek/Kconfig
> >>> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
> >>>  	select DRM_MIPI_DSI
> >>>  	select DRM_PANEL
> >>>  	select MEMORY
> >>> +	select MTK_MMSYS
> >>>  	select MTK_SMI
> >>>  	select VIDEOMODE_HELPERS
> >>>  	help
> >>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >>> index 0e05683d7b53..579a5a5d4472 100644
> >>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >>> @@ -6,6 +6,7 @@
> >>>  #include <linux/clk.h>
> >>>  #include <linux/pm_runtime.h>
> >>>  #include <linux/soc/mediatek/mtk-cmdq.h>
> >>> +#include <linux/soc/mediatek/mtk-mmsys.h>
> >>>  
> >>>  #include <asm/barrier.h>
> >>>  #include <soc/mediatek/smi.h>
> >>> @@ -28,7 +29,7 @@
> >>>   * @enabled: records whether crtc_enable succeeded
> >>>   * @planes: array of 4 drm_plane structures, one for each overlay plane
> >>>   * @pending_planes: whether any plane has pending changes to be applied
> >>> - * @config_regs: memory mapped mmsys configuration register space
> >>> + * @mmsys_dev: pointer to the mmsys device for configuration registers
> >>>   * @mutex: handle to one of the ten disp_mutex streams
> >>>   * @ddp_comp_nr: number of components in ddp_comp
> >>>   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
> >>> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
> >>>  	u32				cmdq_event;
> >>>  #endif
> >>>  
> >>> -	void __iomem			*config_regs;
> >>> +	struct device			*mmsys_dev;
> >>>  	struct mtk_disp_mutex		*mutex;
> >>>  	unsigned int			ddp_comp_nr;
> >>>  	struct mtk_ddp_comp		**ddp_comp;
> >>> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> >>>  	}
> >>>  
> >>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> >>> -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> >>> -					 mtk_crtc->ddp_comp[i]->id,
> >>> -					 mtk_crtc->ddp_comp[i + 1]->id);
> >>> +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> >>> +				      mtk_crtc->ddp_comp[i]->id,
> >>> +				      mtk_crtc->ddp_comp[i + 1]->id);
> >>>  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
> >>>  					mtk_crtc->ddp_comp[i]->id);
> >>>  	}
> >>> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
> >>>  					   mtk_crtc->ddp_comp[i]->id);
> >>>  	mtk_disp_mutex_disable(mtk_crtc->mutex);
> >>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> >>> -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
> >>> -					      mtk_crtc->ddp_comp[i]->id,
> >>> -					      mtk_crtc->ddp_comp[i + 1]->id);
> >>> +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
> >>> +					 mtk_crtc->ddp_comp[i]->id,
> >>> +					 mtk_crtc->ddp_comp[i + 1]->id);
> >>>  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
> >>>  					   mtk_crtc->ddp_comp[i]->id);
> >>>  	}
> >>> @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >>>  	if (!mtk_crtc)
> >>>  		return -ENOMEM;
> >>>  
> >>> -	mtk_crtc->config_regs = priv->config_regs;
> >>> +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
> >>>  	mtk_crtc->ddp_comp_nr = path_len;
> >>>  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
> >>>  						sizeof(*mtk_crtc->ddp_comp),
> >>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >>> index b885f60f474c..014c1bbe1df2 100644
> >>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >>> @@ -13,26 +13,6 @@
> >>>  #include "mtk_drm_ddp.h"
> >>>  #include "mtk_drm_ddp_comp.h"
> >>>  
> >>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> >>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> >>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> >>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> >>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> >>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> >>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> >>> -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> >>> -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> >>> -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> >>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> >>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> >>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> >>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> >>> -
> >>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> >>> -#define DISP_REG_CONFIG_OUT_SEL			0x04c
> >>> -#define DISP_REG_CONFIG_DSI_SEL			0x050
> >>> -#define DISP_REG_CONFIG_DPI_SEL			0x064
> >>> -
> >>>  #define MT2701_DISP_MUTEX0_MOD0			0x2c
> >>>  #define MT2701_DISP_MUTEX0_SOF0			0x30
> >>>  
> >>> @@ -94,48 +74,6 @@
> >>>  #define MUTEX_SOF_DSI2			5
> >>>  #define MUTEX_SOF_DSI3			6
> >>>  
> >>> -#define OVL0_MOUT_EN_COLOR0		0x1
> >>> -#define OD_MOUT_EN_RDMA0		0x1
> >>> -#define OD1_MOUT_EN_RDMA1		BIT(16)
> >>> -#define UFOE_MOUT_EN_DSI0		0x1
> >>> -#define COLOR0_SEL_IN_OVL0		0x1
> >>> -#define OVL1_MOUT_EN_COLOR1		0x1
> >>> -#define GAMMA_MOUT_EN_RDMA1		0x1
> >>> -#define RDMA0_SOUT_DPI0			0x2
> >>> -#define RDMA0_SOUT_DPI1			0x3
> >>> -#define RDMA0_SOUT_DSI1			0x1
> >>> -#define RDMA0_SOUT_DSI2			0x4
> >>> -#define RDMA0_SOUT_DSI3			0x5
> >>> -#define RDMA1_SOUT_DPI0			0x2
> >>> -#define RDMA1_SOUT_DPI1			0x3
> >>> -#define RDMA1_SOUT_DSI1			0x1
> >>> -#define RDMA1_SOUT_DSI2			0x4
> >>> -#define RDMA1_SOUT_DSI3			0x5
> >>> -#define RDMA2_SOUT_DPI0			0x2
> >>> -#define RDMA2_SOUT_DPI1			0x3
> >>> -#define RDMA2_SOUT_DSI1			0x1
> >>> -#define RDMA2_SOUT_DSI2			0x4
> >>> -#define RDMA2_SOUT_DSI3			0x5
> >>> -#define DPI0_SEL_IN_RDMA1		0x1
> >>> -#define DPI0_SEL_IN_RDMA2		0x3
> >>> -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> >>> -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> >>> -#define DSI0_SEL_IN_RDMA1		0x1
> >>> -#define DSI0_SEL_IN_RDMA2		0x4
> >>> -#define DSI1_SEL_IN_RDMA1		0x1
> >>> -#define DSI1_SEL_IN_RDMA2		0x4
> >>> -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> >>> -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
> >>> -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> >>> -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
> >>> -#define COLOR1_SEL_IN_OVL1		0x1
> >>> -
> >>> -#define OVL_MOUT_EN_RDMA		0x1
> >>> -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> >>> -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
> >>> -#define DSI_SEL_IN_BLS			0x0
> >>> -#define DPI_SEL_IN_BLS			0x0
> >>> -#define DSI_SEL_IN_RDMA			0x1
> >>>  
> >>>  struct mtk_disp_mutex {
> >>>  	int id;
> >>> @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> >>>  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> >>>  };
> >>>  
> >>> -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> >>> -				    enum mtk_ddp_comp_id next,
> >>> -				    unsigned int *addr)
> >>> -{
> >>> -	unsigned int value;
> >>> -
> >>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> >>> -		value = OVL0_MOUT_EN_COLOR0;
> >>> -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> >>> -		value = OVL_MOUT_EN_RDMA;
> >>> -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>> -		value = OD_MOUT_EN_RDMA0;
> >>> -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> >>> -		value = UFOE_MOUT_EN_DSI0;
> >>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> >>> -		value = OVL1_MOUT_EN_COLOR1;
> >>> -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> >>> -		value = GAMMA_MOUT_EN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>> -		value = OD1_MOUT_EN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> -		value = RDMA0_SOUT_DPI0;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> -		value = RDMA0_SOUT_DPI1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> -		value = RDMA0_SOUT_DSI1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> -		value = RDMA0_SOUT_DSI2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> -		value = RDMA0_SOUT_DSI3;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> -		value = RDMA1_SOUT_DSI1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> -		value = RDMA1_SOUT_DSI2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> -		value = RDMA1_SOUT_DSI3;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> -		value = RDMA1_SOUT_DPI0;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> -		value = RDMA1_SOUT_DPI1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> -		value = RDMA2_SOUT_DPI0;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> -		value = RDMA2_SOUT_DPI1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> -		value = RDMA2_SOUT_DSI1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> -		value = RDMA2_SOUT_DSI2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> -		value = RDMA2_SOUT_DSI3;
> >>> -	} else {
> >>> -		value = 0;
> >>> -	}
> >>> -
> >>> -	return value;
> >>> -}
> >>> -
> >>> -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> >>> -				   enum mtk_ddp_comp_id next,
> >>> -				   unsigned int *addr)
> >>> -{
> >>> -	unsigned int value;
> >>> -
> >>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> >>> -		value = COLOR0_SEL_IN_OVL0;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> -		value = DPI0_SEL_IN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> -		value = DPI1_SEL_IN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> >>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> -		value = DSI0_SEL_IN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>> -		value = DSI1_SEL_IN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> -		value = DSI2_SEL_IN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>> -		value = DSI3_SEL_IN_RDMA1;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> -		value = DPI0_SEL_IN_RDMA2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> -		value = DPI1_SEL_IN_RDMA2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> >>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> -		value = DSI0_SEL_IN_RDMA2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>> -		value = DSI1_SEL_IN_RDMA2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> -		value = DSI2_SEL_IN_RDMA2;
> >>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> -		value = DSI3_SEL_IN_RDMA2;
> >>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>> -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> >>> -		value = COLOR1_SEL_IN_OVL1;
> >>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>> -		*addr = DISP_REG_CONFIG_DSI_SEL;
> >>> -		value = DSI_SEL_IN_BLS;
> >>> -	} else {
> >>> -		value = 0;
> >>> -	}
> >>> -
> >>> -	return value;
> >>> -}
> >>> -
> >>> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
> >>> -			     enum mtk_ddp_comp_id cur,
> >>> -			     enum mtk_ddp_comp_id next)
> >>> -{
> >>> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>> -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> >>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> >>> -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> >>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>> -		writel_relaxed(DSI_SEL_IN_RDMA,
> >>> -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> >>> -		writel_relaxed(DPI_SEL_IN_BLS,
> >>> -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> >>> -	}
> >>> -}
> >>> -
> >>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> >>> -			      enum mtk_ddp_comp_id cur,
> >>> -			      enum mtk_ddp_comp_id next)
> >>> -{
> >>> -	unsigned int addr, value, reg;
> >>> -
> >>> -	value = mtk_ddp_mout_en(cur, next, &addr);
> >>> -	if (value) {
> >>> -		reg = readl_relaxed(config_regs + addr) | value;
> >>> -		writel_relaxed(reg, config_regs + addr);
> >>> -	}
> >>> -
> >>> -	mtk_ddp_sout_sel(config_regs, cur, next);
> >>> -
> >>> -	value = mtk_ddp_sel_in(cur, next, &addr);
> >>> -	if (value) {
> >>> -		reg = readl_relaxed(config_regs + addr) | value;
> >>> -		writel_relaxed(reg, config_regs + addr);
> >>> -	}
> >>> -}
> >>> -
> >>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> >>> -				   enum mtk_ddp_comp_id cur,
> >>> -				   enum mtk_ddp_comp_id next)
> >>> -{
> >>> -	unsigned int addr, value, reg;
> >>> -
> >>> -	value = mtk_ddp_mout_en(cur, next, &addr);
> >>> -	if (value) {
> >>> -		reg = readl_relaxed(config_regs + addr) & ~value;
> >>> -		writel_relaxed(reg, config_regs + addr);
> >>> -	}
> >>> -
> >>> -	value = mtk_ddp_sel_in(cur, next, &addr);
> >>> -	if (value) {
> >>> -		reg = readl_relaxed(config_regs + addr) & ~value;
> >>> -		writel_relaxed(reg, config_regs + addr);
> >>> -	}
> >>> -}
> >>> -
> >>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
> >>>  {
> >>>  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
> >>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> >>> index 827be424a148..6b691a57be4a 100644
> >>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> >>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> >>> @@ -12,13 +12,6 @@ struct regmap;
> >>>  struct device;
> >>>  struct mtk_disp_mutex;
> >>>  
> >>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> >>> -			      enum mtk_ddp_comp_id cur,
> >>> -			      enum mtk_ddp_comp_id next);
> >>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> >>> -				   enum mtk_ddp_comp_id cur,
> >>> -				   enum mtk_ddp_comp_id next);
> >>> -
> >>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
> >>>  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
> >>>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> >>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> >>> index 8e2d3cb62ad5..208f9c5256ef 100644
> >>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> >>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> >>> @@ -10,6 +10,7 @@
> >>>  #include <linux/of_address.h>
> >>>  #include <linux/of_platform.h>
> >>>  #include <linux/pm_runtime.h>
> >>> +#include <linux/soc/mediatek/mtk-mmsys.h>
> >>>  #include <linux/dma-mapping.h>
> >>>  
> >>>  #include <drm/drm_atomic.h>
> >>> @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >>>  {
> >>>  	struct device *dev = &pdev->dev;
> >>>  	struct mtk_drm_private *private;
> >>> -	struct resource *mem;
> >>>  	struct device_node *node;
> >>>  	struct component_match *match = NULL;
> >>>  	int ret;
> >>> @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >>>  		return -ENOMEM;
> >>>  
> >>>  	private->data = of_device_get_match_data(dev);
> >>> -
> >>> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>> -	private->config_regs = devm_ioremap_resource(dev, mem);
> >>> -	if (IS_ERR(private->config_regs)) {
> >>> -		ret = PTR_ERR(private->config_regs);
> >>> -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> >>> -			ret);
> >>> -		return ret;
> >>> +	private->mmsys_dev = dev->parent;
> >>> +	if (!private->mmsys_dev) {
> >>> +		dev_err(dev, "Failed to get MMSYS device\n");
> >>> +		return -ENODEV;
> >>>  	}
> >>>  
> >>>  	/* Iterate over sibling DISP function blocks */
> >>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> >>> index 17bc99b9f5d4..b5be63e53176 100644
> >>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> >>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> >>> @@ -39,7 +39,7 @@ struct mtk_drm_private {
> >>>  
> >>>  	struct device_node *mutex_node;
> >>>  	struct device *mutex_dev;
> >>> -	void __iomem *config_regs;
> >>> +	struct device *mmsys_dev;
> >>>  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
> >>>  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
> >>>  	const struct mtk_mmsys_driver_data *data;
> >>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> >>> index dbdfedd302fa..4b286b525cd3 100644
> >>> --- a/drivers/soc/mediatek/mtk-mmsys.c
> >>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> >>> @@ -5,8 +5,76 @@
> >>>   */
> >>>  
> >>>  #include <linux/clk-provider.h>
> >>> +#include <linux/device.h>
> >>>  #include <linux/of_device.h>
> >>>  #include <linux/platform_device.h>
> >>> +#include <linux/soc/mediatek/mtk-mmsys.h>
> >>> +
> >>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
> >>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
> >>> +
> >>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> >>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> >>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> >>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> >>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> >>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> >>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> >>> +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> >>> +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> >>> +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> >>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> >>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> >>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> >>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> >>> +
> >>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> >>> +#define DISP_REG_CONFIG_OUT_SEL			0x04c
> >>> +#define DISP_REG_CONFIG_DSI_SEL			0x050
> >>> +#define DISP_REG_CONFIG_DPI_SEL			0x064
> >>> +
> >>> +#define OVL0_MOUT_EN_COLOR0			0x1
> >>> +#define OD_MOUT_EN_RDMA0			0x1
> >>> +#define OD1_MOUT_EN_RDMA1			BIT(16)
> >>> +#define UFOE_MOUT_EN_DSI0			0x1
> >>> +#define COLOR0_SEL_IN_OVL0			0x1
> >>> +#define OVL1_MOUT_EN_COLOR1			0x1
> >>> +#define GAMMA_MOUT_EN_RDMA1			0x1
> >>> +#define RDMA0_SOUT_DPI0				0x2
> >>> +#define RDMA0_SOUT_DPI1				0x3
> >>> +#define RDMA0_SOUT_DSI1				0x1
> >>> +#define RDMA0_SOUT_DSI2				0x4
> >>> +#define RDMA0_SOUT_DSI3				0x5
> >>> +#define RDMA1_SOUT_DPI0				0x2
> >>> +#define RDMA1_SOUT_DPI1				0x3
> >>> +#define RDMA1_SOUT_DSI1				0x1
> >>> +#define RDMA1_SOUT_DSI2				0x4
> >>> +#define RDMA1_SOUT_DSI3				0x5
> >>> +#define RDMA2_SOUT_DPI0				0x2
> >>> +#define RDMA2_SOUT_DPI1				0x3
> >>> +#define RDMA2_SOUT_DSI1				0x1
> >>> +#define RDMA2_SOUT_DSI2				0x4
> >>> +#define RDMA2_SOUT_DSI3				0x5
> >>> +#define DPI0_SEL_IN_RDMA1			0x1
> >>> +#define DPI0_SEL_IN_RDMA2			0x3
> >>> +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
> >>> +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
> >>> +#define DSI0_SEL_IN_RDMA1			0x1
> >>> +#define DSI0_SEL_IN_RDMA2			0x4
> >>> +#define DSI1_SEL_IN_RDMA1			0x1
> >>> +#define DSI1_SEL_IN_RDMA2			0x4
> >>> +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
> >>> +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
> >>> +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
> >>> +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
> >>> +#define COLOR1_SEL_IN_OVL1			0x1
> >>> +
> >>> +#define OVL_MOUT_EN_RDMA			0x1
> >>> +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
> >>> +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
> >>> +#define DSI_SEL_IN_BLS				0x0
> >>> +#define DPI_SEL_IN_BLS				0x0
> >>> +#define DSI_SEL_IN_RDMA				0x1
> >>>  
> >>>  struct mtk_mmsys_driver_data {
> >>>  	const char *clk_driver;
> >>> @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> >>>  	.clk_driver = "clk-mt8173-mm",
> >>>  };
> >>>  
> >>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> >>> +					  enum mtk_ddp_comp_id next,
> >>> +					  unsigned int *addr)
> >>> +{
> >>> +	unsigned int value;
> >>> +
> >>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> >>> +		value = OVL0_MOUT_EN_COLOR0;
> >>> +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> >>> +		value = OVL_MOUT_EN_RDMA;
> >>> +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>> +		value = OD_MOUT_EN_RDMA0;
> >>> +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> >>> +		value = UFOE_MOUT_EN_DSI0;
> >>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> >>> +		value = OVL1_MOUT_EN_COLOR1;
> >>> +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> >>> +		value = GAMMA_MOUT_EN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>> +		value = OD1_MOUT_EN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> +		value = RDMA0_SOUT_DPI0;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> +		value = RDMA0_SOUT_DPI1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> +		value = RDMA0_SOUT_DSI1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> +		value = RDMA0_SOUT_DSI2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>> +		value = RDMA0_SOUT_DSI3;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> +		value = RDMA1_SOUT_DSI1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> +		value = RDMA1_SOUT_DSI2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> +		value = RDMA1_SOUT_DSI3;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> +		value = RDMA1_SOUT_DPI0;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>> +		value = RDMA1_SOUT_DPI1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> +		value = RDMA2_SOUT_DPI0;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> +		value = RDMA2_SOUT_DPI1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> +		value = RDMA2_SOUT_DSI1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> +		value = RDMA2_SOUT_DSI2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>> +		value = RDMA2_SOUT_DSI3;
> >>> +	} else {
> >>> +		value = 0;
> >>> +	}
> >>> +
> >>> +	return value;
> >>> +}
> >>> +
> >>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> >>> +					 enum mtk_ddp_comp_id next,
> >>> +					 unsigned int *addr)
> >>> +{
> >>> +	unsigned int value;
> >>> +
> >>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> >>> +		value = COLOR0_SEL_IN_OVL0;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> +		value = DPI0_SEL_IN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> +		value = DPI1_SEL_IN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> >>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> +		value = DSI0_SEL_IN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>> +		value = DSI1_SEL_IN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> +		value = DSI2_SEL_IN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>> +		value = DSI3_SEL_IN_RDMA1;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> +		value = DPI0_SEL_IN_RDMA2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>> +		value = DPI1_SEL_IN_RDMA2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> >>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> +		value = DSI0_SEL_IN_RDMA2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>> +		value = DSI1_SEL_IN_RDMA2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> +		value = DSI2_SEL_IN_RDMA2;
> >>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>> +		value = DSI3_SEL_IN_RDMA2;
> >>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>> +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> >>> +		value = COLOR1_SEL_IN_OVL1;
> >>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>> +		*addr = DISP_REG_CONFIG_DSI_SEL;
> >>> +		value = DSI_SEL_IN_BLS;
> >>> +	} else {
> >>> +		value = 0;
> >>> +	}
> >>> +
> >>> +	return value;
> >>> +}
> >>> +
> >>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> >>> +				   enum mtk_ddp_comp_id cur,
> >>> +				   enum mtk_ddp_comp_id next)
> >>> +{
> >>> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> >>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> >>> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> >>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>> +		writel_relaxed(DSI_SEL_IN_RDMA,
> >>> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> >>> +		writel_relaxed(DPI_SEL_IN_BLS,
> >>> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> >>> +	}
> >>> +}
> >>> +
> >>> +void mtk_mmsys_ddp_connect(struct device *dev,
> >>> +			   enum mtk_ddp_comp_id cur,
> >>> +			   enum mtk_ddp_comp_id next)
> >>> +{
> >>> +	void __iomem *config_regs = dev_get_drvdata(dev);
> >>> +	unsigned int addr, value, reg;
> >>> +
> >>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> >>> +	if (value) {
> >>> +		reg = readl_relaxed(config_regs + addr) | value;
> >>> +		writel_relaxed(reg, config_regs + addr);
> >>> +	}
> >>> +
> >>> +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> >>> +
> >>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> >>> +	if (value) {
> >>> +		reg = readl_relaxed(config_regs + addr) | value;
> >>> +		writel_relaxed(reg, config_regs + addr);
> >>> +	}
> >>> +}
> >>> +
> >>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> >>> +			      enum mtk_ddp_comp_id cur,
> >>> +			      enum mtk_ddp_comp_id next)
> >>> +{
> >>> +	void __iomem *config_regs = dev_get_drvdata(dev);
> >>> +	unsigned int addr, value, reg;
> >>> +
> >>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> >>> +	if (value) {
> >>> +		reg = readl_relaxed(config_regs + addr) & ~value;
> >>> +		writel_relaxed(reg, config_regs + addr);
> >>> +	}
> >>> +
> >>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> >>> +	if (value) {
> >>> +		reg = readl_relaxed(config_regs + addr) & ~value;
> >>> +		writel_relaxed(reg, config_regs + addr);
> >>> +	}
> >>> +}
> >>> +
> >>>  static int mtk_mmsys_probe(struct platform_device *pdev)
> >>>  {
> >>>  	const struct mtk_mmsys_driver_data *data;
> >>> +	struct device *dev = &pdev->dev;
> >>>  	struct platform_device *clks;
> >>> +	void __iomem *config_regs;
> >>> +	struct resource *mem;
> >>> +	int ret;
> >>> +
> >>> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>> +	config_regs = devm_ioremap_resource(dev, mem);
> >>> +	if (IS_ERR(config_regs)) {
> >>> +		ret = PTR_ERR(config_regs);
> >>> +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> >>> +			ret);
> >>> +		return ret;
> >>> +	}
> >>> +
> >>> +	platform_set_drvdata(pdev, config_regs);
> >>>  
> >>>  	data = of_device_get_match_data(&pdev->dev);
> >>>  
> >>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> new file mode 100644
> >>> index 000000000000..7bab5d9a3d31
> >>> --- /dev/null
> >>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>> @@ -0,0 +1,20 @@
> >>> +/* SPDX-License-Identifier: GPL-2.0-only */
> >>> +/*
> >>> + * Copyright (c) 2015 MediaTek Inc.
> >>> + */
> >>> +
> >>> +#ifndef __MTK_MMSYS_H
> >>> +#define __MTK_MMSYS_H
> >>> +
> >>> +enum mtk_ddp_comp_id;
> >>> +struct device;
> >>> +
> >>> +void mtk_mmsys_ddp_connect(struct device *dev,
> >>> +			   enum mtk_ddp_comp_id cur,
> >>> +			   enum mtk_ddp_comp_id next);
> >>> +
> >>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> >>> +			      enum mtk_ddp_comp_id cur,
> >>> +			      enum mtk_ddp_comp_id next);
> >>> +
> >>> +#endif /* __MTK_MMSYS_H */
> >>>
> > 
> 
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-26 14:51         ` CK Hu
@ 2020-03-26 15:45           ` Matthias Brugger
  2020-03-27  1:55             ` CK Hu
  0 siblings, 1 reply; 16+ messages in thread
From: Matthias Brugger @ 2020-03-26 15:45 UTC (permalink / raw)
  To: CK Hu
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, Allison Randal, mtk01761, linux-media,
	devicetree, p.zabel, frank-w, Seiya Wang, sean.wang, Houlong Wei,
	robh+dt, linux-mediatek, hsinyi, Matthias Brugger,
	Thomas Gleixner, Mauro Carvalho Chehab, linux-arm-kernel, sboyd,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg, Enric Balletbo i Serra



On 26/03/2020 15:51, CK Hu wrote:
> Hi, Matthias:
> 
> On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote:
>> Hi CK,
>>
>> On 26/03/2020 00:05, CK Hu wrote:
>>> Hi, Matthias:
>>>
>>> On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
>>>>
>>>> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
>>>>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
>>>>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
>>>>> Those functions will allow DRM driver and others to control the data
>>>>> path routing.
>>>>>
>>>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>>>>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
>>>>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>>>>> Acked-by: CK Hu <ck.hu@mediatek.com>
>>>>
>>>> This patch does not apply against v5.6-rc1.
>>>> Please rebase as this is a quite big patch and it won't be easy to do that by hand.
>>>
>>> I think this patch depends on [1] which has been acked by me and I have
>>> not picked it. The simple way is that you pick [1] first and then pick
>>> this series.
>>>
>>> [1] 
>>> https://patchwork.kernel.org/patch/11406227/
>>>
>>
>> You would need to provide a stable tag for me that I can merge into my tree. You
>> can also try to merge my for-next [1] which has the newest version from Enric.
>> If you see any merge conflict, then we have to do something about it :)
>>
>> Regards,
>> Matthias
>>
>> [1]
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
>>
> 
> You have applied this series, so I would not apply other patches which
> would conflict with this series. After this series land on main stream
> (wish it happen in this merge window), I would rebase other patch on
> main stream.
> 

I haven't (yet) send the pull request. If you want to bring in your patches in
v5.7 as well we can find a solution to that. Shall I provide you with a stable
branch which you can merge? This way you can add all your patches in the pull
request as well and we don't have to wait for v5.8 to get things into mainline.

Let me know and I'll provide you with a stable branch.

Regards,
Matthias

> Regards,
> CK
> 
>>> Regards,
>>> CK
>>>
>>>>
>>>> Regards,
>>>> Matthias
>>>>
>>>>> ---
>>>>>
>>>>> Changes in v12: None
>>>>> Changes in v10:
>>>>> - Select CONFIG_MTK_MMSYS (CK)
>>>>> - Pass device pointer of mmsys device instead of config regs (CK)
>>>>>
>>>>> Changes in v9:
>>>>> - Introduced a new patch to move routing control into mmsys driver.
>>>>> - Removed the patch to use regmap as is not needed anymore.
>>>>>
>>>>> Changes in v8: None
>>>>> Changes in v7: None
>>>>>
>>>>>  drivers/gpu/drm/mediatek/Kconfig        |   1 +
>>>>>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
>>>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
>>>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
>>>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
>>>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
>>>>>  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
>>>>>  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
>>>>>  8 files changed, 316 insertions(+), 282 deletions(-)
>>>>>  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
>>>>>
>>>>> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
>>>>> index fa5ffc4fe823..c420f5a3d33b 100644
>>>>> --- a/drivers/gpu/drm/mediatek/Kconfig
>>>>> +++ b/drivers/gpu/drm/mediatek/Kconfig
>>>>> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
>>>>>  	select DRM_MIPI_DSI
>>>>>  	select DRM_PANEL
>>>>>  	select MEMORY
>>>>> +	select MTK_MMSYS
>>>>>  	select MTK_SMI
>>>>>  	select VIDEOMODE_HELPERS
>>>>>  	help
>>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>>>> index 0e05683d7b53..579a5a5d4472 100644
>>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>>>> @@ -6,6 +6,7 @@
>>>>>  #include <linux/clk.h>
>>>>>  #include <linux/pm_runtime.h>
>>>>>  #include <linux/soc/mediatek/mtk-cmdq.h>
>>>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>>>  
>>>>>  #include <asm/barrier.h>
>>>>>  #include <soc/mediatek/smi.h>
>>>>> @@ -28,7 +29,7 @@
>>>>>   * @enabled: records whether crtc_enable succeeded
>>>>>   * @planes: array of 4 drm_plane structures, one for each overlay plane
>>>>>   * @pending_planes: whether any plane has pending changes to be applied
>>>>> - * @config_regs: memory mapped mmsys configuration register space
>>>>> + * @mmsys_dev: pointer to the mmsys device for configuration registers
>>>>>   * @mutex: handle to one of the ten disp_mutex streams
>>>>>   * @ddp_comp_nr: number of components in ddp_comp
>>>>>   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
>>>>> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
>>>>>  	u32				cmdq_event;
>>>>>  #endif
>>>>>  
>>>>> -	void __iomem			*config_regs;
>>>>> +	struct device			*mmsys_dev;
>>>>>  	struct mtk_disp_mutex		*mutex;
>>>>>  	unsigned int			ddp_comp_nr;
>>>>>  	struct mtk_ddp_comp		**ddp_comp;
>>>>> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
>>>>>  	}
>>>>>  
>>>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
>>>>> -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
>>>>> -					 mtk_crtc->ddp_comp[i]->id,
>>>>> -					 mtk_crtc->ddp_comp[i + 1]->id);
>>>>> +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
>>>>> +				      mtk_crtc->ddp_comp[i]->id,
>>>>> +				      mtk_crtc->ddp_comp[i + 1]->id);
>>>>>  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
>>>>>  					mtk_crtc->ddp_comp[i]->id);
>>>>>  	}
>>>>> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
>>>>>  					   mtk_crtc->ddp_comp[i]->id);
>>>>>  	mtk_disp_mutex_disable(mtk_crtc->mutex);
>>>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
>>>>> -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
>>>>> -					      mtk_crtc->ddp_comp[i]->id,
>>>>> -					      mtk_crtc->ddp_comp[i + 1]->id);
>>>>> +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
>>>>> +					 mtk_crtc->ddp_comp[i]->id,
>>>>> +					 mtk_crtc->ddp_comp[i + 1]->id);
>>>>>  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
>>>>>  					   mtk_crtc->ddp_comp[i]->id);
>>>>>  	}
>>>>> @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>>>>>  	if (!mtk_crtc)
>>>>>  		return -ENOMEM;
>>>>>  
>>>>> -	mtk_crtc->config_regs = priv->config_regs;
>>>>> +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
>>>>>  	mtk_crtc->ddp_comp_nr = path_len;
>>>>>  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
>>>>>  						sizeof(*mtk_crtc->ddp_comp),
>>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>>>> index b885f60f474c..014c1bbe1df2 100644
>>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>>>> @@ -13,26 +13,6 @@
>>>>>  #include "mtk_drm_ddp.h"
>>>>>  #include "mtk_drm_ddp_comp.h"
>>>>>  
>>>>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
>>>>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
>>>>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
>>>>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
>>>>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
>>>>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
>>>>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
>>>>> -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
>>>>> -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
>>>>> -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
>>>>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
>>>>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
>>>>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
>>>>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
>>>>> -
>>>>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>>>>> -#define DISP_REG_CONFIG_OUT_SEL			0x04c
>>>>> -#define DISP_REG_CONFIG_DSI_SEL			0x050
>>>>> -#define DISP_REG_CONFIG_DPI_SEL			0x064
>>>>> -
>>>>>  #define MT2701_DISP_MUTEX0_MOD0			0x2c
>>>>>  #define MT2701_DISP_MUTEX0_SOF0			0x30
>>>>>  
>>>>> @@ -94,48 +74,6 @@
>>>>>  #define MUTEX_SOF_DSI2			5
>>>>>  #define MUTEX_SOF_DSI3			6
>>>>>  
>>>>> -#define OVL0_MOUT_EN_COLOR0		0x1
>>>>> -#define OD_MOUT_EN_RDMA0		0x1
>>>>> -#define OD1_MOUT_EN_RDMA1		BIT(16)
>>>>> -#define UFOE_MOUT_EN_DSI0		0x1
>>>>> -#define COLOR0_SEL_IN_OVL0		0x1
>>>>> -#define OVL1_MOUT_EN_COLOR1		0x1
>>>>> -#define GAMMA_MOUT_EN_RDMA1		0x1
>>>>> -#define RDMA0_SOUT_DPI0			0x2
>>>>> -#define RDMA0_SOUT_DPI1			0x3
>>>>> -#define RDMA0_SOUT_DSI1			0x1
>>>>> -#define RDMA0_SOUT_DSI2			0x4
>>>>> -#define RDMA0_SOUT_DSI3			0x5
>>>>> -#define RDMA1_SOUT_DPI0			0x2
>>>>> -#define RDMA1_SOUT_DPI1			0x3
>>>>> -#define RDMA1_SOUT_DSI1			0x1
>>>>> -#define RDMA1_SOUT_DSI2			0x4
>>>>> -#define RDMA1_SOUT_DSI3			0x5
>>>>> -#define RDMA2_SOUT_DPI0			0x2
>>>>> -#define RDMA2_SOUT_DPI1			0x3
>>>>> -#define RDMA2_SOUT_DSI1			0x1
>>>>> -#define RDMA2_SOUT_DSI2			0x4
>>>>> -#define RDMA2_SOUT_DSI3			0x5
>>>>> -#define DPI0_SEL_IN_RDMA1		0x1
>>>>> -#define DPI0_SEL_IN_RDMA2		0x3
>>>>> -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
>>>>> -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
>>>>> -#define DSI0_SEL_IN_RDMA1		0x1
>>>>> -#define DSI0_SEL_IN_RDMA2		0x4
>>>>> -#define DSI1_SEL_IN_RDMA1		0x1
>>>>> -#define DSI1_SEL_IN_RDMA2		0x4
>>>>> -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
>>>>> -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
>>>>> -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
>>>>> -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
>>>>> -#define COLOR1_SEL_IN_OVL1		0x1
>>>>> -
>>>>> -#define OVL_MOUT_EN_RDMA		0x1
>>>>> -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
>>>>> -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
>>>>> -#define DSI_SEL_IN_BLS			0x0
>>>>> -#define DPI_SEL_IN_BLS			0x0
>>>>> -#define DSI_SEL_IN_RDMA			0x1
>>>>>  
>>>>>  struct mtk_disp_mutex {
>>>>>  	int id;
>>>>> @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
>>>>>  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
>>>>>  };
>>>>>  
>>>>> -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>>>> -				    enum mtk_ddp_comp_id next,
>>>>> -				    unsigned int *addr)
>>>>> -{
>>>>> -	unsigned int value;
>>>>> -
>>>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>>>> -		value = OVL0_MOUT_EN_COLOR0;
>>>>> -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>>>> -		value = OVL_MOUT_EN_RDMA;
>>>>> -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>>>> -		value = OD_MOUT_EN_RDMA0;
>>>>> -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>>>> -		value = UFOE_MOUT_EN_DSI0;
>>>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>>>> -		value = OVL1_MOUT_EN_COLOR1;
>>>>> -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>>>> -		value = GAMMA_MOUT_EN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>>>> -		value = OD1_MOUT_EN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> -		value = RDMA0_SOUT_DPI0;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> -		value = RDMA0_SOUT_DPI1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> -		value = RDMA0_SOUT_DSI1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> -		value = RDMA0_SOUT_DSI2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> -		value = RDMA0_SOUT_DSI3;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> -		value = RDMA1_SOUT_DSI1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> -		value = RDMA1_SOUT_DSI2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> -		value = RDMA1_SOUT_DSI3;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> -		value = RDMA1_SOUT_DPI0;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> -		value = RDMA1_SOUT_DPI1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> -		value = RDMA2_SOUT_DPI0;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> -		value = RDMA2_SOUT_DPI1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> -		value = RDMA2_SOUT_DSI1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> -		value = RDMA2_SOUT_DSI2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> -		value = RDMA2_SOUT_DSI3;
>>>>> -	} else {
>>>>> -		value = 0;
>>>>> -	}
>>>>> -
>>>>> -	return value;
>>>>> -}
>>>>> -
>>>>> -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>>>> -				   enum mtk_ddp_comp_id next,
>>>>> -				   unsigned int *addr)
>>>>> -{
>>>>> -	unsigned int value;
>>>>> -
>>>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>>>> -		value = COLOR0_SEL_IN_OVL0;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> -		value = DPI0_SEL_IN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> -		value = DPI1_SEL_IN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> -		value = DSI0_SEL_IN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>>>> -		value = DSI1_SEL_IN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> -		value = DSI2_SEL_IN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>>>> -		value = DSI3_SEL_IN_RDMA1;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> -		value = DPI0_SEL_IN_RDMA2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> -		value = DPI1_SEL_IN_RDMA2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> -		value = DSI0_SEL_IN_RDMA2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>>>> -		value = DSI1_SEL_IN_RDMA2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> -		value = DSI2_SEL_IN_RDMA2;
>>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> -		value = DSI3_SEL_IN_RDMA2;
>>>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>>>> -		value = COLOR1_SEL_IN_OVL1;
>>>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>>>> -		*addr = DISP_REG_CONFIG_DSI_SEL;
>>>>> -		value = DSI_SEL_IN_BLS;
>>>>> -	} else {
>>>>> -		value = 0;
>>>>> -	}
>>>>> -
>>>>> -	return value;
>>>>> -}
>>>>> -
>>>>> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
>>>>> -			     enum mtk_ddp_comp_id cur,
>>>>> -			     enum mtk_ddp_comp_id next)
>>>>> -{
>>>>> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>>>> -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>>>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>>>>> -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>>>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>>>> -		writel_relaxed(DSI_SEL_IN_RDMA,
>>>>> -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
>>>>> -		writel_relaxed(DPI_SEL_IN_BLS,
>>>>> -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
>>>>> -	}
>>>>> -}
>>>>> -
>>>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
>>>>> -			      enum mtk_ddp_comp_id cur,
>>>>> -			      enum mtk_ddp_comp_id next)
>>>>> -{
>>>>> -	unsigned int addr, value, reg;
>>>>> -
>>>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
>>>>> -	if (value) {
>>>>> -		reg = readl_relaxed(config_regs + addr) | value;
>>>>> -		writel_relaxed(reg, config_regs + addr);
>>>>> -	}
>>>>> -
>>>>> -	mtk_ddp_sout_sel(config_regs, cur, next);
>>>>> -
>>>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
>>>>> -	if (value) {
>>>>> -		reg = readl_relaxed(config_regs + addr) | value;
>>>>> -		writel_relaxed(reg, config_regs + addr);
>>>>> -	}
>>>>> -}
>>>>> -
>>>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
>>>>> -				   enum mtk_ddp_comp_id cur,
>>>>> -				   enum mtk_ddp_comp_id next)
>>>>> -{
>>>>> -	unsigned int addr, value, reg;
>>>>> -
>>>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
>>>>> -	if (value) {
>>>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
>>>>> -		writel_relaxed(reg, config_regs + addr);
>>>>> -	}
>>>>> -
>>>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
>>>>> -	if (value) {
>>>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
>>>>> -		writel_relaxed(reg, config_regs + addr);
>>>>> -	}
>>>>> -}
>>>>> -
>>>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
>>>>>  {
>>>>>  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
>>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>>>> index 827be424a148..6b691a57be4a 100644
>>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>>>> @@ -12,13 +12,6 @@ struct regmap;
>>>>>  struct device;
>>>>>  struct mtk_disp_mutex;
>>>>>  
>>>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
>>>>> -			      enum mtk_ddp_comp_id cur,
>>>>> -			      enum mtk_ddp_comp_id next);
>>>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
>>>>> -				   enum mtk_ddp_comp_id cur,
>>>>> -				   enum mtk_ddp_comp_id next);
>>>>> -
>>>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
>>>>>  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
>>>>>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
>>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>>>> index 8e2d3cb62ad5..208f9c5256ef 100644
>>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>>>> @@ -10,6 +10,7 @@
>>>>>  #include <linux/of_address.h>
>>>>>  #include <linux/of_platform.h>
>>>>>  #include <linux/pm_runtime.h>
>>>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>>>  #include <linux/dma-mapping.h>
>>>>>  
>>>>>  #include <drm/drm_atomic.h>
>>>>> @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
>>>>>  {
>>>>>  	struct device *dev = &pdev->dev;
>>>>>  	struct mtk_drm_private *private;
>>>>> -	struct resource *mem;
>>>>>  	struct device_node *node;
>>>>>  	struct component_match *match = NULL;
>>>>>  	int ret;
>>>>> @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
>>>>>  		return -ENOMEM;
>>>>>  
>>>>>  	private->data = of_device_get_match_data(dev);
>>>>> -
>>>>> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>> -	private->config_regs = devm_ioremap_resource(dev, mem);
>>>>> -	if (IS_ERR(private->config_regs)) {
>>>>> -		ret = PTR_ERR(private->config_regs);
>>>>> -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
>>>>> -			ret);
>>>>> -		return ret;
>>>>> +	private->mmsys_dev = dev->parent;
>>>>> +	if (!private->mmsys_dev) {
>>>>> +		dev_err(dev, "Failed to get MMSYS device\n");
>>>>> +		return -ENODEV;
>>>>>  	}
>>>>>  
>>>>>  	/* Iterate over sibling DISP function blocks */
>>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>>>> index 17bc99b9f5d4..b5be63e53176 100644
>>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>>>> @@ -39,7 +39,7 @@ struct mtk_drm_private {
>>>>>  
>>>>>  	struct device_node *mutex_node;
>>>>>  	struct device *mutex_dev;
>>>>> -	void __iomem *config_regs;
>>>>> +	struct device *mmsys_dev;
>>>>>  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
>>>>>  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
>>>>>  	const struct mtk_mmsys_driver_data *data;
>>>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>>>>> index dbdfedd302fa..4b286b525cd3 100644
>>>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>>>> @@ -5,8 +5,76 @@
>>>>>   */
>>>>>  
>>>>>  #include <linux/clk-provider.h>
>>>>> +#include <linux/device.h>
>>>>>  #include <linux/of_device.h>
>>>>>  #include <linux/platform_device.h>
>>>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>>> +
>>>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
>>>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
>>>>> +
>>>>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
>>>>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
>>>>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
>>>>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
>>>>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
>>>>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
>>>>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
>>>>> +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
>>>>> +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
>>>>> +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
>>>>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
>>>>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
>>>>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
>>>>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
>>>>> +
>>>>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>>>>> +#define DISP_REG_CONFIG_OUT_SEL			0x04c
>>>>> +#define DISP_REG_CONFIG_DSI_SEL			0x050
>>>>> +#define DISP_REG_CONFIG_DPI_SEL			0x064
>>>>> +
>>>>> +#define OVL0_MOUT_EN_COLOR0			0x1
>>>>> +#define OD_MOUT_EN_RDMA0			0x1
>>>>> +#define OD1_MOUT_EN_RDMA1			BIT(16)
>>>>> +#define UFOE_MOUT_EN_DSI0			0x1
>>>>> +#define COLOR0_SEL_IN_OVL0			0x1
>>>>> +#define OVL1_MOUT_EN_COLOR1			0x1
>>>>> +#define GAMMA_MOUT_EN_RDMA1			0x1
>>>>> +#define RDMA0_SOUT_DPI0				0x2
>>>>> +#define RDMA0_SOUT_DPI1				0x3
>>>>> +#define RDMA0_SOUT_DSI1				0x1
>>>>> +#define RDMA0_SOUT_DSI2				0x4
>>>>> +#define RDMA0_SOUT_DSI3				0x5
>>>>> +#define RDMA1_SOUT_DPI0				0x2
>>>>> +#define RDMA1_SOUT_DPI1				0x3
>>>>> +#define RDMA1_SOUT_DSI1				0x1
>>>>> +#define RDMA1_SOUT_DSI2				0x4
>>>>> +#define RDMA1_SOUT_DSI3				0x5
>>>>> +#define RDMA2_SOUT_DPI0				0x2
>>>>> +#define RDMA2_SOUT_DPI1				0x3
>>>>> +#define RDMA2_SOUT_DSI1				0x1
>>>>> +#define RDMA2_SOUT_DSI2				0x4
>>>>> +#define RDMA2_SOUT_DSI3				0x5
>>>>> +#define DPI0_SEL_IN_RDMA1			0x1
>>>>> +#define DPI0_SEL_IN_RDMA2			0x3
>>>>> +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
>>>>> +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
>>>>> +#define DSI0_SEL_IN_RDMA1			0x1
>>>>> +#define DSI0_SEL_IN_RDMA2			0x4
>>>>> +#define DSI1_SEL_IN_RDMA1			0x1
>>>>> +#define DSI1_SEL_IN_RDMA2			0x4
>>>>> +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
>>>>> +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
>>>>> +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
>>>>> +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
>>>>> +#define COLOR1_SEL_IN_OVL1			0x1
>>>>> +
>>>>> +#define OVL_MOUT_EN_RDMA			0x1
>>>>> +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
>>>>> +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
>>>>> +#define DSI_SEL_IN_BLS				0x0
>>>>> +#define DPI_SEL_IN_BLS				0x0
>>>>> +#define DSI_SEL_IN_RDMA				0x1
>>>>>  
>>>>>  struct mtk_mmsys_driver_data {
>>>>>  	const char *clk_driver;
>>>>> @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>>>>>  	.clk_driver = "clk-mt8173-mm",
>>>>>  };
>>>>>  
>>>>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>>>> +					  enum mtk_ddp_comp_id next,
>>>>> +					  unsigned int *addr)
>>>>> +{
>>>>> +	unsigned int value;
>>>>> +
>>>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>>>> +		value = OVL0_MOUT_EN_COLOR0;
>>>>> +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>>>> +		value = OVL_MOUT_EN_RDMA;
>>>>> +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>>>> +		value = OD_MOUT_EN_RDMA0;
>>>>> +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>>>> +		value = UFOE_MOUT_EN_DSI0;
>>>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>>>> +		value = OVL1_MOUT_EN_COLOR1;
>>>>> +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>>>> +		value = GAMMA_MOUT_EN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>>>> +		value = OD1_MOUT_EN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> +		value = RDMA0_SOUT_DPI0;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> +		value = RDMA0_SOUT_DPI1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> +		value = RDMA0_SOUT_DSI1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> +		value = RDMA0_SOUT_DSI2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>>>> +		value = RDMA0_SOUT_DSI3;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> +		value = RDMA1_SOUT_DSI1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> +		value = RDMA1_SOUT_DSI2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> +		value = RDMA1_SOUT_DSI3;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> +		value = RDMA1_SOUT_DPI0;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>>>> +		value = RDMA1_SOUT_DPI1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> +		value = RDMA2_SOUT_DPI0;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> +		value = RDMA2_SOUT_DPI1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> +		value = RDMA2_SOUT_DSI1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> +		value = RDMA2_SOUT_DSI2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>>>> +		value = RDMA2_SOUT_DSI3;
>>>>> +	} else {
>>>>> +		value = 0;
>>>>> +	}
>>>>> +
>>>>> +	return value;
>>>>> +}
>>>>> +
>>>>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>>>> +					 enum mtk_ddp_comp_id next,
>>>>> +					 unsigned int *addr)
>>>>> +{
>>>>> +	unsigned int value;
>>>>> +
>>>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>>>> +		value = COLOR0_SEL_IN_OVL0;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> +		value = DPI0_SEL_IN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> +		value = DPI1_SEL_IN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> +		value = DSI0_SEL_IN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>>>> +		value = DSI1_SEL_IN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> +		value = DSI2_SEL_IN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>>>> +		value = DSI3_SEL_IN_RDMA1;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> +		value = DPI0_SEL_IN_RDMA2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>>>> +		value = DPI1_SEL_IN_RDMA2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> +		value = DSI0_SEL_IN_RDMA2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>>>> +		value = DSI1_SEL_IN_RDMA2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> +		value = DSI2_SEL_IN_RDMA2;
>>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>>>> +		value = DSI3_SEL_IN_RDMA2;
>>>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>>>> +		value = COLOR1_SEL_IN_OVL1;
>>>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>>>> +		*addr = DISP_REG_CONFIG_DSI_SEL;
>>>>> +		value = DSI_SEL_IN_BLS;
>>>>> +	} else {
>>>>> +		value = 0;
>>>>> +	}
>>>>> +
>>>>> +	return value;
>>>>> +}
>>>>> +
>>>>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>>>> +				   enum mtk_ddp_comp_id cur,
>>>>> +				   enum mtk_ddp_comp_id next)
>>>>> +{
>>>>> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>>>> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>>>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>>>>> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>>>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>>>> +		writel_relaxed(DSI_SEL_IN_RDMA,
>>>>> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
>>>>> +		writel_relaxed(DPI_SEL_IN_BLS,
>>>>> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
>>>>> +	}
>>>>> +}
>>>>> +
>>>>> +void mtk_mmsys_ddp_connect(struct device *dev,
>>>>> +			   enum mtk_ddp_comp_id cur,
>>>>> +			   enum mtk_ddp_comp_id next)
>>>>> +{
>>>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
>>>>> +	unsigned int addr, value, reg;
>>>>> +
>>>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>>>> +	if (value) {
>>>>> +		reg = readl_relaxed(config_regs + addr) | value;
>>>>> +		writel_relaxed(reg, config_regs + addr);
>>>>> +	}
>>>>> +
>>>>> +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>>>>> +
>>>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>>>> +	if (value) {
>>>>> +		reg = readl_relaxed(config_regs + addr) | value;
>>>>> +		writel_relaxed(reg, config_regs + addr);
>>>>> +	}
>>>>> +}
>>>>> +
>>>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>>>>> +			      enum mtk_ddp_comp_id cur,
>>>>> +			      enum mtk_ddp_comp_id next)
>>>>> +{
>>>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
>>>>> +	unsigned int addr, value, reg;
>>>>> +
>>>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>>>> +	if (value) {
>>>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
>>>>> +		writel_relaxed(reg, config_regs + addr);
>>>>> +	}
>>>>> +
>>>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>>>> +	if (value) {
>>>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
>>>>> +		writel_relaxed(reg, config_regs + addr);
>>>>> +	}
>>>>> +}
>>>>> +
>>>>>  static int mtk_mmsys_probe(struct platform_device *pdev)
>>>>>  {
>>>>>  	const struct mtk_mmsys_driver_data *data;
>>>>> +	struct device *dev = &pdev->dev;
>>>>>  	struct platform_device *clks;
>>>>> +	void __iomem *config_regs;
>>>>> +	struct resource *mem;
>>>>> +	int ret;
>>>>> +
>>>>> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>>>> +	config_regs = devm_ioremap_resource(dev, mem);
>>>>> +	if (IS_ERR(config_regs)) {
>>>>> +		ret = PTR_ERR(config_regs);
>>>>> +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
>>>>> +			ret);
>>>>> +		return ret;
>>>>> +	}
>>>>> +
>>>>> +	platform_set_drvdata(pdev, config_regs);
>>>>>  
>>>>>  	data = of_device_get_match_data(&pdev->dev);
>>>>>  
>>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> new file mode 100644
>>>>> index 000000000000..7bab5d9a3d31
>>>>> --- /dev/null
>>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>>>> @@ -0,0 +1,20 @@
>>>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>>>> +/*
>>>>> + * Copyright (c) 2015 MediaTek Inc.
>>>>> + */
>>>>> +
>>>>> +#ifndef __MTK_MMSYS_H
>>>>> +#define __MTK_MMSYS_H
>>>>> +
>>>>> +enum mtk_ddp_comp_id;
>>>>> +struct device;
>>>>> +
>>>>> +void mtk_mmsys_ddp_connect(struct device *dev,
>>>>> +			   enum mtk_ddp_comp_id cur,
>>>>> +			   enum mtk_ddp_comp_id next);
>>>>> +
>>>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>>>>> +			      enum mtk_ddp_comp_id cur,
>>>>> +			      enum mtk_ddp_comp_id next);
>>>>> +
>>>>> +#endif /* __MTK_MMSYS_H */
>>>>>
>>>
>>
>> _______________________________________________
>> Linux-mediatek mailing list
>> Linux-mediatek@lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-26 15:45           ` Matthias Brugger
@ 2020-03-27  1:55             ` CK Hu
  0 siblings, 0 replies; 16+ messages in thread
From: CK Hu @ 2020-03-27  1:55 UTC (permalink / raw)
  To: Matthias Brugger
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, Allison Randal, mtk01761, linux-media,
	devicetree, p.zabel, frank-w, Seiya Wang, sean.wang, Houlong Wei,
	robh+dt, linux-mediatek, hsinyi, Matthias Brugger,
	Thomas Gleixner, Mauro Carvalho Chehab, linux-arm-kernel, sboyd,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg, Enric Balletbo i Serra

Hi, Matthias:

On Thu, 2020-03-26 at 16:45 +0100, Matthias Brugger wrote:
> 
> On 26/03/2020 15:51, CK Hu wrote:
> > Hi, Matthias:
> > 
> > On Thu, 2020-03-26 at 12:54 +0100, Matthias Brugger wrote:
> >> Hi CK,
> >>
> >> On 26/03/2020 00:05, CK Hu wrote:
> >>> Hi, Matthias:
> >>>
> >>> On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
> >>>>
> >>>> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
> >>>>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
> >>>>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
> >>>>> Those functions will allow DRM driver and others to control the data
> >>>>> path routing.
> >>>>>
> >>>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
> >>>>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
> >>>>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> >>>>> Acked-by: CK Hu <ck.hu@mediatek.com>
> >>>>
> >>>> This patch does not apply against v5.6-rc1.
> >>>> Please rebase as this is a quite big patch and it won't be easy to do that by hand.
> >>>
> >>> I think this patch depends on [1] which has been acked by me and I have
> >>> not picked it. The simple way is that you pick [1] first and then pick
> >>> this series.
> >>>
> >>> [1] 
> >>> https://patchwork.kernel.org/patch/11406227/
> >>>
> >>
> >> You would need to provide a stable tag for me that I can merge into my tree. You
> >> can also try to merge my for-next [1] which has the newest version from Enric.
> >> If you see any merge conflict, then we have to do something about it :)
> >>
> >> Regards,
> >> Matthias
> >>
> >> [1]
> >> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=for-next
> >>
> > 
> > You have applied this series, so I would not apply other patches which
> > would conflict with this series. After this series land on main stream
> > (wish it happen in this merge window), I would rebase other patch on
> > main stream.
> > 
> 
> I haven't (yet) send the pull request. If you want to bring in your patches in
> v5.7 as well we can find a solution to that. Shall I provide you with a stable
> branch which you can merge? This way you can add all your patches in the pull
> request as well and we don't have to wait for v5.8 to get things into mainline.
> 
> Let me know and I'll provide you with a stable branch.
> 

Other drm patches is not in a hurry, for now I don't need a stable
branch. If I need one, I would tell you, thanks.

Regards,
CK

> Regards,
> Matthias
> 
> > Regards,
> > CK
> > 
> >>> Regards,
> >>> CK
> >>>
> >>>>
> >>>> Regards,
> >>>> Matthias
> >>>>
> >>>>> ---
> >>>>>
> >>>>> Changes in v12: None
> >>>>> Changes in v10:
> >>>>> - Select CONFIG_MTK_MMSYS (CK)
> >>>>> - Pass device pointer of mmsys device instead of config regs (CK)
> >>>>>
> >>>>> Changes in v9:
> >>>>> - Introduced a new patch to move routing control into mmsys driver.
> >>>>> - Removed the patch to use regmap as is not needed anymore.
> >>>>>
> >>>>> Changes in v8: None
> >>>>> Changes in v7: None
> >>>>>
> >>>>>  drivers/gpu/drm/mediatek/Kconfig        |   1 +
> >>>>>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
> >>>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
> >>>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
> >>>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
> >>>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
> >>>>>  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
> >>>>>  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
> >>>>>  8 files changed, 316 insertions(+), 282 deletions(-)
> >>>>>  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
> >>>>>
> >>>>> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
> >>>>> index fa5ffc4fe823..c420f5a3d33b 100644
> >>>>> --- a/drivers/gpu/drm/mediatek/Kconfig
> >>>>> +++ b/drivers/gpu/drm/mediatek/Kconfig
> >>>>> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
> >>>>>  	select DRM_MIPI_DSI
> >>>>>  	select DRM_PANEL
> >>>>>  	select MEMORY
> >>>>> +	select MTK_MMSYS
> >>>>>  	select MTK_SMI
> >>>>>  	select VIDEOMODE_HELPERS
> >>>>>  	help
> >>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >>>>> index 0e05683d7b53..579a5a5d4472 100644
> >>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> >>>>> @@ -6,6 +6,7 @@
> >>>>>  #include <linux/clk.h>
> >>>>>  #include <linux/pm_runtime.h>
> >>>>>  #include <linux/soc/mediatek/mtk-cmdq.h>
> >>>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
> >>>>>  
> >>>>>  #include <asm/barrier.h>
> >>>>>  #include <soc/mediatek/smi.h>
> >>>>> @@ -28,7 +29,7 @@
> >>>>>   * @enabled: records whether crtc_enable succeeded
> >>>>>   * @planes: array of 4 drm_plane structures, one for each overlay plane
> >>>>>   * @pending_planes: whether any plane has pending changes to be applied
> >>>>> - * @config_regs: memory mapped mmsys configuration register space
> >>>>> + * @mmsys_dev: pointer to the mmsys device for configuration registers
> >>>>>   * @mutex: handle to one of the ten disp_mutex streams
> >>>>>   * @ddp_comp_nr: number of components in ddp_comp
> >>>>>   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
> >>>>> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
> >>>>>  	u32				cmdq_event;
> >>>>>  #endif
> >>>>>  
> >>>>> -	void __iomem			*config_regs;
> >>>>> +	struct device			*mmsys_dev;
> >>>>>  	struct mtk_disp_mutex		*mutex;
> >>>>>  	unsigned int			ddp_comp_nr;
> >>>>>  	struct mtk_ddp_comp		**ddp_comp;
> >>>>> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> >>>>>  	}
> >>>>>  
> >>>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> >>>>> -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
> >>>>> -					 mtk_crtc->ddp_comp[i]->id,
> >>>>> -					 mtk_crtc->ddp_comp[i + 1]->id);
> >>>>> +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
> >>>>> +				      mtk_crtc->ddp_comp[i]->id,
> >>>>> +				      mtk_crtc->ddp_comp[i + 1]->id);
> >>>>>  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
> >>>>>  					mtk_crtc->ddp_comp[i]->id);
> >>>>>  	}
> >>>>> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
> >>>>>  					   mtk_crtc->ddp_comp[i]->id);
> >>>>>  	mtk_disp_mutex_disable(mtk_crtc->mutex);
> >>>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
> >>>>> -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
> >>>>> -					      mtk_crtc->ddp_comp[i]->id,
> >>>>> -					      mtk_crtc->ddp_comp[i + 1]->id);
> >>>>> +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
> >>>>> +					 mtk_crtc->ddp_comp[i]->id,
> >>>>> +					 mtk_crtc->ddp_comp[i + 1]->id);
> >>>>>  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
> >>>>>  					   mtk_crtc->ddp_comp[i]->id);
> >>>>>  	}
> >>>>> @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> >>>>>  	if (!mtk_crtc)
> >>>>>  		return -ENOMEM;
> >>>>>  
> >>>>> -	mtk_crtc->config_regs = priv->config_regs;
> >>>>> +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
> >>>>>  	mtk_crtc->ddp_comp_nr = path_len;
> >>>>>  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
> >>>>>  						sizeof(*mtk_crtc->ddp_comp),
> >>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >>>>> index b885f60f474c..014c1bbe1df2 100644
> >>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
> >>>>> @@ -13,26 +13,6 @@
> >>>>>  #include "mtk_drm_ddp.h"
> >>>>>  #include "mtk_drm_ddp_comp.h"
> >>>>>  
> >>>>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> >>>>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> >>>>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> >>>>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> >>>>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> >>>>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> >>>>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> >>>>> -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> >>>>> -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> >>>>> -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> >>>>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> >>>>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> >>>>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> >>>>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> >>>>> -
> >>>>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> >>>>> -#define DISP_REG_CONFIG_OUT_SEL			0x04c
> >>>>> -#define DISP_REG_CONFIG_DSI_SEL			0x050
> >>>>> -#define DISP_REG_CONFIG_DPI_SEL			0x064
> >>>>> -
> >>>>>  #define MT2701_DISP_MUTEX0_MOD0			0x2c
> >>>>>  #define MT2701_DISP_MUTEX0_SOF0			0x30
> >>>>>  
> >>>>> @@ -94,48 +74,6 @@
> >>>>>  #define MUTEX_SOF_DSI2			5
> >>>>>  #define MUTEX_SOF_DSI3			6
> >>>>>  
> >>>>> -#define OVL0_MOUT_EN_COLOR0		0x1
> >>>>> -#define OD_MOUT_EN_RDMA0		0x1
> >>>>> -#define OD1_MOUT_EN_RDMA1		BIT(16)
> >>>>> -#define UFOE_MOUT_EN_DSI0		0x1
> >>>>> -#define COLOR0_SEL_IN_OVL0		0x1
> >>>>> -#define OVL1_MOUT_EN_COLOR1		0x1
> >>>>> -#define GAMMA_MOUT_EN_RDMA1		0x1
> >>>>> -#define RDMA0_SOUT_DPI0			0x2
> >>>>> -#define RDMA0_SOUT_DPI1			0x3
> >>>>> -#define RDMA0_SOUT_DSI1			0x1
> >>>>> -#define RDMA0_SOUT_DSI2			0x4
> >>>>> -#define RDMA0_SOUT_DSI3			0x5
> >>>>> -#define RDMA1_SOUT_DPI0			0x2
> >>>>> -#define RDMA1_SOUT_DPI1			0x3
> >>>>> -#define RDMA1_SOUT_DSI1			0x1
> >>>>> -#define RDMA1_SOUT_DSI2			0x4
> >>>>> -#define RDMA1_SOUT_DSI3			0x5
> >>>>> -#define RDMA2_SOUT_DPI0			0x2
> >>>>> -#define RDMA2_SOUT_DPI1			0x3
> >>>>> -#define RDMA2_SOUT_DSI1			0x1
> >>>>> -#define RDMA2_SOUT_DSI2			0x4
> >>>>> -#define RDMA2_SOUT_DSI3			0x5
> >>>>> -#define DPI0_SEL_IN_RDMA1		0x1
> >>>>> -#define DPI0_SEL_IN_RDMA2		0x3
> >>>>> -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
> >>>>> -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
> >>>>> -#define DSI0_SEL_IN_RDMA1		0x1
> >>>>> -#define DSI0_SEL_IN_RDMA2		0x4
> >>>>> -#define DSI1_SEL_IN_RDMA1		0x1
> >>>>> -#define DSI1_SEL_IN_RDMA2		0x4
> >>>>> -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
> >>>>> -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
> >>>>> -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
> >>>>> -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
> >>>>> -#define COLOR1_SEL_IN_OVL1		0x1
> >>>>> -
> >>>>> -#define OVL_MOUT_EN_RDMA		0x1
> >>>>> -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
> >>>>> -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
> >>>>> -#define DSI_SEL_IN_BLS			0x0
> >>>>> -#define DPI_SEL_IN_BLS			0x0
> >>>>> -#define DSI_SEL_IN_RDMA			0x1
> >>>>>  
> >>>>>  struct mtk_disp_mutex {
> >>>>>  	int id;
> >>>>> @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
> >>>>>  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
> >>>>>  };
> >>>>>  
> >>>>> -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
> >>>>> -				    enum mtk_ddp_comp_id next,
> >>>>> -				    unsigned int *addr)
> >>>>> -{
> >>>>> -	unsigned int value;
> >>>>> -
> >>>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> >>>>> -		value = OVL0_MOUT_EN_COLOR0;
> >>>>> -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> >>>>> -		value = OVL_MOUT_EN_RDMA;
> >>>>> -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>>>> -		value = OD_MOUT_EN_RDMA0;
> >>>>> -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> >>>>> -		value = UFOE_MOUT_EN_DSI0;
> >>>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> >>>>> -		value = OVL1_MOUT_EN_COLOR1;
> >>>>> -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> >>>>> -		value = GAMMA_MOUT_EN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>>>> -		value = OD1_MOUT_EN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> -		value = RDMA0_SOUT_DPI0;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> -		value = RDMA0_SOUT_DPI1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> -		value = RDMA0_SOUT_DSI1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> -		value = RDMA0_SOUT_DSI2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> -		value = RDMA0_SOUT_DSI3;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> -		value = RDMA1_SOUT_DSI1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> -		value = RDMA1_SOUT_DSI2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> -		value = RDMA1_SOUT_DSI3;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> -		value = RDMA1_SOUT_DPI0;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> -		value = RDMA1_SOUT_DPI1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> -		value = RDMA2_SOUT_DPI0;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> -		value = RDMA2_SOUT_DPI1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> -		value = RDMA2_SOUT_DSI1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> -		value = RDMA2_SOUT_DSI2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> -		value = RDMA2_SOUT_DSI3;
> >>>>> -	} else {
> >>>>> -		value = 0;
> >>>>> -	}
> >>>>> -
> >>>>> -	return value;
> >>>>> -}
> >>>>> -
> >>>>> -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
> >>>>> -				   enum mtk_ddp_comp_id next,
> >>>>> -				   unsigned int *addr)
> >>>>> -{
> >>>>> -	unsigned int value;
> >>>>> -
> >>>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> >>>>> -		value = COLOR0_SEL_IN_OVL0;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> -		value = DPI0_SEL_IN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> -		value = DPI1_SEL_IN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> -		value = DSI0_SEL_IN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>>>> -		value = DSI1_SEL_IN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> -		value = DSI2_SEL_IN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>>>> -		value = DSI3_SEL_IN_RDMA1;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> -		value = DPI0_SEL_IN_RDMA2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> -		value = DPI1_SEL_IN_RDMA2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> -		value = DSI0_SEL_IN_RDMA2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>>>> -		value = DSI1_SEL_IN_RDMA2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> -		value = DSI2_SEL_IN_RDMA2;
> >>>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> -		value = DSI3_SEL_IN_RDMA2;
> >>>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> >>>>> -		value = COLOR1_SEL_IN_OVL1;
> >>>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>>>> -		*addr = DISP_REG_CONFIG_DSI_SEL;
> >>>>> -		value = DSI_SEL_IN_BLS;
> >>>>> -	} else {
> >>>>> -		value = 0;
> >>>>> -	}
> >>>>> -
> >>>>> -	return value;
> >>>>> -}
> >>>>> -
> >>>>> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
> >>>>> -			     enum mtk_ddp_comp_id cur,
> >>>>> -			     enum mtk_ddp_comp_id next)
> >>>>> -{
> >>>>> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>>>> -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> >>>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> >>>>> -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> >>>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>>>> -		writel_relaxed(DSI_SEL_IN_RDMA,
> >>>>> -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> >>>>> -		writel_relaxed(DPI_SEL_IN_BLS,
> >>>>> -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> >>>>> -	}
> >>>>> -}
> >>>>> -
> >>>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> >>>>> -			      enum mtk_ddp_comp_id cur,
> >>>>> -			      enum mtk_ddp_comp_id next)
> >>>>> -{
> >>>>> -	unsigned int addr, value, reg;
> >>>>> -
> >>>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
> >>>>> -	if (value) {
> >>>>> -		reg = readl_relaxed(config_regs + addr) | value;
> >>>>> -		writel_relaxed(reg, config_regs + addr);
> >>>>> -	}
> >>>>> -
> >>>>> -	mtk_ddp_sout_sel(config_regs, cur, next);
> >>>>> -
> >>>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
> >>>>> -	if (value) {
> >>>>> -		reg = readl_relaxed(config_regs + addr) | value;
> >>>>> -		writel_relaxed(reg, config_regs + addr);
> >>>>> -	}
> >>>>> -}
> >>>>> -
> >>>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> >>>>> -				   enum mtk_ddp_comp_id cur,
> >>>>> -				   enum mtk_ddp_comp_id next)
> >>>>> -{
> >>>>> -	unsigned int addr, value, reg;
> >>>>> -
> >>>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
> >>>>> -	if (value) {
> >>>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
> >>>>> -		writel_relaxed(reg, config_regs + addr);
> >>>>> -	}
> >>>>> -
> >>>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
> >>>>> -	if (value) {
> >>>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
> >>>>> -		writel_relaxed(reg, config_regs + addr);
> >>>>> -	}
> >>>>> -}
> >>>>> -
> >>>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
> >>>>>  {
> >>>>>  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
> >>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> >>>>> index 827be424a148..6b691a57be4a 100644
> >>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> >>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
> >>>>> @@ -12,13 +12,6 @@ struct regmap;
> >>>>>  struct device;
> >>>>>  struct mtk_disp_mutex;
> >>>>>  
> >>>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
> >>>>> -			      enum mtk_ddp_comp_id cur,
> >>>>> -			      enum mtk_ddp_comp_id next);
> >>>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
> >>>>> -				   enum mtk_ddp_comp_id cur,
> >>>>> -				   enum mtk_ddp_comp_id next);
> >>>>> -
> >>>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
> >>>>>  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
> >>>>>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
> >>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> >>>>> index 8e2d3cb62ad5..208f9c5256ef 100644
> >>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> >>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> >>>>> @@ -10,6 +10,7 @@
> >>>>>  #include <linux/of_address.h>
> >>>>>  #include <linux/of_platform.h>
> >>>>>  #include <linux/pm_runtime.h>
> >>>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
> >>>>>  #include <linux/dma-mapping.h>
> >>>>>  
> >>>>>  #include <drm/drm_atomic.h>
> >>>>> @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >>>>>  {
> >>>>>  	struct device *dev = &pdev->dev;
> >>>>>  	struct mtk_drm_private *private;
> >>>>> -	struct resource *mem;
> >>>>>  	struct device_node *node;
> >>>>>  	struct component_match *match = NULL;
> >>>>>  	int ret;
> >>>>> @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
> >>>>>  		return -ENOMEM;
> >>>>>  
> >>>>>  	private->data = of_device_get_match_data(dev);
> >>>>> -
> >>>>> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>>>> -	private->config_regs = devm_ioremap_resource(dev, mem);
> >>>>> -	if (IS_ERR(private->config_regs)) {
> >>>>> -		ret = PTR_ERR(private->config_regs);
> >>>>> -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> >>>>> -			ret);
> >>>>> -		return ret;
> >>>>> +	private->mmsys_dev = dev->parent;
> >>>>> +	if (!private->mmsys_dev) {
> >>>>> +		dev_err(dev, "Failed to get MMSYS device\n");
> >>>>> +		return -ENODEV;
> >>>>>  	}
> >>>>>  
> >>>>>  	/* Iterate over sibling DISP function blocks */
> >>>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> >>>>> index 17bc99b9f5d4..b5be63e53176 100644
> >>>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> >>>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> >>>>> @@ -39,7 +39,7 @@ struct mtk_drm_private {
> >>>>>  
> >>>>>  	struct device_node *mutex_node;
> >>>>>  	struct device *mutex_dev;
> >>>>> -	void __iomem *config_regs;
> >>>>> +	struct device *mmsys_dev;
> >>>>>  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
> >>>>>  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
> >>>>>  	const struct mtk_mmsys_driver_data *data;
> >>>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> >>>>> index dbdfedd302fa..4b286b525cd3 100644
> >>>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
> >>>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> >>>>> @@ -5,8 +5,76 @@
> >>>>>   */
> >>>>>  
> >>>>>  #include <linux/clk-provider.h>
> >>>>> +#include <linux/device.h>
> >>>>>  #include <linux/of_device.h>
> >>>>>  #include <linux/platform_device.h>
> >>>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
> >>>>> +
> >>>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
> >>>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
> >>>>> +
> >>>>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
> >>>>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
> >>>>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
> >>>>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
> >>>>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
> >>>>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
> >>>>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
> >>>>> +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
> >>>>> +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
> >>>>> +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
> >>>>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
> >>>>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
> >>>>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
> >>>>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
> >>>>> +
> >>>>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
> >>>>> +#define DISP_REG_CONFIG_OUT_SEL			0x04c
> >>>>> +#define DISP_REG_CONFIG_DSI_SEL			0x050
> >>>>> +#define DISP_REG_CONFIG_DPI_SEL			0x064
> >>>>> +
> >>>>> +#define OVL0_MOUT_EN_COLOR0			0x1
> >>>>> +#define OD_MOUT_EN_RDMA0			0x1
> >>>>> +#define OD1_MOUT_EN_RDMA1			BIT(16)
> >>>>> +#define UFOE_MOUT_EN_DSI0			0x1
> >>>>> +#define COLOR0_SEL_IN_OVL0			0x1
> >>>>> +#define OVL1_MOUT_EN_COLOR1			0x1
> >>>>> +#define GAMMA_MOUT_EN_RDMA1			0x1
> >>>>> +#define RDMA0_SOUT_DPI0				0x2
> >>>>> +#define RDMA0_SOUT_DPI1				0x3
> >>>>> +#define RDMA0_SOUT_DSI1				0x1
> >>>>> +#define RDMA0_SOUT_DSI2				0x4
> >>>>> +#define RDMA0_SOUT_DSI3				0x5
> >>>>> +#define RDMA1_SOUT_DPI0				0x2
> >>>>> +#define RDMA1_SOUT_DPI1				0x3
> >>>>> +#define RDMA1_SOUT_DSI1				0x1
> >>>>> +#define RDMA1_SOUT_DSI2				0x4
> >>>>> +#define RDMA1_SOUT_DSI3				0x5
> >>>>> +#define RDMA2_SOUT_DPI0				0x2
> >>>>> +#define RDMA2_SOUT_DPI1				0x3
> >>>>> +#define RDMA2_SOUT_DSI1				0x1
> >>>>> +#define RDMA2_SOUT_DSI2				0x4
> >>>>> +#define RDMA2_SOUT_DSI3				0x5
> >>>>> +#define DPI0_SEL_IN_RDMA1			0x1
> >>>>> +#define DPI0_SEL_IN_RDMA2			0x3
> >>>>> +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
> >>>>> +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
> >>>>> +#define DSI0_SEL_IN_RDMA1			0x1
> >>>>> +#define DSI0_SEL_IN_RDMA2			0x4
> >>>>> +#define DSI1_SEL_IN_RDMA1			0x1
> >>>>> +#define DSI1_SEL_IN_RDMA2			0x4
> >>>>> +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
> >>>>> +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
> >>>>> +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
> >>>>> +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
> >>>>> +#define COLOR1_SEL_IN_OVL1			0x1
> >>>>> +
> >>>>> +#define OVL_MOUT_EN_RDMA			0x1
> >>>>> +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
> >>>>> +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
> >>>>> +#define DSI_SEL_IN_BLS				0x0
> >>>>> +#define DPI_SEL_IN_BLS				0x0
> >>>>> +#define DSI_SEL_IN_RDMA				0x1
> >>>>>  
> >>>>>  struct mtk_mmsys_driver_data {
> >>>>>  	const char *clk_driver;
> >>>>> @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
> >>>>>  	.clk_driver = "clk-mt8173-mm",
> >>>>>  };
> >>>>>  
> >>>>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
> >>>>> +					  enum mtk_ddp_comp_id next,
> >>>>> +					  unsigned int *addr)
> >>>>> +{
> >>>>> +	unsigned int value;
> >>>>> +
> >>>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
> >>>>> +		value = OVL0_MOUT_EN_COLOR0;
> >>>>> +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
> >>>>> +		value = OVL_MOUT_EN_RDMA;
> >>>>> +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>>>> +		value = OD_MOUT_EN_RDMA0;
> >>>>> +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
> >>>>> +		value = UFOE_MOUT_EN_DSI0;
> >>>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
> >>>>> +		value = OVL1_MOUT_EN_COLOR1;
> >>>>> +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
> >>>>> +		value = GAMMA_MOUT_EN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
> >>>>> +		value = OD1_MOUT_EN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> +		value = RDMA0_SOUT_DPI0;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> +		value = RDMA0_SOUT_DPI1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> +		value = RDMA0_SOUT_DSI1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> +		value = RDMA0_SOUT_DSI2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
> >>>>> +		value = RDMA0_SOUT_DSI3;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> +		value = RDMA1_SOUT_DSI1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> +		value = RDMA1_SOUT_DSI2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> +		value = RDMA1_SOUT_DSI3;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> +		value = RDMA1_SOUT_DPI0;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
> >>>>> +		value = RDMA1_SOUT_DPI1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> +		value = RDMA2_SOUT_DPI0;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> +		value = RDMA2_SOUT_DPI1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> +		value = RDMA2_SOUT_DSI1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> +		value = RDMA2_SOUT_DSI2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
> >>>>> +		value = RDMA2_SOUT_DSI3;
> >>>>> +	} else {
> >>>>> +		value = 0;
> >>>>> +	}
> >>>>> +
> >>>>> +	return value;
> >>>>> +}
> >>>>> +
> >>>>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
> >>>>> +					 enum mtk_ddp_comp_id next,
> >>>>> +					 unsigned int *addr)
> >>>>> +{
> >>>>> +	unsigned int value;
> >>>>> +
> >>>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
> >>>>> +		value = COLOR0_SEL_IN_OVL0;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> +		value = DPI0_SEL_IN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> +		value = DPI1_SEL_IN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> +		value = DSI0_SEL_IN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>>>> +		value = DSI1_SEL_IN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> +		value = DSI2_SEL_IN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>>>> +		value = DSI3_SEL_IN_RDMA1;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> +		value = DPI0_SEL_IN_RDMA2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
> >>>>> +		value = DPI1_SEL_IN_RDMA2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> +		value = DSI0_SEL_IN_RDMA2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
> >>>>> +		value = DSI1_SEL_IN_RDMA2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> +		value = DSI2_SEL_IN_RDMA2;
> >>>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
> >>>>> +		value = DSI3_SEL_IN_RDMA2;
> >>>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
> >>>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
> >>>>> +		value = COLOR1_SEL_IN_OVL1;
> >>>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>>>> +		*addr = DISP_REG_CONFIG_DSI_SEL;
> >>>>> +		value = DSI_SEL_IN_BLS;
> >>>>> +	} else {
> >>>>> +		value = 0;
> >>>>> +	}
> >>>>> +
> >>>>> +	return value;
> >>>>> +}
> >>>>> +
> >>>>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
> >>>>> +				   enum mtk_ddp_comp_id cur,
> >>>>> +				   enum mtk_ddp_comp_id next)
> >>>>> +{
> >>>>> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> >>>>> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> >>>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
> >>>>> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
> >>>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> >>>>> +		writel_relaxed(DSI_SEL_IN_RDMA,
> >>>>> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
> >>>>> +		writel_relaxed(DPI_SEL_IN_BLS,
> >>>>> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
> >>>>> +	}
> >>>>> +}
> >>>>> +
> >>>>> +void mtk_mmsys_ddp_connect(struct device *dev,
> >>>>> +			   enum mtk_ddp_comp_id cur,
> >>>>> +			   enum mtk_ddp_comp_id next)
> >>>>> +{
> >>>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
> >>>>> +	unsigned int addr, value, reg;
> >>>>> +
> >>>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> >>>>> +	if (value) {
> >>>>> +		reg = readl_relaxed(config_regs + addr) | value;
> >>>>> +		writel_relaxed(reg, config_regs + addr);
> >>>>> +	}
> >>>>> +
> >>>>> +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
> >>>>> +
> >>>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> >>>>> +	if (value) {
> >>>>> +		reg = readl_relaxed(config_regs + addr) | value;
> >>>>> +		writel_relaxed(reg, config_regs + addr);
> >>>>> +	}
> >>>>> +}
> >>>>> +
> >>>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> >>>>> +			      enum mtk_ddp_comp_id cur,
> >>>>> +			      enum mtk_ddp_comp_id next)
> >>>>> +{
> >>>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
> >>>>> +	unsigned int addr, value, reg;
> >>>>> +
> >>>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
> >>>>> +	if (value) {
> >>>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
> >>>>> +		writel_relaxed(reg, config_regs + addr);
> >>>>> +	}
> >>>>> +
> >>>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
> >>>>> +	if (value) {
> >>>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
> >>>>> +		writel_relaxed(reg, config_regs + addr);
> >>>>> +	}
> >>>>> +}
> >>>>> +
> >>>>>  static int mtk_mmsys_probe(struct platform_device *pdev)
> >>>>>  {
> >>>>>  	const struct mtk_mmsys_driver_data *data;
> >>>>> +	struct device *dev = &pdev->dev;
> >>>>>  	struct platform_device *clks;
> >>>>> +	void __iomem *config_regs;
> >>>>> +	struct resource *mem;
> >>>>> +	int ret;
> >>>>> +
> >>>>> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>>>> +	config_regs = devm_ioremap_resource(dev, mem);
> >>>>> +	if (IS_ERR(config_regs)) {
> >>>>> +		ret = PTR_ERR(config_regs);
> >>>>> +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
> >>>>> +			ret);
> >>>>> +		return ret;
> >>>>> +	}
> >>>>> +
> >>>>> +	platform_set_drvdata(pdev, config_regs);
> >>>>>  
> >>>>>  	data = of_device_get_match_data(&pdev->dev);
> >>>>>  
> >>>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> >>>>> new file mode 100644
> >>>>> index 000000000000..7bab5d9a3d31
> >>>>> --- /dev/null
> >>>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> >>>>> @@ -0,0 +1,20 @@
> >>>>> +/* SPDX-License-Identifier: GPL-2.0-only */
> >>>>> +/*
> >>>>> + * Copyright (c) 2015 MediaTek Inc.
> >>>>> + */
> >>>>> +
> >>>>> +#ifndef __MTK_MMSYS_H
> >>>>> +#define __MTK_MMSYS_H
> >>>>> +
> >>>>> +enum mtk_ddp_comp_id;
> >>>>> +struct device;
> >>>>> +
> >>>>> +void mtk_mmsys_ddp_connect(struct device *dev,
> >>>>> +			   enum mtk_ddp_comp_id cur,
> >>>>> +			   enum mtk_ddp_comp_id next);
> >>>>> +
> >>>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
> >>>>> +			      enum mtk_ddp_comp_id cur,
> >>>>> +			      enum mtk_ddp_comp_id next);
> >>>>> +
> >>>>> +#endif /* __MTK_MMSYS_H */
> >>>>>
> >>>
> >>
> >> _______________________________________________
> >> Linux-mediatek mailing list
> >> Linux-mediatek@lists.infradead.org
> >> http://lists.infradead.org/mailman/listinfo/linux-mediatek
> > 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

* Re: [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device
  2020-03-25 23:05     ` CK Hu
  2020-03-26 11:54       ` Matthias Brugger
@ 2020-03-27 17:04       ` Matthias Brugger
  1 sibling, 0 replies; 16+ messages in thread
From: Matthias Brugger @ 2020-03-27 17:04 UTC (permalink / raw)
  To: CK Hu, Matthias Brugger
  Cc: mark.rutland, Kate Stewart, Minghsiu Tsai, Andrew-CT Chen,
	airlied, mturquette, dri-devel, Richard Fontana,
	laurent.pinchart, ulrich.hecht+renesas, Collabora Kernel ML,
	linux-clk, Weiyi Lu, wens, Allison Randal, mtk01761, linux-media,
	devicetree, p.zabel, frank-w, Seiya Wang, sean.wang, Houlong Wei,
	robh+dt, linux-mediatek, hsinyi, Thomas Gleixner,
	Mauro Carvalho Chehab, linux-arm-kernel, sboyd,
	Greg Kroah-Hartman, rdunlap, linux-kernel, Daniel Vetter,
	matthias.bgg, Enric Balletbo i Serra

Hi CK,

On 26/03/2020 00:05, CK Hu wrote:
> Hi, Matthias:
> 
> On Wed, 2020-03-25 at 17:16 +0100, Matthias Brugger wrote:
>>
>> On 11/03/2020 17:53, Enric Balletbo i Serra wrote:
>>> Provide a mtk_mmsys_ddp_connect() and mtk_mmsys_disconnect() functions to
>>> replace mtk_ddp_add_comp_to_path() and mtk_ddp_remove_comp_from_path().
>>> Those functions will allow DRM driver and others to control the data
>>> path routing.
>>>
>>> Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
>>> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
>>> Reviewed-by: CK Hu <ck.hu@mediatek.com>
>>> Acked-by: CK Hu <ck.hu@mediatek.com>
>>
>> This patch does not apply against v5.6-rc1.
>> Please rebase as this is a quite big patch and it won't be easy to do that by hand.
> 
> I think this patch depends on [1] which has been acked by me and I have
> not picked it. The simple way is that you pick [1] first and then pick
> this series.
> 
> [1] 
> https://patchwork.kernel.org/patch/11406227/

In the end Enric rebased his branch on top of v5.6-rc1 so I won't take this
patch into branch. So feel free to take it through yours.

Regards,
Matthias

> 
> Regards,
> CK
> 
>>
>> Regards,
>> Matthias
>>
>>> ---
>>>
>>> Changes in v12: None
>>> Changes in v10:
>>> - Select CONFIG_MTK_MMSYS (CK)
>>> - Pass device pointer of mmsys device instead of config regs (CK)
>>>
>>> Changes in v9:
>>> - Introduced a new patch to move routing control into mmsys driver.
>>> - Removed the patch to use regmap as is not needed anymore.
>>>
>>> Changes in v8: None
>>> Changes in v7: None
>>>
>>>  drivers/gpu/drm/mediatek/Kconfig        |   1 +
>>>  drivers/gpu/drm/mediatek/mtk_drm_crtc.c |  19 +-
>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.c  | 256 ----------------------
>>>  drivers/gpu/drm/mediatek/mtk_drm_ddp.h  |   7 -
>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.c  |  14 +-
>>>  drivers/gpu/drm/mediatek/mtk_drm_drv.h  |   2 +-
>>>  drivers/soc/mediatek/mtk-mmsys.c        | 279 ++++++++++++++++++++++++
>>>  include/linux/soc/mediatek/mtk-mmsys.h  |  20 ++
>>>  8 files changed, 316 insertions(+), 282 deletions(-)
>>>  create mode 100644 include/linux/soc/mediatek/mtk-mmsys.h
>>>
>>> diff --git a/drivers/gpu/drm/mediatek/Kconfig b/drivers/gpu/drm/mediatek/Kconfig
>>> index fa5ffc4fe823..c420f5a3d33b 100644
>>> --- a/drivers/gpu/drm/mediatek/Kconfig
>>> +++ b/drivers/gpu/drm/mediatek/Kconfig
>>> @@ -11,6 +11,7 @@ config DRM_MEDIATEK
>>>  	select DRM_MIPI_DSI
>>>  	select DRM_PANEL
>>>  	select MEMORY
>>> +	select MTK_MMSYS
>>>  	select MTK_SMI
>>>  	select VIDEOMODE_HELPERS
>>>  	help
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> index 0e05683d7b53..579a5a5d4472 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
>>> @@ -6,6 +6,7 @@
>>>  #include <linux/clk.h>
>>>  #include <linux/pm_runtime.h>
>>>  #include <linux/soc/mediatek/mtk-cmdq.h>
>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>  
>>>  #include <asm/barrier.h>
>>>  #include <soc/mediatek/smi.h>
>>> @@ -28,7 +29,7 @@
>>>   * @enabled: records whether crtc_enable succeeded
>>>   * @planes: array of 4 drm_plane structures, one for each overlay plane
>>>   * @pending_planes: whether any plane has pending changes to be applied
>>> - * @config_regs: memory mapped mmsys configuration register space
>>> + * @mmsys_dev: pointer to the mmsys device for configuration registers
>>>   * @mutex: handle to one of the ten disp_mutex streams
>>>   * @ddp_comp_nr: number of components in ddp_comp
>>>   * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
>>> @@ -50,7 +51,7 @@ struct mtk_drm_crtc {
>>>  	u32				cmdq_event;
>>>  #endif
>>>  
>>> -	void __iomem			*config_regs;
>>> +	struct device			*mmsys_dev;
>>>  	struct mtk_disp_mutex		*mutex;
>>>  	unsigned int			ddp_comp_nr;
>>>  	struct mtk_ddp_comp		**ddp_comp;
>>> @@ -296,9 +297,9 @@ static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
>>>  	}
>>>  
>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
>>> -		mtk_ddp_add_comp_to_path(mtk_crtc->config_regs,
>>> -					 mtk_crtc->ddp_comp[i]->id,
>>> -					 mtk_crtc->ddp_comp[i + 1]->id);
>>> +		mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
>>> +				      mtk_crtc->ddp_comp[i]->id,
>>> +				      mtk_crtc->ddp_comp[i + 1]->id);
>>>  		mtk_disp_mutex_add_comp(mtk_crtc->mutex,
>>>  					mtk_crtc->ddp_comp[i]->id);
>>>  	}
>>> @@ -355,9 +356,9 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
>>>  					   mtk_crtc->ddp_comp[i]->id);
>>>  	mtk_disp_mutex_disable(mtk_crtc->mutex);
>>>  	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
>>> -		mtk_ddp_remove_comp_from_path(mtk_crtc->config_regs,
>>> -					      mtk_crtc->ddp_comp[i]->id,
>>> -					      mtk_crtc->ddp_comp[i + 1]->id);
>>> +		mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
>>> +					 mtk_crtc->ddp_comp[i]->id,
>>> +					 mtk_crtc->ddp_comp[i + 1]->id);
>>>  		mtk_disp_mutex_remove_comp(mtk_crtc->mutex,
>>>  					   mtk_crtc->ddp_comp[i]->id);
>>>  	}
>>> @@ -761,7 +762,7 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
>>>  	if (!mtk_crtc)
>>>  		return -ENOMEM;
>>>  
>>> -	mtk_crtc->config_regs = priv->config_regs;
>>> +	mtk_crtc->mmsys_dev = priv->mmsys_dev;
>>>  	mtk_crtc->ddp_comp_nr = path_len;
>>>  	mtk_crtc->ddp_comp = devm_kmalloc_array(dev, mtk_crtc->ddp_comp_nr,
>>>  						sizeof(*mtk_crtc->ddp_comp),
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>> index b885f60f474c..014c1bbe1df2 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
>>> @@ -13,26 +13,6 @@
>>>  #include "mtk_drm_ddp.h"
>>>  #include "mtk_drm_ddp_comp.h"
>>>  
>>> -#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
>>> -#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
>>> -#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
>>> -#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
>>> -#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
>>> -#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
>>> -#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
>>> -#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
>>> -#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
>>> -#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
>>> -#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
>>> -#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
>>> -#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
>>> -#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
>>> -
>>> -#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>>> -#define DISP_REG_CONFIG_OUT_SEL			0x04c
>>> -#define DISP_REG_CONFIG_DSI_SEL			0x050
>>> -#define DISP_REG_CONFIG_DPI_SEL			0x064
>>> -
>>>  #define MT2701_DISP_MUTEX0_MOD0			0x2c
>>>  #define MT2701_DISP_MUTEX0_SOF0			0x30
>>>  
>>> @@ -94,48 +74,6 @@
>>>  #define MUTEX_SOF_DSI2			5
>>>  #define MUTEX_SOF_DSI3			6
>>>  
>>> -#define OVL0_MOUT_EN_COLOR0		0x1
>>> -#define OD_MOUT_EN_RDMA0		0x1
>>> -#define OD1_MOUT_EN_RDMA1		BIT(16)
>>> -#define UFOE_MOUT_EN_DSI0		0x1
>>> -#define COLOR0_SEL_IN_OVL0		0x1
>>> -#define OVL1_MOUT_EN_COLOR1		0x1
>>> -#define GAMMA_MOUT_EN_RDMA1		0x1
>>> -#define RDMA0_SOUT_DPI0			0x2
>>> -#define RDMA0_SOUT_DPI1			0x3
>>> -#define RDMA0_SOUT_DSI1			0x1
>>> -#define RDMA0_SOUT_DSI2			0x4
>>> -#define RDMA0_SOUT_DSI3			0x5
>>> -#define RDMA1_SOUT_DPI0			0x2
>>> -#define RDMA1_SOUT_DPI1			0x3
>>> -#define RDMA1_SOUT_DSI1			0x1
>>> -#define RDMA1_SOUT_DSI2			0x4
>>> -#define RDMA1_SOUT_DSI3			0x5
>>> -#define RDMA2_SOUT_DPI0			0x2
>>> -#define RDMA2_SOUT_DPI1			0x3
>>> -#define RDMA2_SOUT_DSI1			0x1
>>> -#define RDMA2_SOUT_DSI2			0x4
>>> -#define RDMA2_SOUT_DSI3			0x5
>>> -#define DPI0_SEL_IN_RDMA1		0x1
>>> -#define DPI0_SEL_IN_RDMA2		0x3
>>> -#define DPI1_SEL_IN_RDMA1		(0x1 << 8)
>>> -#define DPI1_SEL_IN_RDMA2		(0x3 << 8)
>>> -#define DSI0_SEL_IN_RDMA1		0x1
>>> -#define DSI0_SEL_IN_RDMA2		0x4
>>> -#define DSI1_SEL_IN_RDMA1		0x1
>>> -#define DSI1_SEL_IN_RDMA2		0x4
>>> -#define DSI2_SEL_IN_RDMA1		(0x1 << 16)
>>> -#define DSI2_SEL_IN_RDMA2		(0x4 << 16)
>>> -#define DSI3_SEL_IN_RDMA1		(0x1 << 16)
>>> -#define DSI3_SEL_IN_RDMA2		(0x4 << 16)
>>> -#define COLOR1_SEL_IN_OVL1		0x1
>>> -
>>> -#define OVL_MOUT_EN_RDMA		0x1
>>> -#define BLS_TO_DSI_RDMA1_TO_DPI1	0x8
>>> -#define BLS_TO_DPI_RDMA1_TO_DSI		0x2
>>> -#define DSI_SEL_IN_BLS			0x0
>>> -#define DPI_SEL_IN_BLS			0x0
>>> -#define DSI_SEL_IN_RDMA			0x1
>>>  
>>>  struct mtk_disp_mutex {
>>>  	int id;
>>> @@ -246,200 +184,6 @@ static const struct mtk_ddp_data mt8173_ddp_driver_data = {
>>>  	.mutex_sof_reg = MT2701_DISP_MUTEX0_SOF0,
>>>  };
>>>  
>>> -static unsigned int mtk_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> -				    enum mtk_ddp_comp_id next,
>>> -				    unsigned int *addr)
>>> -{
>>> -	unsigned int value;
>>> -
>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> -		value = OVL0_MOUT_EN_COLOR0;
>>> -	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> -		value = OVL_MOUT_EN_RDMA;
>>> -	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> -		value = OD_MOUT_EN_RDMA0;
>>> -	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> -		value = UFOE_MOUT_EN_DSI0;
>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> -		value = OVL1_MOUT_EN_COLOR1;
>>> -	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> -		value = GAMMA_MOUT_EN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> -		value = OD1_MOUT_EN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DPI0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DPI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DSI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DSI2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> -		value = RDMA0_SOUT_DSI3;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DSI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DSI2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DSI3;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DPI0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> -		value = RDMA1_SOUT_DPI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DPI0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DPI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DSI1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DSI2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> -		value = RDMA2_SOUT_DSI3;
>>> -	} else {
>>> -		value = 0;
>>> -	}
>>> -
>>> -	return value;
>>> -}
>>> -
>>> -static unsigned int mtk_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> -				   enum mtk_ddp_comp_id next,
>>> -				   unsigned int *addr)
>>> -{
>>> -	unsigned int value;
>>> -
>>> -	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> -		value = COLOR0_SEL_IN_OVL0;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI0_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI1_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI0_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> -		value = DSI1_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI2_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> -		value = DSI3_SEL_IN_RDMA1;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI0_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> -		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> -		value = DPI1_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI0_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> -		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> -		value = DSI1_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI2_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> -		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> -		value = DSI3_SEL_IN_RDMA2;
>>> -	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> -		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> -		value = COLOR1_SEL_IN_OVL1;
>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> -		*addr = DISP_REG_CONFIG_DSI_SEL;
>>> -		value = DSI_SEL_IN_BLS;
>>> -	} else {
>>> -		value = 0;
>>> -	}
>>> -
>>> -	return value;
>>> -}
>>> -
>>> -static void mtk_ddp_sout_sel(void __iomem *config_regs,
>>> -			     enum mtk_ddp_comp_id cur,
>>> -			     enum mtk_ddp_comp_id next)
>>> -{
>>> -	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> -		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> -	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>>> -		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>>> -			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> -		writel_relaxed(DSI_SEL_IN_RDMA,
>>> -			       config_regs + DISP_REG_CONFIG_DSI_SEL);
>>> -		writel_relaxed(DPI_SEL_IN_BLS,
>>> -			       config_regs + DISP_REG_CONFIG_DPI_SEL);
>>> -	}
>>> -}
>>> -
>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
>>> -			      enum mtk_ddp_comp_id cur,
>>> -			      enum mtk_ddp_comp_id next)
>>> -{
>>> -	unsigned int addr, value, reg;
>>> -
>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) | value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -
>>> -	mtk_ddp_sout_sel(config_regs, cur, next);
>>> -
>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) | value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -}
>>> -
>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
>>> -				   enum mtk_ddp_comp_id cur,
>>> -				   enum mtk_ddp_comp_id next)
>>> -{
>>> -	unsigned int addr, value, reg;
>>> -
>>> -	value = mtk_ddp_mout_en(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -
>>> -	value = mtk_ddp_sel_in(cur, next, &addr);
>>> -	if (value) {
>>> -		reg = readl_relaxed(config_regs + addr) & ~value;
>>> -		writel_relaxed(reg, config_regs + addr);
>>> -	}
>>> -}
>>> -
>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id)
>>>  {
>>>  	struct mtk_ddp *ddp = dev_get_drvdata(dev);
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>> index 827be424a148..6b691a57be4a 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.h
>>> @@ -12,13 +12,6 @@ struct regmap;
>>>  struct device;
>>>  struct mtk_disp_mutex;
>>>  
>>> -void mtk_ddp_add_comp_to_path(void __iomem *config_regs,
>>> -			      enum mtk_ddp_comp_id cur,
>>> -			      enum mtk_ddp_comp_id next);
>>> -void mtk_ddp_remove_comp_from_path(void __iomem *config_regs,
>>> -				   enum mtk_ddp_comp_id cur,
>>> -				   enum mtk_ddp_comp_id next);
>>> -
>>>  struct mtk_disp_mutex *mtk_disp_mutex_get(struct device *dev, unsigned int id);
>>>  int mtk_disp_mutex_prepare(struct mtk_disp_mutex *mutex);
>>>  void mtk_disp_mutex_add_comp(struct mtk_disp_mutex *mutex,
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>> index 8e2d3cb62ad5..208f9c5256ef 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
>>> @@ -10,6 +10,7 @@
>>>  #include <linux/of_address.h>
>>>  #include <linux/of_platform.h>
>>>  #include <linux/pm_runtime.h>
>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>>  #include <linux/dma-mapping.h>
>>>  
>>>  #include <drm/drm_atomic.h>
>>> @@ -425,7 +426,6 @@ static int mtk_drm_probe(struct platform_device *pdev)
>>>  {
>>>  	struct device *dev = &pdev->dev;
>>>  	struct mtk_drm_private *private;
>>> -	struct resource *mem;
>>>  	struct device_node *node;
>>>  	struct component_match *match = NULL;
>>>  	int ret;
>>> @@ -436,14 +436,10 @@ static int mtk_drm_probe(struct platform_device *pdev)
>>>  		return -ENOMEM;
>>>  
>>>  	private->data = of_device_get_match_data(dev);
>>> -
>>> -	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> -	private->config_regs = devm_ioremap_resource(dev, mem);
>>> -	if (IS_ERR(private->config_regs)) {
>>> -		ret = PTR_ERR(private->config_regs);
>>> -		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
>>> -			ret);
>>> -		return ret;
>>> +	private->mmsys_dev = dev->parent;
>>> +	if (!private->mmsys_dev) {
>>> +		dev_err(dev, "Failed to get MMSYS device\n");
>>> +		return -ENODEV;
>>>  	}
>>>  
>>>  	/* Iterate over sibling DISP function blocks */
>>> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>> index 17bc99b9f5d4..b5be63e53176 100644
>>> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
>>> @@ -39,7 +39,7 @@ struct mtk_drm_private {
>>>  
>>>  	struct device_node *mutex_node;
>>>  	struct device *mutex_dev;
>>> -	void __iomem *config_regs;
>>> +	struct device *mmsys_dev;
>>>  	struct device_node *comp_node[DDP_COMPONENT_ID_MAX];
>>>  	struct mtk_ddp_comp *ddp_comp[DDP_COMPONENT_ID_MAX];
>>>  	const struct mtk_mmsys_driver_data *data;
>>> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
>>> index dbdfedd302fa..4b286b525cd3 100644
>>> --- a/drivers/soc/mediatek/mtk-mmsys.c
>>> +++ b/drivers/soc/mediatek/mtk-mmsys.c
>>> @@ -5,8 +5,76 @@
>>>   */
>>>  
>>>  #include <linux/clk-provider.h>
>>> +#include <linux/device.h>
>>>  #include <linux/of_device.h>
>>>  #include <linux/platform_device.h>
>>> +#include <linux/soc/mediatek/mtk-mmsys.h>
>>> +
>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp.h"
>>> +#include "../../gpu/drm/mediatek/mtk_drm_ddp_comp.h"
>>> +
>>> +#define DISP_REG_CONFIG_DISP_OVL0_MOUT_EN	0x040
>>> +#define DISP_REG_CONFIG_DISP_OVL1_MOUT_EN	0x044
>>> +#define DISP_REG_CONFIG_DISP_OD_MOUT_EN		0x048
>>> +#define DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN	0x04c
>>> +#define DISP_REG_CONFIG_DISP_UFOE_MOUT_EN	0x050
>>> +#define DISP_REG_CONFIG_DISP_COLOR0_SEL_IN	0x084
>>> +#define DISP_REG_CONFIG_DISP_COLOR1_SEL_IN	0x088
>>> +#define DISP_REG_CONFIG_DSIE_SEL_IN		0x0a4
>>> +#define DISP_REG_CONFIG_DSIO_SEL_IN		0x0a8
>>> +#define DISP_REG_CONFIG_DPI_SEL_IN		0x0ac
>>> +#define DISP_REG_CONFIG_DISP_RDMA2_SOUT		0x0b8
>>> +#define DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN	0x0c4
>>> +#define DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN	0x0c8
>>> +#define DISP_REG_CONFIG_MMSYS_CG_CON0		0x100
>>> +
>>> +#define DISP_REG_CONFIG_DISP_OVL_MOUT_EN	0x030
>>> +#define DISP_REG_CONFIG_OUT_SEL			0x04c
>>> +#define DISP_REG_CONFIG_DSI_SEL			0x050
>>> +#define DISP_REG_CONFIG_DPI_SEL			0x064
>>> +
>>> +#define OVL0_MOUT_EN_COLOR0			0x1
>>> +#define OD_MOUT_EN_RDMA0			0x1
>>> +#define OD1_MOUT_EN_RDMA1			BIT(16)
>>> +#define UFOE_MOUT_EN_DSI0			0x1
>>> +#define COLOR0_SEL_IN_OVL0			0x1
>>> +#define OVL1_MOUT_EN_COLOR1			0x1
>>> +#define GAMMA_MOUT_EN_RDMA1			0x1
>>> +#define RDMA0_SOUT_DPI0				0x2
>>> +#define RDMA0_SOUT_DPI1				0x3
>>> +#define RDMA0_SOUT_DSI1				0x1
>>> +#define RDMA0_SOUT_DSI2				0x4
>>> +#define RDMA0_SOUT_DSI3				0x5
>>> +#define RDMA1_SOUT_DPI0				0x2
>>> +#define RDMA1_SOUT_DPI1				0x3
>>> +#define RDMA1_SOUT_DSI1				0x1
>>> +#define RDMA1_SOUT_DSI2				0x4
>>> +#define RDMA1_SOUT_DSI3				0x5
>>> +#define RDMA2_SOUT_DPI0				0x2
>>> +#define RDMA2_SOUT_DPI1				0x3
>>> +#define RDMA2_SOUT_DSI1				0x1
>>> +#define RDMA2_SOUT_DSI2				0x4
>>> +#define RDMA2_SOUT_DSI3				0x5
>>> +#define DPI0_SEL_IN_RDMA1			0x1
>>> +#define DPI0_SEL_IN_RDMA2			0x3
>>> +#define DPI1_SEL_IN_RDMA1			(0x1 << 8)
>>> +#define DPI1_SEL_IN_RDMA2			(0x3 << 8)
>>> +#define DSI0_SEL_IN_RDMA1			0x1
>>> +#define DSI0_SEL_IN_RDMA2			0x4
>>> +#define DSI1_SEL_IN_RDMA1			0x1
>>> +#define DSI1_SEL_IN_RDMA2			0x4
>>> +#define DSI2_SEL_IN_RDMA1			(0x1 << 16)
>>> +#define DSI2_SEL_IN_RDMA2			(0x4 << 16)
>>> +#define DSI3_SEL_IN_RDMA1			(0x1 << 16)
>>> +#define DSI3_SEL_IN_RDMA2			(0x4 << 16)
>>> +#define COLOR1_SEL_IN_OVL1			0x1
>>> +
>>> +#define OVL_MOUT_EN_RDMA			0x1
>>> +#define BLS_TO_DSI_RDMA1_TO_DPI1		0x8
>>> +#define BLS_TO_DPI_RDMA1_TO_DSI			0x2
>>> +#define DSI_SEL_IN_BLS				0x0
>>> +#define DPI_SEL_IN_BLS				0x0
>>> +#define DSI_SEL_IN_RDMA				0x1
>>>  
>>>  struct mtk_mmsys_driver_data {
>>>  	const char *clk_driver;
>>> @@ -16,10 +84,221 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
>>>  	.clk_driver = "clk-mt8173-mm",
>>>  };
>>>  
>>> +static unsigned int mtk_mmsys_ddp_mout_en(enum mtk_ddp_comp_id cur,
>>> +					  enum mtk_ddp_comp_id next,
>>> +					  unsigned int *addr)
>>> +{
>>> +	unsigned int value;
>>> +
>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OVL0_MOUT_EN;
>>> +		value = OVL0_MOUT_EN_COLOR0;
>>> +	} else if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_RDMA0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OVL_MOUT_EN;
>>> +		value = OVL_MOUT_EN_RDMA;
>>> +	} else if (cur == DDP_COMPONENT_OD0 && next == DDP_COMPONENT_RDMA0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> +		value = OD_MOUT_EN_RDMA0;
>>> +	} else if (cur == DDP_COMPONENT_UFOE && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_UFOE_MOUT_EN;
>>> +		value = UFOE_MOUT_EN_DSI0;
>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OVL1_MOUT_EN;
>>> +		value = OVL1_MOUT_EN_COLOR1;
>>> +	} else if (cur == DDP_COMPONENT_GAMMA && next == DDP_COMPONENT_RDMA1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN;
>>> +		value = GAMMA_MOUT_EN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
>>> +		value = OD1_MOUT_EN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DPI0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DPI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DSI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DSI2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
>>> +		value = RDMA0_SOUT_DSI3;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DSI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DSI2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DSI3;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DPI0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
>>> +		value = RDMA1_SOUT_DPI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DPI0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DPI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DSI1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DSI2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
>>> +		value = RDMA2_SOUT_DSI3;
>>> +	} else {
>>> +		value = 0;
>>> +	}
>>> +
>>> +	return value;
>>> +}
>>> +
>>> +static unsigned int mtk_mmsys_ddp_sel_in(enum mtk_ddp_comp_id cur,
>>> +					 enum mtk_ddp_comp_id next,
>>> +					 unsigned int *addr)
>>> +{
>>> +	unsigned int value;
>>> +
>>> +	if (cur == DDP_COMPONENT_OVL0 && next == DDP_COMPONENT_COLOR0) {
>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR0_SEL_IN;
>>> +		value = COLOR0_SEL_IN_OVL0;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI0_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI1_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI0_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> +		value = DSI1_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI2_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> +		value = DSI3_SEL_IN_RDMA1;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI0_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
>>> +		*addr = DISP_REG_CONFIG_DPI_SEL_IN;
>>> +		value = DPI1_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI0_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
>>> +		*addr = DISP_REG_CONFIG_DSIO_SEL_IN;
>>> +		value = DSI1_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI2_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
>>> +		*addr = DISP_REG_CONFIG_DSIE_SEL_IN;
>>> +		value = DSI3_SEL_IN_RDMA2;
>>> +	} else if (cur == DDP_COMPONENT_OVL1 && next == DDP_COMPONENT_COLOR1) {
>>> +		*addr = DISP_REG_CONFIG_DISP_COLOR1_SEL_IN;
>>> +		value = COLOR1_SEL_IN_OVL1;
>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> +		*addr = DISP_REG_CONFIG_DSI_SEL;
>>> +		value = DSI_SEL_IN_BLS;
>>> +	} else {
>>> +		value = 0;
>>> +	}
>>> +
>>> +	return value;
>>> +}
>>> +
>>> +static void mtk_mmsys_ddp_sout_sel(void __iomem *config_regs,
>>> +				   enum mtk_ddp_comp_id cur,
>>> +				   enum mtk_ddp_comp_id next)
>>> +{
>>> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
>>> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> +	} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
>>> +		writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI,
>>> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
>>> +		writel_relaxed(DSI_SEL_IN_RDMA,
>>> +			       config_regs + DISP_REG_CONFIG_DSI_SEL);
>>> +		writel_relaxed(DPI_SEL_IN_BLS,
>>> +			       config_regs + DISP_REG_CONFIG_DPI_SEL);
>>> +	}
>>> +}
>>> +
>>> +void mtk_mmsys_ddp_connect(struct device *dev,
>>> +			   enum mtk_ddp_comp_id cur,
>>> +			   enum mtk_ddp_comp_id next)
>>> +{
>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
>>> +	unsigned int addr, value, reg;
>>> +
>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) | value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +
>>> +	mtk_mmsys_ddp_sout_sel(config_regs, cur, next);
>>> +
>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) | value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +}
>>> +
>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> +			      enum mtk_ddp_comp_id cur,
>>> +			      enum mtk_ddp_comp_id next)
>>> +{
>>> +	void __iomem *config_regs = dev_get_drvdata(dev);
>>> +	unsigned int addr, value, reg;
>>> +
>>> +	value = mtk_mmsys_ddp_mout_en(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +
>>> +	value = mtk_mmsys_ddp_sel_in(cur, next, &addr);
>>> +	if (value) {
>>> +		reg = readl_relaxed(config_regs + addr) & ~value;
>>> +		writel_relaxed(reg, config_regs + addr);
>>> +	}
>>> +}
>>> +
>>>  static int mtk_mmsys_probe(struct platform_device *pdev)
>>>  {
>>>  	const struct mtk_mmsys_driver_data *data;
>>> +	struct device *dev = &pdev->dev;
>>>  	struct platform_device *clks;
>>> +	void __iomem *config_regs;
>>> +	struct resource *mem;
>>> +	int ret;
>>> +
>>> +	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>>> +	config_regs = devm_ioremap_resource(dev, mem);
>>> +	if (IS_ERR(config_regs)) {
>>> +		ret = PTR_ERR(config_regs);
>>> +		dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n",
>>> +			ret);
>>> +		return ret;
>>> +	}
>>> +
>>> +	platform_set_drvdata(pdev, config_regs);
>>>  
>>>  	data = of_device_get_match_data(&pdev->dev);
>>>  
>>> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
>>> new file mode 100644
>>> index 000000000000..7bab5d9a3d31
>>> --- /dev/null
>>> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
>>> @@ -0,0 +1,20 @@
>>> +/* SPDX-License-Identifier: GPL-2.0-only */
>>> +/*
>>> + * Copyright (c) 2015 MediaTek Inc.
>>> + */
>>> +
>>> +#ifndef __MTK_MMSYS_H
>>> +#define __MTK_MMSYS_H
>>> +
>>> +enum mtk_ddp_comp_id;
>>> +struct device;
>>> +
>>> +void mtk_mmsys_ddp_connect(struct device *dev,
>>> +			   enum mtk_ddp_comp_id cur,
>>> +			   enum mtk_ddp_comp_id next);
>>> +
>>> +void mtk_mmsys_ddp_disconnect(struct device *dev,
>>> +			      enum mtk_ddp_comp_id cur,
>>> +			      enum mtk_ddp_comp_id next);
>>> +
>>> +#endif /* __MTK_MMSYS_H */
>>>
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, back to index

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-11 16:53 [PATCH v12 0/5] arm/arm64: mediatek: Fix mt8173 mmsys device probing Enric Balletbo i Serra
2020-03-11 16:53 ` [PATCH v12 1/5] drm/mediatek: Omit warning on probe defers Enric Balletbo i Serra
2020-03-11 16:53 ` [PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller Enric Balletbo i Serra
2020-03-12 15:22   ` Rob Herring
2020-03-11 16:53 ` [PATCH v12 3/5] clk / soc: mediatek: Move mt8173 MMSYS to platform driver Enric Balletbo i Serra
2020-03-11 16:58   ` Enric Balletbo i Serra
     [not found]   ` <158474603935.125146.14986079780178656133@swboyd.mtv.corp.google.com>
2020-03-25 15:36     ` Chun-Kuang Hu
2020-03-11 16:53 ` [PATCH v12 4/5] soc / drm: mediatek: Move routing control to mmsys device Enric Balletbo i Serra
2020-03-25 16:16   ` Matthias Brugger
2020-03-25 23:05     ` CK Hu
2020-03-26 11:54       ` Matthias Brugger
2020-03-26 14:51         ` CK Hu
2020-03-26 15:45           ` Matthias Brugger
2020-03-27  1:55             ` CK Hu
2020-03-27 17:04       ` Matthias Brugger
2020-03-11 16:53 ` [PATCH v12 5/5] soc / drm: mediatek: Fix mediatek-drm device probing Enric Balletbo i Serra

Linux-ARM-Kernel Archive on lore.kernel.org

Archives are clonable:
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/0 linux-arm-kernel/git/0.git
	git clone --mirror https://lore.kernel.org/linux-arm-kernel/1 linux-arm-kernel/git/1.git

	# If you have public-inbox 1.1+ installed, you may
	# initialize and index your mirror using the following commands:
	public-inbox-init -V2 linux-arm-kernel linux-arm-kernel/ https://lore.kernel.org/linux-arm-kernel \
		linux-arm-kernel@lists.infradead.org
	public-inbox-index linux-arm-kernel

Example config snippet for mirrors

Newsgroup available over NNTP:
	nntp://nntp.lore.kernel.org/org.infradead.lists.linux-arm-kernel


AGPL code for this site: git clone https://public-inbox.org/public-inbox.git