[PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON

[PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON

[Julien Thierry]

On a system with two security states, if SCR_EL3.FIQ is set, non-secure
IRQ priorities get shifted to fit the secure view but priority masks
aren't.

On such system, it turns out that GIC_PRIO_IRQON masks the priority of
normal interrupts, which obviously ends up in a hang.

Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure
interrupts are not blocked by it.

Fixes: bd82d4bd21880b7c ("arm64: Fix incorrect irqflag restore for
       priority masking")
Signed-off-by: Julien Thierry <julien.thierry.kdev@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Marc Zyngier <maz@kernel.org>
---
 arch/arm64/include/asm/arch_gicv3.h | 6 ++++++
 arch/arm64/include/asm/ptrace.h     | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

Hopefully the last surprise...

diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
index 79155a8..89e4c8b 100644
--- a/arch/arm64/include/asm/arch_gicv3.h
+++ b/arch/arm64/include/asm/arch_gicv3.h
@@ -155,6 +155,12 @@ static inline void gic_pmr_mask_irqs(void)
 	BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
 					 GIC_PRIO_PSR_I_SET));
 	BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
+	/*
+	 * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
+	 * and non-secure PMR accesses are not subject to the shifts that
+	 * are applied to IRQ priorities
+	 */
+	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
 	gic_write_pmr(GIC_PRIO_IRQOFF);
 }

diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
index b1dd039..1dcf63a 100644
--- a/arch/arm64/include/asm/ptrace.h
+++ b/arch/arm64/include/asm/ptrace.h
@@ -30,7 +30,7 @@
  * in the  the priority mask, it indicates that PSR.I should be set and
  * interrupt disabling temporarily does not rely on IRQ priorities.
  */
-#define GIC_PRIO_IRQON			0xc0
+#define GIC_PRIO_IRQON			0xe0
 #define GIC_PRIO_IRQOFF			(GIC_PRIO_IRQON & ~0x80)
 #define GIC_PRIO_PSR_I_SET		(1 << 4)

--
1.9.1

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Re: [PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON

[Julien Thierry]

Hi,

On Mon, 29 Jul 2019 at 15:57, Julien Thierry
<julien.thierry.kdev@gmail.com> wrote:
>
> On a system with two security states, if SCR_EL3.FIQ is set, non-secure

I meant to say when "SCR_EL3.FIQ is cleared".

Cheers,

Julien

> IRQ priorities get shifted to fit the secure view but priority masks
> aren't.
>
> On such system, it turns out that GIC_PRIO_IRQON masks the priority of
> normal interrupts, which obviously ends up in a hang.
>
> Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure
> interrupts are not blocked by it.
>
> Fixes: bd82d4bd21880b7c ("arm64: Fix incorrect irqflag restore for
>        priority masking")
> Signed-off-by: Julien Thierry <julien.thierry.kdev@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Oleg Nesterov <oleg@redhat.com>
> Cc: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/arch_gicv3.h | 6 ++++++
>  arch/arm64/include/asm/ptrace.h     | 2 +-
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> Hopefully the last surprise...
>
> diff --git a/arch/arm64/include/asm/arch_gicv3.h b/arch/arm64/include/asm/arch_gicv3.h
> index 79155a8..89e4c8b 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -155,6 +155,12 @@ static inline void gic_pmr_mask_irqs(void)
>         BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
>                                          GIC_PRIO_PSR_I_SET));
>         BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
> +       /*
> +        * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
> +        * and non-secure PMR accesses are not subject to the shifts that
> +        * are applied to IRQ priorities
> +        */
> +       BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
>         gic_write_pmr(GIC_PRIO_IRQOFF);
>  }
>
> diff --git a/arch/arm64/include/asm/ptrace.h b/arch/arm64/include/asm/ptrace.h
> index b1dd039..1dcf63a 100644
> --- a/arch/arm64/include/asm/ptrace.h
> +++ b/arch/arm64/include/asm/ptrace.h
> @@ -30,7 +30,7 @@
>   * in the  the priority mask, it indicates that PSR.I should be set and
>   * interrupt disabling temporarily does not rely on IRQ priorities.
>   */
> -#define GIC_PRIO_IRQON                 0xc0
> +#define GIC_PRIO_IRQON                 0xe0
>  #define GIC_PRIO_IRQOFF                        (GIC_PRIO_IRQON & ~0x80)
>  #define GIC_PRIO_PSR_I_SET             (1 << 4)
>
> --
> 1.9.1

-- 
Julien Thierry

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Re: [PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON

[Marc Zyngier]

On 2019-07-29 15:57, Julien Thierry wrote:
> On a system with two security states, if SCR_EL3.FIQ is set, 
> non-secure
> IRQ priorities get shifted to fit the secure view but priority masks
> aren't.
>
> On such system, it turns out that GIC_PRIO_IRQON masks the priority 
> of
> normal interrupts, which obviously ends up in a hang.
>
> Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure
> interrupts are not blocked by it.
>
> Fixes: bd82d4bd21880b7c ("arm64: Fix incorrect irqflag restore for
>        priority masking")
> Signed-off-by: Julien Thierry <julien.thierry.kdev@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Oleg Nesterov <oleg@redhat.com>
> Cc: Marc Zyngier <maz@kernel.org>
> ---
>  arch/arm64/include/asm/arch_gicv3.h | 6 ++++++
>  arch/arm64/include/asm/ptrace.h     | 2 +-
>  2 files changed, 7 insertions(+), 1 deletion(-)
>
> Hopefully the last surprise...
>
> diff --git a/arch/arm64/include/asm/arch_gicv3.h
> b/arch/arm64/include/asm/arch_gicv3.h
> index 79155a8..89e4c8b 100644
> --- a/arch/arm64/include/asm/arch_gicv3.h
> +++ b/arch/arm64/include/asm/arch_gicv3.h
> @@ -155,6 +155,12 @@ static inline void gic_pmr_mask_irqs(void)
>  	BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
>  					 GIC_PRIO_PSR_I_SET));
>  	BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
> +	/*
> +	 * Need to make sure IRQON allows IRQs when SCR_EL3.FIQ is cleared
> +	 * and non-secure PMR accesses are not subject to the shifts that
> +	 * are applied to IRQ priorities
> +	 */
> +	BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
>  	gic_write_pmr(GIC_PRIO_IRQOFF);
>  }
>
> diff --git a/arch/arm64/include/asm/ptrace.h
> b/arch/arm64/include/asm/ptrace.h
> index b1dd039..1dcf63a 100644
> --- a/arch/arm64/include/asm/ptrace.h
> +++ b/arch/arm64/include/asm/ptrace.h
> @@ -30,7 +30,7 @@
>   * in the  the priority mask, it indicates that PSR.I should be set 
> and
>   * interrupt disabling temporarily does not rely on IRQ priorities.
>   */
> -#define GIC_PRIO_IRQON			0xc0
> +#define GIC_PRIO_IRQON			0xe0
>  #define GIC_PRIO_IRQOFF			(GIC_PRIO_IRQON & ~0x80)
>  #define GIC_PRIO_PSR_I_SET		(1 << 4)
>
> --
> 1.9.1

With the commit message fixed (s/set/cleared/):

Acked-by: Marc Zyngier <marc.zyngier@arm.com>

Thanks,

         M.
-- 
Jazz is not dead. It just smells funny...

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Re: [PATCH] arm64: Lower priority mask for GIC_PRIO_IRQON

[Catalin Marinas]

On Mon, Jul 29, 2019 at 03:57:46PM +0100, Julien Thierry wrote:
> On a system with two security states, if SCR_EL3.FIQ is set, non-secure
> IRQ priorities get shifted to fit the secure view but priority masks
> aren't.
> 
> On such system, it turns out that GIC_PRIO_IRQON masks the priority of
> normal interrupts, which obviously ends up in a hang.
> 
> Increase GIC_PRIO_IRQON value (i.e. lower priority) to make sure
> interrupts are not blocked by it.
> 
> Fixes: bd82d4bd21880b7c ("arm64: Fix incorrect irqflag restore for
>        priority masking")
> Signed-off-by: Julien Thierry <julien.thierry.kdev@gmail.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Oleg Nesterov <oleg@redhat.com>
> Cc: Marc Zyngier <maz@kernel.org>

I queued this through the arm64 for-next/fixes tree. Thanks.

-- 
Catalin

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