* [PATCH 0/3] Add S4 SoC clock controller driver
@ 2022-07-08 6:27 Yu Tu
2022-07-08 6:27 ` [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
` (2 more replies)
0 siblings, 3 replies; 15+ messages in thread
From: Yu Tu @ 2022-07-08 6:27 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Cc: Yu Tu
1. Add clock controller driver for S4 SOC.
Yu Tu (3):
dt-bindings: clk: meson: add S4 SoC clock controller bindings
arm64: dts: meson: add S4 Soc clock controller in DT
clk: meson: s4: add s4 SoC clock controller driver
.../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
MAINTAINERS | 3 +-
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 9 +-
drivers/clk/meson/Kconfig | 17 +
drivers/clk/meson/Makefile | 1 +
drivers/clk/meson/s4.c | 4678 +++++++++++++++++
drivers/clk/meson/s4.h | 156 +
include/dt-bindings/clock/s4-clkc.h | 354 ++
8 files changed, 5217 insertions(+), 2 deletions(-)
create mode 100644 drivers/clk/meson/s4.c
create mode 100644 drivers/clk/meson/s4.h
create mode 100644 include/dt-bindings/clock/s4-clkc.h
base-commit: 292dcfc1f60eee7d389d0184df4ef27be8b55077
--
2.33.1
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings
2022-07-08 6:27 [PATCH 0/3] Add S4 SoC clock controller driver Yu Tu
@ 2022-07-08 6:27 ` Yu Tu
2022-07-11 12:25 ` Jerome Brunet
2022-07-12 9:40 ` Krzysztof Kozlowski
2022-07-08 6:27 ` [PATCH 2/3] arm64: dts: meson: add S4 Soc clock controller in DT Yu Tu
[not found] ` <20220708062757.3662-4-yu.tu@amlogic.com>
2 siblings, 2 replies; 15+ messages in thread
From: Yu Tu @ 2022-07-08 6:27 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Cc: Yu Tu
Add new clock controller compatible and dt-bindings header for the
Everything-Else domain of the S4 SoC.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
.../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
MAINTAINERS | 1 +
include/dt-bindings/clock/s4-clkc.h | 354 ++++++++++++++++++
3 files changed, 356 insertions(+)
create mode 100644 include/dt-bindings/clock/s4-clkc.h
diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
index 7ccecd5c02c1..301b43dea912 100644
--- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
+++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
@@ -12,6 +12,7 @@ Required Properties:
"amlogic,g12a-clkc" for G12A SoC.
"amlogic,g12b-clkc" for G12B SoC.
"amlogic,sm1-clkc" for SM1 SoC.
+ "amlogic,s4-clkc" for S4 SoC.
- clocks : list of clock phandle, one for each entry clock-names.
- clock-names : should contain the following:
* "xtal": the platform xtal
diff --git a/MAINTAINERS b/MAINTAINERS
index c1abc53f9e91..e4ca46c5c8a1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
F: drivers/clk/meson/
F: include/dt-bindings/clock/gxbb*
F: include/dt-bindings/clock/meson*
+F: include/dt-bindings/clock/s*
ARM/Amlogic Meson SoC Crypto Drivers
M: Corentin Labbe <clabbe@baylibre.com>
diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
new file mode 100644
index 000000000000..8b46d54d79fe
--- /dev/null
+++ b/include/dt-bindings/clock/s4-clkc.h
@@ -0,0 +1,354 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
+ * Author: Yu Tu <yu.tu@amlogic.com>
+ */
+
+#ifndef __S4_CLKC_H
+#define __S4_CLKC_H
+
+/*
+ * CLKID index values
+ */
+
+#define CLKID_PLL_BASE 0
+#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
+#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
+#define CLKID_FCLK_DIV2_DIV (CLKID_PLL_BASE + 2)
+#define CLKID_FCLK_DIV2 (CLKID_PLL_BASE + 3)
+#define CLKID_FCLK_DIV3_DIV (CLKID_PLL_BASE + 4)
+#define CLKID_FCLK_DIV3 (CLKID_PLL_BASE + 5)
+#define CLKID_FCLK_DIV4_DIV (CLKID_PLL_BASE + 6)
+#define CLKID_FCLK_DIV4 (CLKID_PLL_BASE + 7)
+#define CLKID_FCLK_DIV5_DIV (CLKID_PLL_BASE + 8)
+#define CLKID_FCLK_DIV5 (CLKID_PLL_BASE + 9)
+#define CLKID_FCLK_DIV7_DIV (CLKID_PLL_BASE + 10)
+#define CLKID_FCLK_DIV7 (CLKID_PLL_BASE + 11)
+#define CLKID_FCLK_DIV2P5_DIV (CLKID_PLL_BASE + 12)
+#define CLKID_FCLK_DIV2P5 (CLKID_PLL_BASE + 13)
+#define CLKID_GP0_PLL_DCO (CLKID_PLL_BASE + 14)
+#define CLKID_GP0_PLL (CLKID_PLL_BASE + 15)
+#define CLKID_HIFI_PLL_DCO (CLKID_PLL_BASE + 16)
+#define CLKID_HIFI_PLL (CLKID_PLL_BASE + 17)
+#define CLKID_HDMI_PLL_DCO (CLKID_PLL_BASE + 18)
+#define CLKID_HDMI_PLL_OD (CLKID_PLL_BASE + 19)
+#define CLKID_HDMI_PLL (CLKID_PLL_BASE + 20)
+#define CLKID_MPLL_50M_DIV (CLKID_PLL_BASE + 21)
+#define CLKID_MPLL_50M (CLKID_PLL_BASE + 22)
+#define CLKID_MPLL_PREDIV (CLKID_PLL_BASE + 23)
+#define CLKID_MPLL0_DIV (CLKID_PLL_BASE + 24)
+#define CLKID_MPLL0 (CLKID_PLL_BASE + 25)
+#define CLKID_MPLL1_DIV (CLKID_PLL_BASE + 26)
+#define CLKID_MPLL1 (CLKID_PLL_BASE + 27)
+#define CLKID_MPLL2_DIV (CLKID_PLL_BASE + 28)
+#define CLKID_MPLL2 (CLKID_PLL_BASE + 29)
+#define CLKID_MPLL3_DIV (CLKID_PLL_BASE + 30)
+#define CLKID_MPLL3 (CLKID_PLL_BASE + 31)
+
+#define CLKID_BASE (CLKID_PLL_BASE + 32)
+#define CLKID_RTC_32K_CLKIN (CLKID_BASE + 0)
+#define CLKID_RTC_32K_DIV (CLKID_BASE + 1)
+#define CLKID_RTC_32K_SEL (CLKID_BASE + 2)
+#define CLKID_RTC_32K_XATL (CLKID_BASE + 3)
+#define CLKID_RTC_CLK (CLKID_BASE + 4)
+#define CLKID_SYS_CLK_B_SEL (CLKID_BASE + 5)
+#define CLKID_SYS_CLK_B_DIV (CLKID_BASE + 6)
+#define CLKID_SYS_CLK_B_GATE (CLKID_BASE + 7)
+#define CLKID_SYS_CLK_A_SEL (CLKID_BASE + 8)
+#define CLKID_SYS_CLK_A_DIV (CLKID_BASE + 9)
+#define CLKID_SYS_CLK_A_GATE (CLKID_BASE + 10)
+#define CLKID_SYS_CLK (CLKID_BASE + 11)
+
+#define CLKID_CECA_32K_CLKIN (CLKID_BASE + 12)
+#define CLKID_CECA_32K_DIV (CLKID_BASE + 13)
+#define CLKID_CECA_32K_SEL_PRE (CLKID_BASE + 14)
+#define CLKID_CECA_32K_SEL (CLKID_BASE + 15)
+#define CLKID_CECA_32K_CLKOUT (CLKID_BASE + 16)
+#define CLKID_CECB_32K_CLKIN (CLKID_BASE + 17)
+#define CLKID_CECB_32K_DIV (CLKID_BASE + 18)
+#define CLKID_CECB_32K_SEL_PRE (CLKID_BASE + 19)
+#define CLKID_CECB_32K_SEL (CLKID_BASE + 20)
+#define CLKID_CECB_32K_CLKOUT (CLKID_BASE + 21)
+
+#define CLKID_SC_CLK_SEL (CLKID_BASE + 22)
+#define CLKID_SC_CLK_DIV (CLKID_BASE + 23)
+#define CLKID_SC_CLK_GATE (CLKID_BASE + 24)
+
+#define CLKID_DSPA_CLK_B_SEL (CLKID_BASE + 25)
+#define CLKID_DSPA_CLK_B_DIV (CLKID_BASE + 26)
+#define CLKID_DSPA_CLK_B_GATE (CLKID_BASE + 27)
+#define CLKID_DSPA_CLK_A_SEL (CLKID_BASE + 28)
+#define CLKID_DSPA_CLK_A_DIV (CLKID_BASE + 29)
+#define CLKID_DSPA_CLK_A_GATE (CLKID_BASE + 30)
+#define CLKID_DSPA_CLK (CLKID_BASE + 31)
+
+#define CLKID_12_24M_CLK_GATE (CLKID_BASE + 32)
+#define CLKID_12M_CLK_DIV (CLKID_BASE + 33)
+#define CLKID_12_24M_CLK_SEL (CLKID_BASE + 34)
+#define CLKID_25M_CLK_DIV (CLKID_BASE + 35)
+#define CLKID_25M_CLK_GATE (CLKID_BASE + 36)
+
+#define CLKID_VID_PLL_DIV (CLKID_BASE + 37)
+#define CLKID_VID_PLL_SEL (CLKID_BASE + 38)
+#define CLKID_VID_PLL (CLKID_BASE + 39)
+#define CLKID_VCLK_SEL (CLKID_BASE + 40)
+#define CLKID_VCLK2_SEL (CLKID_BASE + 41)
+#define CLKID_VCLK_INPUT (CLKID_BASE + 42)
+#define CLKID_VCLK2_INPUT (CLKID_BASE + 43)
+#define CLKID_VCLK_DIV (CLKID_BASE + 44)
+#define CLKID_VCLK2_DIV (CLKID_BASE + 45)
+#define CLKID_VCLK (CLKID_BASE + 46)
+#define CLKID_VCLK2 (CLKID_BASE + 47)
+#define CLKID_VCLK_DIV1 (CLKID_BASE + 48)
+#define CLKID_VCLK_DIV2_EN (CLKID_BASE + 49)
+#define CLKID_VCLK_DIV4_EN (CLKID_BASE + 50)
+#define CLKID_VCLK_DIV6_EN (CLKID_BASE + 51)
+#define CLKID_VCLK_DIV12_EN (CLKID_BASE + 52)
+#define CLKID_VCLK2_DIV1 (CLKID_BASE + 53)
+#define CLKID_VCLK2_DIV2_EN (CLKID_BASE + 54)
+#define CLKID_VCLK2_DIV4_EN (CLKID_BASE + 55)
+#define CLKID_VCLK2_DIV6_EN (CLKID_BASE + 56)
+#define CLKID_VCLK2_DIV12_EN (CLKID_BASE + 57)
+#define CLKID_VCLK_DIV2 (CLKID_BASE + 58)
+#define CLKID_VCLK_DIV4 (CLKID_BASE + 59)
+#define CLKID_VCLK_DIV6 (CLKID_BASE + 60)
+#define CLKID_VCLK_DIV12 (CLKID_BASE + 61)
+#define CLKID_VCLK2_DIV2 (CLKID_BASE + 62)
+#define CLKID_VCLK2_DIV4 (CLKID_BASE + 63)
+#define CLKID_VCLK2_DIV6 (CLKID_BASE + 64)
+#define CLKID_VCLK2_DIV12 (CLKID_BASE + 65)
+#define CLKID_CTS_ENCI_SEL (CLKID_BASE + 66)
+#define CLKID_CTS_ENCP_SEL (CLKID_BASE + 67)
+#define CLKID_CTS_VDAC_SEL (CLKID_BASE + 68)
+#define CLKID_HDMI_TX_SEL (CLKID_BASE + 69)
+#define CLKID_CTS_ENCI (CLKID_BASE + 70)
+#define CLKID_CTS_ENCP (CLKID_BASE + 71)
+#define CLKID_CTS_VDAC (CLKID_BASE + 72)
+#define CLKID_HDMI_TX (CLKID_BASE + 73)
+
+#define CLKID_HDMI_SEL (CLKID_BASE + 74)
+#define CLKID_HDMI_DIV (CLKID_BASE + 75)
+#define CLKID_HDMI (CLKID_BASE + 76)
+#define CLKID_TS_CLK_DIV (CLKID_BASE + 77)
+#define CLKID_TS_CLK_GATE (CLKID_BASE + 78)
+
+#define CLKID_MALI_0_SEL (CLKID_BASE + 79)
+#define CLKID_MALI_0_DIV (CLKID_BASE + 80)
+#define CLKID_MALI_0 (CLKID_BASE + 81)
+#define CLKID_MALI_1_SEL (CLKID_BASE + 82)
+#define CLKID_MALI_1_DIV (CLKID_BASE + 83)
+#define CLKID_MALI_1 (CLKID_BASE + 84)
+#define CLKID_MALI (CLKID_BASE + 85)
+
+#define CLKID_VDEC_P0_SEL (CLKID_BASE + 86)
+#define CLKID_VDEC_P0_DIV (CLKID_BASE + 87)
+#define CLKID_VDEC_P0 (CLKID_BASE + 88)
+#define CLKID_VDEC_P1_SEL (CLKID_BASE + 89)
+#define CLKID_VDEC_P1_DIV (CLKID_BASE + 90)
+#define CLKID_VDEC_P1 (CLKID_BASE + 91)
+#define CLKID_VDEC_SEL (CLKID_BASE + 92)
+
+#define CLKID_HCODEC_P0_SEL (CLKID_BASE + 93)
+#define CLKID_HCODEC_P0_DIV (CLKID_BASE + 94)
+#define CLKID_HCODEC_P0 (CLKID_BASE + 95)
+#define CLKID_HCODEC_P1_SEL (CLKID_BASE + 96)
+#define CLKID_HCODEC_P1_DIV (CLKID_BASE + 97)
+#define CLKID_HCODEC_P1 (CLKID_BASE + 98)
+#define CLKID_HCODEC_SEL (CLKID_BASE + 99)
+
+#define CLKID_HEVCB_P0_SEL (CLKID_BASE + 100)
+#define CLKID_HEVCB_P0_DIV (CLKID_BASE + 101)
+#define CLKID_HEVCB_P0 (CLKID_BASE + 102)
+#define CLKID_HEVCB_P1_SEL (CLKID_BASE + 103)
+#define CLKID_HEVCB_P1_DIV (CLKID_BASE + 104)
+#define CLKID_HEVCB_P1 (CLKID_BASE + 105)
+#define CLKID_HEVCB_SEL (CLKID_BASE + 106)
+
+#define CLKID_HEVCF_P0_SEL (CLKID_BASE + 107)
+#define CLKID_HEVCF_P0_DIV (CLKID_BASE + 108)
+#define CLKID_HEVCF_P0 (CLKID_BASE + 109)
+#define CLKID_HEVCF_P1_SEL (CLKID_BASE + 110)
+#define CLKID_HEVCF_P1_DIV (CLKID_BASE + 111)
+#define CLKID_HEVCF_P1 (CLKID_BASE + 112)
+#define CLKID_HEVCF_SEL (CLKID_BASE + 113)
+
+#define CLKID_WAVE_A_SEL (CLKID_BASE + 114)
+#define CLKID_WAVE_A_DIV (CLKID_BASE + 115)
+#define CLKID_WAVE_A_GATE (CLKID_BASE + 116)
+#define CLKID_WAVE_B_SEL (CLKID_BASE + 117)
+#define CLKID_WAVE_B_DIV (CLKID_BASE + 118)
+#define CLKID_WAVE_B_GATE (CLKID_BASE + 119)
+#define CLKID_WAVE_C_SEL (CLKID_BASE + 120)
+#define CLKID_WAVE_C_DIV (CLKID_BASE + 121)
+#define CLKID_WAVE_C_GATE (CLKID_BASE + 122)
+
+#define CLKID_VPU_0_SEL (CLKID_BASE + 123)
+#define CLKID_VPU_0_DIV (CLKID_BASE + 124)
+#define CLKID_VPU_0 (CLKID_BASE + 125)
+#define CLKID_VPU_1_SEL (CLKID_BASE + 126)
+#define CLKID_VPU_1_DIV (CLKID_BASE + 127)
+#define CLKID_VPU_1 (CLKID_BASE + 128)
+#define CLKID_VPU (CLKID_BASE + 129)
+
+#define CLKID_VPU_CLKB_TMP_SEL (CLKID_BASE + 130)
+#define CLKID_VPU_CLKB_TMP_DIV (CLKID_BASE + 131)
+#define CLKID_VPU_CLKB_TMP (CLKID_BASE + 132)
+#define CLKID_VPU_CLKB_DIV (CLKID_BASE + 133)
+#define CLKID_VPU_CLKB (CLKID_BASE + 134)
+
+#define CLKID_VPU_CLKC_P0_SEL (CLKID_BASE + 135)
+#define CLKID_VPU_CLKC_P0_DIV (CLKID_BASE + 136)
+#define CLKID_VPU_CLKC_P0 (CLKID_BASE + 137)
+#define CLKID_VPU_CLKC_P1_SEL (CLKID_BASE + 138)
+#define CLKID_VPU_CLKC_P1_DIV (CLKID_BASE + 139)
+#define CLKID_VPU_CLKC_P1 (CLKID_BASE + 140)
+#define CLKID_VPU_CLKC_SEL (CLKID_BASE + 141)
+
+#define CLKID_VAPB_0_SEL (CLKID_BASE + 142)
+#define CLKID_VAPB_0_DIV (CLKID_BASE + 143)
+#define CLKID_VAPB_0 (CLKID_BASE + 144)
+#define CLKID_VAPB_1_SEL (CLKID_BASE + 145)
+#define CLKID_VAPB_1_DIV (CLKID_BASE + 146)
+#define CLKID_VAPB_1 (CLKID_BASE + 147)
+#define CLKID_VAPB (CLKID_BASE + 148)
+
+#define CLKID_GE2D (CLKID_BASE + 149)
+
+#define CLKID_VDIN_MEAS_SEL (CLKID_BASE + 150)
+#define CLKID_VDIN_MEAS_DIV (CLKID_BASE + 151)
+#define CLKID_VDIN_MEAS_GATE (CLKID_BASE + 152)
+
+#define CLKID_SD_EMMC_C_CLK_SEL (CLKID_BASE + 153)
+#define CLKID_SD_EMMC_C_CLK_DIV (CLKID_BASE + 154)
+#define CLKID_SD_EMMC_C_CLK (CLKID_BASE + 155)
+#define CLKID_SD_EMMC_A_CLK_SEL (CLKID_BASE + 156)
+#define CLKID_SD_EMMC_A_CLK_DIV (CLKID_BASE + 157)
+#define CLKID_SD_EMMC_A_CLK (CLKID_BASE + 158)
+#define CLKID_SD_EMMC_B_CLK_SEL (CLKID_BASE + 159)
+#define CLKID_SD_EMMC_B_CLK_DIV (CLKID_BASE + 160)
+#define CLKID_SD_EMMC_B_CLK (CLKID_BASE + 161)
+
+#define CLKID_SPICC0_SEL (CLKID_BASE + 162)
+#define CLKID_SPICC0_DIV (CLKID_BASE + 163)
+#define CLKID_SPICC0_GATE (CLKID_BASE + 164)
+#define CLKID_SPICC1_SEL (CLKID_BASE + 165)
+#define CLKID_SPICC1_DIV (CLKID_BASE + 166)
+#define CLKID_SPICC1_GATE (CLKID_BASE + 167)
+
+#define CLKID_PWM_A_SEL (CLKID_BASE + 168)
+#define CLKID_PWM_A_DIV (CLKID_BASE + 169)
+#define CLKID_PWM_A_GATE (CLKID_BASE + 170)
+#define CLKID_PWM_B_SEL (CLKID_BASE + 171)
+#define CLKID_PWM_B_DIV (CLKID_BASE + 172)
+#define CLKID_PWM_B_GATE (CLKID_BASE + 173)
+#define CLKID_PWM_C_SEL (CLKID_BASE + 174)
+#define CLKID_PWM_C_DIV (CLKID_BASE + 175)
+#define CLKID_PWM_C_GATE (CLKID_BASE + 176)
+#define CLKID_PWM_D_SEL (CLKID_BASE + 177)
+#define CLKID_PWM_D_DIV (CLKID_BASE + 178)
+#define CLKID_PWM_D_GATE (CLKID_BASE + 179)
+#define CLKID_PWM_E_SEL (CLKID_BASE + 180)
+#define CLKID_PWM_E_DIV (CLKID_BASE + 181)
+#define CLKID_PWM_E_GATE (CLKID_BASE + 182)
+#define CLKID_PWM_F_SEL (CLKID_BASE + 183)
+#define CLKID_PWM_F_DIV (CLKID_BASE + 184)
+#define CLKID_PWM_F_GATE (CLKID_BASE + 185)
+#define CLKID_PWM_G_SEL (CLKID_BASE + 186)
+#define CLKID_PWM_G_DIV (CLKID_BASE + 187)
+#define CLKID_PWM_G_GATE (CLKID_BASE + 188)
+#define CLKID_PWM_H_SEL (CLKID_BASE + 189)
+#define CLKID_PWM_H_DIV (CLKID_BASE + 190)
+#define CLKID_PWM_H_GATE (CLKID_BASE + 191)
+#define CLKID_PWM_I_SEL (CLKID_BASE + 192)
+#define CLKID_PWM_I_DIV (CLKID_BASE + 193)
+#define CLKID_PWM_I_GATE (CLKID_BASE + 194)
+#define CLKID_PWM_J_SEL (CLKID_BASE + 195)
+#define CLKID_PWM_J_DIV (CLKID_BASE + 196)
+#define CLKID_PWM_J_GATE (CLKID_BASE + 197)
+
+#define CLKID_SARADC_SEL (CLKID_BASE + 198)
+#define CLKID_SARADC_DIV (CLKID_BASE + 199)
+#define CLKID_SARADC_GATE (CLKID_BASE + 200)
+#define CLKID_GEN_SEL (CLKID_BASE + 201)
+#define CLKID_GEN_DIV (CLKID_BASE + 202)
+#define CLKID_GEN_GATE (CLKID_BASE + 203)
+
+#define CLKID_DDR (CLKID_BASE + 204)
+#define CLKID_DOS (CLKID_BASE + 205)
+#define CLKID_ETHPHY (CLKID_BASE + 206)
+#define CLKID_MALI_GATE (CLKID_BASE + 207)
+#define CLKID_AOCPU (CLKID_BASE + 208)
+#define CLKID_AUCPU (CLKID_BASE + 209)
+#define CLKID_CEC (CLKID_BASE + 210)
+#define CLKID_SD_EMMC_A (CLKID_BASE + 211)
+#define CLKID_SD_EMMC_B (CLKID_BASE + 212)
+#define CLKID_NAND (CLKID_BASE + 213)
+#define CLKID_SMARTCARD (CLKID_BASE + 214)
+#define CLKID_ACODEC (CLKID_BASE + 215)
+#define CLKID_SPIFC (CLKID_BASE + 216)
+#define CLKID_MSR_CLK (CLKID_BASE + 217)
+#define CLKID_IR_CTRL (CLKID_BASE + 218)
+#define CLKID_AUDIO (CLKID_BASE + 219)
+#define CLKID_ETH (CLKID_BASE + 220)
+#define CLKID_UART_A (CLKID_BASE + 221)
+#define CLKID_UART_B (CLKID_BASE + 222)
+#define CLKID_UART_C (CLKID_BASE + 223)
+#define CLKID_UART_D (CLKID_BASE + 224)
+#define CLKID_UART_E (CLKID_BASE + 225)
+#define CLKID_AIFIFO (CLKID_BASE + 226)
+#define CLKID_TS_DDR (CLKID_BASE + 227)
+#define CLKID_TS_PLL (CLKID_BASE + 228)
+#define CLKID_G2D (CLKID_BASE + 229)
+#define CLKID_SPICC0 (CLKID_BASE + 230)
+#define CLKID_SPICC1 (CLKID_BASE + 231)
+#define CLKID_PCIE (CLKID_BASE + 232)
+#define CLKID_USB (CLKID_BASE + 233)
+#define CLKID_PCIE_PHY (CLKID_BASE + 234)
+#define CLKID_I2C_M_A (CLKID_BASE + 235)
+#define CLKID_I2C_M_B (CLKID_BASE + 236)
+#define CLKID_I2C_M_C (CLKID_BASE + 237)
+#define CLKID_I2C_M_D (CLKID_BASE + 238)
+#define CLKID_I2C_M_E (CLKID_BASE + 239)
+#define CLKID_I2C_M_F (CLKID_BASE + 240)
+#define CLKID_HDMITX_APB (CLKID_BASE + 241)
+#define CLKID_I2C_S_A (CLKID_BASE + 242)
+#define CLKID_USB1_TO_DDR (CLKID_BASE + 243)
+#define CLKID_HDCP22 (CLKID_BASE + 244)
+#define CLKID_MMC_APB (CLKID_BASE + 245)
+#define CLKID_RSA (CLKID_BASE + 246)
+#define CLKID_CPU_DEBUG (CLKID_BASE + 247)
+#define CLKID_DSPA (CLKID_BASE + 248)
+#define CLKID_VPU_INTR (CLKID_BASE + 249)
+#define CLKID_SAR_ADC (CLKID_BASE + 250)
+#define CLKID_GIC (CLKID_BASE + 251)
+#define CLKID_PWM_AB (CLKID_BASE + 252)
+#define CLKID_PWM_CD (CLKID_BASE + 253)
+#define CLKID_PWM_EF (CLKID_BASE + 254)
+#define CLKID_PWM_GH (CLKID_BASE + 255)
+#define CLKID_PWM_IJ (CLKID_BASE + 256)
+#define CLKID_DEMOD (CLKID_BASE + 257)
+
+#define CLKID_HDCP22_ESMCLK_SEL (CLKID_BASE + 258)
+#define CLKID_HDCP22_ESMCLK_DIV (CLKID_BASE + 259)
+#define CLKID_HDCP22_ESMCLK_GATE (CLKID_BASE + 260)
+#define CLKID_HDCP22_SKPCLK_SEL (CLKID_BASE + 261)
+#define CLKID_HDCP22_SKPCLK_DIV (CLKID_BASE + 262)
+#define CLKID_HDCP22_SKPCLK_GATE (CLKID_BASE + 263)
+
+#define CLKID_DEMOD_CORE_CLK_SEL (CLKID_BASE + 264)
+#define CLKID_DEMOD_CORE_CLK_DIV (CLKID_BASE + 265)
+#define CLKID_DEMOD_CORE_CLK_GATE (CLKID_BASE + 266)
+#define CLKID_ADC_EXTCLK_IN_SEL (CLKID_BASE + 267)
+#define CLKID_ADC_EXTCLK_IN_DIV (CLKID_BASE + 268)
+#define CLKID_ADC_EXTCLK_IN_GATE (CLKID_BASE + 269)
+#define CLKID_DEMOD_CORE_T2_CLK_SEL (CLKID_BASE + 270)
+#define CLKID_DEMOD_CORE_T2_CLK_DIV (CLKID_BASE + 271)
+#define CLKID_DEMOD_CORE_T2_CLK_GATE (CLKID_BASE + 272)
+#define CLKID_DEMOD_32K_CLKIN (CLKID_BASE + 273)
+#define CLKID_DEMOD_32K_DIV (CLKID_BASE + 274)
+#define CLKID_DEMOD_32K_XTAL (CLKID_BASE + 275)
+#define CLKID_DEMOD_32K_CLK (CLKID_BASE + 276)
+
+#define NR_CLKS (CLKID_BASE + 277)
+
+#endif /* __S4_CLKC_H */
--
2.33.1
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^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] arm64: dts: meson: add S4 Soc clock controller in DT
2022-07-08 6:27 [PATCH 0/3] Add S4 SoC clock controller driver Yu Tu
2022-07-08 6:27 ` [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
@ 2022-07-08 6:27 ` Yu Tu
2022-07-12 9:41 ` Krzysztof Kozlowski
[not found] ` <20220708062757.3662-4-yu.tu@amlogic.com>
2 siblings, 1 reply; 15+ messages in thread
From: Yu Tu @ 2022-07-08 6:27 UTC (permalink / raw)
To: linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Cc: Yu Tu
Added information about the S4 SOC Clock controller in DT.
Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ff213618a598..ad2ec26a1f4a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -86,7 +86,7 @@ gic: interrupt-controller@fff01000 {
};
apb4: apb4@fe000000 {
- compatible = "simple-bus";
+ compatible = "simple-bus", "syscon";
reg = <0x0 0xfe000000 0x0 0x480000>;
#address-cells = <2>;
#size-cells = <2>;
@@ -118,6 +118,13 @@ gpio_intc: interrupt-controller@4080 {
<10 11 12 13 14 15 16 17 18 19 20 21>;
};
+ clkc: clock-controller {
+ compatible = "amlogic,s4-clkc";
+ #clock-cells = <1>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
uart_B: serial@7a000 {
compatible = "amlogic,meson-s4-uart",
"amlogic,meson-ao-uart";
--
2.33.1
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* Re: [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings
2022-07-08 6:27 ` [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
@ 2022-07-11 12:25 ` Jerome Brunet
2022-07-19 5:30 ` Yu Tu
2022-07-12 9:40 ` Krzysztof Kozlowski
1 sibling, 1 reply; 15+ messages in thread
From: Jerome Brunet @ 2022-07-11 12:25 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Kevin Hilman,
Michael Turquette, Stephen Boyd, Krzysztof Kozlowski,
Martin Blumenstingl
On Fri 08 Jul 2022 at 14:27, Yu Tu <yu.tu@amlogic.com> wrote:
> Add new clock controller compatible and dt-bindings header for the
> Everything-Else domain of the S4 SoC.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
> MAINTAINERS | 1 +
> include/dt-bindings/clock/s4-clkc.h | 354 ++++++++++++++++++
> 3 files changed, 356 insertions(+)
> create mode 100644 include/dt-bindings/clock/s4-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
> index 7ccecd5c02c1..301b43dea912 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
> @@ -12,6 +12,7 @@ Required Properties:
> "amlogic,g12a-clkc" for G12A SoC.
> "amlogic,g12b-clkc" for G12B SoC.
> "amlogic,sm1-clkc" for SM1 SoC.
> + "amlogic,s4-clkc" for S4 SoC.
> - clocks : list of clock phandle, one for each entry clock-names.
> - clock-names : should contain the following:
> * "xtal": the platform xtal
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c1abc53f9e91..e4ca46c5c8a1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
> F: drivers/clk/meson/
> F: include/dt-bindings/clock/gxbb*
> F: include/dt-bindings/clock/meson*
> +F: include/dt-bindings/clock/s*
Anything starting with an s ? are you sur about that ?
>
> ARM/Amlogic Meson SoC Crypto Drivers
> M: Corentin Labbe <clabbe@baylibre.com>
> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
> new file mode 100644
> index 000000000000..8b46d54d79fe
> --- /dev/null
> +++ b/include/dt-bindings/clock/s4-clkc.h
> @@ -0,0 +1,354 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef __S4_CLKC_H
> +#define __S4_CLKC_H
> +
> +/*
> + * CLKID index values
> + */
> +
> +#define CLKID_PLL_BASE 0
> +#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
This calculation is really not necessary.
Also you've exposed all the clock elements to DT which is clearly not
necessary.
Some elements just show how clocks are decomposed/implemented in CCF and
have no value in DT.
> +#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
> +#define CLKID_FCLK_DIV2_DIV (CLKID_PLL_BASE + 2)
> +#define CLKID_FCLK_DIV2 (CLKID_PLL_BASE + 3)
> +#define CLKID_FCLK_DIV3_DIV (CLKID_PLL_BASE + 4)
> +#define CLKID_FCLK_DIV3 (CLKID_PLL_BASE + 5)
> +#define CLKID_FCLK_DIV4_DIV (CLKID_PLL_BASE + 6)
> +#define CLKID_FCLK_DIV4 (CLKID_PLL_BASE + 7)
> +#define CLKID_FCLK_DIV5_DIV (CLKID_PLL_BASE + 8)
> +#define CLKID_FCLK_DIV5 (CLKID_PLL_BASE + 9)
> +#define CLKID_FCLK_DIV7_DIV (CLKID_PLL_BASE + 10)
> +#define CLKID_FCLK_DIV7 (CLKID_PLL_BASE + 11)
> +#define CLKID_FCLK_DIV2P5_DIV (CLKID_PLL_BASE + 12)
> +#define CLKID_FCLK_DIV2P5 (CLKID_PLL_BASE + 13)
> +#define CLKID_GP0_PLL_DCO (CLKID_PLL_BASE + 14)
> +#define CLKID_GP0_PLL (CLKID_PLL_BASE + 15)
> +#define CLKID_HIFI_PLL_DCO (CLKID_PLL_BASE + 16)
> +#define CLKID_HIFI_PLL (CLKID_PLL_BASE + 17)
> +#define CLKID_HDMI_PLL_DCO (CLKID_PLL_BASE + 18)
> +#define CLKID_HDMI_PLL_OD (CLKID_PLL_BASE + 19)
> +#define CLKID_HDMI_PLL (CLKID_PLL_BASE + 20)
> +#define CLKID_MPLL_50M_DIV (CLKID_PLL_BASE + 21)
> +#define CLKID_MPLL_50M (CLKID_PLL_BASE + 22)
> +#define CLKID_MPLL_PREDIV (CLKID_PLL_BASE + 23)
> +#define CLKID_MPLL0_DIV (CLKID_PLL_BASE + 24)
> +#define CLKID_MPLL0 (CLKID_PLL_BASE + 25)
> +#define CLKID_MPLL1_DIV (CLKID_PLL_BASE + 26)
> +#define CLKID_MPLL1 (CLKID_PLL_BASE + 27)
> +#define CLKID_MPLL2_DIV (CLKID_PLL_BASE + 28)
> +#define CLKID_MPLL2 (CLKID_PLL_BASE + 29)
> +#define CLKID_MPLL3_DIV (CLKID_PLL_BASE + 30)
> +#define CLKID_MPLL3 (CLKID_PLL_BASE + 31)
> +
> +#define CLKID_BASE (CLKID_PLL_BASE + 32)
> +#define CLKID_RTC_32K_CLKIN (CLKID_BASE + 0)
> +#define CLKID_RTC_32K_DIV (CLKID_BASE + 1)
> +#define CLKID_RTC_32K_SEL (CLKID_BASE + 2)
> +#define CLKID_RTC_32K_XATL (CLKID_BASE + 3)
> +#define CLKID_RTC_CLK (CLKID_BASE + 4)
> +#define CLKID_SYS_CLK_B_SEL (CLKID_BASE + 5)
> +#define CLKID_SYS_CLK_B_DIV (CLKID_BASE + 6)
> +#define CLKID_SYS_CLK_B_GATE (CLKID_BASE + 7)
> +#define CLKID_SYS_CLK_A_SEL (CLKID_BASE + 8)
> +#define CLKID_SYS_CLK_A_DIV (CLKID_BASE + 9)
> +#define CLKID_SYS_CLK_A_GATE (CLKID_BASE + 10)
> +#define CLKID_SYS_CLK (CLKID_BASE + 11)
> +
> +#define CLKID_CECA_32K_CLKIN (CLKID_BASE + 12)
> +#define CLKID_CECA_32K_DIV (CLKID_BASE + 13)
> +#define CLKID_CECA_32K_SEL_PRE (CLKID_BASE + 14)
> +#define CLKID_CECA_32K_SEL (CLKID_BASE + 15)
> +#define CLKID_CECA_32K_CLKOUT (CLKID_BASE + 16)
> +#define CLKID_CECB_32K_CLKIN (CLKID_BASE + 17)
> +#define CLKID_CECB_32K_DIV (CLKID_BASE + 18)
> +#define CLKID_CECB_32K_SEL_PRE (CLKID_BASE + 19)
> +#define CLKID_CECB_32K_SEL (CLKID_BASE + 20)
> +#define CLKID_CECB_32K_CLKOUT (CLKID_BASE + 21)
> +
> +#define CLKID_SC_CLK_SEL (CLKID_BASE + 22)
> +#define CLKID_SC_CLK_DIV (CLKID_BASE + 23)
> +#define CLKID_SC_CLK_GATE (CLKID_BASE + 24)
> +
> +#define CLKID_DSPA_CLK_B_SEL (CLKID_BASE + 25)
> +#define CLKID_DSPA_CLK_B_DIV (CLKID_BASE + 26)
> +#define CLKID_DSPA_CLK_B_GATE (CLKID_BASE + 27)
> +#define CLKID_DSPA_CLK_A_SEL (CLKID_BASE + 28)
> +#define CLKID_DSPA_CLK_A_DIV (CLKID_BASE + 29)
> +#define CLKID_DSPA_CLK_A_GATE (CLKID_BASE + 30)
> +#define CLKID_DSPA_CLK (CLKID_BASE + 31)
> +
> +#define CLKID_12_24M_CLK_GATE (CLKID_BASE + 32)
> +#define CLKID_12M_CLK_DIV (CLKID_BASE + 33)
> +#define CLKID_12_24M_CLK_SEL (CLKID_BASE + 34)
> +#define CLKID_25M_CLK_DIV (CLKID_BASE + 35)
> +#define CLKID_25M_CLK_GATE (CLKID_BASE + 36)
> +
> +#define CLKID_VID_PLL_DIV (CLKID_BASE + 37)
> +#define CLKID_VID_PLL_SEL (CLKID_BASE + 38)
> +#define CLKID_VID_PLL (CLKID_BASE + 39)
> +#define CLKID_VCLK_SEL (CLKID_BASE + 40)
> +#define CLKID_VCLK2_SEL (CLKID_BASE + 41)
> +#define CLKID_VCLK_INPUT (CLKID_BASE + 42)
> +#define CLKID_VCLK2_INPUT (CLKID_BASE + 43)
> +#define CLKID_VCLK_DIV (CLKID_BASE + 44)
> +#define CLKID_VCLK2_DIV (CLKID_BASE + 45)
> +#define CLKID_VCLK (CLKID_BASE + 46)
> +#define CLKID_VCLK2 (CLKID_BASE + 47)
> +#define CLKID_VCLK_DIV1 (CLKID_BASE + 48)
> +#define CLKID_VCLK_DIV2_EN (CLKID_BASE + 49)
> +#define CLKID_VCLK_DIV4_EN (CLKID_BASE + 50)
> +#define CLKID_VCLK_DIV6_EN (CLKID_BASE + 51)
> +#define CLKID_VCLK_DIV12_EN (CLKID_BASE + 52)
> +#define CLKID_VCLK2_DIV1 (CLKID_BASE + 53)
> +#define CLKID_VCLK2_DIV2_EN (CLKID_BASE + 54)
> +#define CLKID_VCLK2_DIV4_EN (CLKID_BASE + 55)
> +#define CLKID_VCLK2_DIV6_EN (CLKID_BASE + 56)
> +#define CLKID_VCLK2_DIV12_EN (CLKID_BASE + 57)
> +#define CLKID_VCLK_DIV2 (CLKID_BASE + 58)
> +#define CLKID_VCLK_DIV4 (CLKID_BASE + 59)
> +#define CLKID_VCLK_DIV6 (CLKID_BASE + 60)
> +#define CLKID_VCLK_DIV12 (CLKID_BASE + 61)
> +#define CLKID_VCLK2_DIV2 (CLKID_BASE + 62)
> +#define CLKID_VCLK2_DIV4 (CLKID_BASE + 63)
> +#define CLKID_VCLK2_DIV6 (CLKID_BASE + 64)
> +#define CLKID_VCLK2_DIV12 (CLKID_BASE + 65)
> +#define CLKID_CTS_ENCI_SEL (CLKID_BASE + 66)
> +#define CLKID_CTS_ENCP_SEL (CLKID_BASE + 67)
> +#define CLKID_CTS_VDAC_SEL (CLKID_BASE + 68)
> +#define CLKID_HDMI_TX_SEL (CLKID_BASE + 69)
> +#define CLKID_CTS_ENCI (CLKID_BASE + 70)
> +#define CLKID_CTS_ENCP (CLKID_BASE + 71)
> +#define CLKID_CTS_VDAC (CLKID_BASE + 72)
> +#define CLKID_HDMI_TX (CLKID_BASE + 73)
> +
> +#define CLKID_HDMI_SEL (CLKID_BASE + 74)
> +#define CLKID_HDMI_DIV (CLKID_BASE + 75)
> +#define CLKID_HDMI (CLKID_BASE + 76)
> +#define CLKID_TS_CLK_DIV (CLKID_BASE + 77)
> +#define CLKID_TS_CLK_GATE (CLKID_BASE + 78)
> +
> +#define CLKID_MALI_0_SEL (CLKID_BASE + 79)
> +#define CLKID_MALI_0_DIV (CLKID_BASE + 80)
> +#define CLKID_MALI_0 (CLKID_BASE + 81)
> +#define CLKID_MALI_1_SEL (CLKID_BASE + 82)
> +#define CLKID_MALI_1_DIV (CLKID_BASE + 83)
> +#define CLKID_MALI_1 (CLKID_BASE + 84)
> +#define CLKID_MALI (CLKID_BASE + 85)
> +
> +#define CLKID_VDEC_P0_SEL (CLKID_BASE + 86)
> +#define CLKID_VDEC_P0_DIV (CLKID_BASE + 87)
> +#define CLKID_VDEC_P0 (CLKID_BASE + 88)
> +#define CLKID_VDEC_P1_SEL (CLKID_BASE + 89)
> +#define CLKID_VDEC_P1_DIV (CLKID_BASE + 90)
> +#define CLKID_VDEC_P1 (CLKID_BASE + 91)
> +#define CLKID_VDEC_SEL (CLKID_BASE + 92)
> +
> +#define CLKID_HCODEC_P0_SEL (CLKID_BASE + 93)
> +#define CLKID_HCODEC_P0_DIV (CLKID_BASE + 94)
> +#define CLKID_HCODEC_P0 (CLKID_BASE + 95)
> +#define CLKID_HCODEC_P1_SEL (CLKID_BASE + 96)
> +#define CLKID_HCODEC_P1_DIV (CLKID_BASE + 97)
> +#define CLKID_HCODEC_P1 (CLKID_BASE + 98)
> +#define CLKID_HCODEC_SEL (CLKID_BASE + 99)
> +
> +#define CLKID_HEVCB_P0_SEL (CLKID_BASE + 100)
> +#define CLKID_HEVCB_P0_DIV (CLKID_BASE + 101)
> +#define CLKID_HEVCB_P0 (CLKID_BASE + 102)
> +#define CLKID_HEVCB_P1_SEL (CLKID_BASE + 103)
> +#define CLKID_HEVCB_P1_DIV (CLKID_BASE + 104)
> +#define CLKID_HEVCB_P1 (CLKID_BASE + 105)
> +#define CLKID_HEVCB_SEL (CLKID_BASE + 106)
> +
> +#define CLKID_HEVCF_P0_SEL (CLKID_BASE + 107)
> +#define CLKID_HEVCF_P0_DIV (CLKID_BASE + 108)
> +#define CLKID_HEVCF_P0 (CLKID_BASE + 109)
> +#define CLKID_HEVCF_P1_SEL (CLKID_BASE + 110)
> +#define CLKID_HEVCF_P1_DIV (CLKID_BASE + 111)
> +#define CLKID_HEVCF_P1 (CLKID_BASE + 112)
> +#define CLKID_HEVCF_SEL (CLKID_BASE + 113)
> +
> +#define CLKID_WAVE_A_SEL (CLKID_BASE + 114)
> +#define CLKID_WAVE_A_DIV (CLKID_BASE + 115)
> +#define CLKID_WAVE_A_GATE (CLKID_BASE + 116)
> +#define CLKID_WAVE_B_SEL (CLKID_BASE + 117)
> +#define CLKID_WAVE_B_DIV (CLKID_BASE + 118)
> +#define CLKID_WAVE_B_GATE (CLKID_BASE + 119)
> +#define CLKID_WAVE_C_SEL (CLKID_BASE + 120)
> +#define CLKID_WAVE_C_DIV (CLKID_BASE + 121)
> +#define CLKID_WAVE_C_GATE (CLKID_BASE + 122)
> +
> +#define CLKID_VPU_0_SEL (CLKID_BASE + 123)
> +#define CLKID_VPU_0_DIV (CLKID_BASE + 124)
> +#define CLKID_VPU_0 (CLKID_BASE + 125)
> +#define CLKID_VPU_1_SEL (CLKID_BASE + 126)
> +#define CLKID_VPU_1_DIV (CLKID_BASE + 127)
> +#define CLKID_VPU_1 (CLKID_BASE + 128)
> +#define CLKID_VPU (CLKID_BASE + 129)
> +
> +#define CLKID_VPU_CLKB_TMP_SEL (CLKID_BASE + 130)
> +#define CLKID_VPU_CLKB_TMP_DIV (CLKID_BASE + 131)
> +#define CLKID_VPU_CLKB_TMP (CLKID_BASE + 132)
> +#define CLKID_VPU_CLKB_DIV (CLKID_BASE + 133)
> +#define CLKID_VPU_CLKB (CLKID_BASE + 134)
> +
> +#define CLKID_VPU_CLKC_P0_SEL (CLKID_BASE + 135)
> +#define CLKID_VPU_CLKC_P0_DIV (CLKID_BASE + 136)
> +#define CLKID_VPU_CLKC_P0 (CLKID_BASE + 137)
> +#define CLKID_VPU_CLKC_P1_SEL (CLKID_BASE + 138)
> +#define CLKID_VPU_CLKC_P1_DIV (CLKID_BASE + 139)
> +#define CLKID_VPU_CLKC_P1 (CLKID_BASE + 140)
> +#define CLKID_VPU_CLKC_SEL (CLKID_BASE + 141)
> +
> +#define CLKID_VAPB_0_SEL (CLKID_BASE + 142)
> +#define CLKID_VAPB_0_DIV (CLKID_BASE + 143)
> +#define CLKID_VAPB_0 (CLKID_BASE + 144)
> +#define CLKID_VAPB_1_SEL (CLKID_BASE + 145)
> +#define CLKID_VAPB_1_DIV (CLKID_BASE + 146)
> +#define CLKID_VAPB_1 (CLKID_BASE + 147)
> +#define CLKID_VAPB (CLKID_BASE + 148)
> +
> +#define CLKID_GE2D (CLKID_BASE + 149)
> +
> +#define CLKID_VDIN_MEAS_SEL (CLKID_BASE + 150)
> +#define CLKID_VDIN_MEAS_DIV (CLKID_BASE + 151)
> +#define CLKID_VDIN_MEAS_GATE (CLKID_BASE + 152)
> +
> +#define CLKID_SD_EMMC_C_CLK_SEL (CLKID_BASE + 153)
> +#define CLKID_SD_EMMC_C_CLK_DIV (CLKID_BASE + 154)
> +#define CLKID_SD_EMMC_C_CLK (CLKID_BASE + 155)
> +#define CLKID_SD_EMMC_A_CLK_SEL (CLKID_BASE + 156)
> +#define CLKID_SD_EMMC_A_CLK_DIV (CLKID_BASE + 157)
> +#define CLKID_SD_EMMC_A_CLK (CLKID_BASE + 158)
> +#define CLKID_SD_EMMC_B_CLK_SEL (CLKID_BASE + 159)
> +#define CLKID_SD_EMMC_B_CLK_DIV (CLKID_BASE + 160)
> +#define CLKID_SD_EMMC_B_CLK (CLKID_BASE + 161)
> +
> +#define CLKID_SPICC0_SEL (CLKID_BASE + 162)
> +#define CLKID_SPICC0_DIV (CLKID_BASE + 163)
> +#define CLKID_SPICC0_GATE (CLKID_BASE + 164)
> +#define CLKID_SPICC1_SEL (CLKID_BASE + 165)
> +#define CLKID_SPICC1_DIV (CLKID_BASE + 166)
> +#define CLKID_SPICC1_GATE (CLKID_BASE + 167)
> +
> +#define CLKID_PWM_A_SEL (CLKID_BASE + 168)
> +#define CLKID_PWM_A_DIV (CLKID_BASE + 169)
> +#define CLKID_PWM_A_GATE (CLKID_BASE + 170)
> +#define CLKID_PWM_B_SEL (CLKID_BASE + 171)
> +#define CLKID_PWM_B_DIV (CLKID_BASE + 172)
> +#define CLKID_PWM_B_GATE (CLKID_BASE + 173)
> +#define CLKID_PWM_C_SEL (CLKID_BASE + 174)
> +#define CLKID_PWM_C_DIV (CLKID_BASE + 175)
> +#define CLKID_PWM_C_GATE (CLKID_BASE + 176)
> +#define CLKID_PWM_D_SEL (CLKID_BASE + 177)
> +#define CLKID_PWM_D_DIV (CLKID_BASE + 178)
> +#define CLKID_PWM_D_GATE (CLKID_BASE + 179)
> +#define CLKID_PWM_E_SEL (CLKID_BASE + 180)
> +#define CLKID_PWM_E_DIV (CLKID_BASE + 181)
> +#define CLKID_PWM_E_GATE (CLKID_BASE + 182)
> +#define CLKID_PWM_F_SEL (CLKID_BASE + 183)
> +#define CLKID_PWM_F_DIV (CLKID_BASE + 184)
> +#define CLKID_PWM_F_GATE (CLKID_BASE + 185)
> +#define CLKID_PWM_G_SEL (CLKID_BASE + 186)
> +#define CLKID_PWM_G_DIV (CLKID_BASE + 187)
> +#define CLKID_PWM_G_GATE (CLKID_BASE + 188)
> +#define CLKID_PWM_H_SEL (CLKID_BASE + 189)
> +#define CLKID_PWM_H_DIV (CLKID_BASE + 190)
> +#define CLKID_PWM_H_GATE (CLKID_BASE + 191)
> +#define CLKID_PWM_I_SEL (CLKID_BASE + 192)
> +#define CLKID_PWM_I_DIV (CLKID_BASE + 193)
> +#define CLKID_PWM_I_GATE (CLKID_BASE + 194)
> +#define CLKID_PWM_J_SEL (CLKID_BASE + 195)
> +#define CLKID_PWM_J_DIV (CLKID_BASE + 196)
> +#define CLKID_PWM_J_GATE (CLKID_BASE + 197)
> +
> +#define CLKID_SARADC_SEL (CLKID_BASE + 198)
> +#define CLKID_SARADC_DIV (CLKID_BASE + 199)
> +#define CLKID_SARADC_GATE (CLKID_BASE + 200)
> +#define CLKID_GEN_SEL (CLKID_BASE + 201)
> +#define CLKID_GEN_DIV (CLKID_BASE + 202)
> +#define CLKID_GEN_GATE (CLKID_BASE + 203)
> +
> +#define CLKID_DDR (CLKID_BASE + 204)
> +#define CLKID_DOS (CLKID_BASE + 205)
> +#define CLKID_ETHPHY (CLKID_BASE + 206)
> +#define CLKID_MALI_GATE (CLKID_BASE + 207)
> +#define CLKID_AOCPU (CLKID_BASE + 208)
> +#define CLKID_AUCPU (CLKID_BASE + 209)
> +#define CLKID_CEC (CLKID_BASE + 210)
> +#define CLKID_SD_EMMC_A (CLKID_BASE + 211)
> +#define CLKID_SD_EMMC_B (CLKID_BASE + 212)
> +#define CLKID_NAND (CLKID_BASE + 213)
> +#define CLKID_SMARTCARD (CLKID_BASE + 214)
> +#define CLKID_ACODEC (CLKID_BASE + 215)
> +#define CLKID_SPIFC (CLKID_BASE + 216)
> +#define CLKID_MSR_CLK (CLKID_BASE + 217)
> +#define CLKID_IR_CTRL (CLKID_BASE + 218)
> +#define CLKID_AUDIO (CLKID_BASE + 219)
> +#define CLKID_ETH (CLKID_BASE + 220)
> +#define CLKID_UART_A (CLKID_BASE + 221)
> +#define CLKID_UART_B (CLKID_BASE + 222)
> +#define CLKID_UART_C (CLKID_BASE + 223)
> +#define CLKID_UART_D (CLKID_BASE + 224)
> +#define CLKID_UART_E (CLKID_BASE + 225)
> +#define CLKID_AIFIFO (CLKID_BASE + 226)
> +#define CLKID_TS_DDR (CLKID_BASE + 227)
> +#define CLKID_TS_PLL (CLKID_BASE + 228)
> +#define CLKID_G2D (CLKID_BASE + 229)
> +#define CLKID_SPICC0 (CLKID_BASE + 230)
> +#define CLKID_SPICC1 (CLKID_BASE + 231)
> +#define CLKID_PCIE (CLKID_BASE + 232)
> +#define CLKID_USB (CLKID_BASE + 233)
> +#define CLKID_PCIE_PHY (CLKID_BASE + 234)
> +#define CLKID_I2C_M_A (CLKID_BASE + 235)
> +#define CLKID_I2C_M_B (CLKID_BASE + 236)
> +#define CLKID_I2C_M_C (CLKID_BASE + 237)
> +#define CLKID_I2C_M_D (CLKID_BASE + 238)
> +#define CLKID_I2C_M_E (CLKID_BASE + 239)
> +#define CLKID_I2C_M_F (CLKID_BASE + 240)
> +#define CLKID_HDMITX_APB (CLKID_BASE + 241)
> +#define CLKID_I2C_S_A (CLKID_BASE + 242)
> +#define CLKID_USB1_TO_DDR (CLKID_BASE + 243)
> +#define CLKID_HDCP22 (CLKID_BASE + 244)
> +#define CLKID_MMC_APB (CLKID_BASE + 245)
> +#define CLKID_RSA (CLKID_BASE + 246)
> +#define CLKID_CPU_DEBUG (CLKID_BASE + 247)
> +#define CLKID_DSPA (CLKID_BASE + 248)
> +#define CLKID_VPU_INTR (CLKID_BASE + 249)
> +#define CLKID_SAR_ADC (CLKID_BASE + 250)
> +#define CLKID_GIC (CLKID_BASE + 251)
> +#define CLKID_PWM_AB (CLKID_BASE + 252)
> +#define CLKID_PWM_CD (CLKID_BASE + 253)
> +#define CLKID_PWM_EF (CLKID_BASE + 254)
> +#define CLKID_PWM_GH (CLKID_BASE + 255)
> +#define CLKID_PWM_IJ (CLKID_BASE + 256)
> +#define CLKID_DEMOD (CLKID_BASE + 257)
> +
> +#define CLKID_HDCP22_ESMCLK_SEL (CLKID_BASE + 258)
> +#define CLKID_HDCP22_ESMCLK_DIV (CLKID_BASE + 259)
> +#define CLKID_HDCP22_ESMCLK_GATE (CLKID_BASE + 260)
> +#define CLKID_HDCP22_SKPCLK_SEL (CLKID_BASE + 261)
> +#define CLKID_HDCP22_SKPCLK_DIV (CLKID_BASE + 262)
> +#define CLKID_HDCP22_SKPCLK_GATE (CLKID_BASE + 263)
> +
> +#define CLKID_DEMOD_CORE_CLK_SEL (CLKID_BASE + 264)
> +#define CLKID_DEMOD_CORE_CLK_DIV (CLKID_BASE + 265)
> +#define CLKID_DEMOD_CORE_CLK_GATE (CLKID_BASE + 266)
> +#define CLKID_ADC_EXTCLK_IN_SEL (CLKID_BASE + 267)
> +#define CLKID_ADC_EXTCLK_IN_DIV (CLKID_BASE + 268)
> +#define CLKID_ADC_EXTCLK_IN_GATE (CLKID_BASE + 269)
> +#define CLKID_DEMOD_CORE_T2_CLK_SEL (CLKID_BASE + 270)
> +#define CLKID_DEMOD_CORE_T2_CLK_DIV (CLKID_BASE + 271)
> +#define CLKID_DEMOD_CORE_T2_CLK_GATE (CLKID_BASE + 272)
> +#define CLKID_DEMOD_32K_CLKIN (CLKID_BASE + 273)
> +#define CLKID_DEMOD_32K_DIV (CLKID_BASE + 274)
> +#define CLKID_DEMOD_32K_XTAL (CLKID_BASE + 275)
> +#define CLKID_DEMOD_32K_CLK (CLKID_BASE + 276)
> +
> +#define NR_CLKS (CLKID_BASE + 277)
> +
> +#endif /* __S4_CLKC_H */
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings
2022-07-08 6:27 ` [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
2022-07-11 12:25 ` Jerome Brunet
@ 2022-07-12 9:40 ` Krzysztof Kozlowski
2022-07-19 5:55 ` Yu Tu
1 sibling, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-12 9:40 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
On 08/07/2022 08:27, Yu Tu wrote:
> Add new clock controller compatible and dt-bindings header for the
> Everything-Else domain of the S4 SoC.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
> MAINTAINERS | 1 +
> include/dt-bindings/clock/s4-clkc.h | 354 ++++++++++++++++++
> 3 files changed, 356 insertions(+)
> create mode 100644 include/dt-bindings/clock/s4-clkc.h
>
> diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
> index 7ccecd5c02c1..301b43dea912 100644
> --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
> +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
> @@ -12,6 +12,7 @@ Required Properties:
> "amlogic,g12a-clkc" for G12A SoC.
> "amlogic,g12b-clkc" for G12B SoC.
> "amlogic,sm1-clkc" for SM1 SoC.
> + "amlogic,s4-clkc" for S4 SoC.
> - clocks : list of clock phandle, one for each entry clock-names.
> - clock-names : should contain the following:
> * "xtal": the platform xtal
> diff --git a/MAINTAINERS b/MAINTAINERS
> index c1abc53f9e91..e4ca46c5c8a1 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
> F: drivers/clk/meson/
> F: include/dt-bindings/clock/gxbb*
> F: include/dt-bindings/clock/meson*
> +F: include/dt-bindings/clock/s*
>
> ARM/Amlogic Meson SoC Crypto Drivers
> M: Corentin Labbe <clabbe@baylibre.com>
> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
> new file mode 100644
> index 000000000000..8b46d54d79fe
> --- /dev/null
> +++ b/include/dt-bindings/clock/s4-clkc.h
> @@ -0,0 +1,354 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef __S4_CLKC_H
> +#define __S4_CLKC_H
Use header guards mathcing paths. See other files for examples.
> +
> +/*
> + * CLKID index values
> + */
> +
> +#define CLKID_PLL_BASE 0
> +#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
Drop CLKID_PLL_BASE
> +#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
ditto... and so on.
Best regards,
Krzysztof
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] arm64: dts: meson: add S4 Soc clock controller in DT
2022-07-08 6:27 ` [PATCH 2/3] arm64: dts: meson: add S4 Soc clock controller in DT Yu Tu
@ 2022-07-12 9:41 ` Krzysztof Kozlowski
2022-07-19 5:57 ` Yu Tu
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-12 9:41 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
On 08/07/2022 08:27, Yu Tu wrote:
> Added information about the S4 SOC Clock controller in DT.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> index ff213618a598..ad2ec26a1f4a 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
> @@ -86,7 +86,7 @@ gic: interrupt-controller@fff01000 {
> };
>
> apb4: apb4@fe000000 {
> - compatible = "simple-bus";
> + compatible = "simple-bus", "syscon";
This is not allowed.
1. syscon needs also dedicated compatible
2. simple-bus with syscon means it is not a simple bus anymore, so nope.
> reg = <0x0 0xfe000000 0x0 0x480000>;
> #address-cells = <2>;
> #size-cells = <2>;
> @@ -118,6 +118,13 @@ gpio_intc: interrupt-controller@4080 {
> <10 11 12 13 14 15 16 17 18 19 20 21>;
> };
>
> + clkc: clock-controller {
> + compatible = "amlogic,s4-clkc";
> + #clock-cells = <1>;
> + clocks = <&xtal>;
> + clock-names = "xtal";
> + };
> +
> uart_B: serial@7a000 {
> compatible = "amlogic,meson-s4-uart",
> "amlogic,meson-ao-uart";
Best regards,
Krzysztof
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver
[not found] ` <20220708062757.3662-4-yu.tu@amlogic.com>
@ 2022-07-12 9:44 ` Krzysztof Kozlowski
2022-07-19 6:02 ` Yu Tu
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-12 9:44 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
On 08/07/2022 08:27, Yu Tu wrote:
> Add the peripheral clock controller found in the s4 SoC family.
>
> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
> ---
> MAINTAINERS | 2 +-
> drivers/clk/meson/Kconfig | 17 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/s4.c | 4678 ++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/s4.h | 156 ++
> 5 files changed, 4853 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/meson/s4.c
> create mode 100644 drivers/clk/meson/s4.h
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index e4ca46c5c8a1..f116ec0642f2 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1772,7 +1772,7 @@ M: Jerome Brunet <jbrunet@baylibre.com>
> L: linux-amlogic@lists.infradead.org
> S: Maintained
> F: Documentation/devicetree/bindings/clock/amlogic*
> -F: drivers/clk/meson/
> +F: drivers/clk/meson/*
Why?
> F: include/dt-bindings/clock/gxbb*
> F: include/dt-bindings/clock/meson*
> F: include/dt-bindings/clock/s*
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index fc002c155bc3..1a344b0564e8 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -115,4 +115,21 @@ config COMMON_CLK_G12A
> help
> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
> devices, aka g12a. Say Y if you want peripherals to work.
> +
> +config COMMON_CLK_S4
> + tristate "S4 SoC clock controllers support"
> + depends on ARM64
> + default y
> + select COMMON_CLK_MESON_REGMAP
> + select HAVE_ARM_SMCCC
> + select COMMON_CLK_MESON_DUALDIV
> + select COMMON_CLK_MESON_MPLL
> + select COMMON_CLK_MESON_PLL
> + select COMMON_CLK_MESON_CPU_DYNDIV
> + select COMMON_CLK_MESON_VID_PLL_DIV
> + select MFD_SYSCON
> + help
> + Support for the clock controller on Amlogic S805X2 and S905Y4 devices,
> + aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
> + Say Y if you want peripherals and CPU frequency scaling to work.
> endmenu
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 6eca2a406ee3..b3ef5f67820f 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
> +obj-$(CONFIG_COMMON_CLK_S4) += s4.o
> diff --git a/drivers/clk/meson/s4.c b/drivers/clk/meson/s4.c
> new file mode 100644
> index 000000000000..a97159222f0e
> --- /dev/null
> +++ b/drivers/clk/meson/s4.c
> @@ -0,0 +1,4678 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-S4 Clock Controller Driver
> + *
> + * Copyright (c) 2021 Amlogic, inc.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#include <linux/clk-provider.h>
> +#include <linux/init.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/clk.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <dt-bindings/clock/s4-clkc.h>
> +
> +#include "clk-mpll.h"
> +#include "clk-pll.h"
> +#include "clk-regmap.h"
> +#include "vid-pll-div.h"
> +#include "clk-dualdiv.h"
> +#include "s4.h"
> +#include "meson-eeclk.h"
> +
> +static DEFINE_SPINLOCK(meson_clk_lock);
> +
> +static struct clk_regmap s4_fixed_pll_dco = {
None of these are const?
> + .data = &(struct meson_clk_pll_data){
> + .en = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 28,
> + .width = 1,
> + },
> + .m = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 0,
> + .width = 8,
> + },
> + .n = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 10,
> + .width = 5,
> + },
> + .frac = {
> + .reg_off = ANACTRL_FIXPLL_CTRL1,
> + .shift = 0,
> + .width = 17,
> + },
> + .l = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = ANACTRL_FIXPLL_CTRL0,
> + .shift = 29,
> + .width = 1,
> + },
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll_dco",
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_data = (const struct clk_parent_data []) {
> + { .fw_name = "xtal", }
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fixed_pll = {
> + .data = &(struct clk_regmap_div_data){
> + .offset = ANACTRL_FIXPLL_CTRL0,
> + .shift = 16,
> + .width = 2,
> + .flags = CLK_DIVIDER_POWER_OF_TWO,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll",
> + .ops = &clk_regmap_divider_ro_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll_dco.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock won't ever change at runtime so
> + * CLK_SET_RATE_PARENT is not required
> + */
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div2_div = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div2 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 24,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div2_div.hw
> + },
> + .num_parents = 1,
> + /*
> + * Similar to fclk_div3, it seems that this clock is used by
> + * the resident firmware and is required by the platform to
> + * operate correctly.
> + * Until the following condition are met, we need this clock to
> + * be marked as critical:
> + * a) Mark the clock used by a firmware resource, if possible
> + * b) CCF has a clock hand-off mechanism to make the sure the
> + * clock stays on until the proper driver comes along
> + */
> + .flags = CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div3_div = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div3 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 20,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div3_div.hw
> + },
> + .num_parents = 1,
> + /*
> + * This clock is used by the resident firmware and is required
> + * by the platform to operate correctly.
> + * Until the following condition are met, we need this clock to
> + * be marked as critical:
> + * a) Mark the clock used by a firmware resource, if possible
> + * b) CCF has a clock hand-off mechanism to make the sure the
> + * clock stays on until the proper driver comes along
> + */
> + .flags = CLK_IS_CRITICAL,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div4_div = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div4 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 21,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div4_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div5_div = {
> + .mult = 1,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 22,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div5_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div7_div = {
> + .mult = 1,
> + .div = 7,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div7 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 23,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div7_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor s4_fclk_div2p5_div = {
> + .mult = 2,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2p5_div",
> + .ops = &clk_fixed_factor_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fixed_pll.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap s4_fclk_div2p5 = {
> + .data = &(struct clk_regmap_gate_data){
> + .offset = ANACTRL_FIXPLL_CTRL1,
> + .bit_idx = 25,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2p5",
> + .ops = &clk_regmap_gate_ops,
> + .parent_hws = (const struct clk_hw *[]) {
> + &s4_fclk_div2p5_div.hw
> + },
> + .num_parents = 1,
> + },
> +};
> +
> +static const struct pll_mult_range s4_gp0_pll_mult_range = {
Not const?
> + .min = 125,
> + .max = 250,
> +};
> +
(...)
> +/* Convenience table to populate regmap in .probe */
> +static struct clk_regmap *const s4_clk_regmaps[] = {
> + &s4_rtc_32k_by_oscin_clkin,
> + &s4_rtc_32k_by_oscin_div,
> + &s4_rtc_32k_by_oscin_sel,
> + &s4_rtc_32k_by_oscin,
> + &s4_rtc_clk,
> +
> + &s4_sysclk_b_sel,
> + &s4_sysclk_b_div,
> + &s4_sysclk_b,
> + &s4_sysclk_a_sel,
> + &s4_sysclk_a_div,
> + &s4_sysclk_a,
> + &s4_sys_clk,
> +
> + &s4_ceca_32k_clkin,
> + &s4_ceca_32k_div,
> + &s4_ceca_32k_sel_pre,
> + &s4_ceca_32k_sel,
> + &s4_ceca_32k_clkout,
> + &s4_cecb_32k_clkin,
> + &s4_cecb_32k_div,
> + &s4_cecb_32k_sel_pre,
> + &s4_cecb_32k_sel,
> + &s4_cecb_32k_clkout,
> +
> + &s4_sc_clk_mux,
> + &s4_sc_clk_div,
> + &s4_sc_clk_gate,
> +
> + &s4_12_24M_clk_gate,
> + &s4_12_24M_clk,
> + &s4_vid_pll_div,
> + &s4_vid_pll_sel,
> + &s4_vid_pll,
> + &s4_vclk_sel,
> + &s4_vclk2_sel,
> + &s4_vclk_input,
> + &s4_vclk2_input,
> + &s4_vclk_div,
> + &s4_vclk2_div,
> + &s4_vclk,
> + &s4_vclk2,
> + &s4_vclk_div1,
> + &s4_vclk_div2_en,
> + &s4_vclk_div4_en,
> + &s4_vclk_div6_en,
> + &s4_vclk_div12_en,
> + &s4_vclk2_div1,
> + &s4_vclk2_div2_en,
> + &s4_vclk2_div4_en,
> + &s4_vclk2_div6_en,
> + &s4_vclk2_div12_en,
> + &s4_cts_enci_sel,
> + &s4_cts_encp_sel,
> + &s4_cts_vdac_sel,
> + &s4_hdmi_tx_sel,
> + &s4_cts_enci,
> + &s4_cts_encp,
> + &s4_cts_vdac,
> + &s4_hdmi_tx,
> +
> + &s4_hdmi_sel,
> + &s4_hdmi_div,
> + &s4_hdmi,
> + &s4_ts_clk_div,
> + &s4_ts_clk_gate,
> +
> + &s4_mali_0_sel,
> + &s4_mali_0_div,
> + &s4_mali_0,
> + &s4_mali_1_sel,
> + &s4_mali_1_div,
> + &s4_mali_1,
> + &s4_mali_mux,
> +
> + &s4_vdec_p0_mux,
> + &s4_vdec_p0_div,
> + &s4_vdec_p0,
> + &s4_vdec_p1_mux,
> + &s4_vdec_p1_div,
> + &s4_vdec_p1,
> + &s4_vdec_mux,
> +
> + &s4_hevcf_p0_mux,
> + &s4_hevcf_p0_div,
> + &s4_hevcf_p0,
> + &s4_hevcf_p1_mux,
> + &s4_hevcf_p1_div,
> + &s4_hevcf_p1,
> + &s4_hevcf_mux,
> +
> + &s4_vpu_0_sel,
> + &s4_vpu_0_div,
> + &s4_vpu_0,
> + &s4_vpu_1_sel,
> + &s4_vpu_1_div,
> + &s4_vpu_1,
> + &s4_vpu,
> + &s4_vpu_clkb_tmp_mux,
> + &s4_vpu_clkb_tmp_div,
> + &s4_vpu_clkb_tmp,
> + &s4_vpu_clkb_div,
> + &s4_vpu_clkb,
> + &s4_vpu_clkc_p0_mux,
> + &s4_vpu_clkc_p0_div,
> + &s4_vpu_clkc_p0,
> + &s4_vpu_clkc_p1_mux,
> + &s4_vpu_clkc_p1_div,
> + &s4_vpu_clkc_p1,
> + &s4_vpu_clkc_mux,
> +
> + &s4_vapb_0_sel,
> + &s4_vapb_0_div,
> + &s4_vapb_0,
> + &s4_vapb_1_sel,
> + &s4_vapb_1_div,
> + &s4_vapb_1,
> + &s4_vapb,
> + &s4_ge2d_gate,
> +
> + &s4_hdcp22_esmclk_mux,
> + &s4_hdcp22_esmclk_div,
> + &s4_hdcp22_esmclk_gate,
> + &s4_hdcp22_skpclk_mux,
> + &s4_hdcp22_skpclk_div,
> + &s4_hdcp22_skpclk_gate,
> +
> + &s4_vdin_meas_mux,
> + &s4_vdin_meas_div,
> + &s4_vdin_meas_gate,
> +
> + &s4_sd_emmc_c_clk0_sel,
> + &s4_sd_emmc_c_clk0_div,
> + &s4_sd_emmc_c_clk0,
> + &s4_sd_emmc_a_clk0_sel,
> + &s4_sd_emmc_a_clk0_div,
> + &s4_sd_emmc_a_clk0,
> + &s4_sd_emmc_b_clk0_sel,
> + &s4_sd_emmc_b_clk0_div,
> + &s4_sd_emmc_b_clk0,
> +
> + &s4_spicc0_mux,
> + &s4_spicc0_div,
> + &s4_spicc0_gate,
> +
> + &s4_pwm_a_mux,
> + &s4_pwm_a_div,
> + &s4_pwm_a_gate,
> + &s4_pwm_b_mux,
> + &s4_pwm_b_div,
> + &s4_pwm_b_gate,
> + &s4_pwm_c_mux,
> + &s4_pwm_c_div,
> + &s4_pwm_c_gate,
> + &s4_pwm_d_mux,
> + &s4_pwm_d_div,
> + &s4_pwm_d_gate,
> + &s4_pwm_e_mux,
> + &s4_pwm_e_div,
> + &s4_pwm_e_gate,
> + &s4_pwm_f_mux,
> + &s4_pwm_f_div,
> + &s4_pwm_f_gate,
> + &s4_pwm_g_mux,
> + &s4_pwm_g_div,
> + &s4_pwm_g_gate,
> + &s4_pwm_h_mux,
> + &s4_pwm_h_div,
> + &s4_pwm_h_gate,
> + &s4_pwm_i_mux,
> + &s4_pwm_i_div,
> + &s4_pwm_i_gate,
> + &s4_pwm_j_mux,
> + &s4_pwm_j_div,
> + &s4_pwm_j_gate,
> +
> + &s4_saradc_mux,
> + &s4_saradc_div,
> + &s4_saradc_gate,
> +
> + &s4_gen_clk_sel,
> + &s4_gen_clk_div,
> + &s4_gen_clk,
> +
> + &s4_ddr,
> + &s4_dos,
> + &s4_ethphy,
> + &s4_mali,
> + &s4_aocpu,
> + &s4_aucpu,
> + &s4_cec,
> + &s4_sdemmca,
> + &s4_sdemmcb,
> + &s4_nand,
> + &s4_smartcard,
> + &s4_acodec,
> + &s4_spifc,
> + &s4_msr_clk,
> + &s4_ir_ctrl,
> + &s4_audio,
> + &s4_eth,
> + &s4_uart_a,
> + &s4_uart_b,
> + &s4_uart_c,
> + &s4_uart_d,
> + &s4_uart_e,
> + &s4_aififo,
> + &s4_ts_ddr,
> + &s4_ts_pll,
> + &s4_g2d,
> + &s4_spicc0,
> + &s4_usb,
> + &s4_i2c_m_a,
> + &s4_i2c_m_b,
> + &s4_i2c_m_c,
> + &s4_i2c_m_d,
> + &s4_i2c_m_e,
> + &s4_hdmitx_apb,
> + &s4_i2c_s_a,
> + &s4_usb1_to_ddr,
> + &s4_hdcp22,
> + &s4_mmc_apb,
> + &s4_rsa,
> + &s4_cpu_debug,
> + &s4_vpu_intr,
> + &s4_demod,
> + &s4_sar_adc,
> + &s4_gic,
> + &s4_pwm_ab,
> + &s4_pwm_cd,
> + &s4_pwm_ef,
> + &s4_pwm_gh,
> + &s4_pwm_ij,
> + &s4_demod_core_clk_mux,
> + &s4_demod_core_clk_div,
> + &s4_demod_core_clk_gate,
> + &s4_adc_extclk_in_mux,
> + &s4_adc_extclk_in_div,
> + &s4_adc_extclk_in_gate,
> +
> + &s4_fixed_pll_dco,
> + &s4_fixed_pll,
> + &s4_fclk_div2,
> + &s4_fclk_div3,
> + &s4_fclk_div4,
> + &s4_fclk_div5,
> + &s4_fclk_div7,
> + &s4_fclk_div2p5,
> + &s4_gp0_pll_dco,
> + &s4_gp0_pll,
> +
> + &s4_hifi_pll_dco,
> + &s4_hifi_pll,
> + &s4_hdmi_pll_dco,
> + &s4_hdmi_pll_od,
> + &s4_hdmi_pll,
> + &s4_mpll_50m,
> + &s4_mpll0_div,
> + &s4_mpll0,
> + &s4_mpll1_div,
> + &s4_mpll1,
> + &s4_mpll2_div,
> + &s4_mpll2,
> + &s4_mpll3_div,
> + &s4_mpll3,
> +};
> +
> +static const struct reg_sequence s4_init_regs[] = {
> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
> +};
> +
> +static const struct meson_eeclkc_data s4_clkc_data = {
> + .regmap_clks = s4_clk_regmaps,
> + .regmap_clk_num = ARRAY_SIZE(s4_clk_regmaps),
> + .hw_onecell_data = &s4_hw_onecell_data,
> + .init_regs = s4_init_regs,
> + .init_count = ARRAY_SIZE(s4_init_regs),
> +};
> +
> +static const struct of_device_id clkc_match_table[] = {
> + {
> + .compatible = "amlogic,s4-clkc",
> + .data = &s4_clkc_data
> + },
> + {}
> +};
> +
> +static struct platform_driver s4_driver = {
> + .probe = meson_eeclkc_probe,
> + .driver = {
> + .name = "s4-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +module_platform_driver(s4_driver);
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/clk/meson/s4.h b/drivers/clk/meson/s4.h
> new file mode 100644
> index 000000000000..d5563dcbd52e
> --- /dev/null
> +++ b/drivers/clk/meson/s4.h
> @@ -0,0 +1,156 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2021 Amlogic, inc.
> + * Author: Yu Tu <yu.tu@amlogic.com>
> + */
> +
> +#ifndef __S4_H
> +#define __S4_H
> +
> +/*
> + * Clock controller register offsets
> + * REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
> + */
> +#define CLKCTRL_OSCIN_CTRL ((0x0001 << 2))
No need for double ((
> +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 ((0x0002 << 2))
> +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 ((0x0003 << 2))
Best regards,
Krzysztof
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings
2022-07-11 12:25 ` Jerome Brunet
@ 2022-07-19 5:30 ` Yu Tu
0 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2022-07-19 5:30 UTC (permalink / raw)
To: Jerome Brunet, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Hi Jerome,
Thank you for your advice.
On 2022/7/11 20:25, Jerome Brunet wrote:
> [ EXTERNAL EMAIL ]
>
>
> On Fri 08 Jul 2022 at 14:27, Yu Tu <yu.tu@amlogic.com> wrote:
>
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
>> MAINTAINERS | 1 +
>> include/dt-bindings/clock/s4-clkc.h | 354 ++++++++++++++++++
>> 3 files changed, 356 insertions(+)
>> create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
>> index 7ccecd5c02c1..301b43dea912 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
>> @@ -12,6 +12,7 @@ Required Properties:
>> "amlogic,g12a-clkc" for G12A SoC.
>> "amlogic,g12b-clkc" for G12B SoC.
>> "amlogic,sm1-clkc" for SM1 SoC.
>> + "amlogic,s4-clkc" for S4 SoC.
>> - clocks : list of clock phandle, one for each entry clock-names.
>> - clock-names : should contain the following:
>> * "xtal": the platform xtal
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..e4ca46c5c8a1 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
>> F: drivers/clk/meson/
>> F: include/dt-bindings/clock/gxbb*
>> F: include/dt-bindings/clock/meson*
>> +F: include/dt-bindings/clock/s*
>
> Anything starting with an s ? are you sur about that ?
I'm going to correct this.
The reason for adding this at that time is that the warning is triggered
when checkpatch is used.
>
>>
>> ARM/Amlogic Meson SoC Crypto Drivers
>> M: Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..8b46d54d79fe
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
>> @@ -0,0 +1,354 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef __S4_CLKC_H
>> +#define __S4_CLKC_H
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_PLL_BASE 0
>> +#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
>
> This calculation is really not necessary.
I will correct it.
>
> Also you've exposed all the clock elements to DT which is clearly not
> necessary.
>
> Some elements just show how clocks are decomposed/implemented in CCF and
> have no value in DT.
I will refer to the previous chip how this place.
>
>> +#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
>> +#define CLKID_FCLK_DIV2_DIV (CLKID_PLL_BASE + 2)
>> +#define CLKID_FCLK_DIV2 (CLKID_PLL_BASE + 3)
>> +#define CLKID_FCLK_DIV3_DIV (CLKID_PLL_BASE + 4)
>> +#define CLKID_FCLK_DIV3 (CLKID_PLL_BASE + 5)
>> +#define CLKID_FCLK_DIV4_DIV (CLKID_PLL_BASE + 6)
>> +#define CLKID_FCLK_DIV4 (CLKID_PLL_BASE + 7)
>> +#define CLKID_FCLK_DIV5_DIV (CLKID_PLL_BASE + 8)
>> +#define CLKID_FCLK_DIV5 (CLKID_PLL_BASE + 9)
>> +#define CLKID_FCLK_DIV7_DIV (CLKID_PLL_BASE + 10)
>> +#define CLKID_FCLK_DIV7 (CLKID_PLL_BASE + 11)
>> +#define CLKID_FCLK_DIV2P5_DIV (CLKID_PLL_BASE + 12)
>> +#define CLKID_FCLK_DIV2P5 (CLKID_PLL_BASE + 13)
>> +#define CLKID_GP0_PLL_DCO (CLKID_PLL_BASE + 14)
>> +#define CLKID_GP0_PLL (CLKID_PLL_BASE + 15)
>> +#define CLKID_HIFI_PLL_DCO (CLKID_PLL_BASE + 16)
>> +#define CLKID_HIFI_PLL (CLKID_PLL_BASE + 17)
>> +#define CLKID_HDMI_PLL_DCO (CLKID_PLL_BASE + 18)
>> +#define CLKID_HDMI_PLL_OD (CLKID_PLL_BASE + 19)
>> +#define CLKID_HDMI_PLL (CLKID_PLL_BASE + 20)
>> +#define CLKID_MPLL_50M_DIV (CLKID_PLL_BASE + 21)
>> +#define CLKID_MPLL_50M (CLKID_PLL_BASE + 22)
>> +#define CLKID_MPLL_PREDIV (CLKID_PLL_BASE + 23)
>> +#define CLKID_MPLL0_DIV (CLKID_PLL_BASE + 24)
>> +#define CLKID_MPLL0 (CLKID_PLL_BASE + 25)
>> +#define CLKID_MPLL1_DIV (CLKID_PLL_BASE + 26)
>> +#define CLKID_MPLL1 (CLKID_PLL_BASE + 27)
>> +#define CLKID_MPLL2_DIV (CLKID_PLL_BASE + 28)
>> +#define CLKID_MPLL2 (CLKID_PLL_BASE + 29)
>> +#define CLKID_MPLL3_DIV (CLKID_PLL_BASE + 30)
>> +#define CLKID_MPLL3 (CLKID_PLL_BASE + 31)
>> +
>> +#define CLKID_BASE (CLKID_PLL_BASE + 32)
>> +#define CLKID_RTC_32K_CLKIN (CLKID_BASE + 0)
>> +#define CLKID_RTC_32K_DIV (CLKID_BASE + 1)
>> +#define CLKID_RTC_32K_SEL (CLKID_BASE + 2)
>> +#define CLKID_RTC_32K_XATL (CLKID_BASE + 3)
>> +#define CLKID_RTC_CLK (CLKID_BASE + 4)
>> +#define CLKID_SYS_CLK_B_SEL (CLKID_BASE + 5)
>> +#define CLKID_SYS_CLK_B_DIV (CLKID_BASE + 6)
>> +#define CLKID_SYS_CLK_B_GATE (CLKID_BASE + 7)
>> +#define CLKID_SYS_CLK_A_SEL (CLKID_BASE + 8)
>> +#define CLKID_SYS_CLK_A_DIV (CLKID_BASE + 9)
>> +#define CLKID_SYS_CLK_A_GATE (CLKID_BASE + 10)
>> +#define CLKID_SYS_CLK (CLKID_BASE + 11)
>> +
>> +#define CLKID_CECA_32K_CLKIN (CLKID_BASE + 12)
>> +#define CLKID_CECA_32K_DIV (CLKID_BASE + 13)
>> +#define CLKID_CECA_32K_SEL_PRE (CLKID_BASE + 14)
>> +#define CLKID_CECA_32K_SEL (CLKID_BASE + 15)
>> +#define CLKID_CECA_32K_CLKOUT (CLKID_BASE + 16)
>> +#define CLKID_CECB_32K_CLKIN (CLKID_BASE + 17)
>> +#define CLKID_CECB_32K_DIV (CLKID_BASE + 18)
>> +#define CLKID_CECB_32K_SEL_PRE (CLKID_BASE + 19)
>> +#define CLKID_CECB_32K_SEL (CLKID_BASE + 20)
>> +#define CLKID_CECB_32K_CLKOUT (CLKID_BASE + 21)
>> +
>> +#define CLKID_SC_CLK_SEL (CLKID_BASE + 22)
>> +#define CLKID_SC_CLK_DIV (CLKID_BASE + 23)
>> +#define CLKID_SC_CLK_GATE (CLKID_BASE + 24)
>> +
>> +#define CLKID_DSPA_CLK_B_SEL (CLKID_BASE + 25)
>> +#define CLKID_DSPA_CLK_B_DIV (CLKID_BASE + 26)
>> +#define CLKID_DSPA_CLK_B_GATE (CLKID_BASE + 27)
>> +#define CLKID_DSPA_CLK_A_SEL (CLKID_BASE + 28)
>> +#define CLKID_DSPA_CLK_A_DIV (CLKID_BASE + 29)
>> +#define CLKID_DSPA_CLK_A_GATE (CLKID_BASE + 30)
>> +#define CLKID_DSPA_CLK (CLKID_BASE + 31)
>> +
>> +#define CLKID_12_24M_CLK_GATE (CLKID_BASE + 32)
>> +#define CLKID_12M_CLK_DIV (CLKID_BASE + 33)
>> +#define CLKID_12_24M_CLK_SEL (CLKID_BASE + 34)
>> +#define CLKID_25M_CLK_DIV (CLKID_BASE + 35)
>> +#define CLKID_25M_CLK_GATE (CLKID_BASE + 36)
>> +
>> +#define CLKID_VID_PLL_DIV (CLKID_BASE + 37)
>> +#define CLKID_VID_PLL_SEL (CLKID_BASE + 38)
>> +#define CLKID_VID_PLL (CLKID_BASE + 39)
>> +#define CLKID_VCLK_SEL (CLKID_BASE + 40)
>> +#define CLKID_VCLK2_SEL (CLKID_BASE + 41)
>> +#define CLKID_VCLK_INPUT (CLKID_BASE + 42)
>> +#define CLKID_VCLK2_INPUT (CLKID_BASE + 43)
>> +#define CLKID_VCLK_DIV (CLKID_BASE + 44)
>> +#define CLKID_VCLK2_DIV (CLKID_BASE + 45)
>> +#define CLKID_VCLK (CLKID_BASE + 46)
>> +#define CLKID_VCLK2 (CLKID_BASE + 47)
>> +#define CLKID_VCLK_DIV1 (CLKID_BASE + 48)
>> +#define CLKID_VCLK_DIV2_EN (CLKID_BASE + 49)
>> +#define CLKID_VCLK_DIV4_EN (CLKID_BASE + 50)
>> +#define CLKID_VCLK_DIV6_EN (CLKID_BASE + 51)
>> +#define CLKID_VCLK_DIV12_EN (CLKID_BASE + 52)
>> +#define CLKID_VCLK2_DIV1 (CLKID_BASE + 53)
>> +#define CLKID_VCLK2_DIV2_EN (CLKID_BASE + 54)
>> +#define CLKID_VCLK2_DIV4_EN (CLKID_BASE + 55)
>> +#define CLKID_VCLK2_DIV6_EN (CLKID_BASE + 56)
>> +#define CLKID_VCLK2_DIV12_EN (CLKID_BASE + 57)
>> +#define CLKID_VCLK_DIV2 (CLKID_BASE + 58)
>> +#define CLKID_VCLK_DIV4 (CLKID_BASE + 59)
>> +#define CLKID_VCLK_DIV6 (CLKID_BASE + 60)
>> +#define CLKID_VCLK_DIV12 (CLKID_BASE + 61)
>> +#define CLKID_VCLK2_DIV2 (CLKID_BASE + 62)
>> +#define CLKID_VCLK2_DIV4 (CLKID_BASE + 63)
>> +#define CLKID_VCLK2_DIV6 (CLKID_BASE + 64)
>> +#define CLKID_VCLK2_DIV12 (CLKID_BASE + 65)
>> +#define CLKID_CTS_ENCI_SEL (CLKID_BASE + 66)
>> +#define CLKID_CTS_ENCP_SEL (CLKID_BASE + 67)
>> +#define CLKID_CTS_VDAC_SEL (CLKID_BASE + 68)
>> +#define CLKID_HDMI_TX_SEL (CLKID_BASE + 69)
>> +#define CLKID_CTS_ENCI (CLKID_BASE + 70)
>> +#define CLKID_CTS_ENCP (CLKID_BASE + 71)
>> +#define CLKID_CTS_VDAC (CLKID_BASE + 72)
>> +#define CLKID_HDMI_TX (CLKID_BASE + 73)
>> +
>> +#define CLKID_HDMI_SEL (CLKID_BASE + 74)
>> +#define CLKID_HDMI_DIV (CLKID_BASE + 75)
>> +#define CLKID_HDMI (CLKID_BASE + 76)
>> +#define CLKID_TS_CLK_DIV (CLKID_BASE + 77)
>> +#define CLKID_TS_CLK_GATE (CLKID_BASE + 78)
>> +
>> +#define CLKID_MALI_0_SEL (CLKID_BASE + 79)
>> +#define CLKID_MALI_0_DIV (CLKID_BASE + 80)
>> +#define CLKID_MALI_0 (CLKID_BASE + 81)
>> +#define CLKID_MALI_1_SEL (CLKID_BASE + 82)
>> +#define CLKID_MALI_1_DIV (CLKID_BASE + 83)
>> +#define CLKID_MALI_1 (CLKID_BASE + 84)
>> +#define CLKID_MALI (CLKID_BASE + 85)
>> +
>> +#define CLKID_VDEC_P0_SEL (CLKID_BASE + 86)
>> +#define CLKID_VDEC_P0_DIV (CLKID_BASE + 87)
>> +#define CLKID_VDEC_P0 (CLKID_BASE + 88)
>> +#define CLKID_VDEC_P1_SEL (CLKID_BASE + 89)
>> +#define CLKID_VDEC_P1_DIV (CLKID_BASE + 90)
>> +#define CLKID_VDEC_P1 (CLKID_BASE + 91)
>> +#define CLKID_VDEC_SEL (CLKID_BASE + 92)
>> +
>> +#define CLKID_HCODEC_P0_SEL (CLKID_BASE + 93)
>> +#define CLKID_HCODEC_P0_DIV (CLKID_BASE + 94)
>> +#define CLKID_HCODEC_P0 (CLKID_BASE + 95)
>> +#define CLKID_HCODEC_P1_SEL (CLKID_BASE + 96)
>> +#define CLKID_HCODEC_P1_DIV (CLKID_BASE + 97)
>> +#define CLKID_HCODEC_P1 (CLKID_BASE + 98)
>> +#define CLKID_HCODEC_SEL (CLKID_BASE + 99)
>> +
>> +#define CLKID_HEVCB_P0_SEL (CLKID_BASE + 100)
>> +#define CLKID_HEVCB_P0_DIV (CLKID_BASE + 101)
>> +#define CLKID_HEVCB_P0 (CLKID_BASE + 102)
>> +#define CLKID_HEVCB_P1_SEL (CLKID_BASE + 103)
>> +#define CLKID_HEVCB_P1_DIV (CLKID_BASE + 104)
>> +#define CLKID_HEVCB_P1 (CLKID_BASE + 105)
>> +#define CLKID_HEVCB_SEL (CLKID_BASE + 106)
>> +
>> +#define CLKID_HEVCF_P0_SEL (CLKID_BASE + 107)
>> +#define CLKID_HEVCF_P0_DIV (CLKID_BASE + 108)
>> +#define CLKID_HEVCF_P0 (CLKID_BASE + 109)
>> +#define CLKID_HEVCF_P1_SEL (CLKID_BASE + 110)
>> +#define CLKID_HEVCF_P1_DIV (CLKID_BASE + 111)
>> +#define CLKID_HEVCF_P1 (CLKID_BASE + 112)
>> +#define CLKID_HEVCF_SEL (CLKID_BASE + 113)
>> +
>> +#define CLKID_WAVE_A_SEL (CLKID_BASE + 114)
>> +#define CLKID_WAVE_A_DIV (CLKID_BASE + 115)
>> +#define CLKID_WAVE_A_GATE (CLKID_BASE + 116)
>> +#define CLKID_WAVE_B_SEL (CLKID_BASE + 117)
>> +#define CLKID_WAVE_B_DIV (CLKID_BASE + 118)
>> +#define CLKID_WAVE_B_GATE (CLKID_BASE + 119)
>> +#define CLKID_WAVE_C_SEL (CLKID_BASE + 120)
>> +#define CLKID_WAVE_C_DIV (CLKID_BASE + 121)
>> +#define CLKID_WAVE_C_GATE (CLKID_BASE + 122)
>> +
>> +#define CLKID_VPU_0_SEL (CLKID_BASE + 123)
>> +#define CLKID_VPU_0_DIV (CLKID_BASE + 124)
>> +#define CLKID_VPU_0 (CLKID_BASE + 125)
>> +#define CLKID_VPU_1_SEL (CLKID_BASE + 126)
>> +#define CLKID_VPU_1_DIV (CLKID_BASE + 127)
>> +#define CLKID_VPU_1 (CLKID_BASE + 128)
>> +#define CLKID_VPU (CLKID_BASE + 129)
>> +
>> +#define CLKID_VPU_CLKB_TMP_SEL (CLKID_BASE + 130)
>> +#define CLKID_VPU_CLKB_TMP_DIV (CLKID_BASE + 131)
>> +#define CLKID_VPU_CLKB_TMP (CLKID_BASE + 132)
>> +#define CLKID_VPU_CLKB_DIV (CLKID_BASE + 133)
>> +#define CLKID_VPU_CLKB (CLKID_BASE + 134)
>> +
>> +#define CLKID_VPU_CLKC_P0_SEL (CLKID_BASE + 135)
>> +#define CLKID_VPU_CLKC_P0_DIV (CLKID_BASE + 136)
>> +#define CLKID_VPU_CLKC_P0 (CLKID_BASE + 137)
>> +#define CLKID_VPU_CLKC_P1_SEL (CLKID_BASE + 138)
>> +#define CLKID_VPU_CLKC_P1_DIV (CLKID_BASE + 139)
>> +#define CLKID_VPU_CLKC_P1 (CLKID_BASE + 140)
>> +#define CLKID_VPU_CLKC_SEL (CLKID_BASE + 141)
>> +
>> +#define CLKID_VAPB_0_SEL (CLKID_BASE + 142)
>> +#define CLKID_VAPB_0_DIV (CLKID_BASE + 143)
>> +#define CLKID_VAPB_0 (CLKID_BASE + 144)
>> +#define CLKID_VAPB_1_SEL (CLKID_BASE + 145)
>> +#define CLKID_VAPB_1_DIV (CLKID_BASE + 146)
>> +#define CLKID_VAPB_1 (CLKID_BASE + 147)
>> +#define CLKID_VAPB (CLKID_BASE + 148)
>> +
>> +#define CLKID_GE2D (CLKID_BASE + 149)
>> +
>> +#define CLKID_VDIN_MEAS_SEL (CLKID_BASE + 150)
>> +#define CLKID_VDIN_MEAS_DIV (CLKID_BASE + 151)
>> +#define CLKID_VDIN_MEAS_GATE (CLKID_BASE + 152)
>> +
>> +#define CLKID_SD_EMMC_C_CLK_SEL (CLKID_BASE + 153)
>> +#define CLKID_SD_EMMC_C_CLK_DIV (CLKID_BASE + 154)
>> +#define CLKID_SD_EMMC_C_CLK (CLKID_BASE + 155)
>> +#define CLKID_SD_EMMC_A_CLK_SEL (CLKID_BASE + 156)
>> +#define CLKID_SD_EMMC_A_CLK_DIV (CLKID_BASE + 157)
>> +#define CLKID_SD_EMMC_A_CLK (CLKID_BASE + 158)
>> +#define CLKID_SD_EMMC_B_CLK_SEL (CLKID_BASE + 159)
>> +#define CLKID_SD_EMMC_B_CLK_DIV (CLKID_BASE + 160)
>> +#define CLKID_SD_EMMC_B_CLK (CLKID_BASE + 161)
>> +
>> +#define CLKID_SPICC0_SEL (CLKID_BASE + 162)
>> +#define CLKID_SPICC0_DIV (CLKID_BASE + 163)
>> +#define CLKID_SPICC0_GATE (CLKID_BASE + 164)
>> +#define CLKID_SPICC1_SEL (CLKID_BASE + 165)
>> +#define CLKID_SPICC1_DIV (CLKID_BASE + 166)
>> +#define CLKID_SPICC1_GATE (CLKID_BASE + 167)
>> +
>> +#define CLKID_PWM_A_SEL (CLKID_BASE + 168)
>> +#define CLKID_PWM_A_DIV (CLKID_BASE + 169)
>> +#define CLKID_PWM_A_GATE (CLKID_BASE + 170)
>> +#define CLKID_PWM_B_SEL (CLKID_BASE + 171)
>> +#define CLKID_PWM_B_DIV (CLKID_BASE + 172)
>> +#define CLKID_PWM_B_GATE (CLKID_BASE + 173)
>> +#define CLKID_PWM_C_SEL (CLKID_BASE + 174)
>> +#define CLKID_PWM_C_DIV (CLKID_BASE + 175)
>> +#define CLKID_PWM_C_GATE (CLKID_BASE + 176)
>> +#define CLKID_PWM_D_SEL (CLKID_BASE + 177)
>> +#define CLKID_PWM_D_DIV (CLKID_BASE + 178)
>> +#define CLKID_PWM_D_GATE (CLKID_BASE + 179)
>> +#define CLKID_PWM_E_SEL (CLKID_BASE + 180)
>> +#define CLKID_PWM_E_DIV (CLKID_BASE + 181)
>> +#define CLKID_PWM_E_GATE (CLKID_BASE + 182)
>> +#define CLKID_PWM_F_SEL (CLKID_BASE + 183)
>> +#define CLKID_PWM_F_DIV (CLKID_BASE + 184)
>> +#define CLKID_PWM_F_GATE (CLKID_BASE + 185)
>> +#define CLKID_PWM_G_SEL (CLKID_BASE + 186)
>> +#define CLKID_PWM_G_DIV (CLKID_BASE + 187)
>> +#define CLKID_PWM_G_GATE (CLKID_BASE + 188)
>> +#define CLKID_PWM_H_SEL (CLKID_BASE + 189)
>> +#define CLKID_PWM_H_DIV (CLKID_BASE + 190)
>> +#define CLKID_PWM_H_GATE (CLKID_BASE + 191)
>> +#define CLKID_PWM_I_SEL (CLKID_BASE + 192)
>> +#define CLKID_PWM_I_DIV (CLKID_BASE + 193)
>> +#define CLKID_PWM_I_GATE (CLKID_BASE + 194)
>> +#define CLKID_PWM_J_SEL (CLKID_BASE + 195)
>> +#define CLKID_PWM_J_DIV (CLKID_BASE + 196)
>> +#define CLKID_PWM_J_GATE (CLKID_BASE + 197)
>> +
>> +#define CLKID_SARADC_SEL (CLKID_BASE + 198)
>> +#define CLKID_SARADC_DIV (CLKID_BASE + 199)
>> +#define CLKID_SARADC_GATE (CLKID_BASE + 200)
>> +#define CLKID_GEN_SEL (CLKID_BASE + 201)
>> +#define CLKID_GEN_DIV (CLKID_BASE + 202)
>> +#define CLKID_GEN_GATE (CLKID_BASE + 203)
>> +
>> +#define CLKID_DDR (CLKID_BASE + 204)
>> +#define CLKID_DOS (CLKID_BASE + 205)
>> +#define CLKID_ETHPHY (CLKID_BASE + 206)
>> +#define CLKID_MALI_GATE (CLKID_BASE + 207)
>> +#define CLKID_AOCPU (CLKID_BASE + 208)
>> +#define CLKID_AUCPU (CLKID_BASE + 209)
>> +#define CLKID_CEC (CLKID_BASE + 210)
>> +#define CLKID_SD_EMMC_A (CLKID_BASE + 211)
>> +#define CLKID_SD_EMMC_B (CLKID_BASE + 212)
>> +#define CLKID_NAND (CLKID_BASE + 213)
>> +#define CLKID_SMARTCARD (CLKID_BASE + 214)
>> +#define CLKID_ACODEC (CLKID_BASE + 215)
>> +#define CLKID_SPIFC (CLKID_BASE + 216)
>> +#define CLKID_MSR_CLK (CLKID_BASE + 217)
>> +#define CLKID_IR_CTRL (CLKID_BASE + 218)
>> +#define CLKID_AUDIO (CLKID_BASE + 219)
>> +#define CLKID_ETH (CLKID_BASE + 220)
>> +#define CLKID_UART_A (CLKID_BASE + 221)
>> +#define CLKID_UART_B (CLKID_BASE + 222)
>> +#define CLKID_UART_C (CLKID_BASE + 223)
>> +#define CLKID_UART_D (CLKID_BASE + 224)
>> +#define CLKID_UART_E (CLKID_BASE + 225)
>> +#define CLKID_AIFIFO (CLKID_BASE + 226)
>> +#define CLKID_TS_DDR (CLKID_BASE + 227)
>> +#define CLKID_TS_PLL (CLKID_BASE + 228)
>> +#define CLKID_G2D (CLKID_BASE + 229)
>> +#define CLKID_SPICC0 (CLKID_BASE + 230)
>> +#define CLKID_SPICC1 (CLKID_BASE + 231)
>> +#define CLKID_PCIE (CLKID_BASE + 232)
>> +#define CLKID_USB (CLKID_BASE + 233)
>> +#define CLKID_PCIE_PHY (CLKID_BASE + 234)
>> +#define CLKID_I2C_M_A (CLKID_BASE + 235)
>> +#define CLKID_I2C_M_B (CLKID_BASE + 236)
>> +#define CLKID_I2C_M_C (CLKID_BASE + 237)
>> +#define CLKID_I2C_M_D (CLKID_BASE + 238)
>> +#define CLKID_I2C_M_E (CLKID_BASE + 239)
>> +#define CLKID_I2C_M_F (CLKID_BASE + 240)
>> +#define CLKID_HDMITX_APB (CLKID_BASE + 241)
>> +#define CLKID_I2C_S_A (CLKID_BASE + 242)
>> +#define CLKID_USB1_TO_DDR (CLKID_BASE + 243)
>> +#define CLKID_HDCP22 (CLKID_BASE + 244)
>> +#define CLKID_MMC_APB (CLKID_BASE + 245)
>> +#define CLKID_RSA (CLKID_BASE + 246)
>> +#define CLKID_CPU_DEBUG (CLKID_BASE + 247)
>> +#define CLKID_DSPA (CLKID_BASE + 248)
>> +#define CLKID_VPU_INTR (CLKID_BASE + 249)
>> +#define CLKID_SAR_ADC (CLKID_BASE + 250)
>> +#define CLKID_GIC (CLKID_BASE + 251)
>> +#define CLKID_PWM_AB (CLKID_BASE + 252)
>> +#define CLKID_PWM_CD (CLKID_BASE + 253)
>> +#define CLKID_PWM_EF (CLKID_BASE + 254)
>> +#define CLKID_PWM_GH (CLKID_BASE + 255)
>> +#define CLKID_PWM_IJ (CLKID_BASE + 256)
>> +#define CLKID_DEMOD (CLKID_BASE + 257)
>> +
>> +#define CLKID_HDCP22_ESMCLK_SEL (CLKID_BASE + 258)
>> +#define CLKID_HDCP22_ESMCLK_DIV (CLKID_BASE + 259)
>> +#define CLKID_HDCP22_ESMCLK_GATE (CLKID_BASE + 260)
>> +#define CLKID_HDCP22_SKPCLK_SEL (CLKID_BASE + 261)
>> +#define CLKID_HDCP22_SKPCLK_DIV (CLKID_BASE + 262)
>> +#define CLKID_HDCP22_SKPCLK_GATE (CLKID_BASE + 263)
>> +
>> +#define CLKID_DEMOD_CORE_CLK_SEL (CLKID_BASE + 264)
>> +#define CLKID_DEMOD_CORE_CLK_DIV (CLKID_BASE + 265)
>> +#define CLKID_DEMOD_CORE_CLK_GATE (CLKID_BASE + 266)
>> +#define CLKID_ADC_EXTCLK_IN_SEL (CLKID_BASE + 267)
>> +#define CLKID_ADC_EXTCLK_IN_DIV (CLKID_BASE + 268)
>> +#define CLKID_ADC_EXTCLK_IN_GATE (CLKID_BASE + 269)
>> +#define CLKID_DEMOD_CORE_T2_CLK_SEL (CLKID_BASE + 270)
>> +#define CLKID_DEMOD_CORE_T2_CLK_DIV (CLKID_BASE + 271)
>> +#define CLKID_DEMOD_CORE_T2_CLK_GATE (CLKID_BASE + 272)
>> +#define CLKID_DEMOD_32K_CLKIN (CLKID_BASE + 273)
>> +#define CLKID_DEMOD_32K_DIV (CLKID_BASE + 274)
>> +#define CLKID_DEMOD_32K_XTAL (CLKID_BASE + 275)
>> +#define CLKID_DEMOD_32K_CLK (CLKID_BASE + 276)
>> +
>> +#define NR_CLKS (CLKID_BASE + 277)
>> +
>> +#endif /* __S4_CLKC_H */
>
> .
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings
2022-07-12 9:40 ` Krzysztof Kozlowski
@ 2022-07-19 5:55 ` Yu Tu
0 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2022-07-19 5:55 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Hi Krzysztof,
Thank you for your advice.
On 2022/7/12 17:40, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 08/07/2022 08:27, Yu Tu wrote:
>> Add new clock controller compatible and dt-bindings header for the
>> Everything-Else domain of the S4 SoC.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> .../bindings/clock/amlogic,gxbb-clkc.txt | 1 +
>> MAINTAINERS | 1 +
>> include/dt-bindings/clock/s4-clkc.h | 354 ++++++++++++++++++
>> 3 files changed, 356 insertions(+)
>> create mode 100644 include/dt-bindings/clock/s4-clkc.h
>>
>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
>> index 7ccecd5c02c1..301b43dea912 100644
>> --- a/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
>> +++ b/Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
>> @@ -12,6 +12,7 @@ Required Properties:
>> "amlogic,g12a-clkc" for G12A SoC.
>> "amlogic,g12b-clkc" for G12B SoC.
>> "amlogic,sm1-clkc" for SM1 SoC.
>> + "amlogic,s4-clkc" for S4 SoC.
>> - clocks : list of clock phandle, one for each entry clock-names.
>> - clock-names : should contain the following:
>> * "xtal": the platform xtal
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index c1abc53f9e91..e4ca46c5c8a1 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1775,6 +1775,7 @@ F: Documentation/devicetree/bindings/clock/amlogic*
>> F: drivers/clk/meson/
>> F: include/dt-bindings/clock/gxbb*
>> F: include/dt-bindings/clock/meson*
>> +F: include/dt-bindings/clock/s*
>>
>> ARM/Amlogic Meson SoC Crypto Drivers
>> M: Corentin Labbe <clabbe@baylibre.com>
>> diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
>> new file mode 100644
>> index 000000000000..8b46d54d79fe
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/s4-clkc.h
>> @@ -0,0 +1,354 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, Inc. All rights reserved.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef __S4_CLKC_H
>> +#define __S4_CLKC_H
>
> Use header guards mathcing paths. See other files for examples.
I will correct it.
>
>> +
>> +/*
>> + * CLKID index values
>> + */
>> +
>> +#define CLKID_PLL_BASE 0
>> +#define CLKID_FIXED_PLL_DCO (CLKID_PLL_BASE + 0)
>
> Drop CLKID_PLL_BASE
I will correct it.
>
>> +#define CLKID_FIXED_PLL (CLKID_PLL_BASE + 1)
>
> ditto... and so on.
I will correct it.
>
>
> Best regards,
> Krzysztof
>
> .
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/3] arm64: dts: meson: add S4 Soc clock controller in DT
2022-07-12 9:41 ` Krzysztof Kozlowski
@ 2022-07-19 5:57 ` Yu Tu
0 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2022-07-19 5:57 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Hi Krzysztof,
Thank you for your advice.
On 2022/7/12 17:41, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 08/07/2022 08:27, Yu Tu wrote:
>> Added information about the S4 SOC Clock controller in DT.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 9 ++++++++-
>> 1 file changed, 8 insertions(+), 1 deletion(-)
>>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> index ff213618a598..ad2ec26a1f4a 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> +++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
>> @@ -86,7 +86,7 @@ gic: interrupt-controller@fff01000 {
>> };
>>
>> apb4: apb4@fe000000 {
>> - compatible = "simple-bus";
>> + compatible = "simple-bus", "syscon";
>
> This is not allowed.
> 1. syscon needs also dedicated compatible
> 2. simple-bus with syscon means it is not a simple bus anymore, so nope.
I will correct it.
>
>> reg = <0x0 0xfe000000 0x0 0x480000>;
>> #address-cells = <2>;
>> #size-cells = <2>;
>> @@ -118,6 +118,13 @@ gpio_intc: interrupt-controller@4080 {
>> <10 11 12 13 14 15 16 17 18 19 20 21>;
>> };
>>
>> + clkc: clock-controller {
>> + compatible = "amlogic,s4-clkc";
>> + #clock-cells = <1>;
>> + clocks = <&xtal>;
>> + clock-names = "xtal";
>> + };
>> +
>> uart_B: serial@7a000 {
>> compatible = "amlogic,meson-s4-uart",
>> "amlogic,meson-ao-uart";
>
>
> Best regards,
> Krzysztof
>
> .
_______________________________________________
linux-arm-kernel mailing list
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver
2022-07-12 9:44 ` [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver Krzysztof Kozlowski
@ 2022-07-19 6:02 ` Yu Tu
2022-07-19 6:29 ` Krzysztof Kozlowski
0 siblings, 1 reply; 15+ messages in thread
From: Yu Tu @ 2022-07-19 6:02 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Hi Krzysztof,
Thank you for your advice.
On 2022/7/12 17:44, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 08/07/2022 08:27, Yu Tu wrote:
>> Add the peripheral clock controller found in the s4 SoC family.
>>
>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>> ---
>> MAINTAINERS | 2 +-
>> drivers/clk/meson/Kconfig | 17 +
>> drivers/clk/meson/Makefile | 1 +
>> drivers/clk/meson/s4.c | 4678 ++++++++++++++++++++++++++++++++++++
>> drivers/clk/meson/s4.h | 156 ++
>> 5 files changed, 4853 insertions(+), 1 deletion(-)
>> create mode 100644 drivers/clk/meson/s4.c
>> create mode 100644 drivers/clk/meson/s4.h
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index e4ca46c5c8a1..f116ec0642f2 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -1772,7 +1772,7 @@ M: Jerome Brunet <jbrunet@baylibre.com>
>> L: linux-amlogic@lists.infradead.org
>> S: Maintained
>> F: Documentation/devicetree/bindings/clock/amlogic*
>> -F: drivers/clk/meson/
>> +F: drivers/clk/meson/*
>
> Why?
Warning is displayed when using checkpatch. I will correct it.
>
>> F: include/dt-bindings/clock/gxbb*
>> F: include/dt-bindings/clock/meson*
>> F: include/dt-bindings/clock/s*
>> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
>> index fc002c155bc3..1a344b0564e8 100644
>> --- a/drivers/clk/meson/Kconfig
>> +++ b/drivers/clk/meson/Kconfig
>> @@ -115,4 +115,21 @@ config COMMON_CLK_G12A
>> help
>> Support for the clock controller on Amlogic S905D2, S905X2 and S905Y2
>> devices, aka g12a. Say Y if you want peripherals to work.
>> +
>> +config COMMON_CLK_S4
>> + tristate "S4 SoC clock controllers support"
>> + depends on ARM64
>> + default y
>> + select COMMON_CLK_MESON_REGMAP
>> + select HAVE_ARM_SMCCC
>> + select COMMON_CLK_MESON_DUALDIV
>> + select COMMON_CLK_MESON_MPLL
>> + select COMMON_CLK_MESON_PLL
>> + select COMMON_CLK_MESON_CPU_DYNDIV
>> + select COMMON_CLK_MESON_VID_PLL_DIV
>> + select MFD_SYSCON
>> + help
>> + Support for the clock controller on Amlogic S805X2 and S905Y4 devices,
>> + aka s4. Amlogic S805X2 and S905Y4 devices include AQ222 and AQ229.
>> + Say Y if you want peripherals and CPU frequency scaling to work.
>> endmenu
>> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
>> index 6eca2a406ee3..b3ef5f67820f 100644
>> --- a/drivers/clk/meson/Makefile
>> +++ b/drivers/clk/meson/Makefile
>> @@ -19,3 +19,4 @@ obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
>> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.o
>> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o meson8-ddr.o
>> +obj-$(CONFIG_COMMON_CLK_S4) += s4.o
>> diff --git a/drivers/clk/meson/s4.c b/drivers/clk/meson/s4.c
>> new file mode 100644
>> index 000000000000..a97159222f0e
>> --- /dev/null
>> +++ b/drivers/clk/meson/s4.c
>> @@ -0,0 +1,4678 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Amlogic Meson-S4 Clock Controller Driver
>> + *
>> + * Copyright (c) 2021 Amlogic, inc.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#include <linux/clk-provider.h>
>> +#include <linux/init.h>
>> +#include <linux/of_device.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/clk.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <dt-bindings/clock/s4-clkc.h>
>> +
>> +#include "clk-mpll.h"
>> +#include "clk-pll.h"
>> +#include "clk-regmap.h"
>> +#include "vid-pll-div.h"
>> +#include "clk-dualdiv.h"
>> +#include "s4.h"
>> +#include "meson-eeclk.h"
>> +
>> +static DEFINE_SPINLOCK(meson_clk_lock);
>> +
>> +static struct clk_regmap s4_fixed_pll_dco = {
>
> None of these are const?
I will correct it.
>
>> + .data = &(struct meson_clk_pll_data){
>> + .en = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 28,
>> + .width = 1,
>> + },
>> + .m = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 0,
>> + .width = 8,
>> + },
>> + .n = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 10,
>> + .width = 5,
>> + },
>> + .frac = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL1,
>> + .shift = 0,
>> + .width = 17,
>> + },
>> + .l = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 31,
>> + .width = 1,
>> + },
>> + .rst = {
>> + .reg_off = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 29,
>> + .width = 1,
>> + },
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fixed_pll_dco",
>> + .ops = &meson_clk_pll_ro_ops,
>> + .parent_data = (const struct clk_parent_data []) {
>> + { .fw_name = "xtal", }
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fixed_pll = {
>> + .data = &(struct clk_regmap_div_data){
>> + .offset = ANACTRL_FIXPLL_CTRL0,
>> + .shift = 16,
>> + .width = 2,
>> + .flags = CLK_DIVIDER_POWER_OF_TWO,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fixed_pll",
>> + .ops = &clk_regmap_divider_ro_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll_dco.hw
>> + },
>> + .num_parents = 1,
>> + /*
>> + * This clock won't ever change at runtime so
>> + * CLK_SET_RATE_PARENT is not required
>> + */
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div2_div = {
>> + .mult = 1,
>> + .div = 2,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div2 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 24,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div2_div.hw
>> + },
>> + .num_parents = 1,
>> + /*
>> + * Similar to fclk_div3, it seems that this clock is used by
>> + * the resident firmware and is required by the platform to
>> + * operate correctly.
>> + * Until the following condition are met, we need this clock to
>> + * be marked as critical:
>> + * a) Mark the clock used by a firmware resource, if possible
>> + * b) CCF has a clock hand-off mechanism to make the sure the
>> + * clock stays on until the proper driver comes along
>> + */
>> + .flags = CLK_IS_CRITICAL,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div3_div = {
>> + .mult = 1,
>> + .div = 3,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div3_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div3 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 20,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div3",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div3_div.hw
>> + },
>> + .num_parents = 1,
>> + /*
>> + * This clock is used by the resident firmware and is required
>> + * by the platform to operate correctly.
>> + * Until the following condition are met, we need this clock to
>> + * be marked as critical:
>> + * a) Mark the clock used by a firmware resource, if possible
>> + * b) CCF has a clock hand-off mechanism to make the sure the
>> + * clock stays on until the proper driver comes along
>> + */
>> + .flags = CLK_IS_CRITICAL,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div4_div = {
>> + .mult = 1,
>> + .div = 4,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div4_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div4 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 21,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div4",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div4_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div5_div = {
>> + .mult = 1,
>> + .div = 5,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div5_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div5 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 22,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div5",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div5_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div7_div = {
>> + .mult = 1,
>> + .div = 7,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div7_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) { &s4_fixed_pll.hw },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div7 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 23,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div7",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div7_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_fixed_factor s4_fclk_div2p5_div = {
>> + .mult = 2,
>> + .div = 5,
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2p5_div",
>> + .ops = &clk_fixed_factor_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fixed_pll.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static struct clk_regmap s4_fclk_div2p5 = {
>> + .data = &(struct clk_regmap_gate_data){
>> + .offset = ANACTRL_FIXPLL_CTRL1,
>> + .bit_idx = 25,
>> + },
>> + .hw.init = &(struct clk_init_data){
>> + .name = "fclk_div2p5",
>> + .ops = &clk_regmap_gate_ops,
>> + .parent_hws = (const struct clk_hw *[]) {
>> + &s4_fclk_div2p5_div.hw
>> + },
>> + .num_parents = 1,
>> + },
>> +};
>> +
>> +static const struct pll_mult_range s4_gp0_pll_mult_range = {
>
> Not const?
I will correct it.
>
>> + .min = 125,
>> + .max = 250,
>> +};
>> +
>
> (...)
>
>> +/* Convenience table to populate regmap in .probe */
>> +static struct clk_regmap *const s4_clk_regmaps[] = {
>> + &s4_rtc_32k_by_oscin_clkin,
>> + &s4_rtc_32k_by_oscin_div,
>> + &s4_rtc_32k_by_oscin_sel,
>> + &s4_rtc_32k_by_oscin,
>> + &s4_rtc_clk,
>> +
>> + &s4_sysclk_b_sel,
>> + &s4_sysclk_b_div,
>> + &s4_sysclk_b,
>> + &s4_sysclk_a_sel,
>> + &s4_sysclk_a_div,
>> + &s4_sysclk_a,
>> + &s4_sys_clk,
>> +
>> + &s4_ceca_32k_clkin,
>> + &s4_ceca_32k_div,
>> + &s4_ceca_32k_sel_pre,
>> + &s4_ceca_32k_sel,
>> + &s4_ceca_32k_clkout,
>> + &s4_cecb_32k_clkin,
>> + &s4_cecb_32k_div,
>> + &s4_cecb_32k_sel_pre,
>> + &s4_cecb_32k_sel,
>> + &s4_cecb_32k_clkout,
>> +
>> + &s4_sc_clk_mux,
>> + &s4_sc_clk_div,
>> + &s4_sc_clk_gate,
>> +
>> + &s4_12_24M_clk_gate,
>> + &s4_12_24M_clk,
>> + &s4_vid_pll_div,
>> + &s4_vid_pll_sel,
>> + &s4_vid_pll,
>> + &s4_vclk_sel,
>> + &s4_vclk2_sel,
>> + &s4_vclk_input,
>> + &s4_vclk2_input,
>> + &s4_vclk_div,
>> + &s4_vclk2_div,
>> + &s4_vclk,
>> + &s4_vclk2,
>> + &s4_vclk_div1,
>> + &s4_vclk_div2_en,
>> + &s4_vclk_div4_en,
>> + &s4_vclk_div6_en,
>> + &s4_vclk_div12_en,
>> + &s4_vclk2_div1,
>> + &s4_vclk2_div2_en,
>> + &s4_vclk2_div4_en,
>> + &s4_vclk2_div6_en,
>> + &s4_vclk2_div12_en,
>> + &s4_cts_enci_sel,
>> + &s4_cts_encp_sel,
>> + &s4_cts_vdac_sel,
>> + &s4_hdmi_tx_sel,
>> + &s4_cts_enci,
>> + &s4_cts_encp,
>> + &s4_cts_vdac,
>> + &s4_hdmi_tx,
>> +
>> + &s4_hdmi_sel,
>> + &s4_hdmi_div,
>> + &s4_hdmi,
>> + &s4_ts_clk_div,
>> + &s4_ts_clk_gate,
>> +
>> + &s4_mali_0_sel,
>> + &s4_mali_0_div,
>> + &s4_mali_0,
>> + &s4_mali_1_sel,
>> + &s4_mali_1_div,
>> + &s4_mali_1,
>> + &s4_mali_mux,
>> +
>> + &s4_vdec_p0_mux,
>> + &s4_vdec_p0_div,
>> + &s4_vdec_p0,
>> + &s4_vdec_p1_mux,
>> + &s4_vdec_p1_div,
>> + &s4_vdec_p1,
>> + &s4_vdec_mux,
>> +
>> + &s4_hevcf_p0_mux,
>> + &s4_hevcf_p0_div,
>> + &s4_hevcf_p0,
>> + &s4_hevcf_p1_mux,
>> + &s4_hevcf_p1_div,
>> + &s4_hevcf_p1,
>> + &s4_hevcf_mux,
>> +
>> + &s4_vpu_0_sel,
>> + &s4_vpu_0_div,
>> + &s4_vpu_0,
>> + &s4_vpu_1_sel,
>> + &s4_vpu_1_div,
>> + &s4_vpu_1,
>> + &s4_vpu,
>> + &s4_vpu_clkb_tmp_mux,
>> + &s4_vpu_clkb_tmp_div,
>> + &s4_vpu_clkb_tmp,
>> + &s4_vpu_clkb_div,
>> + &s4_vpu_clkb,
>> + &s4_vpu_clkc_p0_mux,
>> + &s4_vpu_clkc_p0_div,
>> + &s4_vpu_clkc_p0,
>> + &s4_vpu_clkc_p1_mux,
>> + &s4_vpu_clkc_p1_div,
>> + &s4_vpu_clkc_p1,
>> + &s4_vpu_clkc_mux,
>> +
>> + &s4_vapb_0_sel,
>> + &s4_vapb_0_div,
>> + &s4_vapb_0,
>> + &s4_vapb_1_sel,
>> + &s4_vapb_1_div,
>> + &s4_vapb_1,
>> + &s4_vapb,
>> + &s4_ge2d_gate,
>> +
>> + &s4_hdcp22_esmclk_mux,
>> + &s4_hdcp22_esmclk_div,
>> + &s4_hdcp22_esmclk_gate,
>> + &s4_hdcp22_skpclk_mux,
>> + &s4_hdcp22_skpclk_div,
>> + &s4_hdcp22_skpclk_gate,
>> +
>> + &s4_vdin_meas_mux,
>> + &s4_vdin_meas_div,
>> + &s4_vdin_meas_gate,
>> +
>> + &s4_sd_emmc_c_clk0_sel,
>> + &s4_sd_emmc_c_clk0_div,
>> + &s4_sd_emmc_c_clk0,
>> + &s4_sd_emmc_a_clk0_sel,
>> + &s4_sd_emmc_a_clk0_div,
>> + &s4_sd_emmc_a_clk0,
>> + &s4_sd_emmc_b_clk0_sel,
>> + &s4_sd_emmc_b_clk0_div,
>> + &s4_sd_emmc_b_clk0,
>> +
>> + &s4_spicc0_mux,
>> + &s4_spicc0_div,
>> + &s4_spicc0_gate,
>> +
>> + &s4_pwm_a_mux,
>> + &s4_pwm_a_div,
>> + &s4_pwm_a_gate,
>> + &s4_pwm_b_mux,
>> + &s4_pwm_b_div,
>> + &s4_pwm_b_gate,
>> + &s4_pwm_c_mux,
>> + &s4_pwm_c_div,
>> + &s4_pwm_c_gate,
>> + &s4_pwm_d_mux,
>> + &s4_pwm_d_div,
>> + &s4_pwm_d_gate,
>> + &s4_pwm_e_mux,
>> + &s4_pwm_e_div,
>> + &s4_pwm_e_gate,
>> + &s4_pwm_f_mux,
>> + &s4_pwm_f_div,
>> + &s4_pwm_f_gate,
>> + &s4_pwm_g_mux,
>> + &s4_pwm_g_div,
>> + &s4_pwm_g_gate,
>> + &s4_pwm_h_mux,
>> + &s4_pwm_h_div,
>> + &s4_pwm_h_gate,
>> + &s4_pwm_i_mux,
>> + &s4_pwm_i_div,
>> + &s4_pwm_i_gate,
>> + &s4_pwm_j_mux,
>> + &s4_pwm_j_div,
>> + &s4_pwm_j_gate,
>> +
>> + &s4_saradc_mux,
>> + &s4_saradc_div,
>> + &s4_saradc_gate,
>> +
>> + &s4_gen_clk_sel,
>> + &s4_gen_clk_div,
>> + &s4_gen_clk,
>> +
>> + &s4_ddr,
>> + &s4_dos,
>> + &s4_ethphy,
>> + &s4_mali,
>> + &s4_aocpu,
>> + &s4_aucpu,
>> + &s4_cec,
>> + &s4_sdemmca,
>> + &s4_sdemmcb,
>> + &s4_nand,
>> + &s4_smartcard,
>> + &s4_acodec,
>> + &s4_spifc,
>> + &s4_msr_clk,
>> + &s4_ir_ctrl,
>> + &s4_audio,
>> + &s4_eth,
>> + &s4_uart_a,
>> + &s4_uart_b,
>> + &s4_uart_c,
>> + &s4_uart_d,
>> + &s4_uart_e,
>> + &s4_aififo,
>> + &s4_ts_ddr,
>> + &s4_ts_pll,
>> + &s4_g2d,
>> + &s4_spicc0,
>> + &s4_usb,
>> + &s4_i2c_m_a,
>> + &s4_i2c_m_b,
>> + &s4_i2c_m_c,
>> + &s4_i2c_m_d,
>> + &s4_i2c_m_e,
>> + &s4_hdmitx_apb,
>> + &s4_i2c_s_a,
>> + &s4_usb1_to_ddr,
>> + &s4_hdcp22,
>> + &s4_mmc_apb,
>> + &s4_rsa,
>> + &s4_cpu_debug,
>> + &s4_vpu_intr,
>> + &s4_demod,
>> + &s4_sar_adc,
>> + &s4_gic,
>> + &s4_pwm_ab,
>> + &s4_pwm_cd,
>> + &s4_pwm_ef,
>> + &s4_pwm_gh,
>> + &s4_pwm_ij,
>> + &s4_demod_core_clk_mux,
>> + &s4_demod_core_clk_div,
>> + &s4_demod_core_clk_gate,
>> + &s4_adc_extclk_in_mux,
>> + &s4_adc_extclk_in_div,
>> + &s4_adc_extclk_in_gate,
>> +
>> + &s4_fixed_pll_dco,
>> + &s4_fixed_pll,
>> + &s4_fclk_div2,
>> + &s4_fclk_div3,
>> + &s4_fclk_div4,
>> + &s4_fclk_div5,
>> + &s4_fclk_div7,
>> + &s4_fclk_div2p5,
>> + &s4_gp0_pll_dco,
>> + &s4_gp0_pll,
>> +
>> + &s4_hifi_pll_dco,
>> + &s4_hifi_pll,
>> + &s4_hdmi_pll_dco,
>> + &s4_hdmi_pll_od,
>> + &s4_hdmi_pll,
>> + &s4_mpll_50m,
>> + &s4_mpll0_div,
>> + &s4_mpll0,
>> + &s4_mpll1_div,
>> + &s4_mpll1,
>> + &s4_mpll2_div,
>> + &s4_mpll2,
>> + &s4_mpll3_div,
>> + &s4_mpll3,
>> +};
>> +
>> +static const struct reg_sequence s4_init_regs[] = {
>> + { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
>> +};
>> +
>> +static const struct meson_eeclkc_data s4_clkc_data = {
>> + .regmap_clks = s4_clk_regmaps,
>> + .regmap_clk_num = ARRAY_SIZE(s4_clk_regmaps),
>> + .hw_onecell_data = &s4_hw_onecell_data,
>> + .init_regs = s4_init_regs,
>> + .init_count = ARRAY_SIZE(s4_init_regs),
>> +};
>> +
>> +static const struct of_device_id clkc_match_table[] = {
>> + {
>> + .compatible = "amlogic,s4-clkc",
>> + .data = &s4_clkc_data
>> + },
>> + {}
>> +};
>> +
>> +static struct platform_driver s4_driver = {
>> + .probe = meson_eeclkc_probe,
>> + .driver = {
>> + .name = "s4-clkc",
>> + .of_match_table = clkc_match_table,
>> + },
>> +};
>> +
>> +module_platform_driver(s4_driver);
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/clk/meson/s4.h b/drivers/clk/meson/s4.h
>> new file mode 100644
>> index 000000000000..d5563dcbd52e
>> --- /dev/null
>> +++ b/drivers/clk/meson/s4.h
>> @@ -0,0 +1,156 @@
>> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
>> +/*
>> + * Copyright (c) 2021 Amlogic, inc.
>> + * Author: Yu Tu <yu.tu@amlogic.com>
>> + */
>> +
>> +#ifndef __S4_H
>> +#define __S4_H
>> +
>> +/*
>> + * Clock controller register offsets
>> + * REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
>> + */
>> +#define CLKCTRL_OSCIN_CTRL ((0x0001 << 2))
>
> No need for double ((
I will correct it.
>
>> +#define CLKCTRL_RTC_BY_OSCIN_CTRL0 ((0x0002 << 2))
>> +#define CLKCTRL_RTC_BY_OSCIN_CTRL1 ((0x0003 << 2))
>
>
>
> Best regards,
> Krzysztof
>
> .
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver
2022-07-19 6:02 ` Yu Tu
@ 2022-07-19 6:29 ` Krzysztof Kozlowski
2022-07-19 6:58 ` Yu Tu
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-19 6:29 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
On 19/07/2022 08:02, Yu Tu wrote:
> Hi Krzysztof,
> Thank you for your advice.
>
> On 2022/7/12 17:44, Krzysztof Kozlowski wrote:
>> [ EXTERNAL EMAIL ]
>>
>> On 08/07/2022 08:27, Yu Tu wrote:
>>> Add the peripheral clock controller found in the s4 SoC family.
>>>
>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>> ---
>>> MAINTAINERS | 2 +-
>>> drivers/clk/meson/Kconfig | 17 +
>>> drivers/clk/meson/Makefile | 1 +
>>> drivers/clk/meson/s4.c | 4678 ++++++++++++++++++++++++++++++++++++
>>> drivers/clk/meson/s4.h | 156 ++
>>> 5 files changed, 4853 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/clk/meson/s4.c
>>> create mode 100644 drivers/clk/meson/s4.h
>>>
>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>> index e4ca46c5c8a1..f116ec0642f2 100644
>>> --- a/MAINTAINERS
>>> +++ b/MAINTAINERS
>>> @@ -1772,7 +1772,7 @@ M: Jerome Brunet <jbrunet@baylibre.com>
>>> L: linux-amlogic@lists.infradead.org
>>> S: Maintained
>>> F: Documentation/devicetree/bindings/clock/amlogic*
>>> -F: drivers/clk/meson/
>>> +F: drivers/clk/meson/*
>>
>> Why?
> Warning is displayed when using checkpatch. I will correct it.
What warning?
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver
2022-07-19 6:29 ` Krzysztof Kozlowski
@ 2022-07-19 6:58 ` Yu Tu
2022-07-19 7:29 ` Krzysztof Kozlowski
0 siblings, 1 reply; 15+ messages in thread
From: Yu Tu @ 2022-07-19 6:58 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
Hi Krzysztof,
Thank you very much for your prompt reply.
On 2022/7/19 14:29, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 19/07/2022 08:02, Yu Tu wrote:
>> Hi Krzysztof,
>> Thank you for your advice.
>>
>> On 2022/7/12 17:44, Krzysztof Kozlowski wrote:
>>> [ EXTERNAL EMAIL ]
>>>
>>> On 08/07/2022 08:27, Yu Tu wrote:
>>>> Add the peripheral clock controller found in the s4 SoC family.
>>>>
>>>> Signed-off-by: Yu Tu <yu.tu@amlogic.com>
>>>> ---
>>>> MAINTAINERS | 2 +-
>>>> drivers/clk/meson/Kconfig | 17 +
>>>> drivers/clk/meson/Makefile | 1 +
>>>> drivers/clk/meson/s4.c | 4678 ++++++++++++++++++++++++++++++++++++
>>>> drivers/clk/meson/s4.h | 156 ++
>>>> 5 files changed, 4853 insertions(+), 1 deletion(-)
>>>> create mode 100644 drivers/clk/meson/s4.c
>>>> create mode 100644 drivers/clk/meson/s4.h
>>>>
>>>> diff --git a/MAINTAINERS b/MAINTAINERS
>>>> index e4ca46c5c8a1..f116ec0642f2 100644
>>>> --- a/MAINTAINERS
>>>> +++ b/MAINTAINERS
>>>> @@ -1772,7 +1772,7 @@ M: Jerome Brunet <jbrunet@baylibre.com>
>>>> L: linux-amlogic@lists.infradead.org
>>>> S: Maintained
>>>> F: Documentation/devicetree/bindings/clock/amlogic*
>>>> -F: drivers/clk/meson/
>>>> +F: drivers/clk/meson/*
>>>
>>> Why?
>> Warning is displayed when using checkpatch. I will correct it.
>
> What warning?
./scripts/checkpatch.pl --strict
0001-clk-meson-s4-add-s4-SoC-clock-controller-driver.patch
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
If I add that strange change, I won't have this WARNING.
Should I ignore this warning?
>
> Best regards,
> Krzysztof
>
> .
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver
2022-07-19 6:58 ` Yu Tu
@ 2022-07-19 7:29 ` Krzysztof Kozlowski
2022-07-19 7:33 ` Yu Tu
0 siblings, 1 reply; 15+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-19 7:29 UTC (permalink / raw)
To: Yu Tu, linux-clk, linux-arm-kernel, linux-amlogic, linux-kernel,
devicetree, Rob Herring, Neil Armstrong, Jerome Brunet,
Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
On 19/07/2022 08:58, Yu Tu wrote:
>>>>> @@ -1772,7 +1772,7 @@ M: Jerome Brunet <jbrunet@baylibre.com>
>>>>> L: linux-amlogic@lists.infradead.org
>>>>> S: Maintained
>>>>> F: Documentation/devicetree/bindings/clock/amlogic*
>>>>> -F: drivers/clk/meson/
>>>>> +F: drivers/clk/meson/*
>>>>
>>>> Why?
>>> Warning is displayed when using checkpatch. I will correct it.
>>
>> What warning?
> ./scripts/checkpatch.pl --strict
> 0001-clk-meson-s4-add-s4-SoC-clock-controller-driver.patch
> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
> If I add that strange change, I won't have this WARNING.
> Should I ignore this warning?
Yes, it's not related to the patch and the change you made looks not
correct.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver
2022-07-19 7:29 ` Krzysztof Kozlowski
@ 2022-07-19 7:33 ` Yu Tu
0 siblings, 0 replies; 15+ messages in thread
From: Yu Tu @ 2022-07-19 7:33 UTC (permalink / raw)
To: Krzysztof Kozlowski, linux-clk, linux-arm-kernel, linux-amlogic,
linux-kernel, devicetree, Rob Herring, Neil Armstrong,
Jerome Brunet, Kevin Hilman, Michael Turquette, Stephen Boyd,
Krzysztof Kozlowski, Martin Blumenstingl
On 2022/7/19 15:29, Krzysztof Kozlowski wrote:
> [ EXTERNAL EMAIL ]
>
> On 19/07/2022 08:58, Yu Tu wrote:
>>>>>> @@ -1772,7 +1772,7 @@ M: Jerome Brunet <jbrunet@baylibre.com>
>>>>>> L: linux-amlogic@lists.infradead.org
>>>>>> S: Maintained
>>>>>> F: Documentation/devicetree/bindings/clock/amlogic*
>>>>>> -F: drivers/clk/meson/
>>>>>> +F: drivers/clk/meson/*
>>>>>
>>>>> Why?
>>>> Warning is displayed when using checkpatch. I will correct it.
>>>
>>> What warning?
>> ./scripts/checkpatch.pl --strict
>> 0001-clk-meson-s4-add-s4-SoC-clock-controller-driver.patch
>> WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
>> If I add that strange change, I won't have this WARNING.
>> Should I ignore this warning?
>
> Yes, it's not related to the patch and the change you made looks not
> correct.
Thank you very much for your suggestion and I will correct it in the
next patch.
>
>
> Best regards,
> Krzysztof
>
> .
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-07-19 7:34 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-08 6:27 [PATCH 0/3] Add S4 SoC clock controller driver Yu Tu
2022-07-08 6:27 ` [PATCH 1/3] dt-bindings: clk: meson: add S4 SoC clock controller bindings Yu Tu
2022-07-11 12:25 ` Jerome Brunet
2022-07-19 5:30 ` Yu Tu
2022-07-12 9:40 ` Krzysztof Kozlowski
2022-07-19 5:55 ` Yu Tu
2022-07-08 6:27 ` [PATCH 2/3] arm64: dts: meson: add S4 Soc clock controller in DT Yu Tu
2022-07-12 9:41 ` Krzysztof Kozlowski
2022-07-19 5:57 ` Yu Tu
[not found] ` <20220708062757.3662-4-yu.tu@amlogic.com>
2022-07-12 9:44 ` [PATCH 3/3] clk: meson: s4: add s4 SoC clock controller driver Krzysztof Kozlowski
2022-07-19 6:02 ` Yu Tu
2022-07-19 6:29 ` Krzysztof Kozlowski
2022-07-19 6:58 ` Yu Tu
2022-07-19 7:29 ` Krzysztof Kozlowski
2022-07-19 7:33 ` Yu Tu
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