* [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs
@ 2020-06-17 16:48 Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 01/11] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Manivannan Sadhasivam, Philipp Zabel
Cc: devicetree, Stephen Boyd, Michael Turquette, linux-actions,
linux-kernel, linux-clk, linux-arm-kernel
This patch series improves the existing implementation of the Clock
Management Unit for the Actions Semi S500 SoC, by adding support for
some missing clocks, like DMAC and GPIO.
Additionally, it enables the UART nodes in the common owl-s500 DTS to
use the clock provided by the CMU. That means the S500 based SBCs can
now get rid of their (fake) UART fixed clock and, as a matter of fact,
this has been already done here for RoseapplePi, the new board which
is going to be supported (hopefully) via the following patchset:
https://lore.kernel.org/lkml/cover.1592123160.git.cristian.ciocaltea@gmail.com/
Eventually, the patchset adds support for the Actions Semi S500 SoC's
DMA controller and Reset Management Unit. Please note the already
existing Actions Semi Owl SoCs DMA driver seems to be fully compatible
with S500, even though this is not explicitly mentioned in the source
code. For the moment, I have just enabled the DMA controller node in
owl-s500 DTS using the "actions,s900-dma" compatible string.
In the upcoming patch series I will provide a pinctrl driver and enable
access to MMC and I2C.
Thanks,
Cristi
Cristian Ciocaltea (11):
clk: actions: Fix h_clk for Actions S500 SoC
arm: dts: owl-s500: Add Clock Management Unit
arm: dts: owl-s500: Set UART clock refs from CMU
arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
arm: dts: owl-s500: Add DMA controller
dt-bindings: reset: Add binding constants for Actions S500 RMU
clk: actions: Add Actions S500 SoC Reset Management Unit support
arm: dts: owl-s500: Add Reset Controller support
MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs
MAINTAINERS | 1 +
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 --
arch/arm/boot/dts/owl-s500.dtsi | 37 ++++++++
drivers/clk/actions/owl-s500.c | 91 ++++++++++++++++++-
include/dt-bindings/clock/actions,s500-cmu.h | 77 ++++++++--------
.../dt-bindings/reset/actions,s500-reset.h | 67 ++++++++++++++
6 files changed, 235 insertions(+), 45 deletions(-)
create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
--
2.27.0
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 01/11] clk: actions: Fix h_clk for Actions S500 SoC
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 02/11] arm: dts: owl-s500: Add Clock Management Unit Cristian Ciocaltea
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Andreas Färber, Manivannan Sadhasivam
Cc: Stephen Boyd, Michael Turquette, linux-actions, linux-kernel,
linux-clk, linux-arm-kernel
The h_clk clock in the Actions Semi S500 SoC clock driver has an
invalid parent. Replace with the correct one.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
drivers/clk/actions/owl-s500.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index e2007ac4d235..0eb83a0b70bc 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
-static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
--
2.27.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 02/11] arm: dts: owl-s500: Add Clock Management Unit
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 01/11] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 03/11] arm: dts: owl-s500: Set UART clock refs from CMU Cristian Ciocaltea
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Manivannan Sadhasivam
Cc: devicetree, linux-actions, linux-kernel, linux-arm-kernel
Add Clock Management Unit for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 1dbe4e8b38ac..5d5ad9db549b 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -5,6 +5,7 @@
* Copyright (c) 2016-2017 Andreas Färber
*/
+#include <dt-bindings/clock/actions,s500-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/owl-s500-powergate.h>
@@ -70,6 +71,12 @@ hosc: hosc {
#clock-cells = <0>;
};
+ losc: losc {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
soc {
compatible = "simple-bus";
#address-cells = <1>;
@@ -169,6 +176,13 @@ uart6: serial@b012c000 {
status = "disabled";
};
+ cmu: clock-controller@b0160000 {
+ compatible = "actions,s500-cmu";
+ reg = <0xb0160000 0x8000>;
+ clocks = <&hosc>, <&losc>;
+ #clock-cells = <1>;
+ };
+
timer: timer@b0168000 {
compatible = "actions,s500-timer";
reg = <0xb0168000 0x8000>;
--
2.27.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 03/11] arm: dts: owl-s500: Set UART clock refs from CMU
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 01/11] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 02/11] arm: dts: owl-s500: Add Clock Management Unit Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 04/11] arm: dts: owl-s500-roseapplepi: Use UART clock " Cristian Ciocaltea
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Manivannan Sadhasivam
Cc: devicetree, linux-actions, linux-kernel, linux-arm-kernel
Enable using Clock Management Unit clocks for every UART node
of the Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
arch/arm/boot/dts/owl-s500.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 5d5ad9db549b..ac3d04c75dd5 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -131,6 +131,7 @@ uart0: serial@b0120000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0120000 0x2000>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART0>;
status = "disabled";
};
@@ -138,6 +139,7 @@ uart1: serial@b0122000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0122000 0x2000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART1>;
status = "disabled";
};
@@ -145,6 +147,7 @@ uart2: serial@b0124000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0124000 0x2000>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART2>;
status = "disabled";
};
@@ -152,6 +155,7 @@ uart3: serial@b0126000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0126000 0x2000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART3>;
status = "disabled";
};
@@ -159,6 +163,7 @@ uart4: serial@b0128000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb0128000 0x2000>;
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART4>;
status = "disabled";
};
@@ -166,6 +171,7 @@ uart5: serial@b012a000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb012a000 0x2000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART5>;
status = "disabled";
};
@@ -173,6 +179,7 @@ uart6: serial@b012c000 {
compatible = "actions,s500-uart", "actions,owl-uart";
reg = <0xb012c000 0x2000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cmu CLK_UART6>;
status = "disabled";
};
--
2.27.0
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 04/11] arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
` (2 preceding siblings ...)
2020-06-17 16:48 ` [PATCH 03/11] arm: dts: owl-s500: Set UART clock refs from CMU Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 06/11] clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC Cristian Ciocaltea
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Manivannan Sadhasivam
Cc: devicetree, linux-actions, linux-kernel, linux-arm-kernel
Remove the UART fixed clock and enable using the one provided by CMU.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 -------
1 file changed, 7 deletions(-)
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
index a2087e617cb2..800edf5d2d12 100644
--- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts
+++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts
@@ -25,12 +25,6 @@ memory@0 {
device_type = "memory";
reg = <0x0 0x80000000>; /* 2GB */
};
-
- uart2_clk: uart2-clk {
- compatible = "fixed-clock";
- clock-frequency = <921600>;
- #clock-cells = <0>;
- };
};
&twd_timer {
@@ -43,5 +37,4 @@ &timer {
&uart2 {
status = "okay";
- clocks = <&uart2_clk>;
};
--
2.27.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 06/11] clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
` (3 preceding siblings ...)
2020-06-17 16:48 ` [PATCH 04/11] arm: dts: owl-s500-roseapplepi: Use UART clock " Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 07/11] arm: dts: owl-s500: Add DMA controller Cristian Ciocaltea
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Andreas Färber, Manivannan Sadhasivam
Cc: Stephen Boyd, Michael Turquette, linux-actions, linux-kernel,
linux-clk, linux-arm-kernel
Add support for the missing APB, DMAC and GPIO clocks in the Actions
Semi S500 SoC clock driver.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
drivers/clk/actions/owl-s500.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 0eb83a0b70bc..025a8f6d6482 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -175,6 +175,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
/* gate clocks */
+static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
+static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
@@ -184,6 +186,7 @@ static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
/* divider clocks */
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
+static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
/* factor clocks */
@@ -428,6 +431,9 @@ static struct owl_clk_common *s500_clks[] = {
&spdif_clk.common,
&nand_clk.common,
&ecc_clk.common,
+ &apb_clk.common,
+ &dmac_clk.common,
+ &gpio_clk.common,
};
static struct clk_hw_onecell_data s500_hw_clks = {
@@ -484,6 +490,9 @@ static struct clk_hw_onecell_data s500_hw_clks = {
[CLK_SPDIF] = &spdif_clk.common.hw,
[CLK_NAND] = &nand_clk.common.hw,
[CLK_ECC] = &ecc_clk.common.hw,
+ [CLK_APB] = &apb_clk.common.hw,
+ [CLK_DMAC] = &dmac_clk.common.hw,
+ [CLK_GPIO] = &gpio_clk.common.hw,
},
.num = CLK_NR_CLKS,
};
--
2.27.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 07/11] arm: dts: owl-s500: Add DMA controller
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
` (4 preceding siblings ...)
2020-06-17 16:48 ` [PATCH 06/11] clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 08/11] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Manivannan Sadhasivam
Cc: devicetree, linux-actions, linux-kernel, linux-arm-kernel
Add DMA controller node for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
arch/arm/boot/dts/owl-s500.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index ac3d04c75dd5..0f4fc5487dad 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -205,5 +205,19 @@ sps: power-controller@b01b0100 {
reg = <0xb01b0100 0x100>;
#power-domain-cells = <1>;
};
+
+ dma: dma-controller@b0260000 {
+ compatible = "actions,s900-dma";
+ reg = <0xb0260000 0xd00>;
+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ dma-channels = <12>;
+ dma-requests = <46>;
+ clocks = <&cmu CLK_DMAC>;
+ power-domains = <&sps S500_PD_DMA>;
+ };
};
};
--
2.27.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 08/11] dt-bindings: reset: Add binding constants for Actions S500 RMU
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
` (5 preceding siblings ...)
2020-06-17 16:48 ` [PATCH 07/11] arm: dts: owl-s500: Add DMA controller Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 09/11] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 10/11] arm: dts: owl-s500: Add Reset Controller support Cristian Ciocaltea
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Andreas Färber, Manivannan Sadhasivam, Philipp Zabel
Cc: devicetree, Rob Herring, linux-actions, linux-kernel, linux-arm-kernel
Add device tree binding constants for Actions Semi S500 SoC Reset
Management Unit (RMU).
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
.../dt-bindings/reset/actions,s500-reset.h | 67 +++++++++++++++++++
1 file changed, 67 insertions(+)
create mode 100644 include/dt-bindings/reset/actions,s500-reset.h
diff --git a/include/dt-bindings/reset/actions,s500-reset.h b/include/dt-bindings/reset/actions,s500-reset.h
new file mode 100644
index 000000000000..f5d94176d10b
--- /dev/null
+++ b/include/dt-bindings/reset/actions,s500-reset.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Device Tree binding constants for Actions Semi S500 Reset Management Unit
+ *
+ * Copyright (c) 2014 Actions Semi Inc.
+ * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
+ */
+
+#ifndef __DT_BINDINGS_ACTIONS_S500_RESET_H
+#define __DT_BINDINGS_ACTIONS_S500_RESET_H
+
+#define RESET_DMAC 0
+#define RESET_NORIF 1
+#define RESET_DDR 2
+#define RESET_NANDC 3
+#define RESET_SD0 4
+#define RESET_SD1 5
+#define RESET_PCM1 6
+#define RESET_DE 7
+#define RESET_LCD 8
+#define RESET_SD2 9
+#define RESET_DSI 10
+#define RESET_CSI 11
+#define RESET_BISP 12
+#define RESET_KEY 13
+#define RESET_GPIO 14
+#define RESET_AUDIO 15
+#define RESET_PCM0 16
+#define RESET_VDE 17
+#define RESET_VCE 18
+#define RESET_GPU3D 19
+#define RESET_NIC301 20
+#define RESET_LENS 21
+#define RESET_PERIPHRESET 22
+#define RESET_USB2_0 23
+#define RESET_TVOUT 24
+#define RESET_HDMI 25
+#define RESET_HDCP2TX 26
+#define RESET_UART6 27
+#define RESET_UART0 28
+#define RESET_UART1 29
+#define RESET_UART2 30
+#define RESET_SPI0 31
+#define RESET_SPI1 32
+#define RESET_SPI2 33
+#define RESET_SPI3 34
+#define RESET_I2C0 35
+#define RESET_I2C1 36
+#define RESET_USB3 37
+#define RESET_UART3 38
+#define RESET_UART4 39
+#define RESET_UART5 40
+#define RESET_I2C2 41
+#define RESET_I2C3 42
+#define RESET_ETHERNET 43
+#define RESET_CHIPID 44
+#define RESET_USB2_1 45
+#define RESET_WD0RESET 46
+#define RESET_WD1RESET 47
+#define RESET_WD2RESET 48
+#define RESET_WD3RESET 49
+#define RESET_DBG0RESET 50
+#define RESET_DBG1RESET 51
+#define RESET_DBG2RESET 52
+#define RESET_DBG3RESET 53
+
+#endif /* __DT_BINDINGS_ACTIONS_S500_RESET_H */
--
2.27.0
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^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 09/11] clk: actions: Add Actions S500 SoC Reset Management Unit support
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
` (6 preceding siblings ...)
2020-06-17 16:48 ` [PATCH 08/11] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 10/11] arm: dts: owl-s500: Add Reset Controller support Cristian Ciocaltea
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Andreas Färber, Manivannan Sadhasivam, Philipp Zabel
Cc: Stephen Boyd, Michael Turquette, linux-actions, linux-kernel,
linux-clk, linux-arm-kernel
Add Reset Management Unit (RMU) support for Actions Semi S500 SoC.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
drivers/clk/actions/owl-s500.c | 80 ++++++++++++++++++++++++++++++++++
1 file changed, 80 insertions(+)
diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
index 025a8f6d6482..3bce72301c65 100644
--- a/drivers/clk/actions/owl-s500.c
+++ b/drivers/clk/actions/owl-s500.c
@@ -10,6 +10,8 @@
*
* Copyright (c) 2018 LSI-TEC - Caninos Loucos
* Author: Edgar Bernardi Righi <edgar.righi@lsitec.org.br>
+ *
+ * Copyright (c) 2020 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
*/
#include <linux/clk-provider.h>
@@ -23,8 +25,10 @@
#include "owl-gate.h"
#include "owl-mux.h"
#include "owl-pll.h"
+#include "owl-reset.h"
#include <dt-bindings/clock/actions,s500-cmu.h>
+#include <dt-bindings/reset/actions,s500-reset.h>
#define CMU_COREPLL (0x0000)
#define CMU_DEVPLL (0x0004)
@@ -497,20 +501,96 @@ static struct clk_hw_onecell_data s500_hw_clks = {
.num = CLK_NR_CLKS,
};
+static const struct owl_reset_map s500_resets[] = {
+ [RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
+ [RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
+ [RESET_DDR] = { CMU_DEVRST0, BIT(2) },
+ [RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
+ [RESET_SD0] = { CMU_DEVRST0, BIT(4) },
+ [RESET_SD1] = { CMU_DEVRST0, BIT(5) },
+ [RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
+ [RESET_DE] = { CMU_DEVRST0, BIT(7) },
+ [RESET_LCD] = { CMU_DEVRST0, BIT(8) },
+ [RESET_SD2] = { CMU_DEVRST0, BIT(9) },
+ [RESET_DSI] = { CMU_DEVRST0, BIT(10) },
+ [RESET_CSI] = { CMU_DEVRST0, BIT(11) },
+ [RESET_BISP] = { CMU_DEVRST0, BIT(12) },
+ [RESET_KEY] = { CMU_DEVRST0, BIT(14) },
+ [RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
+ [RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
+ [RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
+ [RESET_VDE] = { CMU_DEVRST0, BIT(19) },
+ [RESET_VCE] = { CMU_DEVRST0, BIT(20) },
+ [RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
+ [RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
+ [RESET_LENS] = { CMU_DEVRST0, BIT(26) },
+ [RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
+ [RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
+ [RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
+ [RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
+ [RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
+ [RESET_UART6] = { CMU_DEVRST1, BIT(4) },
+ [RESET_UART0] = { CMU_DEVRST1, BIT(5) },
+ [RESET_UART1] = { CMU_DEVRST1, BIT(6) },
+ [RESET_UART2] = { CMU_DEVRST1, BIT(7) },
+ [RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
+ [RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
+ [RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
+ [RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
+ [RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
+ [RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
+ [RESET_USB3] = { CMU_DEVRST1, BIT(14) },
+ [RESET_UART3] = { CMU_DEVRST1, BIT(15) },
+ [RESET_UART4] = { CMU_DEVRST1, BIT(16) },
+ [RESET_UART5] = { CMU_DEVRST1, BIT(17) },
+ [RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
+ [RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
+ [RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
+ [RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
+ [RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
+ [RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
+ [RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
+ [RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
+ [RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
+ [RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
+ [RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
+ [RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
+ [RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
+};
+
static struct owl_clk_desc s500_clk_desc = {
.clks = s500_clks,
.num_clks = ARRAY_SIZE(s500_clks),
.hw_clks = &s500_hw_clks,
+
+ .resets = s500_resets,
+ .num_resets = ARRAY_SIZE(s500_resets),
};
static int s500_clk_probe(struct platform_device *pdev)
{
struct owl_clk_desc *desc;
+ struct owl_reset *reset;
+ int ret;
desc = &s500_clk_desc;
owl_clk_regmap_init(pdev, desc);
+ reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
+ if (!reset)
+ return -ENOMEM;
+
+ reset->rcdev.of_node = pdev->dev.of_node;
+ reset->rcdev.ops = &owl_reset_ops;
+ reset->rcdev.nr_resets = desc->num_resets;
+ reset->reset_map = desc->resets;
+ reset->regmap = desc->regmap;
+
+ ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
+ if (ret)
+ dev_err(&pdev->dev, "Failed to register reset controller\n");
+
return owl_clk_probe(&pdev->dev, desc->hw_clks);
}
--
2.27.0
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 10/11] arm: dts: owl-s500: Add Reset Controller support
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
` (7 preceding siblings ...)
2020-06-17 16:48 ` [PATCH 09/11] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
@ 2020-06-17 16:48 ` Cristian Ciocaltea
8 siblings, 0 replies; 10+ messages in thread
From: Cristian Ciocaltea @ 2020-06-17 16:48 UTC (permalink / raw)
To: Rob Herring, Andreas Färber, Manivannan Sadhasivam
Cc: devicetree, linux-actions, linux-kernel, linux-arm-kernel
Add reset controller property and bindings header for the
Actions Semi S500 SoC DTS.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
---
arch/arm/boot/dts/owl-s500.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/owl-s500.dtsi b/arch/arm/boot/dts/owl-s500.dtsi
index 0f4fc5487dad..0b7ba2926f0e 100644
--- a/arch/arm/boot/dts/owl-s500.dtsi
+++ b/arch/arm/boot/dts/owl-s500.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/actions,s500-cmu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/owl-s500-powergate.h>
+#include <dt-bindings/reset/actions,s500-reset.h>
/ {
compatible = "actions,s500";
@@ -188,6 +189,7 @@ cmu: clock-controller@b0160000 {
reg = <0xb0160000 0x8000>;
clocks = <&hosc>, <&losc>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
timer: timer@b0168000 {
--
2.27.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-06-17 16:51 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-17 16:48 [PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 01/11] clk: actions: Fix h_clk for Actions S500 SoC Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 02/11] arm: dts: owl-s500: Add Clock Management Unit Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 03/11] arm: dts: owl-s500: Set UART clock refs from CMU Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 04/11] arm: dts: owl-s500-roseapplepi: Use UART clock " Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 06/11] clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 07/11] arm: dts: owl-s500: Add DMA controller Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 08/11] dt-bindings: reset: Add binding constants for Actions S500 RMU Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 09/11] clk: actions: Add Actions S500 SoC Reset Management Unit support Cristian Ciocaltea
2020-06-17 16:48 ` [PATCH 10/11] arm: dts: owl-s500: Add Reset Controller support Cristian Ciocaltea
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