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* [PATCH] phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED
@ 2022-03-12  1:38 Marek Vasut
  2022-03-14  1:51 ` Hongxing Zhu
  2022-04-13  9:36 ` Vinod Koul
  0 siblings, 2 replies; 8+ messages in thread
From: Marek Vasut @ 2022-03-12  1:38 UTC (permalink / raw)
  To: linux-phy
  Cc: Marek Vasut, Fabio Estevam, Kishon Vijay Abraham I,
	Marcel Ziswiler, NXP Linux Team, Peng Fan, Richard Zhu,
	Shawn Guo, Vinod Koul, linux-arm-kernel

The 'fsl,refclk-pad-mode' DT property used to select clock source for
PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
two options are handled correctly by the driver, the last one is not,
this patch implements support for the last option.

The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
internal PLL and output to PCIE_RESREF external IO pin. The last
IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
clock are sourced from SoC internal PLL and not output anywhere.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Vinod Koul <vkoul@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
To: linux-phy@lists.infradead.org
---
 drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
index e56954063108c..7d8e6991279f4 100644
--- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
+++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c
@@ -156,15 +156,21 @@ static int imx8_pcie_phy_init(struct phy *phy)
 		break;
 	}
 
-	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT) {
+	if (pad_mode == IMX8_PCIE_REFCLK_PAD_INPUT ||
+	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
 		/* Configure the pad as input */
 		val = readl(imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
 		writel(val & ~ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
-	} else if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT) {
+	} else {
 		/* Configure the PHY to output the refclock via pad */
 		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_EN,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG061);
+	}
+
+	if (pad_mode == IMX8_PCIE_REFCLK_PAD_OUTPUT ||
+	    pad_mode == IMX8_PCIE_REFCLK_PAD_UNUSED) {
+		/* Source clock from SoC internal PLL */
 		writel(ANA_PLL_CLK_OUT_TO_EXT_IO_SEL,
 		       imx8_phy->base + IMX8MM_PCIE_PHY_CMN_REG062);
 		writel(AUX_PLL_REFCLK_SEL_SYS_PLL,
-- 
2.34.1


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^ permalink raw reply related	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2022-04-13 14:09 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-12  1:38 [PATCH] phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED Marek Vasut
2022-03-14  1:51 ` Hongxing Zhu
2022-03-14  2:51   ` Marek Vasut
2022-03-14  3:29     ` Hongxing Zhu
2022-03-14 10:52       ` Marek Vasut
2022-03-15  0:15         ` Hongxing Zhu
2022-04-13  9:36 ` Vinod Koul
2022-04-13 14:08   ` Marek Vasut

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