* [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl
@ 2022-11-02 12:46 Jagan Teki
2022-11-02 12:46 ` [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Jagan Teki @ 2022-11-02 12:46 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Add pinctrl definitions for Rockchip RV1126.
From RK3568 on-wards pinctrl configurations are maintained
in common conf file rockchip-pinconf.dtsi and it is available
in arm64 path (arch/arm64/boot/dts/rockchip/rockchip-pinconf.dtsi).
So, include the same conf file to RV1126 pinctrl from arm64 path.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v6:
- updated commit message
Changes for v5:
- none
Changes for v4:
- update i2c pins
- rebase on -next
Changes for v3:
- none
Changes for v2:
- spilt pinctrl as separate patch
MAINTAINERS | 2 +-
arch/arm/boot/dts/rv1126-pinctrl.dtsi | 212 ++++++++++++++++++++++++++
2 files changed, 213 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rv1126-pinctrl.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 5f66378dcfb0..4fd0fa773209 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2750,7 +2750,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml
F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml
F: arch/arm/boot/dts/rk3*
-F: arch/arm/boot/dts/rv1108*
+F: arch/arm/boot/dts/rv11*
F: arch/arm/mach-rockchip/
F: drivers/*/*/*rockchip*
F: drivers/*/*rockchip*
diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
new file mode 100644
index 000000000000..8d660d7c81ba
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <arm64/rockchip/rockchip-pinconf.dtsi>
+
+/*
+ * This file is auto generated by pin2dts tool, please keep these code
+ * by adding changes at end of this file.
+ */
+&pinctrl {
+ emmc {
+ /omit-if-no-ref/
+ emmc_rstnout: emmc-rstnout {
+ rockchip,pins =
+ /* emmc_rstn */
+ <1 RK_PA3 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ emmc_bus8: emmc-bus8 {
+ rockchip,pins =
+ /* emmc_d0 */
+ <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d1 */
+ <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d2 */
+ <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d3 */
+ <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d4 */
+ <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d5 */
+ <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d6 */
+ <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
+ /* emmc_d7 */
+ <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_clk: emmc-clk {
+ rockchip,pins =
+ /* emmc_clko */
+ <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ emmc_cmd: emmc-cmd {
+ rockchip,pins =
+ /* emmc_cmd */
+ <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>;
+ };
+ };
+ i2c0 {
+ /omit-if-no-ref/
+ i2c0_xfer: i2c0-xfer {
+ rockchip,pins =
+ /* i2c0_scl */
+ <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>,
+ /* i2c0_sda */
+ <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>;
+ };
+ };
+ sdmmc0 {
+ /omit-if-no-ref/
+ sdmmc0_bus4: sdmmc0-bus4 {
+ rockchip,pins =
+ /* sdmmc0_d0 */
+ <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d1 */
+ <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d2 */
+ <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc0_d3 */
+ <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_clk: sdmmc0-clk {
+ rockchip,pins =
+ /* sdmmc0_clk */
+ <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_cmd: sdmmc0-cmd {
+ rockchip,pins =
+ /* sdmmc0_cmd */
+ <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_det: sdmmc0-det {
+ rockchip,pins =
+ <0 RK_PA3 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc0_pwr: sdmmc0-pwr {
+ rockchip,pins =
+ <0 RK_PC0 1 &pcfg_pull_none>;
+ };
+ };
+ sdmmc1 {
+ /omit-if-no-ref/
+ sdmmc1_bus4: sdmmc1-bus4 {
+ rockchip,pins =
+ /* sdmmc1_d0 */
+ <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d1 */
+ <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d2 */
+ <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>,
+ /* sdmmc1_d3 */
+ <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_clk: sdmmc1-clk {
+ rockchip,pins =
+ /* sdmmc1_clk */
+ <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_cmd: sdmmc1-cmd {
+ rockchip,pins =
+ /* sdmmc1_cmd */
+ <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_det: sdmmc1-det {
+ rockchip,pins =
+ <1 RK_PD0 2 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ sdmmc1_pwr: sdmmc1-pwr {
+ rockchip,pins =
+ <1 RK_PD1 2 &pcfg_pull_none>;
+ };
+ };
+ uart0 {
+ /omit-if-no-ref/
+ uart0_xfer: uart0-xfer {
+ rockchip,pins =
+ /* uart0_rx */
+ <1 RK_PC2 1 &pcfg_pull_up>,
+ /* uart0_tx */
+ <1 RK_PC3 1 &pcfg_pull_up>;
+ };
+ /omit-if-no-ref/
+ uart0_ctsn: uart0-ctsn {
+ rockchip,pins =
+ <1 RK_PC1 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn: uart0-rtsn {
+ rockchip,pins =
+ <1 RK_PC0 1 &pcfg_pull_none>;
+ };
+ /omit-if-no-ref/
+ uart0_rtsn_gpio: uart0-rts-pin {
+ rockchip,pins =
+ <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+ uart1 {
+ /omit-if-no-ref/
+ uart1m0_xfer: uart1m0-xfer {
+ rockchip,pins =
+ /* uart1_rx_m0 */
+ <0 RK_PB7 2 &pcfg_pull_up>,
+ /* uart1_tx_m0 */
+ <0 RK_PB6 2 &pcfg_pull_up>;
+ };
+ };
+ uart2 {
+ /omit-if-no-ref/
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins =
+ /* uart2_rx_m1 */
+ <3 RK_PA3 1 &pcfg_pull_up>,
+ /* uart2_tx_m1 */
+ <3 RK_PA2 1 &pcfg_pull_up>;
+ };
+ };
+ uart3 {
+ /omit-if-no-ref/
+ uart3m0_xfer: uart3m0-xfer {
+ rockchip,pins =
+ /* uart3_rx_m0 */
+ <3 RK_PC7 4 &pcfg_pull_up>,
+ /* uart3_tx_m0 */
+ <3 RK_PC6 4 &pcfg_pull_up>;
+ };
+ };
+ uart4 {
+ /omit-if-no-ref/
+ uart4m0_xfer: uart4m0-xfer {
+ rockchip,pins =
+ /* uart4_rx_m0 */
+ <3 RK_PA5 4 &pcfg_pull_up>,
+ /* uart4_tx_m0 */
+ <3 RK_PA4 4 &pcfg_pull_up>;
+ };
+ };
+ uart5 {
+ /omit-if-no-ref/
+ uart5m0_xfer: uart5m0-xfer {
+ rockchip,pins =
+ /* uart5_rx_m0 */
+ <3 RK_PA7 4 &pcfg_pull_up>,
+ /* uart5_tx_m0 */
+ <3 RK_PA6 4 &pcfg_pull_up>;
+ };
+ };
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC
2022-11-02 12:46 [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Jagan Teki
@ 2022-11-02 12:46 ` Jagan Teki
2022-11-04 10:42 ` Johan Jonker
2022-11-02 12:46 ` [PATCH v6 3/6] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd Jagan Teki
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Jagan Teki @ 2022-11-02 12:46 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki,
Jon Lin, Sugar Zhang
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
hybrid operation and computing power is up to 2.0TOPs.
This patch add basic core dtsi support.
Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v6:
- add psci node
Changes for v5:
- none
Changes for v4:
- update i2c0
- rebase on -next
Changes for v3:
- update cru and power file names
Changes for v2:
- split pinctrl in separate patch
arch/arm/boot/dts/rv1126.dtsi | 439 ++++++++++++++++++++++++++++++++++
1 file changed, 439 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126.dtsi
diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
new file mode 100644
index 000000000000..867f17ab0efd
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126.dtsi
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <dt-bindings/clock/rockchip,rv1126-cru.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/power/rockchip,rv1126-power.h>
+#include <dt-bindings/soc/rockchip,boot-mode.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rv1126";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ i2c0 = &i2c0;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ serial3 = &uart3;
+ serial4 = &uart4;
+ serial5 = &uart5;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu1: cpu@f01 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf01>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu2: cpu@f02 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf02>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+
+ cpu3: cpu@f03 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf03>;
+ enable-method = "psci";
+ clocks = <&cru ARMCLK>;
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ grf: syscon@fe000000 {
+ compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
+ reg = <0xfe000000 0x20000>;
+ };
+
+ pmugrf: syscon@fe020000 {
+ compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
+ reg = <0xfe020000 0x1000>;
+
+ pmu_io_domains: io-domains {
+ compatible = "rockchip,rv1126-pmu-io-voltage-domain";
+ status = "disabled";
+ };
+ };
+
+ qos_emmc: qos@fe860000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860000 0x20>;
+ };
+
+ qos_nandc: qos@fe860080 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860080 0x20>;
+ };
+
+ qos_sfc: qos@fe860200 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe860200 0x20>;
+ };
+
+ qos_sdio: qos@fe86c000 {
+ compatible = "rockchip,rv1126-qos", "syscon";
+ reg = <0xfe86c000 0x20>;
+ };
+
+ gic: interrupt-controller@feff0000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0xfeff1000 0x1000>,
+ <0xfeff2000 0x2000>,
+ <0xfeff4000 0x2000>,
+ <0xfeff6000 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ pmu: power-management@ff3e0000 {
+ compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
+ reg = <0xff3e0000 0x1000>;
+
+ power: power-controller {
+ compatible = "rockchip,rv1126-power-controller";
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ power-domain@RV1126_PD_NVM {
+ reg = <RV1126_PD_NVM>;
+ clocks = <&cru HCLK_EMMC>,
+ <&cru CLK_EMMC>,
+ <&cru HCLK_NANDC>,
+ <&cru CLK_NANDC>,
+ <&cru HCLK_SFC>,
+ <&cru HCLK_SFCXIP>,
+ <&cru SCLK_SFC>;
+ pm_qos = <&qos_emmc>,
+ <&qos_nandc>,
+ <&qos_sfc>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@RV1126_PD_SDIO {
+ reg = <RV1126_PD_SDIO>;
+ clocks = <&cru HCLK_SDIO>,
+ <&cru CLK_SDIO>;
+ pm_qos = <&qos_sdio>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ i2c0: i2c@ff3f0000 {
+ compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
+ reg = <0xff3f0000 0x1000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ rockchip,grf = <&pmugrf>;
+ clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
+ clock-names = "i2c", "pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_xfer>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ dmac: dma-controller@ff4e0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0xff4e0000 0x4000>;
+ interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-periph-burst;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+
+ uart1: serial@ff410000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff410000 0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 7>, <&dmac 6>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ pmucru: clock-controller@ff480000 {
+ compatible = "rockchip,rv1126-pmucru";
+ reg = <0xff480000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ cru: clock-controller@ff490000 {
+ compatible = "rockchip,rv1126-cru";
+ reg = <0xff490000 0x1000>;
+ clocks = <&xin24m>;
+ clock-names = "xin24m";
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ uart0: serial@ff560000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff560000 0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 5>, <&dmac 4>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart2: serial@ff570000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff570000 0x100>;
+ interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 9>, <&dmac 8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m1_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart3: serial@ff580000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff580000 0x100>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 11>, <&dmac 10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart3m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart4: serial@ff590000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff590000 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
+ clock-names = "baudclk", "apb_pclk";
+ dmas = <&dmac 13>, <&dmac 12>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ uart5: serial@ff5a0000 {
+ compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
+ reg = <0xff5a0000 0x100>;
+ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
+ dmas = <&dmac 15>, <&dmac 14>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart5m0_xfer>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ status = "disabled";
+ };
+
+ saradc: saradc@ff5e0000 {
+ compatible = "rockchip,rk3399-saradc";
+ reg = <0xff5e0000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ resets = <&cru SRST_SARADC_P>;
+ reset-names = "saradc-apb";
+ status = "disabled";
+ };
+
+ timer: timer@ff660000 {
+ compatible = "rockchip,rk3288-timer";
+ reg = <0xff660000 0x20>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
+ clock-names = "pclk", "timer";
+ };
+
+ emmc: mmc@ffc50000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc50000 0x4000>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_NVM>;
+ status = "disabled";
+ };
+
+ sdmmc: mmc@ffc60000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc60000 0x4000>;
+ interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ status = "disabled";
+ };
+
+ sdio: mmc@ffc70000 {
+ compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
+ reg = <0xffc70000 0x4000>;
+ interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ max-frequency = <200000000>;
+ power-domains = <&power RV1126_PD_SDIO>;
+ status = "disabled";
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rv1126-pinctrl";
+ rockchip,grf = <&grf>;
+ rockchip,pmu = <&pmugrf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@ff460000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff460000 0x100>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@ff620000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff620000 0x100>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@ff630000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff630000 0x100>;
+ interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@ff640000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff640000 0x100>;
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio4: gpio4@ff650000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0xff650000 0x100>;
+ interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+};
+
+#include "rv1126-pinctrl.dtsi"
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 3/6] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd.
2022-11-02 12:46 [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Jagan Teki
2022-11-02 12:46 ` [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
@ 2022-11-02 12:46 ` Jagan Teki
2022-11-02 12:46 ` [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 Jagan Teki
` (2 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Jagan Teki @ 2022-11-02 12:46 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki, Rob Herring
Edgeble AI is an Artificial Intelligence company with a focus on
deploying Neural Acceleration principles at the Edge.
Add vendor prefix for it.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v6:
- none
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 7f9ec8ef8749..6c81565af488 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -368,6 +368,8 @@ patternProperties:
description: EBV Elektronik
"^eckelmann,.*":
description: Eckelmann AG
+ "^edgeble,.*":
+ description: Edgeble AI Technologies Pvt. Ltd.
"^edimax,.*":
description: EDIMAX Technology Co., Ltd
"^edt,.*":
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2
2022-11-02 12:46 [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Jagan Teki
2022-11-02 12:46 ` [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
2022-11-02 12:46 ` [PATCH v6 3/6] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd Jagan Teki
@ 2022-11-02 12:46 ` Jagan Teki
2022-11-04 21:50 ` Rob Herring
2022-11-02 12:46 ` [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) Jagan Teki
2022-11-02 12:46 ` [PATCH v6 6/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO Jagan Teki
4 siblings, 1 reply; 10+ messages in thread
From: Jagan Teki @ 2022-11-02 12:46 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.
Edgeble Neural Compute Module 2(Neu2) IO board is an industrial
form factor evaluation board from Edgeble AI.
Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.
Add dt-bindings for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v6:
- updated SOM and Carrier name
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index 244c42eaae8c..26fdd205a899 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -85,6 +85,12 @@ properties:
- const: chipspark,rayeager-px2
- const: rockchip,rk3066a
+ - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
+ items:
+ - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board
+ - const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM
+ - const: rockchip,rv1126
+
- description: Elgin RV1108 R1
items:
- const: elgin,rv1108-r1
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)
2022-11-02 12:46 [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Jagan Teki
` (2 preceding siblings ...)
2022-11-02 12:46 ` [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 Jagan Teki
@ 2022-11-02 12:46 ` Jagan Teki
2022-11-04 11:19 ` Johan Jonker
2022-11-02 12:46 ` [PATCH v6 6/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO Jagan Teki
4 siblings, 1 reply; 10+ messages in thread
From: Jagan Teki @ 2022-11-02 12:46 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 8/16/32GB eMMC
- 2x MIPI CSI2 FPC connector
- Fn-link 8223A-SR WiFi/BT
Industrial grade (-40 °C to +85 °C) version of the same class of module
called Neu2k powered with Rockchip RV1126K.
Neu2 needs to mount on top of Edgeble IO boards for creating complete
platform solutions.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v6:
- updated the SOM name
arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi | 353 +++++++++++++++++++++
1 file changed, 353 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
new file mode 100644
index 000000000000..6425ba5714ea
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
@@ -0,0 +1,353 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/ {
+ compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+ aliases {
+ mmc0 = &emmc;
+ };
+
+ vcc5v0_sys: vccsys {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vccio_flash: vccio-flash {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&flash_vol_sel>;
+ regulator-name = "vccio_flash";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ vin-supply = <&vcc_3v3>;
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_arm>;
+};
+
+&emmc {
+ bus-width = <8>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vccio_flash>;
+ rockchip,default-sample-phase = <90>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc5v0_sys>;
+ vcc2-supply = <&vcc5v0_sys>;
+ vcc3-supply = <&vcc5v0_sys>;
+ vcc4-supply = <&vcc5v0_sys>;
+ vcc5-supply = <&vcc_buck5>;
+ vcc6-supply = <&vcc_buck5>;
+ vcc7-supply = <&vcc5v0_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc5v0_sys>;
+
+ regulators {
+ vdd_npu_vepu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <650000>;
+ regulator-max-microvolt = <950000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu_vepu";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdd_arm: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <725000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_arm";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vcc3v3_sys: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc3v3_sys";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc_buck5: DCDC_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <2200000>;
+ regulator-name = "vcc_buck5";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <2200000>;
+ };
+ };
+
+ vcc_0v8: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc_0v8";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc1v8_pmu: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc1v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdd0v8_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <800000>;
+ regulator-name = "vcc0v8_pmu";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <800000>;
+ };
+ };
+
+ vcc_1v8: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_1v8";
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_dovdd: LDO_REG5 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc_dovdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_dvdd: LDO_REG6 {
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-name = "vcc_dvdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_avdd: LDO_REG7 {
+ regulator-min-microvolt = <2800000>;
+ regulator-max-microvolt = <2800000>;
+ regulator-name = "vcc_avdd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_sd";
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_5v0: SWITCH_REG1 {
+ regulator-name = "vcc_5v0";
+ };
+
+ vcc_3v3: SWITCH_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+ };
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable: bt-enable {
+ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ flash {
+ flash_vol_sel: flash-vol-sel {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ wifi {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio0-supply = <&vcc1v8_pmu>;
+ pmuio1-supply = <&vcc3v3_sys>;
+ vccio1-supply = <&vccio_flash>;
+ vccio2-supply = <&vccio_sd>;
+ vccio3-supply = <&vcc_1v8>;
+ vccio4-supply = <&vcc_dovdd>;
+ vccio5-supply = <&vcc_1v8>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_dovdd>;
+ status = "okay";
+};
+
+&saradc {
+ vref-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ max-frequency = <100000000>;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr104;
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
+ status = "okay";
+
+ bluetooth {
+ compatible = "qcom,qca9377-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
+ max-speed = <2000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_enable>;
+ vddxo-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcc_1v8>;
+ };
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v6 6/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO
2022-11-02 12:46 [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Jagan Teki
` (3 preceding siblings ...)
2022-11-02 12:46 ` [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) Jagan Teki
@ 2022-11-02 12:46 ` Jagan Teki
4 siblings, 0 replies; 10+ messages in thread
From: Jagan Teki @ 2022-11-02 12:46 UTC (permalink / raw)
To: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jagan Teki
Neural Compute Module 2(Neu2) IO board is an industrial form factor
evaluation board from Edgeble AI.
General features:
- microSD slot
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC battery slot
- 40-pin expansion
Neu2 needs to mount on top of this IO board in order to create complete
Edgeble Neural Compute Module 2(Neu2) IO platform.
Add support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
---
Changes for v6:
- update the carrier name.
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts | 38 ++++++++++++++++++++
2 files changed, 39 insertions(+)
create mode 100644 arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e48cfbc4e8e4..40cc34bd4945 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1122,6 +1122,7 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rv1108-elgin-r1.dtb \
rv1108-evb.dtb \
+ rv1126-edgeble-neu2-io.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
new file mode 100644
index 000000000000..ae1cf344239b
--- /dev/null
+++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+/dts-v1/;
+#include "rv1126.dtsi"
+#include "rv1126-edgeble-neu2.dtsi"
+
+/ {
+ model = "Edgeble Neu2 IO Board";
+ compatible = "edgeble,neural-compute-module-2-io",
+ "edgeble,neural-compute-module-2", "rockchip,rv1126";
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&sdmmc {
+ bus-width = <4>;
+ cap-mmc-highspeed;
+ cap-sd-highspeed;
+ card-detect-delay = <200>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>;
+ rockchip,default-sample-phase = <90>;
+ sd-uhs-sdr12;
+ sd-uhs-sdr25;
+ sd-uhs-sdr104;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC
2022-11-02 12:46 ` [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
@ 2022-11-04 10:42 ` Johan Jonker
2022-11-05 7:35 ` Jagan Teki
0 siblings, 1 reply; 10+ messages in thread
From: Johan Jonker @ 2022-11-04 10:42 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree, Jon Lin, Sugar Zhang
Hi Jagan,
When I run this command below I get a lot text on my screen.
Could you fix them all?
Some more comments below.
Johan
===
ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make dtbs_check
On 11/2/22 13:46, Jagan Teki wrote:
> RV1126 is a high-performance vision processor SoC for IPC/CVR,
> especially for AI related application.
>
> It is based on quad-core ARM Cortex-A7 32-bit core which integrates
> NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
> and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
> hybrid operation and computing power is up to 2.0TOPs.
>
> This patch add basic core dtsi support.
>
> Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Changes for v6:
> - add psci node
> Changes for v5:
> - none
> Changes for v4:
> - update i2c0
> - rebase on -next
> Changes for v3:
> - update cru and power file names
> Changes for v2:
> - split pinctrl in separate patch
>
> arch/arm/boot/dts/rv1126.dtsi | 439 ++++++++++++++++++++++++++++++++++
> 1 file changed, 439 insertions(+)
> create mode 100644 arch/arm/boot/dts/rv1126.dtsi
>
> diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
> new file mode 100644
> index 000000000000..867f17ab0efd
> --- /dev/null
> +++ b/arch/arm/boot/dts/rv1126.dtsi
> @@ -0,0 +1,439 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
Is this an advertisement?
Maybe remove?
Was there added substantial new code?
Compared to the original there was mainly parts removed, sorted and restyled here and there I think.
https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm/boot/dts/rv1126.dtsi
> + */
> +
> +#include <dt-bindings/clock/rockchip,rv1126-cru.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include <dt-bindings/power/rockchip,rv1126-power.h>
> +#include <dt-bindings/soc/rockchip,boot-mode.h>
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + compatible = "rockchip,rv1126";
> +
> + interrupt-parent = <&gic>;
> +
> + aliases {
> + i2c0 = &i2c0;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + };
Comment by Krzysztof:
https://lore.kernel.org/all/f2652e0e-fb08-efb4-e25a-36a335f0c457@linaro.org/
No, not only mmc. UART, I2C, SPI - all of these should go to the board.
Comment by Arnd:
https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/
Each board should have its own aliases node that describes
exactly which of the devices are wired up on that board, and
in which order. If there are connectors on the board that
are labeled in some form, then the aliases are meant to
match what is written on the board or in its documentation.
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@f00 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf00>;
> + enable-method = "psci";
> + clocks = <&cru ARMCLK>;
> + };
> +
> + cpu1: cpu@f01 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf01>;
> + enable-method = "psci";
> + clocks = <&cru ARMCLK>;
> + };
> +
> + cpu2: cpu@f02 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf02>;
> + enable-method = "psci";
> + clocks = <&cru ARMCLK>;
> + };
> +
> + cpu3: cpu@f03 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a7";
> + reg = <0xf03>;
> + enable-method = "psci";
> + clocks = <&cru ARMCLK>;
> + };
> + };
> +
> + arm-pmu {
> + compatible = "arm,cortex-a7-pmu";
> + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + clock-frequency = <24000000>;
> + };
> +
> + xin24m: oscillator {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xin24m";
> + #clock-cells = <0>;
> + };
> +
> + grf: syscon@fe000000 {
> + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
> + reg = <0xfe000000 0x20000>;
> + };
> +
> + pmugrf: syscon@fe020000 {
> + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
> + reg = <0xfe020000 0x1000>;
> +
> + pmu_io_domains: io-domains {
> + compatible = "rockchip,rv1126-pmu-io-voltage-domain";
> + status = "disabled";
> + };
> + };
> +
> + qos_emmc: qos@fe860000 {
> + compatible = "rockchip,rv1126-qos", "syscon";
> + reg = <0xfe860000 0x20>;
> + };
> +
> + qos_nandc: qos@fe860080 {
> + compatible = "rockchip,rv1126-qos", "syscon";
> + reg = <0xfe860080 0x20>;
> + };
> +
> + qos_sfc: qos@fe860200 {
> + compatible = "rockchip,rv1126-qos", "syscon";
> + reg = <0xfe860200 0x20>;
> + };
> +
> + qos_sdio: qos@fe86c000 {
> + compatible = "rockchip,rv1126-qos", "syscon";
> + reg = <0xfe86c000 0x20>;
> + };
> +
> + gic: interrupt-controller@feff0000 {
> + compatible = "arm,gic-400";
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> +
> + reg = <0xfeff1000 0x1000>,
> + <0xfeff2000 0x2000>,
> + <0xfeff4000 0x2000>,
> + <0xfeff6000 0x2000>;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + pmu: power-management@ff3e0000 {
> + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb:0:0: /power-management@ff3e0000: failed to match any schema with compatible: ['rockchip,rv1126-pmu', 'syscon', 'simple-mfd']
> + reg = <0xff3e0000 0x1000>;
> +
> + power: power-controller {
> + compatible = "rockchip,rv1126-power-controller";
> + #power-domain-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + power-domain@RV1126_PD_NVM {
> + reg = <RV1126_PD_NVM>;
> + clocks = <&cru HCLK_EMMC>,
> + <&cru CLK_EMMC>,
> + <&cru HCLK_NANDC>,
> + <&cru CLK_NANDC>,
> + <&cru HCLK_SFC>,
> + <&cru HCLK_SFCXIP>,
> + <&cru SCLK_SFC>;
> + pm_qos = <&qos_emmc>,
> + <&qos_nandc>,
> + <&qos_sfc>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@RV1126_PD_SDIO {
> + reg = <RV1126_PD_SDIO>;
> + clocks = <&cru HCLK_SDIO>,
> + <&cru CLK_SDIO>;
> + pm_qos = <&qos_sdio>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
> +
> + i2c0: i2c@ff3f0000 {
> + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
> + reg = <0xff3f0000 0x1000>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + rockchip,grf = <&pmugrf>;
> + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
> + clock-names = "i2c", "pclk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_xfer>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> + };
> +
> + dmac: dma-controller@ff4e0000 {
Sort nodes with reg property on reg address.
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0xff4e0000 0x4000>;
> + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + #dma-cells = <1>;
> + arm,pl330-periph-burst;
> + clocks = <&cru ACLK_DMAC>;
> + clock-names = "apb_pclk";
> + };
> +
> + uart1: serial@ff410000 {
> + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> + reg = <0xff410000 0x100>;
> + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
> + clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac 7>, <&dmac 6>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1m0_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + pmucru: clock-controller@ff480000 {
> + compatible = "rockchip,rv1126-pmucru";
> + reg = <0xff480000 0x1000>;
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + cru: clock-controller@ff490000 {
> + compatible = "rockchip,rv1126-cru";
> + reg = <0xff490000 0x1000>;
> + clocks = <&xin24m>;
> + clock-names = "xin24m";
> + rockchip,grf = <&grf>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + };
> +
> + uart0: serial@ff560000 {
> + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> + reg = <0xff560000 0x100>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> + clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac 5>, <&dmac 4>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart2: serial@ff570000 {
> + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> + reg = <0xff570000 0x100>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> + clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac 9>, <&dmac 8>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2m1_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart3: serial@ff580000 {
> + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> + reg = <0xff580000 0x100>;
> + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> + clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac 11>, <&dmac 10>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart3m0_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart4: serial@ff590000 {
> + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> + reg = <0xff590000 0x100>;
> + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
> + clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac 13>, <&dmac 12>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart4m0_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + uart5: serial@ff5a0000 {
> + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> + reg = <0xff5a0000 0x100>;
> + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> + clock-frequency = <24000000>;
> + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
> + dmas = <&dmac 15>, <&dmac 14>;
> + clock-names = "baudclk", "apb_pclk";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart5m0_xfer>;
> + reg-shift = <2>;
> + reg-io-width = <4>;
> + status = "disabled";
> + };
> +
> + saradc: saradc@ff5e0000 {
> + compatible = "rockchip,rk3399-saradc";
compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
Add to document.
> + reg = <0xff5e0000 0x100>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> + #io-channel-cells = <1>;
> + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
> + clock-names = "saradc", "apb_pclk";
> + resets = <&cru SRST_SARADC_P>;
> + reset-names = "saradc-apb";
> + status = "disabled";
> + };
> +
> + timer: timer@ff660000 {
> + compatible = "rockchip,rk3288-timer";
compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
Add to document after my patch:
[PATCH v2 2/4] dt-bindings: timer: rockchip: add rockchip,rk3128-timer
https://lore.kernel.org/linux-rockchip/0e57f38f-bace-8556-7258-aa0b3c0ac103@gmail.com/T/#u
> + reg = <0xff660000 0x20>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
> + clock-names = "pclk", "timer";
> + };
> +
> + emmc: mmc@ffc50000 {
> + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0xffc50000 0x4000>;
> + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
> + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <200000000>;
> + power-domains = <&power RV1126_PD_NVM>;
/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb: mmc@ffc50000: Unevaluated properties are not allowed ('power-domains' was unexpected)
From schema: /Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
Add power-domains property to rockchip-dw-mshc.yaml.
> + status = "disabled";
> + };
> +
> + sdmmc: mmc@ffc60000 {
> + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0xffc60000 0x4000>;
> + interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>,
> + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <200000000>;
> + status = "disabled";
> + };
> +
> + sdio: mmc@ffc70000 {
> + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
> + reg = <0xffc70000 0x4000>;
> + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>,
> + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
> + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> + max-frequency = <200000000>;
> + power-domains = <&power RV1126_PD_SDIO>;
> + status = "disabled";
> + };
> +
> + pinctrl: pinctrl {
> + compatible = "rockchip,rv1126-pinctrl";
> + rockchip,grf = <&grf>;
> + rockchip,pmu = <&pmugrf>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + gpio0: gpio0@ff460000 {
gpio
Use generic node name.
> + compatible = "rockchip,gpio-bank";
> + reg = <0xff460000 0x100>;
> + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio1@ff620000 {
same
> + compatible = "rockchip,gpio-bank";
> + reg = <0xff620000 0x100>;
> + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio2: gpio2@ff630000 {
same
> + compatible = "rockchip,gpio-bank";
> + reg = <0xff630000 0x100>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio3: gpio3@ff640000 {
same
> + compatible = "rockchip,gpio-bank";
> + reg = <0xff640000 0x100>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio4: gpio4@ff650000 {
> + compatible = "rockchip,gpio-bank";
same
> + reg = <0xff650000 0x100>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> + };
> +};
> +
> +#include "rv1126-pinctrl.dtsi"
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2)
2022-11-02 12:46 ` [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) Jagan Teki
@ 2022-11-04 11:19 ` Johan Jonker
0 siblings, 0 replies; 10+ messages in thread
From: Johan Jonker @ 2022-11-04 11:19 UTC (permalink / raw)
To: Jagan Teki, Heiko Stuebner, Rob Herring, Krzysztof Kozlowski
Cc: linux-arm-kernel, linux-rockchip, devicetree
Hi Jagan,
On 11/2/22 13:46, Jagan Teki wrote:
> Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
> based on Rockchip RV1126 from Edgeble AI.
>
> General features:
> - Rockchip RV1126
> - 2/4GB LPDDR4
> - 8/16/32GB eMMC
> - 2x MIPI CSI2 FPC connector
> - Fn-link 8223A-SR WiFi/BT
>
> Industrial grade (-40 °C to +85 °C) version of the same class of module
> called Neu2k powered with Rockchip RV1126K.
>
> Neu2 needs to mount on top of Edgeble IO boards for creating complete
> platform solutions.
>
> Add support for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Changes for v6:
> - updated the SOM name
>
> arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi | 353 +++++++++++++++++++++
> 1 file changed, 353 insertions(+)
> create mode 100644 arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
>
> diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
> new file mode 100644
> index 000000000000..6425ba5714ea
> --- /dev/null
> +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi
> @@ -0,0 +1,353 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
> + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
> + */
> +
> +/ {
> + compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126";
> +
> + aliases {
> + mmc0 = &emmc;
> + };
> +
> + vcc5v0_sys: vccsys {
Comment by Krzysztof:
Generic node names, so at least regulator prefix or suffix.
> + compatible = "regulator-fixed";
> + regulator-name = "vcc5v0_sys";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> +
> + vccio_flash: vccio-flash {
same
> + compatible = "regulator-fixed";
> + enable-active-high;
> + gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&flash_vol_sel>;
> + regulator-name = "vccio_flash";
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + vin-supply = <&vcc_3v3>;
> + };
> +
> + sdio_pwrseq: sdio-pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + clocks = <&rk809 1>;
> + clock-names = "ext_clock";
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_enable_h>;
> + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&vdd_arm>;
> +};
> +
> +&emmc {
> + bus-width = <8>;
> + non-removable;
> + pinctrl-names = "default";
> + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>;
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&vccio_flash>
> + rockchip,default-sample-phase = <90>;
sort
> + status = "okay";
> +};
> +
> +&i2c0 {
> + status = "okay";
status below other properties
> + clock-frequency = <400000>;
> +
> + rk809: pmic@20 {
> + compatible = "rockchip,rk809";
> + reg = <0x20>;
> + interrupt-parent = <&gpio0>;
> + interrupts = <RK_PB1 IRQ_TYPE_LEVEL_LOW>;
> + #clock-cells = <1>;
> + clock-output-names = "rk808-clkout1", "rk808-clkout2";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pmic_int_l>;
> + rockchip,system-power-controller;
> + wakeup-source;
> +
> + vcc1-supply = <&vcc5v0_sys>;
> + vcc2-supply = <&vcc5v0_sys>;
> + vcc3-supply = <&vcc5v0_sys>;
> + vcc4-supply = <&vcc5v0_sys>;
> + vcc5-supply = <&vcc_buck5>;
> + vcc6-supply = <&vcc_buck5>;
> + vcc7-supply = <&vcc5v0_sys>;
> + vcc8-supply = <&vcc3v3_sys>;
> + vcc9-supply = <&vcc5v0_sys>;
> +
> + regulators {
> + vdd_npu_vepu: DCDC_REG1 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <650000>;
> + regulator-max-microvolt = <950000>;
> + regulator-ramp-delay = <6001>;
> + regulator-initial-mode = <0x2>;
> + regulator-name = "vdd_npu_vepu";
Exception to the Heiko's sort rules:
regulator-name above all other properties that start with 'regulator-'.
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vdd_arm: DCDC_REG2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <725000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-ramp-delay = <6001>;
> + regulator-initial-mode = <0x2>;
> + regulator-name = "vdd_arm";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_ddr: DCDC_REG3 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-initial-mode = <0x2>;
> + regulator-name = "vcc_ddr";
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + };
> + };
> +
> + vcc3v3_sys: DCDC_REG4 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-initial-mode = <0x2>;
> + regulator-name = "vcc3v3_sys";
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <3300000>;
> + };
> + };
> +
> + vcc_buck5: DCDC_REG5 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <2200000>;
> + regulator-max-microvolt = <2200000>;
> + regulator-name = "vcc_buck5";
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <2200000>;
> + };
> + };
> +
> + vcc_0v8: LDO_REG1 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-name = "vcc_0v8";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc1v8_pmu: LDO_REG2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc1v8_pmu";
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vdd0v8_pmu: LDO_REG3 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <800000>;
> + regulator-name = "vcc0v8_pmu";
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <800000>;
> + };
> + };
> +
> + vcc_1v8: LDO_REG4 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc_1v8";
> +
> + regulator-state-mem {
> + regulator-on-in-suspend;
> + regulator-suspend-microvolt = <1800000>;
> + };
> + };
> +
> + vcc_dovdd: LDO_REG5 {
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-name = "vcc_dovdd";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_dvdd: LDO_REG6 {
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-name = "vcc_dvdd";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_avdd: LDO_REG7 {
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-name = "vcc_avdd";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vccio_sd: LDO_REG8 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vccio_sd";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc3v3_sd: LDO_REG9 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc3v3_sd";
> +
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + vcc_5v0: SWITCH_REG1 {
> + regulator-name = "vcc_5v0";
> + };
> +
> + vcc_3v3: SWITCH_REG2 {
> + regulator-always-on;
> + regulator-boot-on;
> + regulator-name = "vcc_3v3";
> + };
> + };
> + };
> +};
> +
> +&pinctrl {
> + bt {
> + bt_enable: bt-enable {
> + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + flash {
> + flash_vol_sel: flash-vol-sel {
> + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + pmic {
> + pmic_int_l: pmic-int-l {
> + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
> + };
> + };
> +
> + wifi {
> + wifi_enable_h: wifi-enable-h {
> + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +};
> +
> +&pmu_io_domains {
> + pmuio0-supply = <&vcc1v8_pmu>;
> + pmuio1-supply = <&vcc3v3_sys>;
> + vccio1-supply = <&vccio_flash>;
> + vccio2-supply = <&vccio_sd>;
> + vccio3-supply = <&vcc_1v8>;
> + vccio4-supply = <&vcc_dovdd>;
> + vccio5-supply = <&vcc_1v8>;
> + vccio6-supply = <&vcc_1v8>;
> + vccio7-supply = <&vcc_dovdd>;
> + status = "okay";
> +};
> +
> +&saradc {
> + vref-supply = <&vcc_1v8>;
> + status = "okay";
> +};
> +
> +&sdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
Properties that start with '#' down the list as possible, but above status.
Only needed for the interpretation of the DT.
> + max-frequency = <100000000>;
sort
> + bus-width = <4>;
> + cap-sd-highspeed;
> + cap-sdio-irq;
> + keep-power-in-suspend;
> + mmc-pwrseq = <&sdio_pwrseq>;
> + non-removable;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>;
> + vmmc-supply = <&vcc3v3_sys>;
> + vqmmc-supply = <&vcc_1v8>;
> + rockchip,default-sample-phase = <90>;
sort
> + sd-uhs-sdr104;
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>;
> + status = "okay";
> +
> + bluetooth {
> + compatible = "qcom,qca9377-bt";
> + clocks = <&rk809 1>;
> + clock-names = "lpo";
arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb: bluetooth: 'clock-names' does not match any of the regexes: 'pinctrl-[0-9]+'
> + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */
> + max-speed = <2000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&bt_enable>;
> + vddxo-supply = <&vcc3v3_sys>;
> + vddio-supply = <&vcc_1v8>;
> + };
> +};
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2
2022-11-02 12:46 ` [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 Jagan Teki
@ 2022-11-04 21:50 ` Rob Herring
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2022-11-04 21:50 UTC (permalink / raw)
To: Jagan Teki
Cc: Krzysztof Kozlowski, linux-arm-kernel, devicetree, Rob Herring,
linux-rockchip, Heiko Stuebner
On Wed, 02 Nov 2022 18:16:05 +0530, Jagan Teki wrote:
> Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
> based on Rockchip RV1126 from Edgeble AI.
>
> Edgeble Neural Compute Module 2(Neu2) IO board is an industrial
> form factor evaluation board from Edgeble AI.
>
> Neu2 needs to mount on top of this IO board in order to create complete
> Edgeble Neural Compute Module 2(Neu2) IO platform.
>
> Add dt-bindings for it.
>
> Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> ---
> Changes for v6:
> - updated SOM and Carrier name
>
> Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC
2022-11-04 10:42 ` Johan Jonker
@ 2022-11-05 7:35 ` Jagan Teki
0 siblings, 0 replies; 10+ messages in thread
From: Jagan Teki @ 2022-11-05 7:35 UTC (permalink / raw)
To: Johan Jonker
Cc: Heiko Stuebner, Rob Herring, Krzysztof Kozlowski,
linux-arm-kernel, linux-rockchip, devicetree, Jon Lin,
Sugar Zhang
Hi Johan,
On Fri, 4 Nov 2022 at 16:12, Johan Jonker <jbx6244@gmail.com> wrote:
>
> Hi Jagan,
>
> When I run this command below I get a lot text on my screen.
> Could you fix them all?
> Some more comments below.
>
> Johan
>
> ===
>
> ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- make dtbs_check
>
> On 11/2/22 13:46, Jagan Teki wrote:
> > RV1126 is a high-performance vision processor SoC for IPC/CVR,
> > especially for AI related application.
> >
> > It is based on quad-core ARM Cortex-A7 32-bit core which integrates
> > NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
> > and 512KB unified L2 cache. It has build-in NPU supports INT8/INT16
> > hybrid operation and computing power is up to 2.0TOPs.
> >
> > This patch add basic core dtsi support.
> >
> > Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
> > Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> > Signed-off-by: Jagan Teki <jagan@edgeble.ai>
> > ---
> > Changes for v6:
> > - add psci node
> > Changes for v5:
> > - none
> > Changes for v4:
> > - update i2c0
> > - rebase on -next
> > Changes for v3:
> > - update cru and power file names
> > Changes for v2:
> > - split pinctrl in separate patch
> >
> > arch/arm/boot/dts/rv1126.dtsi | 439 ++++++++++++++++++++++++++++++++++
> > 1 file changed, 439 insertions(+)
> > create mode 100644 arch/arm/boot/dts/rv1126.dtsi
> >
> > diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi
> > new file mode 100644
> > index 000000000000..867f17ab0efd
> > --- /dev/null
> > +++ b/arch/arm/boot/dts/rv1126.dtsi
> > @@ -0,0 +1,439 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
>
> > + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
>
> Is this an advertisement?
Not really, add since we made our real efforts to place this on the
upstream tree. Which indeed make sense I think.
> Maybe remove?
> Was there added substantial new code?
> Compared to the original there was mainly parts removed, sorted and restyled here and there I think.
Mostly, yes for now.
>
> https://github.com/rockchip-linux/kernel/blob/develop-5.10/arch/arm/boot/dts/rv1126.dtsi
>
> > + */
> > +
> > +#include <dt-bindings/clock/rockchip,rv1126-cru.h>
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/interrupt-controller/arm-gic.h>
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +#include <dt-bindings/pinctrl/rockchip.h>
> > +#include <dt-bindings/power/rockchip,rv1126-power.h>
> > +#include <dt-bindings/soc/rockchip,boot-mode.h>
> > +
> > +/ {
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > +
> > + compatible = "rockchip,rv1126";
> > +
> > + interrupt-parent = <&gic>;
> > +
>
> > + aliases {
> > + i2c0 = &i2c0;
> > + serial0 = &uart0;
> > + serial1 = &uart1;
> > + serial2 = &uart2;
> > + serial3 = &uart3;
> > + serial4 = &uart4;
> > + serial5 = &uart5;
> > + };
>
> Comment by Krzysztof:
> https://lore.kernel.org/all/f2652e0e-fb08-efb4-e25a-36a335f0c457@linaro.org/
>
> No, not only mmc. UART, I2C, SPI - all of these should go to the board.
>
> Comment by Arnd:
> https://lore.kernel.org/linux-rockchip/CAK8P3a25iYksubCnQb1-e5yj=crEsK37RB9Hn4ZGZMwcVVrG7g@mail.gmail.com/
>
> Each board should have its own aliases node that describes
> exactly which of the devices are wired up on that board, and
> in which order. If there are connectors on the board that
> are labeled in some form, then the aliases are meant to
> match what is written on the board or in its documentation.
I'm not sure whether it would apply to all arch/boards, let Heiko or
someone comment.
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@f00 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf00>;
> > + enable-method = "psci";
> > + clocks = <&cru ARMCLK>;
> > + };
> > +
> > + cpu1: cpu@f01 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf01>;
> > + enable-method = "psci";
> > + clocks = <&cru ARMCLK>;
> > + };
> > +
> > + cpu2: cpu@f02 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf02>;
> > + enable-method = "psci";
> > + clocks = <&cru ARMCLK>;
> > + };
> > +
> > + cpu3: cpu@f03 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a7";
> > + reg = <0xf03>;
> > + enable-method = "psci";
> > + clocks = <&cru ARMCLK>;
> > + };
> > + };
> > +
> > + arm-pmu {
> > + compatible = "arm,cortex-a7-pmu";
> > + interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
> > + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> > + };
> > +
> > + psci {
> > + compatible = "arm,psci-1.0";
> > + method = "smc";
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv7-timer";
> > + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
> > + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + clock-frequency = <24000000>;
> > + };
> > +
> > + xin24m: oscillator {
> > + compatible = "fixed-clock";
> > + clock-frequency = <24000000>;
> > + clock-output-names = "xin24m";
> > + #clock-cells = <0>;
> > + };
> > +
> > + grf: syscon@fe000000 {
> > + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd";
> > + reg = <0xfe000000 0x20000>;
> > + };
> > +
> > + pmugrf: syscon@fe020000 {
> > + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd";
> > + reg = <0xfe020000 0x1000>;
> > +
> > + pmu_io_domains: io-domains {
> > + compatible = "rockchip,rv1126-pmu-io-voltage-domain";
> > + status = "disabled";
> > + };
> > + };
> > +
> > + qos_emmc: qos@fe860000 {
> > + compatible = "rockchip,rv1126-qos", "syscon";
> > + reg = <0xfe860000 0x20>;
> > + };
> > +
> > + qos_nandc: qos@fe860080 {
> > + compatible = "rockchip,rv1126-qos", "syscon";
> > + reg = <0xfe860080 0x20>;
> > + };
> > +
> > + qos_sfc: qos@fe860200 {
> > + compatible = "rockchip,rv1126-qos", "syscon";
> > + reg = <0xfe860200 0x20>;
> > + };
> > +
> > + qos_sdio: qos@fe86c000 {
> > + compatible = "rockchip,rv1126-qos", "syscon";
> > + reg = <0xfe86c000 0x20>;
> > + };
> > +
> > + gic: interrupt-controller@feff0000 {
> > + compatible = "arm,gic-400";
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + #address-cells = <0>;
> > +
> > + reg = <0xfeff1000 0x1000>,
> > + <0xfeff2000 0x2000>,
> > + <0xfeff4000 0x2000>,
> > + <0xfeff6000 0x2000>;
> > + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
> > + };
> > +
> > + pmu: power-management@ff3e0000 {
>
> > + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd";
>
> arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb:0:0: /power-management@ff3e0000: failed to match any schema with compatible: ['rockchip,rv1126-pmu', 'syscon', 'simple-mfd']
>
>
> > + reg = <0xff3e0000 0x1000>;
> > +
> > + power: power-controller {
> > + compatible = "rockchip,rv1126-power-controller";
> > + #power-domain-cells = <1>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + power-domain@RV1126_PD_NVM {
> > + reg = <RV1126_PD_NVM>;
> > + clocks = <&cru HCLK_EMMC>,
> > + <&cru CLK_EMMC>,
> > + <&cru HCLK_NANDC>,
> > + <&cru CLK_NANDC>,
> > + <&cru HCLK_SFC>,
> > + <&cru HCLK_SFCXIP>,
> > + <&cru SCLK_SFC>;
> > + pm_qos = <&qos_emmc>,
> > + <&qos_nandc>,
> > + <&qos_sfc>;
> > + #power-domain-cells = <0>;
> > + };
> > +
> > + power-domain@RV1126_PD_SDIO {
> > + reg = <RV1126_PD_SDIO>;
> > + clocks = <&cru HCLK_SDIO>,
> > + <&cru CLK_SDIO>;
> > + pm_qos = <&qos_sdio>;
> > + #power-domain-cells = <0>;
> > + };
> > + };
> > + };
> > +
> > + i2c0: i2c@ff3f0000 {
> > + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c";
> > + reg = <0xff3f0000 0x1000>;
> > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> > + rockchip,grf = <&pmugrf>;
> > + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
> > + clock-names = "i2c", "pclk";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&i2c0_xfer>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + status = "disabled";
> > + };
> > +
>
> > + dmac: dma-controller@ff4e0000 {
>
> Sort nodes with reg property on reg address.
>
> > + compatible = "arm,pl330", "arm,primecell";
> > + reg = <0xff4e0000 0x4000>;
> > + interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
> > + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> > + #dma-cells = <1>;
> > + arm,pl330-periph-burst;
> > + clocks = <&cru ACLK_DMAC>;
> > + clock-names = "apb_pclk";
> > + };
> > +
> > + uart1: serial@ff410000 {
> > + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> > + reg = <0xff410000 0x100>;
> > + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-frequency = <24000000>;
> > + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>;
> > + clock-names = "baudclk", "apb_pclk";
> > + dmas = <&dmac 7>, <&dmac 6>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart1m0_xfer>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + pmucru: clock-controller@ff480000 {
> > + compatible = "rockchip,rv1126-pmucru";
> > + reg = <0xff480000 0x1000>;
> > + rockchip,grf = <&grf>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + cru: clock-controller@ff490000 {
> > + compatible = "rockchip,rv1126-cru";
> > + reg = <0xff490000 0x1000>;
> > + clocks = <&xin24m>;
> > + clock-names = "xin24m";
> > + rockchip,grf = <&grf>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + uart0: serial@ff560000 {
> > + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> > + reg = <0xff560000 0x100>;
> > + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-frequency = <24000000>;
> > + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> > + clock-names = "baudclk", "apb_pclk";
> > + dmas = <&dmac 5>, <&dmac 4>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart0_xfer>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart2: serial@ff570000 {
> > + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> > + reg = <0xff570000 0x100>;
> > + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-frequency = <24000000>;
> > + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> > + clock-names = "baudclk", "apb_pclk";
> > + dmas = <&dmac 9>, <&dmac 8>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart2m1_xfer>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart3: serial@ff580000 {
> > + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> > + reg = <0xff580000 0x100>;
> > + interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-frequency = <24000000>;
> > + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
> > + clock-names = "baudclk", "apb_pclk";
> > + dmas = <&dmac 11>, <&dmac 10>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart3m0_xfer>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart4: serial@ff590000 {
> > + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> > + reg = <0xff590000 0x100>;
> > + interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-frequency = <24000000>;
> > + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
> > + clock-names = "baudclk", "apb_pclk";
> > + dmas = <&dmac 13>, <&dmac 12>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart4m0_xfer>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + uart5: serial@ff5a0000 {
> > + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart";
> > + reg = <0xff5a0000 0x100>;
> > + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> > + clock-frequency = <24000000>;
> > + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
> > + dmas = <&dmac 15>, <&dmac 14>;
> > + clock-names = "baudclk", "apb_pclk";
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&uart5m0_xfer>;
> > + reg-shift = <2>;
> > + reg-io-width = <4>;
> > + status = "disabled";
> > + };
> > +
> > + saradc: saradc@ff5e0000 {
>
> > + compatible = "rockchip,rk3399-saradc";
>
> compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc";
>
> Add to document.
>
> > + reg = <0xff5e0000 0x100>;
> > + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > + #io-channel-cells = <1>;
> > + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
> > + clock-names = "saradc", "apb_pclk";
> > + resets = <&cru SRST_SARADC_P>;
> > + reset-names = "saradc-apb";
> > + status = "disabled";
> > + };
> > +
> > + timer: timer@ff660000 {
>
> > + compatible = "rockchip,rk3288-timer";
>
> compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer";
>
> Add to document after my patch:
>
> [PATCH v2 2/4] dt-bindings: timer: rockchip: add rockchip,rk3128-timer
> https://lore.kernel.org/linux-rockchip/0e57f38f-bace-8556-7258-aa0b3c0ac103@gmail.com/T/#u
It is better to be on the upstream tree as the code base instead of
intermediate dependencies, Heiko might take care of these conflicts
while applying.
>
> > + reg = <0xff660000 0x20>;
> > + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>;
> > + clock-names = "pclk", "timer";
> > + };
> > +
> > + emmc: mmc@ffc50000 {
> > + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc";
> > + reg = <0xffc50000 0x4000>;
> > + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>,
> > + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
> > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> > + fifo-depth = <0x100>;
> > + max-frequency = <200000000>;
>
> > + power-domains = <&power RV1126_PD_NVM>;
>
> /arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb: mmc@ffc50000: Unevaluated properties are not allowed ('power-domains' was unexpected)
> From schema: /Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
>
> Add power-domains property to rockchip-dw-mshc.yaml.
Thanks, along with the rest of them will fix it in the next version.
Jagan.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-11-05 7:37 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-11-02 12:46 [PATCH v6 1/6] ARM: dts: rockchip: Add Rockchip RV1126 pinctrl Jagan Teki
2022-11-02 12:46 ` [PATCH v6 2/6] ARM: dts: rockchip: Add Rockchip RV1126 SoC Jagan Teki
2022-11-04 10:42 ` Johan Jonker
2022-11-05 7:35 ` Jagan Teki
2022-11-02 12:46 ` [PATCH v6 3/6] dt-bindings: vendor-prefixes: Add Edgeble AI Technologies Pvt. Ltd Jagan Teki
2022-11-02 12:46 ` [PATCH v6 4/6] dt-bindings: arm: rockchip: Add Edgeble Neural Compute Module 2 Jagan Teki
2022-11-04 21:50 ` Rob Herring
2022-11-02 12:46 ` [PATCH v6 5/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) Jagan Teki
2022-11-04 11:19 ` Johan Jonker
2022-11-02 12:46 ` [PATCH v6 6/6] ARM: dts: rockchip: rv1126: Add Edgeble Neural Compute Module 2(Neu2) IO Jagan Teki
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).