From: Dong Aisheng <dongas86@gmail.com>
To: Abel Vesa <abelvesa@kernel.org>
Cc: Rob Herring <robh@kernel.org>, Shawn Guo <shawnguo@kernel.org>,
Sascha Hauer <kernel@pengutronix.de>,
Fabio Estevam <festevam@gmail.com>, Jacky Bai <ping.bai@nxp.com>,
Dong Aisheng <aisheng.dong@nxp.com>,
NXP Linux Team <linux-imx@nxp.com>,
devicetree <devicetree@vger.kernel.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
"moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE"
<linux-arm-kernel@lists.infradead.org>,
Abel Vesa <abel.vesa@nxp.com>
Subject: Re: [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl
Date: Tue, 18 May 2021 15:54:25 +0800 [thread overview]
Message-ID: <CAA+hA=RNfWYaE81yYv5Dyt8QSXd_NTGcwjWwitiRNe4ZOtRWvw@mail.gmail.com> (raw)
In-Reply-To: <20210517171205.1581938-6-abelvesa@kernel.org>
On Tue, May 18, 2021 at 1:16 AM <abelvesa@kernel.org> wrote:
>
> From: Jacky Bai <ping.bai@nxp.com>
>
> Add the ddr subsys dtsi for i.MX8DXL. Additional db pmu is added
> compared to i.MX8QXP.
>
> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
> Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
> ---
> .../boot/dts/freescale/imx8dxl-ss-ddr.dtsi | 34 +++++++++++++++++++
> 1 file changed, 34 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> new file mode 100644
> index 000000000000..640b43f5ae97
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi
> @@ -0,0 +1,34 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2021 NXP
> + */
> +
> +&ddr_subsys {
> + db_ipg_clk: clock-db-ipg {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <456000000>;
> + clock-output-names = "db_ipg_clk";
> + };
> +
> + db_pmu0: db-pmu@5ca40000 {
> + compatible = "fsl,imx8dxl-db-pmu";
> + reg = <0x5ca40000 0x10000>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&db_pmu0_lpcg 1>, <&db_pmu0_lpcg 0>;
fix lpcg index
> + clock-names = "ipg", "cnt";
> + power-domains = <&pd IMX_SC_R_PERF>;
> + };
> +
> + db_pmu0_lpcg: clock-controller@5cae0000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5cae0000 0x10000>;
> + #clock-cells = <1>;
> + clocks = <&db_ipg_clk>, <&db_ipg_clk>;
> + bit-offset = <0 16>;
fix lpcg index by using macro
> + clock-output-names = "perf_lpcg_cnt_clk",
> + "perf_lpcg_ipg_clk";
> + power-domains = <&pd IMX_SC_R_PERF>;
> + };
> +};
> --
> 2.31.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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next prev parent reply other threads:[~2021-05-18 7:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 17:11 [PATCH 0/7] arm64: dts: freescale: Add i.MX8DXL support abelvesa
2021-05-17 17:11 ` [PATCH 1/7] arm64: dts: freescale: Add the top level dtsi support for imx8dxl abelvesa
2021-05-18 7:35 ` Dong Aisheng
2021-06-02 9:29 ` Abel Vesa
2021-05-17 17:12 ` [PATCH 2/7] arm64: dts: imx8-ss-lsio: Add mu5a mailbox abelvesa
2021-05-18 7:50 ` Dong Aisheng
2021-06-02 9:48 ` Abel Vesa
2021-05-17 17:12 ` [PATCH 3/7] arm64: dts: freescale: Add adma subsystem dtsi for imx8dxl abelvesa
2021-05-18 7:52 ` Dong Aisheng
2021-06-02 11:28 ` Abel Vesa
2021-05-17 17:12 ` [PATCH 4/7] arm64: dts: freescale: Add the imx8dxl connectivity subsys dtsi abelvesa
2021-05-18 7:53 ` Dong Aisheng
2021-05-17 17:12 ` [PATCH 5/7] arm64: dts: freescale: Add ddr subsys dtsi for imx8dxl abelvesa
2021-05-18 7:54 ` Dong Aisheng [this message]
2021-05-17 17:12 ` [PATCH 6/7] arm64: dts: freescale: Add lsio " abelvesa
2021-05-18 7:55 ` Dong Aisheng
2021-05-17 17:12 ` [PATCH 7/7] arm64: dts: imx8dxl: Add i.MX8DXL evk board support abelvesa
2021-05-18 7:57 ` Dong Aisheng
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