From: Andrey Konovalov <andreyknvl@google.com>
To: Peter Collingbourne <pcc@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Kostya Serebryany <kcc@google.com>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
linux-api@vger.kernel.org,
Vincenzo Frascino <vincenzo.frascino@arm.com>,
Will Deacon <will@kernel.org>, Dave Martin <Dave.Martin@arm.com>,
Evgenii Stepanov <eugenis@google.com>
Subject: Re: [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled
Date: Mon, 23 Nov 2020 19:20:47 +0100 [thread overview]
Message-ID: <CAAeHK+wvFC+Nx+1==2oidsm=3xFC_0n9jNarnTB2j5eq5CTdkQ@mail.gmail.com> (raw)
In-Reply-To: <20f64e26fc8a1309caa446fffcb1b4e2fe9e229f.1605952129.git.pcc@google.com>
On Sat, Nov 21, 2020 at 10:59 AM Peter Collingbourne <pcc@google.com> wrote:
>
> On hardware supporting pointer authentication, we previously ended up
> enabling TBI on instruction accesses when tag-based ASAN was enabled,
> but this was costing us 8 bits of PAC entropy, which was unnecessary
> since tag-based ASAN does not require TBI on instruction accesses. Get
> them back by setting TCR_EL1.TBID1.
>
> Signed-off-by: Peter Collingbourne <pcc@google.com>
> Link: https://linux-review.googlesource.com/id/I3dded7824be2e70ea64df0aabab9598d5aebfcc4
> ---
> arch/arm64/include/asm/pgtable-hwdef.h | 1 +
> arch/arm64/mm/proc.S | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index 01a96d07ae74..42442a0ae2ab 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -260,6 +260,7 @@
> #define TCR_TBI1 (UL(1) << 38)
> #define TCR_HA (UL(1) << 39)
> #define TCR_HD (UL(1) << 40)
> +#define TCR_TBID1 (UL(1) << 52)
> #define TCR_NFD0 (UL(1) << 53)
> #define TCR_NFD1 (UL(1) << 54)
> #define TCR_E0PD0 (UL(1) << 55)
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 23c326a06b2d..97a97a61a8dc 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -40,7 +40,7 @@
> #define TCR_CACHE_FLAGS TCR_IRGN_WBWA | TCR_ORGN_WBWA
>
> #ifdef CONFIG_KASAN_SW_TAGS
> -#define TCR_KASAN_FLAGS TCR_TBI1
> +#define TCR_KASAN_FLAGS TCR_TBI1 | TCR_TBID1
> #else
> #define TCR_KASAN_FLAGS 0
> #endif
> --
> 2.29.2.454.gaff20da3a2-goog
>
Reviewed-by: Andrey Konovalov <andreyknvl@google.com>
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next prev parent reply other threads:[~2020-11-23 18:21 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-21 9:59 [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled Peter Collingbourne
2020-11-21 9:59 ` [PATCH 2/2] arm64: allow TCR_EL1.TBID0 to be configured Peter Collingbourne
2020-11-24 18:47 ` Catalin Marinas
2020-11-24 19:18 ` Peter Collingbourne
2020-11-25 14:37 ` Szabolcs Nagy
2021-06-15 23:41 ` Peter Collingbourne
2021-06-16 12:55 ` Szabolcs Nagy
2021-06-22 5:13 ` Peter Collingbourne
2020-11-23 18:20 ` Andrey Konovalov [this message]
2020-11-25 18:54 ` [PATCH 1/2] kasan: arm64: set TCR_EL1.TBID1 when enabled Catalin Marinas
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