[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Vikas Sajjan]

Rebased on
1] Kukjin Kim's tree, for-next branch
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
2] Pankaj Dubey's v9 PMU patchset
http://www.spinics.net/lists/arm-kernel/msg367939.html

changes since v8:
	- addressed abhilash's comments to remove the restoring of 
	  the CPU0 low power state register, since it will taken care in mcpm s2r
	  patch from abhilash.

changes since v7:
	- rebased on pankaj's latest patchset.

changes since v6:
	- rebased on 3.17.rc1.

changes since v5:
	- Refactored pm.c to use DT based lookup as suggested by Tomasz Figa.

changes since v4:
	- Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset

changes since v3:
Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz,
Tomasz Figa and Alim Akhtar:
        - Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
        - Merged exynos5420_set_core_flag function into powerdown_conf.
        - Removed XXTI_DURATION3 register setting.
        - Updated the commit message and ordered the clock registers in clock
          patch.
        - Removed the code for SYS_DISP1_BLK_CFG handling.
        - Modified SoC checks to A9 specific checks in PM code.
        - Updated some comments in the code and added macros for register offsets.
        - Fixed code which was changing pad retention code for older SoCs.

changes since v2:
        - Addressed comments from Tomasz figa
        - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
        - dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420",
          will be sent separately.

changes since v1:
        - Addressed comments from Tomasz figa.
        - restructured/consolidated as per Tomasz figa's PM consolidations for exynos

Tested on Kukjin Kim's tree, for-next branch + 
1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK

on Exynos5420 based chromebook (peach-pit board)

Below procedures were followed to test S2R:
Procedure A:
	1. make multi_v7_defconfig 
	2  enable MCPM for 5420
	3. enable S3C RTC
	5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
Procedure B:
	1. make exynos_defconfig 
	4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state

Abhilash Kesavan (1):
  ARM: exynos5: Add PMU support for 5420

Vikas Sajjan (1):
  ARM: exynos5: Add Suspend-to-RAM support for 5420

 arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/suspend.c  |  151 +++++++++++++++++++-
 3 files changed, 663 insertions(+), 2 deletions(-)

-- 
1.7.9.5

[PATCH v9 1/2] ARM: exynos5: Add PMU support for 5420

[Vikas Sajjan]

From: Abhilash Kesavan <a.kesavan@samsung.com>

Adds intial PMU settings for exynos5420. This is required for
future S2R and Switching support.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
---
 arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
 arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
 2 files changed, 514 insertions(+)

diff --git a/arch/arm/mach-exynos/pmu.c b/arch/arm/mach-exynos/pmu.c
index b68cd29a..4110281 100644
--- a/arch/arm/mach-exynos/pmu.c
+++ b/arch/arm/mach-exynos/pmu.c
@@ -12,6 +12,8 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
+#include <linux/delay.h>
+
 
 #include "exynos-pmu.h"
 #include "regs-pmu.h"
@@ -348,6 +350,151 @@ static const struct exynos_pmu_conf exynos5250_pmu_config[] = {
 	{ PMU_TABLE_END,},
 };
 
+static struct exynos_pmu_conf exynos5420_pmu_config[] = {
+	/* { .offset = offset, .val = { AFTR, LPA, SLEEP } */
+	{ EXYNOS5_ARM_CORE0_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_CORE1_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_LOCAL_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ARM_CORE1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_ARM_CORE2_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_ARM_CORE3_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE0_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE1_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE2_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_CORE3_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG,	{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ISP_ARM_SYS_PWR_REG,				{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_ARM_COMMON_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_COMMON_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_ARM_L2_SYS_PWR_REG,				{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_KFC_L2_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_CMU_ACLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SCLKSTOP_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_CMU_RESET_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_DRAM_FREQ_DOWN_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLOFF_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_DDRPHY_DLLLOCK_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_APLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_VPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_EPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_BPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_CPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_MPLLUSER_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_BPLLUSER_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_TOP_BUS_SYS_PWR_REG,				{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYS_PWR_REG,			{ 0x1, 0x1, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYS_PWR_REG,				{ 0x3, 0x3, 0x0} },
+	{ EXYNOS5_TOP_BUS_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_TOP_RETENTION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_TOP_PWR_SYSMEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x0} },
+	{ EXYNOS5_LOGIC_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYS_PWR_REG,			{ 0x1, 0x0, 0x1} },
+	{ EXYNOS5_LOGIC_RESET_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_OSCCLK_GATE_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_INTRAM_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5420_INTROM_MEM_SYS_PWR_REG,			{ 0x3, 0x0, 0x3} },
+	{ EXYNOS5_PAD_RETENTION_DRAM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_RETENTION_MAU_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG,		{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG,	{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_PAD_ISOLATION_SYSMEM_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_PAD_ALV_SEL_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_XUSBXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_XXTI_SYS_PWR_REG,				{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_EXT_REGULATOR_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYS_PWR_REG,			{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GPIO_MODE_SYSMEM_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_GPIO_MODE_MAU_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_RESET_SYS_PWR_REG,			{ 0x1, 0x1, 0x0} },
+	{ EXYNOS5_TOP_ASB_ISOLATION_SYS_PWR_REG,		{ 0x1, 0x0, 0x0} },
+	{ EXYNOS5_GSCL_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_ISP_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_MFC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_G3D_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_DISP1_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_MAU_SYS_PWR_REG,				{ 0x7, 0x7, 0x0} },
+	{ EXYNOS5420_G2D_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_MSC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_FSYS_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_FSYS2_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_PSGEN_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_PERIC_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5420_WCORE_SYS_PWR_REG,				{ 0x7, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_MFC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_MFC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_MFC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,			{ 0x0, 0x0, 0x0} },
+	{ EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,		{ 0x0, 0x0, 0x0} },
+	{ PMU_TABLE_END,},
+};
+
 static unsigned int const exynos5_list_both_cnt_feed[] = {
 	EXYNOS5_ARM_CORE0_OPTION,
 	EXYNOS5_ARM_CORE1_OPTION,
@@ -368,6 +515,75 @@ static unsigned int const exynos5_list_diable_wfi_wfe[] = {
 	EXYNOS5_ISP_ARM_OPTION,
 };
 
+static unsigned int const exynos5420_list_disable_pmu_reg[] = {
+	EXYNOS5_CMU_CLKSTOP_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_CLKSTOP_G3D_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG,
+	EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_SYSCLK_G3D_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG,
+	EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_GSCL_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_ISP_SYS_PWR_REG,
+	EXYNOS5_CMU_RESET_G3D_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG,
+	EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG,
+};
+
+static void exynos5_power_off(void)
+{
+	unsigned int tmp;
+
+	pr_info("Power down.\n");
+	tmp = pmu_raw_readl(EXYNOS_PS_HOLD_CONTROL);
+	tmp ^= (1 << 8);
+	pmu_raw_writel(tmp, EXYNOS_PS_HOLD_CONTROL);
+
+	/* Wait a little so we don't give a false warning below */
+	mdelay(100);
+
+	pr_err("Power down failed, please power off system manually.\n");
+	while (1)
+		;
+}
+
+void exynos5420_powerdown_conf(enum sys_powerdown mode)
+{
+	u32 this_cluster;
+
+	this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+
+	/*
+	 * set the cluster id to IROM register to ensure that we wake
+	 * up with the current cluster.
+	 */
+	pmu_raw_writel(this_cluster, EXYNOS_IROM_DATA2);
+}
+
+
 static void exynos5_powerdown_conf(enum sys_powerdown mode)
 {
 	unsigned int i;
@@ -439,6 +655,68 @@ static void exynos5250_pmu_init(void)
 	pmu_raw_writel(value, EXYNOS5_MASK_WDTRESET_REQUEST);
 }
 
+static void exynos5420_pmu_init(void)
+{
+	unsigned int value;
+	int i;
+
+	/*
+	 * Set the CMU_RESET, CMU_SYSCLK and CMU_CLKSTOP registers
+	 * for local power blocks to Low initially as per Table 8-4:
+	 * "System-Level Power-Down Configuration Registers".
+	 */
+	for (i = 0; i < ARRAY_SIZE(exynos5420_list_disable_pmu_reg); i++)
+		pmu_raw_writel(0, exynos5420_list_disable_pmu_reg[i]);
+
+	/* Enable USE_STANDBY_WFI for all CORE */
+	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL, S5P_CENTRAL_SEQ_OPTION);
+
+	value  = pmu_raw_readl(EXYNOS_L2_OPTION(0));
+	value &= ~EXYNOS5_USE_RETENTION;
+	pmu_raw_writel(value, EXYNOS_L2_OPTION(0));
+
+	value = pmu_raw_readl(EXYNOS_L2_OPTION(1));
+	value &= ~EXYNOS5_USE_RETENTION;
+	pmu_raw_writel(value, EXYNOS_L2_OPTION(1));
+
+	/*
+	 * If L2_COMMON is turned off, clocks related to ATB async
+	 * bridge are gated. Thus, when ISP power is gated, LPI
+	 * may get stuck.
+	 */
+	value = pmu_raw_readl(EXYNOS5420_LPI_MASK);
+	value |= EXYNOS5420_ATB_ISP_ARM;
+	pmu_raw_writel(value, EXYNOS5420_LPI_MASK);
+
+	value  = pmu_raw_readl(EXYNOS5420_LPI_MASK1);
+	value |= EXYNOS5420_ATB_KFC;
+	pmu_raw_writel(value, EXYNOS5420_LPI_MASK1);
+
+	/* Prevent issue of new bus request from L2 memory */
+	value = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
+	value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+	pmu_raw_writel(value, EXYNOS5420_ARM_COMMON_OPTION);
+
+	value = pmu_raw_readl(EXYNOS5420_KFC_COMMON_OPTION);
+	value |= EXYNOS5_SKIP_DEACTIVATE_ACEACP_IN_PWDN;
+	pmu_raw_writel(value, EXYNOS5420_KFC_COMMON_OPTION);
+
+	/* This setting is to reduce suspend/resume time */
+	pmu_raw_writel(DUR_WAIT_RESET, EXYNOS5420_LOGIC_RESET_DURATION3);
+
+	/* Serialized CPU wakeup of Eagle */
+	pmu_raw_writel(SPREAD_ENABLE, EXYNOS5420_ARM_INTR_SPREAD_ENABLE);
+
+	pmu_raw_writel(SPREAD_USE_STANDWFI,
+			EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI);
+
+	pmu_raw_writel(0x1, EXYNOS5420_UP_SCHEDULER);
+
+	pm_power_off = exynos5_power_off;
+	pr_info("EXYNOS5420 PMU initialized\n");
+}
+
+
 static const struct exynos_pmu_data exynos4210_pmu_data = {
 	.pmu_config	= exynos4210_pmu_config,
 };
@@ -458,6 +736,12 @@ static const struct exynos_pmu_data exynos5250_pmu_data = {
 	.powerdown_conf	= exynos5_powerdown_conf,
 };
 
+static struct exynos_pmu_data exynos5420_pmu_data = {
+	.pmu_config	= exynos5420_pmu_config,
+	.pmu_init	= exynos5420_pmu_init,
+	.powerdown_conf	= exynos5420_powerdown_conf,
+};
+
 /*
  * PMU platform driver and devicetree bindings.
  */
@@ -474,6 +758,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = {
 	}, {
 		.compatible = "samsung,exynos5250-pmu",
 		.data = &exynos5250_pmu_data,
+	}, {
+		.compatible = "samsung,exynos5420-pmu",
+		.data = &exynos5420_pmu_data,
 	},
 	{ /*sentinel*/ },
 };
diff --git a/arch/arm/mach-exynos/regs-pmu.h b/arch/arm/mach-exynos/regs-pmu.h
index 322f132..46b973b 100644
--- a/arch/arm/mach-exynos/regs-pmu.h
+++ b/arch/arm/mach-exynos/regs-pmu.h
@@ -38,6 +38,7 @@
 #define S5P_INFORM7				0x081C
 #define S5P_PMU_SPARE3				0x090C
 
+#define EXYNOS_IROM_DATA2			0x0988
 #define S5P_ARM_CORE0_LOWPWR			0x1000
 #define S5P_DIS_IRQ_CORE0			0x1004
 #define S5P_DIS_IRQ_CENTRAL0			0x1008
@@ -120,6 +121,31 @@
 #define EXYNOS_COMMON_OPTION(_nr)		\
 			(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
 
+#define EXYNOS_CORE_LOCAL_PWR_EN		0x3
+
+#define EXYNOS_ARM_COMMON_STATUS		0x2504
+#define EXYNOS_COMMON_OPTION(_nr)		\
+			(EXYNOS_COMMON_CONFIGURATION(_nr) + 0x8)
+
+#define EXYNOS_ARM_L2_CONFIGURATION		0x2600
+#define EXYNOS_L2_CONFIGURATION(_nr)		\
+			(EXYNOS_ARM_L2_CONFIGURATION + ((_nr) * 0x80))
+#define EXYNOS_L2_STATUS(_nr)			\
+			(EXYNOS_L2_CONFIGURATION(_nr) + 0x4)
+#define EXYNOS_L2_OPTION(_nr)			\
+			(EXYNOS_L2_CONFIGURATION(_nr) + 0x8)
+#define EXYNOS_L2_COMMON_PWR_EN			0x3
+
+#define EXYNOS_ARM_CORE_X_STATUS_OFFSET		0x4
+
+#define EXYNOS5_APLL_SYSCLK_CONFIGURATION	0x2A00
+#define EXYNOS5_APLL_SYSCLK_STATUS		0x2A04
+
+#define EXYNOS5_ARM_L2_OPTION			0x2608
+#define EXYNOS5_USE_RETENTION			BIT(4)
+
+#define EXYNOS5_L2RSTDISABLE_VALUE		BIT(3)
+
 #define S5P_PAD_RET_MAUDIO_OPTION		0x3028
 #define S5P_PAD_RET_GPIO_OPTION			0x3108
 #define S5P_PAD_RET_UART_OPTION			0x3128
@@ -193,6 +219,7 @@
 #define EXYNOS5_AUTO_WDTRESET_DISABLE				0x0408
 #define EXYNOS5_MASK_WDTRESET_REQUEST				0x040C
 
+#define EXYNOS5_USE_RETENTION			BIT(4)
 #define EXYNOS5_SYS_WDTRESET					(1 << 20)
 
 #define EXYNOS5_ARM_CORE0_SYS_PWR_REG				0x1000
@@ -332,4 +359,204 @@ static inline unsigned int exynos_pmu_cpunr(unsigned int mpidr)
 		 + MPIDR_AFFINITY_LEVEL(mpidr, 0));
 }
 
+/* Only for EXYNOS5420 */
+#define EXYNOS5420_ISP_ARM_OPTION				0x2488
+#define EXYNOS5420_L2RSTDISABLE_VALUE				BIT(3)
+
+#define EXYNOS5420_LPI_MASK					0x0004
+#define EXYNOS5420_LPI_MASK1					0x0008
+#define EXYNOS5420_UFS						BIT(8)
+#define EXYNOS5420_ATB_KFC					BIT(13)
+#define EXYNOS5420_ATB_ISP_ARM					BIT(19)
+#define EXYNOS5420_EMULATION					BIT(31)
+#define ATB_ISP_ARM						BIT(12)
+#define ATB_KFC							BIT(13)
+#define ATB_NOC							BIT(14)
+
+#define EXYNOS5420_ARM_INTR_SPREAD_ENABLE			0x0100
+#define EXYNOS5420_ARM_INTR_SPREAD_USE_STANDBYWFI		0x0104
+#define EXYNOS5420_UP_SCHEDULER					0x0120
+#define SPREAD_ENABLE						0xF
+#define SPREAD_USE_STANDWFI					0xF
+
+#define EXYNOS5420_BB_CON1					0x0784
+#define EXYNOS5420_BB_SEL_EN					BIT(31)
+#define EXYNOS5420_BB_PMOS_EN					BIT(7)
+#define EXYNOS5420_BB_1300X					0XF
+
+#define EXYNOS5420_ARM_CORE2_SYS_PWR_REG			0x1020
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_LOCAL_SYS_PWR_REG		0x1024
+#define EXYNOS5420_DIS_IRQ_ARM_CORE2_CENTRAL_SYS_PWR_REG	0x1028
+#define EXYNOS5420_ARM_CORE3_SYS_PWR_REG			0x1030
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_LOCAL_SYS_PWR_REG		0x1034
+#define EXYNOS5420_DIS_IRQ_ARM_CORE3_CENTRAL_SYS_PWR_REG	0x1038
+#define EXYNOS5420_KFC_CORE0_SYS_PWR_REG			0x1040
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_LOCAL_SYS_PWR_REG		0x1044
+#define EXYNOS5420_DIS_IRQ_KFC_CORE0_CENTRAL_SYS_PWR_REG	0x1048
+#define EXYNOS5420_KFC_CORE1_SYS_PWR_REG			0x1050
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_LOCAL_SYS_PWR_REG		0x1054
+#define EXYNOS5420_DIS_IRQ_KFC_CORE1_CENTRAL_SYS_PWR_REG	0x1058
+#define EXYNOS5420_KFC_CORE2_SYS_PWR_REG			0x1060
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_LOCAL_SYS_PWR_REG		0x1064
+#define EXYNOS5420_DIS_IRQ_KFC_CORE2_CENTRAL_SYS_PWR_REG	0x1068
+#define EXYNOS5420_KFC_CORE3_SYS_PWR_REG			0x1070
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_LOCAL_SYS_PWR_REG		0x1074
+#define EXYNOS5420_DIS_IRQ_KFC_CORE3_CENTRAL_SYS_PWR_REG	0x1078
+#define EXYNOS5420_ISP_ARM_SYS_PWR_REG				0x1090
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_LOCAL_SYS_PWR_REG		0x1094
+#define EXYNOS5420_DIS_IRQ_ISP_ARM_CENTRAL_SYS_PWR_REG		0x1098
+#define EXYNOS5420_ARM_COMMON_SYS_PWR_REG			0x10A0
+#define EXYNOS5420_KFC_COMMON_SYS_PWR_REG			0x10B0
+#define EXYNOS5420_KFC_L2_SYS_PWR_REG				0x10D0
+#define EXYNOS5420_DPLL_SYSCLK_SYS_PWR_REG			0x1158
+#define EXYNOS5420_IPLL_SYSCLK_SYS_PWR_REG			0x115C
+#define EXYNOS5420_KPLL_SYSCLK_SYS_PWR_REG			0x1160
+#define EXYNOS5420_RPLL_SYSCLK_SYS_PWR_REG                      0x1174
+#define EXYNOS5420_SPLL_SYSCLK_SYS_PWR_REG                      0x1178
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR_REG                       0x11B8
+#define EXYNOS5420_INTROM_MEM_SYS_PWR_REG                       0x11BC
+#define EXYNOS5420_ONENANDXL_MEM_SYS_PWR			0x11C0
+#define EXYNOS5420_USBDEV_MEM_SYS_PWR				0x11CC
+#define EXYNOS5420_USBDEV1_MEM_SYS_PWR				0x11D0
+#define EXYNOS5420_SDMMC_MEM_SYS_PWR				0x11D4
+#define EXYNOS5420_CSSYS_MEM_SYS_PWR				0x11D8
+#define EXYNOS5420_SECSS_MEM_SYS_PWR				0x11DC
+#define EXYNOS5420_ROTATOR_MEM_SYS_PWR				0x11E0
+#define EXYNOS5420_INTRAM_MEM_SYS_PWR				0x11E4
+#define EXYNOS5420_INTROM_MEM_SYS_PWR				0x11E8
+#define EXYNOS5420_PAD_RETENTION_JTAG_SYS_PWR_REG		0x1208
+#define EXYNOS5420_PAD_RETENTION_DRAM_SYS_PWR_REG		0x1210
+#define EXYNOS5420_PAD_RETENTION_UART_SYS_PWR_REG		0x1214
+#define EXYNOS5420_PAD_RETENTION_MMC0_SYS_PWR_REG		0x1218
+#define EXYNOS5420_PAD_RETENTION_MMC1_SYS_PWR_REG		0x121C
+#define EXYNOS5420_PAD_RETENTION_MMC2_SYS_PWR_REG		0x1220
+#define EXYNOS5420_PAD_RETENTION_HSI_SYS_PWR_REG		0x1224
+#define EXYNOS5420_PAD_RETENTION_EBIA_SYS_PWR_REG		0x1228
+#define EXYNOS5420_PAD_RETENTION_EBIB_SYS_PWR_REG		0x122C
+#define EXYNOS5420_PAD_RETENTION_SPI_SYS_PWR_REG		0x1230
+#define EXYNOS5420_PAD_RETENTION_DRAM_COREBLK_SYS_PWR_REG	0x1234
+#define EXYNOS5420_DISP1_SYS_PWR_REG				0x1410
+#define EXYNOS5420_MAU_SYS_PWR_REG				0x1414
+#define EXYNOS5420_G2D_SYS_PWR_REG				0x1418
+#define EXYNOS5420_MSC_SYS_PWR_REG				0x141C
+#define EXYNOS5420_FSYS_SYS_PWR_REG				0x1420
+#define EXYNOS5420_FSYS2_SYS_PWR_REG				0x1424
+#define EXYNOS5420_PSGEN_SYS_PWR_REG				0x1428
+#define EXYNOS5420_PERIC_SYS_PWR_REG				0x142C
+#define EXYNOS5420_WCORE_SYS_PWR_REG				0x1430
+#define EXYNOS5420_CMU_CLKSTOP_DISP1_SYS_PWR_REG		0x1490
+#define EXYNOS5420_CMU_CLKSTOP_MAU_SYS_PWR_REG			0x1494
+#define EXYNOS5420_CMU_CLKSTOP_G2D_SYS_PWR_REG			0x1498
+#define EXYNOS5420_CMU_CLKSTOP_MSC_SYS_PWR_REG			0x149C
+#define EXYNOS5420_CMU_CLKSTOP_FSYS_SYS_PWR_REG			0x14A0
+#define EXYNOS5420_CMU_CLKSTOP_FSYS2_SYS_PWR_REG		0x14A4
+#define EXYNOS5420_CMU_CLKSTOP_PSGEN_SYS_PWR_REG		0x14A8
+#define EXYNOS5420_CMU_CLKSTOP_PERIC_SYS_PWR_REG		0x14AC
+#define EXYNOS5420_CMU_CLKSTOP_WCORE_SYS_PWR_REG		0x14B0
+#define EXYNOS5420_CMU_SYSCLK_TOPPWR_SYS_PWR_REG		0x14BC
+#define EXYNOS5420_CMU_SYSCLK_DISP1_SYS_PWR_REG			0x14D0
+#define EXYNOS5420_CMU_SYSCLK_MAU_SYS_PWR_REG			0x14D4
+#define EXYNOS5420_CMU_SYSCLK_G2D_SYS_PWR_REG			0x14D8
+#define EXYNOS5420_CMU_SYSCLK_MSC_SYS_PWR_REG			0x14DC
+#define EXYNOS5420_CMU_SYSCLK_FSYS_SYS_PWR_REG			0x14E0
+#define EXYNOS5420_CMU_SYSCLK_FSYS2_SYS_PWR_REG			0x14E4
+#define EXYNOS5420_CMU_SYSCLK_PSGEN_SYS_PWR_REG			0x14E8
+#define EXYNOS5420_CMU_SYSCLK_PERIC_SYS_PWR_REG			0x14EC
+#define EXYNOS5420_CMU_SYSCLK_WCORE_SYS_PWR_REG			0x14F0
+#define EXYNOS5420_CMU_SYSCLK_SYSMEM_TOPPWR_SYS_PWR_REG		0x14F4
+#define EXYNOS5420_CMU_RESET_FSYS2_SYS_PWR_REG			0x1570
+#define EXYNOS5420_CMU_RESET_PSGEN_SYS_PWR_REG			0x1574
+#define EXYNOS5420_CMU_RESET_PERIC_SYS_PWR_REG			0x1578
+#define EXYNOS5420_CMU_RESET_WCORE_SYS_PWR_REG			0x157C
+#define EXYNOS5420_CMU_RESET_DISP1_SYS_PWR_REG			0x1590
+#define EXYNOS5420_CMU_RESET_MAU_SYS_PWR_REG			0x1594
+#define EXYNOS5420_CMU_RESET_G2D_SYS_PWR_REG			0x1598
+#define EXYNOS5420_CMU_RESET_MSC_SYS_PWR_REG			0x159C
+#define EXYNOS5420_CMU_RESET_FSYS_SYS_PWR_REG			0x15A0
+#define EXYNOS5420_SFR_AXI_CGDIS1				0x15E4
+#define EXYNOS_ARM_CORE2_CONFIGURATION				0x2100
+#define EXYNOS5420_ARM_CORE2_OPTION				0x2108
+#define EXYNOS_ARM_CORE3_CONFIGURATION				0x2180
+#define EXYNOS5420_ARM_CORE3_OPTION				0x2188
+#define EXYNOS5420_ARM_COMMON_STATUS				0x2504
+#define EXYNOS5420_ARM_COMMON_OPTION				0x2508
+#define EXYNOS5420_KFC_COMMON_STATUS				0x2584
+#define EXYNOS5420_KFC_COMMON_OPTION				0x2588
+#define EXYNOS5420_LOGIC_RESET_DURATION3			0x2D1C
+
+#define EXYNOS5420_PAD_RET_GPIO_OPTION				0x30C8
+#define EXYNOS5420_PAD_RET_UART_OPTION				0x30E8
+#define EXYNOS5420_PAD_RET_MMCA_OPTION				0x3108
+#define EXYNOS5420_PAD_RET_MMCB_OPTION				0x3128
+#define EXYNOS5420_PAD_RET_MMCC_OPTION				0x3148
+#define EXYNOS5420_PAD_RET_HSI_OPTION				0x3168
+#define EXYNOS5420_PAD_RET_SPI_OPTION				0x31C8
+#define EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION			0x31E8
+#define EXYNOS_PAD_RET_DRAM_OPTION				0x3008
+#define EXYNOS_PAD_RET_MAUDIO_OPTION				0x3028
+#define EXYNOS_PAD_RET_JTAG_OPTION				0x3048
+#define EXYNOS_PAD_RET_GPIO_OPTION				0x3108
+#define EXYNOS_PAD_RET_UART_OPTION				0x3128
+#define EXYNOS_PAD_RET_MMCA_OPTION				0x3148
+#define EXYNOS_PAD_RET_MMCB_OPTION				0x3168
+#define EXYNOS_PAD_RET_EBIA_OPTION				0x3188
+#define EXYNOS_PAD_RET_EBIB_OPTION				0x31A8
+
+#define EXYNOS_PS_HOLD_CONTROL					0x330C
+
+/* For SYS_PWR_REG */
+#define EXYNOS_SYS_PWR_CFG					BIT(0)
+
+#define EXYNOS5420_MFC_CONFIGURATION				0x4060
+#define EXYNOS5420_MFC_STATUS					0x4064
+#define EXYNOS5420_MFC_OPTION					0x4068
+#define EXYNOS5420_G3D_CONFIGURATION				0x4080
+#define EXYNOS5420_G3D_STATUS					0x4084
+#define EXYNOS5420_G3D_OPTION					0x4088
+#define EXYNOS5420_DISP0_CONFIGURATION				0x40A0
+#define EXYNOS5420_DISP0_STATUS					0x40A4
+#define EXYNOS5420_DISP0_OPTION					0x40A8
+#define EXYNOS5420_DISP1_CONFIGURATION				0x40C0
+#define EXYNOS5420_DISP1_STATUS					0x40C4
+#define EXYNOS5420_DISP1_OPTION					0x40C8
+#define EXYNOS5420_MAU_CONFIGURATION				0x40E0
+#define EXYNOS5420_MAU_STATUS					0x40E4
+#define EXYNOS5420_MAU_OPTION					0x40E8
+#define EXYNOS5420_FSYS2_OPTION					0x4168
+#define EXYNOS5420_PSGEN_OPTION					0x4188
+
+/* For EXYNOS_CENTRAL_SEQ_OPTION */
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE0			BIT(16)
+#define EXYNOS5_USE_STANDBYWFI_ARM_CORE1			BUT(17)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE0			BIT(24)
+#define EXYNOS5_USE_STANDBYWFE_ARM_CORE1			BIT(25)
+
+#define EXYNOS5420_ARM_USE_STANDBY_WFI0				BIT(4)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI1				BIT(5)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI2				BIT(6)
+#define EXYNOS5420_ARM_USE_STANDBY_WFI3				BIT(7)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI0				BIT(8)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI1				BIT(9)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI2				BIT(10)
+#define EXYNOS5420_KFC_USE_STANDBY_WFI3				BIT(11)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE0				BIT(16)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE1				BIT(17)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE2				BIT(18)
+#define EXYNOS5420_ARM_USE_STANDBY_WFE3				BIT(19)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE0				BIT(20)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE1				BIT(21)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE2				BIT(22)
+#define EXYNOS5420_KFC_USE_STANDBY_WFE3				BIT(23)
+
+#define DUR_WAIT_RESET				0xF
+
+#define EXYNOS5420_USE_STANDBY_WFI_ALL	(EXYNOS5420_ARM_USE_STANDBY_WFI0    \
+					 | EXYNOS5420_ARM_USE_STANDBY_WFI1  \
+					 | EXYNOS5420_ARM_USE_STANDBY_WFI2  \
+					 | EXYNOS5420_ARM_USE_STANDBY_WFI3  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI0  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI1  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI2  \
+					 | EXYNOS5420_KFC_USE_STANDBY_WFI3)
+
 #endif /* __ASM_ARCH_REGS_PMU_H */
-- 
1.7.9.5

[PATCH v9 1/2] ARM: exynos5: Add PMU support for 5420

[Javier Martinez Canillas]

Hellos Vikas,

On Tue, Oct 7, 2014 at 11:22 AM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
> From: Abhilash Kesavan <a.kesavan@samsung.com>
>
> Adds intial PMU settings for exynos5420. This is required for
> future S2R and Switching support.
>
> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
> ---
>  arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
>  2 files changed, 514 insertions(+)

S2R is working on my Exynos5420 Peach Pit Chromebook with your series:

Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

Best regards,
Javier

[PATCH v9 1/2] ARM: exynos5: Add PMU support for 5420

[Vikas Sajjan]

Hi Javier,

On Tue, Oct 7, 2014 at 6:17 PM, Javier Martinez Canillas
<javier@dowhile0.org> wrote:
> Hellos Vikas,
>
> On Tue, Oct 7, 2014 at 11:22 AM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
>> From: Abhilash Kesavan <a.kesavan@samsung.com>
>>
>> Adds intial PMU settings for exynos5420. This is required for
>> future S2R and Switching support.
>>
>> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
>> ---
>>  arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
>>  arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
>>  2 files changed, 514 insertions(+)
>
> S2R is working on my Exynos5420 Peach Pit Chromebook with your series:
>
> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>


Thanks for testing.



> Best regards,
> Javier

[PATCH v9 2/2] ARM: exynos5: Add Suspend-to-RAM support for 5420

[Vikas Sajjan]

Adds Suspend-to-RAM support for EXYNOS5420

Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
---
 arch/arm/mach-exynos/suspend.c |  151 +++++++++++++++++++++++++++++++++++++++-
 1 file changed, 149 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index 079d999..8cef614 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -39,6 +39,8 @@
 
 #define REG_TABLE_END (-1U)
 
+#define EXYNOS5420_CPU_STATE	0x28
+
 /**
  * struct exynos_wkup_irq - Exynos GIC to PMU IRQ mapping
  * @hwirq: Hardware IRQ signal of the GIC
@@ -77,6 +79,9 @@ struct exynos_pm_data {
 
 struct exynos_pm_data *pm_data;
 
+static int exynos5420_cpu_state;
+static unsigned int exynos_pmu_spare3;
+
 /*
  * GIC wake-up support
  */
@@ -106,6 +111,23 @@ unsigned int exynos_release_ret_regs[] = {
 	REG_TABLE_END,
 };
 
+unsigned int exynos5420_release_ret_regs[] = {
+	EXYNOS_PAD_RET_DRAM_OPTION,
+	EXYNOS_PAD_RET_MAUDIO_OPTION,
+	EXYNOS_PAD_RET_JTAG_OPTION,
+	EXYNOS5420_PAD_RET_GPIO_OPTION,
+	EXYNOS5420_PAD_RET_UART_OPTION,
+	EXYNOS5420_PAD_RET_MMCA_OPTION,
+	EXYNOS5420_PAD_RET_MMCB_OPTION,
+	EXYNOS5420_PAD_RET_MMCC_OPTION,
+	EXYNOS5420_PAD_RET_HSI_OPTION,
+	EXYNOS_PAD_RET_EBIA_OPTION,
+	EXYNOS_PAD_RET_EBIB_OPTION,
+	EXYNOS5420_PAD_RET_SPI_OPTION,
+	EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
+	REG_TABLE_END,
+};
+
 static int exynos_irq_set_wake(struct irq_data *data, unsigned int state)
 {
 	const struct exynos_wkup_irq *wkup_irq;
@@ -136,11 +158,22 @@ static int exynos_cpu_do_idle(void)
 	pr_info("Failed to suspend the system\n");
 	return 1; /* Aborting suspend */
 }
-
-static int exynos_cpu_suspend(unsigned long arg)
+static void exynos_flush_cache_all(void)
 {
 	flush_cache_all();
 	outer_flush_all();
+}
+
+static int exynos_cpu_suspend(unsigned long arg)
+{
+	exynos_flush_cache_all();
+	return exynos_cpu_do_idle();
+}
+
+static int exynos5420_cpu_suspend(unsigned long arg)
+{
+	exynos_flush_cache_all();
+	__raw_writel(0x0, sysram_base_addr + EXYNOS5420_CPU_STATE);
 	return exynos_cpu_do_idle();
 }
 
@@ -175,6 +208,50 @@ static void exynos_pm_prepare(void)
 	exynos_pm_enter_sleep_mode();
 }
 
+static void exynos5420_pm_prepare(void)
+{
+	unsigned int tmp;
+
+	/* Set wake-up mask registers */
+	exynos_pm_set_wakeup_mask();
+
+	s3c_pm_do_save(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+
+	exynos_pmu_spare3 = pmu_raw_readl(S5P_PMU_SPARE3);
+	/*
+	 * The cpu state needs to be saved and restored so that the
+	 * secondary CPUs will enter low power start. Though the U-Boot
+	 * is setting the cpu state with low power flag, the kernel
+	 * needs to restore it back in case, the primary cpu fails to
+	 * suspend for any reason.
+	 */
+	exynos5420_cpu_state = __raw_readl(sysram_base_addr +
+						EXYNOS5420_CPU_STATE);
+
+	exynos_pm_enter_sleep_mode();
+
+	tmp = pmu_raw_readl(EXYNOS5_ARM_L2_OPTION);
+	tmp &= ~EXYNOS5_USE_RETENTION;
+	pmu_raw_writel(tmp, EXYNOS5_ARM_L2_OPTION);
+
+	tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
+	tmp |= EXYNOS5420_UFS;
+	pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
+
+	tmp = pmu_raw_readl(EXYNOS5420_ARM_COMMON_OPTION);
+	tmp &= ~EXYNOS5420_L2RSTDISABLE_VALUE;
+	pmu_raw_writel(tmp, EXYNOS5420_ARM_COMMON_OPTION);
+
+	tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
+	tmp |= EXYNOS5420_EMULATION;
+	pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
+
+	tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
+	tmp |= EXYNOS5420_EMULATION;
+	pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
+}
+
+
 static int exynos_pm_suspend(void)
 {
 	exynos_pm_central_suspend();
@@ -185,6 +262,24 @@ static int exynos_pm_suspend(void)
 	return 0;
 }
 
+static int exynos5420_pm_suspend(void)
+{
+	u32 this_cluster;
+
+	exynos_pm_central_suspend();
+
+	/* Setting SEQ_OPTION register */
+
+	this_cluster = MPIDR_AFFINITY_LEVEL(read_cpuid_mpidr(), 1);
+	if (!this_cluster)
+		pmu_raw_writel(EXYNOS5420_ARM_USE_STANDBY_WFI0,
+				S5P_CENTRAL_SEQ_OPTION);
+	else
+		pmu_raw_writel(EXYNOS5420_KFC_USE_STANDBY_WFI0,
+				S5P_CENTRAL_SEQ_OPTION);
+	return 0;
+}
+
 static void exynos_pm_release_retention(void)
 {
 	unsigned int i;
@@ -223,6 +318,45 @@ early_wakeup:
 	pmu_raw_writel(0x0, S5P_INFORM1);
 }
 
+static void exynos5420_pm_resume(void)
+{
+	unsigned long tmp;
+
+	/* Restore the sysram cpu state register */
+	__raw_writel(exynos5420_cpu_state,
+		sysram_base_addr + EXYNOS5420_CPU_STATE);
+
+	pmu_raw_writel(EXYNOS5420_USE_STANDBY_WFI_ALL,
+			S5P_CENTRAL_SEQ_OPTION);
+
+	if (exynos_pm_central_resume())
+		goto early_wakeup;
+
+	/* For release retention */
+	exynos_pm_release_retention();
+
+	pmu_raw_writel(exynos_pmu_spare3, S5P_PMU_SPARE3);
+
+	s3c_pm_do_restore_core(exynos_core_save, ARRAY_SIZE(exynos_core_save));
+
+early_wakeup:
+
+	tmp = pmu_raw_readl(EXYNOS5420_SFR_AXI_CGDIS1);
+	tmp &= ~EXYNOS5420_UFS;
+	pmu_raw_writel(tmp, EXYNOS5420_SFR_AXI_CGDIS1);
+
+	tmp = pmu_raw_readl(EXYNOS5420_FSYS2_OPTION);
+	tmp &= ~EXYNOS5420_EMULATION;
+	pmu_raw_writel(tmp, EXYNOS5420_FSYS2_OPTION);
+
+	tmp = pmu_raw_readl(EXYNOS5420_PSGEN_OPTION);
+	tmp &= ~EXYNOS5420_EMULATION;
+	pmu_raw_writel(tmp, EXYNOS5420_PSGEN_OPTION);
+
+	/* Clear SLEEP mode set in INFORM1 */
+	pmu_raw_writel(0x0, S5P_INFORM1);
+}
+
 /*
  * Suspend Ops
  */
@@ -310,6 +444,16 @@ static const struct exynos_pm_data exynos5250_pm_data = {
 	.cpu_suspend	= exynos_cpu_suspend,
 };
 
+static struct exynos_pm_data exynos5420_pm_data = {
+	.wkup_irq	= exynos5250_wkup_irq,
+	.wake_disable_mask = (0x7F << 7) | (0x1F << 1),
+	.release_ret_regs = exynos5420_release_ret_regs,
+	.pm_resume	= exynos5420_pm_resume,
+	.pm_suspend	= exynos5420_pm_suspend,
+	.pm_prepare	= exynos5420_pm_prepare,
+	.cpu_suspend	= exynos5420_cpu_suspend,
+};
+
 static struct of_device_id exynos_pmu_of_device_ids[] = {
 	{
 		.compatible = "samsung,exynos4210-pmu",
@@ -323,6 +467,9 @@ static struct of_device_id exynos_pmu_of_device_ids[] = {
 	}, {
 		.compatible = "samsung,exynos5250-pmu",
 		.data = &exynos5250_pm_data,
+	}, {
+		.compatible = "samsung,exynos5420-pmu",
+		.data = &exynos5420_pm_data,
 	},
 	{ /*sentinel*/ },
 };
-- 
1.7.9.5

[PATCH v9 2/2] ARM: exynos5: Add Suspend-to-RAM support for 5420

[Javier Martinez Canillas]

Hello Vikas,

On Tue, Oct 7, 2014 at 11:22 AM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
> Adds Suspend-to-RAM support for EXYNOS5420
>
> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
> ---
>  arch/arm/mach-exynos/suspend.c |  151 +++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 149 insertions(+), 2 deletions(-)
>

Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>

Best regards,
Javier

[PATCH v9 2/2] ARM: exynos5: Add Suspend-to-RAM support for 5420

[Vikas Sajjan]

On Tue, Oct 7, 2014 at 6:19 PM, Javier Martinez Canillas
<javier@dowhile0.org> wrote:
> Hello Vikas,
>
> On Tue, Oct 7, 2014 at 11:22 AM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
>> Adds Suspend-to-RAM support for EXYNOS5420
>>
>> Signed-off-by: Vikas Sajjan <vikas.sajjan@samsung.com>
>> Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
>> ---
>>  arch/arm/mach-exynos/suspend.c |  151 +++++++++++++++++++++++++++++++++++++++-
>>  1 file changed, 149 insertions(+), 2 deletions(-)
>>
>
> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
>

Thank you, Javier.


> Best regards,
> Javier

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Vikas Sajjan]

Hi Kukjin,


On Tue, Oct 7, 2014 at 3:07 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
> Rebased on
> 1] Kukjin Kim's tree, for-next branch
> https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
> 2] Pankaj Dubey's v9 PMU patchset
> http://www.spinics.net/lists/arm-kernel/msg367939.html
>
> changes since v8:
>         - addressed abhilash's comments to remove the restoring of
>           the CPU0 low power state register, since it will taken care in mcpm s2r
>           patch from abhilash.
>
> changes since v7:
>         - rebased on pankaj's latest patchset.
>
> changes since v6:
>         - rebased on 3.17.rc1.
>
> changes since v5:
>         - Refactored pm.c to use DT based lookup as suggested by Tomasz Figa.
>
> changes since v4:
>         - Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset
>
> changes since v3:
> Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz,
> Tomasz Figa and Alim Akhtar:
>         - Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
>         - Merged exynos5420_set_core_flag function into powerdown_conf.
>         - Removed XXTI_DURATION3 register setting.
>         - Updated the commit message and ordered the clock registers in clock
>           patch.
>         - Removed the code for SYS_DISP1_BLK_CFG handling.
>         - Modified SoC checks to A9 specific checks in PM code.
>         - Updated some comments in the code and added macros for register offsets.
>         - Fixed code which was changing pad retention code for older SoCs.
>
> changes since v2:
>         - Addressed comments from Tomasz figa
>         - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
>         - dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420",
>           will be sent separately.
>
> changes since v1:
>         - Addressed comments from Tomasz figa.
>         - restructured/consolidated as per Tomasz figa's PM consolidations for exynos
>
> Tested on Kukjin Kim's tree, for-next branch +
> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
> 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
> 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
>
> on Exynos5420 based chromebook (peach-pit board)
>
> Below procedures were followed to test S2R:
> Procedure A:
>         1. make multi_v7_defconfig
>         2  enable MCPM for 5420
>         3. enable S3C RTC
>         5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
> Procedure B:
>         1. make exynos_defconfig
>         4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>
> Abhilash Kesavan (1):
>   ARM: exynos5: Add PMU support for 5420
>
> Vikas Sajjan (1):
>   ARM: exynos5: Add Suspend-to-RAM support for 5420
>
>  arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
>  arch/arm/mach-exynos/suspend.c  |  151 +++++++++++++++++++-
>  3 files changed, 663 insertions(+), 2 deletions(-)
>

Can you please pick this series.


> --
> 1.7.9.5
>

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Kukjin Kim]

Vikas Sajjan wrote:
> 
> Hi Kukjin,
> 
Hi,
> 
> On Tue, Oct 7, 2014 at 3:07 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
> > Rebased on
> > 1] Kukjin Kim's tree, for-next branch
> > https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
> > 2] Pankaj Dubey's v9 PMU patchset
> > http://www.spinics.net/lists/arm-kernel/msg367939.html
> >
> > changes since v8:
> >         - addressed abhilash's comments to remove the restoring of
> >           the CPU0 low power state register, since it will taken care in mcpm s2r
> >           patch from abhilash.
> >
> > changes since v7:
> >         - rebased on pankaj's latest patchset.
> >
> > changes since v6:
> >         - rebased on 3.17.rc1.
> >
> > changes since v5:
> >         - Refactored pm.c to use DT based lookup as suggested by Tomasz Figa.
> >
> > changes since v4:
> >         - Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset
> >
> > changes since v3:
> > Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz,
> > Tomasz Figa and Alim Akhtar:
> >         - Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
> >         - Merged exynos5420_set_core_flag function into powerdown_conf.
> >         - Removed XXTI_DURATION3 register setting.
> >         - Updated the commit message and ordered the clock registers in clock
> >           patch.
> >         - Removed the code for SYS_DISP1_BLK_CFG handling.
> >         - Modified SoC checks to A9 specific checks in PM code.
> >         - Updated some comments in the code and added macros for register offsets.
> >         - Fixed code which was changing pad retention code for older SoCs.
> >
> > changes since v2:
> >         - Addressed comments from Tomasz figa
> >         - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
> >         - dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420",
> >           will be sent separately.
> >
> > changes since v1:
> >         - Addressed comments from Tomasz figa.
> >         - restructured/consolidated as per Tomasz figa's PM consolidations for exynos
> >
> > Tested on Kukjin Kim's tree, for-next branch +
> > 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
> > 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
> > 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
> >
> > on Exynos5420 based chromebook (peach-pit board)
> >
> > Below procedures were followed to test S2R:
> > Procedure A:
> >         1. make multi_v7_defconfig
> >         2  enable MCPM for 5420
> >         3. enable S3C RTC
> >         5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
> > Procedure B:
> >         1. make exynos_defconfig
> >         4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
> >
> > Abhilash Kesavan (1):
> >   ARM: exynos5: Add PMU support for 5420
> >
> > Vikas Sajjan (1):
> >   ARM: exynos5: Add Suspend-to-RAM support for 5420
> >
> >  arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
> >  arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
> >  arch/arm/mach-exynos/suspend.c  |  151 +++++++++++++++++++-
> >  3 files changed, 663 insertions(+), 2 deletions(-)
> >
> 
> Can you please pick this series.
> 
Yes, sure I will queue this series after -rc1 release.

Thanks,
Kukjin

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Vikas Sajjan]

On Wed, Oct 8, 2014 at 2:22 PM, Kukjin Kim <kgene@kernel.org> wrote:
> Vikas Sajjan wrote:
>>
>> Hi Kukjin,
>>
> Hi,
>>
>> On Tue, Oct 7, 2014 at 3:07 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
>> > Rebased on
>> > 1] Kukjin Kim's tree, for-next branch
>> > https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git/log/?h=for-next
>> > 2] Pankaj Dubey's v9 PMU patchset
>> > http://www.spinics.net/lists/arm-kernel/msg367939.html
>> >
>> > changes since v8:
>> >         - addressed abhilash's comments to remove the restoring of
>> >           the CPU0 low power state register, since it will taken care in mcpm s2r
>> >           patch from abhilash.
>> >
>> > changes since v7:
>> >         - rebased on pankaj's latest patchset.
>> >
>> > changes since v6:
>> >         - rebased on 3.17.rc1.
>> >
>> > changes since v5:
>> >         - Refactored pm.c to use DT based lookup as suggested by Tomasz Figa.
>> >
>> > changes since v4:
>> >         - Adressed comments from Tomasz figa and rebased on Pankaj Dubey's v5 PMU patchset
>> >
>> > changes since v3:
>> > Addressed the following comments from Pankaj Dubey, Bartlomiej Zolnierkiewicz,
>> > Tomasz Figa and Alim Akhtar:
>> >         - Moved EXYNOS5420_USE_STANDBY_WFI_ALL define to regs-pmu.h.
>> >         - Merged exynos5420_set_core_flag function into powerdown_conf.
>> >         - Removed XXTI_DURATION3 register setting.
>> >         - Updated the commit message and ordered the clock registers in clock
>> >           patch.
>> >         - Removed the code for SYS_DISP1_BLK_CFG handling.
>> >         - Modified SoC checks to A9 specific checks in PM code.
>> >         - Updated some comments in the code and added macros for register offsets.
>> >         - Fixed code which was changing pad retention code for older SoCs.
>> >
>> > changes since v2:
>> >         - Addressed comments from Tomasz figa
>> >         - rebased on Pankaj's V3 patchset https://lkml.org/lkml/2014/5/2/612
>> >         - dropped patch "ARM: dts: Add node for GPIO keys on SMDK5420",
>> >           will be sent separately.
>> >
>> > changes since v1:
>> >         - Addressed comments from Tomasz figa.
>> >         - restructured/consolidated as per Tomasz figa's PM consolidations for exynos
>> >
>> > Tested on Kukjin Kim's tree, for-next branch +
>> > 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
>> > 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
>> > 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
>> >
>> > on Exynos5420 based chromebook (peach-pit board)
>> >
>> > Below procedures were followed to test S2R:
>> > Procedure A:
>> >         1. make multi_v7_defconfig
>> >         2  enable MCPM for 5420
>> >         3. enable S3C RTC
>> >         5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>> > Procedure B:
>> >         1. make exynos_defconfig
>> >         4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>> >
>> > Abhilash Kesavan (1):
>> >   ARM: exynos5: Add PMU support for 5420
>> >
>> > Vikas Sajjan (1):
>> >   ARM: exynos5: Add Suspend-to-RAM support for 5420
>> >
>> >  arch/arm/mach-exynos/pmu.c      |  287 +++++++++++++++++++++++++++++++++++++++
>> >  arch/arm/mach-exynos/regs-pmu.h |  227 +++++++++++++++++++++++++++++++
>> >  arch/arm/mach-exynos/suspend.c  |  151 +++++++++++++++++++-
>> >  3 files changed, 663 insertions(+), 2 deletions(-)
>> >
>>
>> Can you please pick this series.
>>
> Yes, sure I will queue this series after -rc1 release.

Thank you.

>
> Thanks,
> Kukjin
>

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Javier Martinez Canillas]

Hello Vikas,

On Wed, Oct 8, 2014 at 11:26 AM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
>>>
>>> Can you please pick this series.
>>>
>> Yes, sure I will queue this series after -rc1 release.
>

Not related to your series but did you figure out why the
aclk200_disp1 and aclk300_disp1 clocks are left unused?

I'm carrying your patch to flag those clocks as CLK_IGNORE_UNUSED to
prevent being disabled by the CCF. And while that allows me to test,
I'm afraid that it may not be the proper solution since it could just
be hiding the real cause of the issue.

Of course this should not block your series from been merged but I
just wondered if you found the cause since it would be nice to have
s2r properly working on exynos5420.

> Thank you.
>
>>
>> Thanks,
>> Kukjin
>>

best regards,
Javier

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Vikas Sajjan]

Hi Javier,

On Wed, Oct 8, 2014 at 3:42 PM, Javier Martinez Canillas
<javier@dowhile0.org> wrote:
> Hello Vikas,
>
> On Wed, Oct 8, 2014 at 11:26 AM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
>>>>
>>>> Can you please pick this series.
>>>>
>>> Yes, sure I will queue this series after -rc1 release.
>>
>
> Not related to your series but did you figure out why the
> aclk200_disp1 and aclk300_disp1 clocks are left unused?
>

As mentioned earlier, I recently noticed that these clocks are
preventing system from suspending.
These clocks are used by the in-flight DRM display driver and once it
is merged the display driver will be handling the clock during boot-up
and suspend/resume.

In our internal tree (3.17-rc5 based) where we have DRM display driver
enabled, we do not see any issues and do not need to add the
CLK_IGNORE_UNUSED flag.

> I'm carrying your patch to flag those clocks as CLK_IGNORE_UNUSED to
> prevent being disabled by the CCF. And while that allows me to test,
> I'm afraid that it may not be the proper solution since it could just
> be hiding the real cause of the issue.

Till the DRM display driver gets merged, we can continue to use this
for testing purposes.

>
> Of course this should not block your series from been merged but I
> just wondered if you found the cause since it would be nice to have
> s2r properly working on exynos5420.


>
>> Thank you.
>>
>>>
>>> Thanks,
>>> Kukjin
>>>
>
> best regards,
> Javier
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Javier Martinez Canillas]

Hello Vikas,

On Wed, Oct 8, 2014 at 1:51 PM, Vikas Sajjan <vikas.sajjan@samsung.com> wrote:
>>
>> Not related to your series but did you figure out why the
>> aclk200_disp1 and aclk300_disp1 clocks are left unused?
>>
>
> As mentioned earlier, I recently noticed that these clocks are
> preventing system from suspending.
> These clocks are used by the in-flight DRM display driver and once it
> is merged the display driver will be handling the clock during boot-up
> and suspend/resume.
>

Perfect, that was exactly what I was wondering. Thanks a lot for the
information!

Best regards,
Javier

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Kevin Hilman]

Vikas Sajjan <vikas.sajjan@samsung.com> writes:

[...]

> Tested on Kukjin Kim's tree, for-next branch + 
> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
> 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
> 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
>
> on Exynos5420 based chromebook (peach-pit board)
>
> Below procedures were followed to test S2R:
> Procedure A:
> 	1. make multi_v7_defconfig 
> 	2  enable MCPM for 5420
> 	3. enable S3C RTC
> 	5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
> Procedure B:
> 	1. make exynos_defconfig 
> 	4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state

I went tried to this on exynos5800-peach-pi and found first that
exynos_defonfig is missing the MAX77802 kconfig options for the RTC
source clock:

CONFIG_REGULATOR_MAX77802=y
CONFIG_COMMON_CLK_MAX77802=y

With those, rtc0 then comes up, but isn't waking from suspend.  However,
writing something to rtc0/wakealarm does result in /proc/interrupts
having an interrupt for the RTC, it's just not waking the system.

Anyone else tried this on 5800/peach-pi?

Kevin

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Abhilash Kesavan]

Hi Kevin,

On Thu, Oct 9, 2014 at 4:49 AM, Kevin Hilman <khilman@kernel.org> wrote:
> Vikas Sajjan <vikas.sajjan@samsung.com> writes:
>
> [...]
>
>> Tested on Kukjin Kim's tree, for-next branch +
>> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
>> 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
>> 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
>>
>> on Exynos5420 based chromebook (peach-pit board)
>>
>> Below procedures were followed to test S2R:
>> Procedure A:
>>       1. make multi_v7_defconfig
>>       2  enable MCPM for 5420
>>       3. enable S3C RTC
>>       5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>> Procedure B:
>>       1. make exynos_defconfig
>>       4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>
> I went tried to this on exynos5800-peach-pi and found first that
> exynos_defonfig is missing the MAX77802 kconfig options for the RTC
> source clock:
>
> CONFIG_REGULATOR_MAX77802=y
> CONFIG_COMMON_CLK_MAX77802=y

I am using exynos_defconfig (no changes) with the internal SoC RTC
which is enabled by default. I did not enable the MAX77802 RTC.
>
> With those, rtc0 then comes up, but isn't waking from suspend.  However,
> writing something to rtc0/wakealarm does result in /proc/interrupts
> having an interrupt for the RTC, it's just not waking the system.
>
> Anyone else tried this on 5800/peach-pi?

I have tested this on a Peach-Pi and the system is resuming fine. The
patches applied on kgene's for-next branch along with the
aclk200_disp1 fix are:
http://lkml.org/lkml/2014/9/30/156
https://lkml.org/lkml/2014/10/6/89
http://www.spinics.net/lists/arm-kernel/msg368207.html
http://www.spinics.net/lists/linux-samsung-soc/msg37647.html

Abhilash

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Javier Martinez Canillas]

Hello Abhilash,

On Thu, Oct 9, 2014 at 4:37 AM, Abhilash Kesavan
<kesavan.abhilash@gmail.com> wrote:
> Hi Kevin,
>
> On Thu, Oct 9, 2014 at 4:49 AM, Kevin Hilman <khilman@kernel.org> wrote:
>> Vikas Sajjan <vikas.sajjan@samsung.com> writes:
>>
>> [...]
>>
>>> Tested on Kukjin Kim's tree, for-next branch +
>>> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
>>> 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
>>> 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
>>>
>>> on Exynos5420 based chromebook (peach-pit board)
>>>
>>> Below procedures were followed to test S2R:
>>> Procedure A:
>>>       1. make multi_v7_defconfig
>>>       2  enable MCPM for 5420
>>>       3. enable S3C RTC
>>>       5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>>> Procedure B:
>>>       1. make exynos_defconfig
>>>       4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>>
>> I went tried to this on exynos5800-peach-pi and found first that
>> exynos_defonfig is missing the MAX77802 kconfig options for the RTC
>> source clock:
>>
>> CONFIG_REGULATOR_MAX77802=y
>> CONFIG_COMMON_CLK_MAX77802=y
>
> I am using exynos_defconfig (no changes) with the internal SoC RTC
> which is enabled by default. I did not enable the MAX77802 RTC.

That is because you probably are using kukjin's for-next branch as a
base but I had the same issue when testing s2r on linux-next.

The problem is that linux-next contains commit 546b117fdf17 ("rtc:
s3c: add support for RTC of Exynos3250 SoC") that added a required
"rtc_src" DT property for the Samsung's S3C RTC that is used to
specify the source clock XrtcXTI.

On Peach boards, the S3C source clock is the max77802 32kHZ AP clock
so I fixed that with commit 8bd43b6 ("ARM: dts: Add rtc_src clk for
s3c-rtc on exynos Peach boards") but didn't send a patch to enable the
max77802 subdevices on exynos_defconfig.

I'll post a patch to enable those config options today and maybe they
can be considered as -rc material.

>>
>> With those, rtc0 then comes up, but isn't waking from suspend.  However,
>> writing something to rtc0/wakealarm does result in /proc/interrupts
>> having an interrupt for the RTC, it's just not waking the system.
>>
>> Anyone else tried this on 5800/peach-pi?
>
> I have tested this on a Peach-Pi and the system is resuming fine. The
> patches applied on kgene's for-next branch along with the
> aclk200_disp1 fix are:
> http://lkml.org/lkml/2014/9/30/156
> https://lkml.org/lkml/2014/10/6/89
> http://www.spinics.net/lists/arm-kernel/msg368207.html
> http://www.spinics.net/lists/linux-samsung-soc/msg37647.html
>

Kevin, I didn't test it on 5800 peach pi but I did test it on 5420
peach pit and as Abhilash said, I also needed Vikas patch [0] to flag
the aclk200_disp1 and aclk300_disp1 clocks as CLK_IGNORE_UNUSED to
prevent the ccf to disable them. With that patch Suspend-to-Ram worked
for me and resuming using both the internal S3C RTC and the max77802
RTC.

Also I tested the pm_tests and all of them passed on my peach pit.

On peach pi you shouldn't need the clock patch AFAIU if you enable the
needed kconfig options to have display working since those clocks are
used by the display controller so they won't be disabled due unused.

Hope it helps,
Javier

[0]: http://www.spinics.net/lists/arm-kernel/msg367197.html

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Kevin Hilman]

Javier Martinez Canillas <javier@dowhile0.org> writes:

> Hello Abhilash,
>
> On Thu, Oct 9, 2014 at 4:37 AM, Abhilash Kesavan
> <kesavan.abhilash@gmail.com> wrote:
>> Hi Kevin,
>>
>> On Thu, Oct 9, 2014 at 4:49 AM, Kevin Hilman <khilman@kernel.org> wrote:
>>> Vikas Sajjan <vikas.sajjan@samsung.com> writes:
>>>
>>> [...]
>>>
>>>> Tested on Kukjin Kim's tree, for-next branch +
>>>> 1] http://www.spinics.net/lists/linux-samsung-soc/msg33750.html
>>>> 2] https://www.mail-archive.com/linux-samsung-soc at vger.kernel.org/msg37260.html
>>>> 3] with the CLK_IGNORE_UNUSED flag for aclk200_disp1 CLK
>>>>
>>>> on Exynos5420 based chromebook (peach-pit board)
>>>>
>>>> Below procedures were followed to test S2R:
>>>> Procedure A:
>>>>       1. make multi_v7_defconfig
>>>>       2  enable MCPM for 5420
>>>>       3. enable S3C RTC
>>>>       5. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>>>> Procedure B:
>>>>       1. make exynos_defconfig
>>>>       4. echo +20 > /sys/class/rtc/rtc0/wakealarm && echo mem > /sys/power/state
>>>
>>> I went tried to this on exynos5800-peach-pi and found first that
>>> exynos_defonfig is missing the MAX77802 kconfig options for the RTC
>>> source clock:
>>>
>>> CONFIG_REGULATOR_MAX77802=y
>>> CONFIG_COMMON_CLK_MAX77802=y
>>
>> I am using exynos_defconfig (no changes) with the internal SoC RTC
>> which is enabled by default. I did not enable the MAX77802 RTC.
>
> That is because you probably are using kukjin's for-next branch as a
> base but I had the same issue when testing s2r on linux-next.
>
> The problem is that linux-next contains commit 546b117fdf17 ("rtc:
> s3c: add support for RTC of Exynos3250 SoC") that added a required
> "rtc_src" DT property for the Samsung's S3C RTC that is used to
> specify the source clock XrtcXTI.
>
> On Peach boards, the S3C source clock is the max77802 32kHZ AP clock
> so I fixed that with commit 8bd43b6 ("ARM: dts: Add rtc_src clk for
> s3c-rtc on exynos Peach boards") but didn't send a patch to enable the
> max77802 subdevices on exynos_defconfig.
>
> I'll post a patch to enable those config options today and maybe they
> can be considered as -rc material.

Great, thanks.

>>>
>>> With those, rtc0 then comes up, but isn't waking from suspend.  However,
>>> writing something to rtc0/wakealarm does result in /proc/interrupts
>>> having an interrupt for the RTC, it's just not waking the system.
>>>
>>> Anyone else tried this on 5800/peach-pi?
>>
>> I have tested this on a Peach-Pi and the system is resuming fine. The
>> patches applied on kgene's for-next branch along with the
>> aclk200_disp1 fix are:
>> http://lkml.org/lkml/2014/9/30/156
>> https://lkml.org/lkml/2014/10/6/89
>> http://www.spinics.net/lists/arm-kernel/msg368207.html
>> http://www.spinics.net/lists/linux-samsung-soc/msg37647.html
>>
>
> Kevin, I didn't test it on 5800 peach pi but I did test it on 5420
> peach pit and as Abhilash said, I also needed Vikas patch [0] to flag
> the aclk200_disp1 and aclk300_disp1 clocks as CLK_IGNORE_UNUSED to
> prevent the ccf to disable them. With that patch Suspend-to-Ram worked
> for me and resuming using both the internal S3C RTC and the max77802
> RTC.
>
> Also I tested the pm_tests and all of them passed on my peach pit.
>
> On peach pi you shouldn't need the clock patch AFAIU if you enable the
> needed kconfig options to have display working since those clocks are
> used by the display controller so they won't be disabled due unused.

Thanks for the explanation. 

Trying $SUBJECT series on top of kukjin's for-next is working fine, but
I'm still not able to make it work on linux-next, with or without the
CLK_IGNORE_UNUSED patch.

Abhilash, can you try this on exynos5800/peach-pi with linux-next and
see what else is missing from linux-next?  It would be really nice to
get this fully working upstream.

Note also the enabling CPUidle depends on $SUBJECT series as well.

Kevin

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Javier Martinez Canillas]

Hello Kevin,

On Thu, Oct 9, 2014 at 11:50 PM, Kevin Hilman <khilman@kernel.org> wrote:
>>
>> On Peach boards, the S3C source clock is the max77802 32kHZ AP clock
>> so I fixed that with commit 8bd43b6 ("ARM: dts: Add rtc_src clk for
>> s3c-rtc on exynos Peach boards") but didn't send a patch to enable the
>> max77802 subdevices on exynos_defconfig.
>>
>> I'll post a patch to enable those config options today and maybe they
>> can be considered as -rc material.
>
> Great, thanks.
>

Now I remember why I didn't enable those options at the time and it
was because Vivek Gautam already did. Now, I see that the max77802
config options were removed on a later patch, probably by mistake.

So I posted a patch [0] to re-enable those options but it seems I
forgot to cc you, sorry about that.

Best regards,
Javier

[0]: https://lkml.org/lkml/2014/10/9/413

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Kevin Hilman]

Kevin Hilman <khilman@kernel.org> writes:

[...]

> Trying $SUBJECT series on top of kukjin's for-next is working fine, but
> I'm still not able to make it work on linux-next, with or without the
> CLK_IGNORE_UNUSED patch.

Nevermind, turns out I didn't apply the CLK_IGNORE_UNUSED PATCH.  If I
actually apply it, I have it working on top of linux-next.  However, it
seems to have some issues with the nonboot CPUs resuming:

[   11.319833] Enabling non-boot CPUs ...
[   12.319134] CPU1: failed to come online
[   12.319235] Error taking CPU1 up: -5
[   13.319137] CPU2: failed to come online
[   13.319209] Error taking CPU2 up: -5
[   14.319133] CPU3: failed to come online
[   14.319224] Error taking CPU3 up: -5

Are you guys seeing all the non-boot CPUs coming up?  They fail to come
online, but the /sys/devices/.../cpu?/online reports that they are
online, which means the next attempt to hotplug them will probably BUG().

Also, If I turn off the switcher (enabled by default exynos_defconfig),
resume still has problems bringing all the nonboot CPUs online, and then
has a bunch of I2C errors[1].

And one more..., if I try enabling CPUidle[1] with exynos_defconfig, S2R
causes a reboot (seems to be on resume.)

Kevin


[1] 
[   47.644273] cros-ec-spi spi2.0: EC failed to respond in time
[   47.648535] cros-ec-spi spi2.0: spi transfer failed: -110
[   47.653866] tps65090-charger tps65090-charger: tps65090_charger_isr(): Error in reading reg 0xa

[2]
CONFIG_CPU_IDLE=y
CONFIG_ARM_BIG_LITTLE_CPUIDLE=y
CONFIG_ARM_EXYNOS_CPUIDLE=n

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Abhilash Kesavan]

Hi Kevin,

On Fri, Oct 10, 2014 at 4:29 AM, Kevin Hilman <khilman@kernel.org> wrote:
> Kevin Hilman <khilman@kernel.org> writes:
>
> [...]
>
>> Trying $SUBJECT series on top of kukjin's for-next is working fine, but
>> I'm still not able to make it work on linux-next, with or without the
>> CLK_IGNORE_UNUSED patch.
>
> Nevermind, turns out I didn't apply the CLK_IGNORE_UNUSED PATCH.  If I
> actually apply it, I have it working on top of linux-next.  However, it
> seems to have some issues with the nonboot CPUs resuming:
>
> [   11.319833] Enabling non-boot CPUs ...
> [   12.319134] CPU1: failed to come online
> [   12.319235] Error taking CPU1 up: -5
> [   13.319137] CPU2: failed to come online
> [   13.319209] Error taking CPU2 up: -5
> [   14.319133] CPU3: failed to come online
> [   14.319224] Error taking CPU3 up: -5
>
> Are you guys seeing all the non-boot CPUs coming up?  They fail to come
> online, but the /sys/devices/.../cpu?/online reports that they are
> online, which means the next attempt to hotplug them will probably BUG().
>
> Also, If I turn off the switcher (enabled by default exynos_defconfig),
> resume still has problems bringing all the nonboot CPUs online, and then
> has a bunch of I2C errors[1].
>
> And one more..., if I try enabling CPUidle[1] with exynos_defconfig, S2R
> causes a reboot (seems to be on resume.)

I tested S2R on my Peach-Pi (Exynos5800) on linux-next-20141009. My tree has:

a57db95 TEMP: Use CLK_IGNORE_UNUSED for aclk200_disp1
18158ac ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
d86cb2d ARM: exynos5: Add Suspend-to-RAM support for 5420
93f1b7c ARM: exynos5: Add PMU support for 5420
8dcc2db ARM: EXYNOS: Move PMU specific definitions from common.h
493a16a ARM: EXYNOS: Add platform driver support for Exynos PMU
64e73fb mfd: syscon: Decouple syscon interface from platform devices
af7b574 Add linux-next specific files for 20141009
4658bc0 Merge branch 'akpm/master'
9784a19 mm: add strictlimit knob

I have tested the following scenarios using exynos_defconfig with
CONFIG_COMMON_CLK_MAX77802 enabled:

1) CONFIG_BIG_LITTLE enabled (default in exynos_defconfig)
2) CONFIG_BIG_LITTLE disabled
3) CONFIG_ARM_BIG_LITTLE_CPUIDLE enabled

In all 3 cases the secondary cores as well as the system resume fine.
Can you please confirm if your kernel has a similar configuration ?

Regards,
Abhilash

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Kevin Hilman]

Abhilash Kesavan <kesavan.abhilash@gmail.com> writes:

> On Fri, Oct 10, 2014 at 4:29 AM, Kevin Hilman <khilman@kernel.org> wrote:
>> Kevin Hilman <khilman@kernel.org> writes:
>>
>> [...]
>>
>>> Trying $SUBJECT series on top of kukjin's for-next is working fine, but
>>> I'm still not able to make it work on linux-next, with or without the
>>> CLK_IGNORE_UNUSED patch.
>>
>> Nevermind, turns out I didn't apply the CLK_IGNORE_UNUSED PATCH.  If I
>> actually apply it, I have it working on top of linux-next.  However, it
>> seems to have some issues with the nonboot CPUs resuming:
>>
>> [   11.319833] Enabling non-boot CPUs ...
>> [   12.319134] CPU1: failed to come online
>> [   12.319235] Error taking CPU1 up: -5
>> [   13.319137] CPU2: failed to come online
>> [   13.319209] Error taking CPU2 up: -5
>> [   14.319133] CPU3: failed to come online
>> [   14.319224] Error taking CPU3 up: -5
>>
>> Are you guys seeing all the non-boot CPUs coming up?  They fail to come
>> online, but the /sys/devices/.../cpu?/online reports that they are
>> online, which means the next attempt to hotplug them will probably BUG().
>>
>> Also, If I turn off the switcher (enabled by default exynos_defconfig),
>> resume still has problems bringing all the nonboot CPUs online, and then
>> has a bunch of I2C errors[1].
>>
>> And one more..., if I try enabling CPUidle[1] with exynos_defconfig, S2R
>> causes a reboot (seems to be on resume.)
>
> I tested S2R on my Peach-Pi (Exynos5800) on linux-next-20141009. My tree has:
>
> a57db95 TEMP: Use CLK_IGNORE_UNUSED for aclk200_disp1
> 18158ac ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420

I was missing this one.

> d86cb2d ARM: exynos5: Add Suspend-to-RAM support for 5420
> 93f1b7c ARM: exynos5: Add PMU support for 5420
> 8dcc2db ARM: EXYNOS: Move PMU specific definitions from common.h
> 493a16a ARM: EXYNOS: Add platform driver support for Exynos PMU
> 64e73fb mfd: syscon: Decouple syscon interface from platform devices
> af7b574 Add linux-next specific files for 20141009
> 4658bc0 Merge branch 'akpm/master'
> 9784a19 mm: add strictlimit knob
>
> I have tested the following scenarios using exynos_defconfig with
> CONFIG_COMMON_CLK_MAX77802 enabled:
>
> 1) CONFIG_BIG_LITTLE enabled (default in exynos_defconfig)
> 2) CONFIG_BIG_LITTLE disabled
> 3) CONFIG_ARM_BIG_LITTLE_CPUIDLE enabled
>
> In all 3 cases the secondary cores as well as the system resume fine.
> Can you please confirm if your kernel has a similar configuration ?

Adding in the missing dependency above, it's now working for me in all 3
scenarios. Looking back at the cover letter, I see it's clearly listed
as a dependency.  Sorry, my fault.

Feel free to add

Tested-by: Kevin Hilman <khilman@linaro.org>

to $SUBJECT series.

Kevin

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Vikas Sajjan]

Hi Kevin,

On Sat, Oct 11, 2014 at 3:47 AM, Kevin Hilman <khilman@kernel.org> wrote:
> Abhilash Kesavan <kesavan.abhilash@gmail.com> writes:
>
>> On Fri, Oct 10, 2014 at 4:29 AM, Kevin Hilman <khilman@kernel.org> wrote:
>>> Kevin Hilman <khilman@kernel.org> writes:
>>>
>>> [...]
>>>
>>>> Trying $SUBJECT series on top of kukjin's for-next is working fine, but
>>>> I'm still not able to make it work on linux-next, with or without the
>>>> CLK_IGNORE_UNUSED patch.
>>>
>>> Nevermind, turns out I didn't apply the CLK_IGNORE_UNUSED PATCH.  If I
>>> actually apply it, I have it working on top of linux-next.  However, it
>>> seems to have some issues with the nonboot CPUs resuming:
>>>
>>> [   11.319833] Enabling non-boot CPUs ...
>>> [   12.319134] CPU1: failed to come online
>>> [   12.319235] Error taking CPU1 up: -5
>>> [   13.319137] CPU2: failed to come online
>>> [   13.319209] Error taking CPU2 up: -5
>>> [   14.319133] CPU3: failed to come online
>>> [   14.319224] Error taking CPU3 up: -5
>>>
>>> Are you guys seeing all the non-boot CPUs coming up?  They fail to come
>>> online, but the /sys/devices/.../cpu?/online reports that they are
>>> online, which means the next attempt to hotplug them will probably BUG().
>>>
>>> Also, If I turn off the switcher (enabled by default exynos_defconfig),
>>> resume still has problems bringing all the nonboot CPUs online, and then
>>> has a bunch of I2C errors[1].
>>>
>>> And one more..., if I try enabling CPUidle[1] with exynos_defconfig, S2R
>>> causes a reboot (seems to be on resume.)
>>
>> I tested S2R on my Peach-Pi (Exynos5800) on linux-next-20141009. My tree has:
>>
>> a57db95 TEMP: Use CLK_IGNORE_UNUSED for aclk200_disp1
>> 18158ac ARM: EXYNOS: Use MCPM call-backs to support S2R on Exynos5420
>
> I was missing this one.
>
>> d86cb2d ARM: exynos5: Add Suspend-to-RAM support for 5420
>> 93f1b7c ARM: exynos5: Add PMU support for 5420
>> 8dcc2db ARM: EXYNOS: Move PMU specific definitions from common.h
>> 493a16a ARM: EXYNOS: Add platform driver support for Exynos PMU
>> 64e73fb mfd: syscon: Decouple syscon interface from platform devices
>> af7b574 Add linux-next specific files for 20141009
>> 4658bc0 Merge branch 'akpm/master'
>> 9784a19 mm: add strictlimit knob
>>
>> I have tested the following scenarios using exynos_defconfig with
>> CONFIG_COMMON_CLK_MAX77802 enabled:
>>
>> 1) CONFIG_BIG_LITTLE enabled (default in exynos_defconfig)
>> 2) CONFIG_BIG_LITTLE disabled
>> 3) CONFIG_ARM_BIG_LITTLE_CPUIDLE enabled
>>
>> In all 3 cases the secondary cores as well as the system resume fine.
>> Can you please confirm if your kernel has a similar configuration ?
>
> Adding in the missing dependency above, it's now working for me in all 3
> scenarios. Looking back at the cover letter, I see it's clearly listed
> as a dependency.  Sorry, my fault.
>
> Feel free to add
>
> Tested-by: Kevin Hilman <khilman@linaro.org>

Thanks a lot for testing.

>
> to $SUBJECT series.
>
> Kevin

[PATCH v9 0/2] Adds PMU and S2R support for exynos5420

[Javier Martinez Canillas]

Hello Kevin,

On Fri, Oct 10, 2014 at 12:59 AM, Kevin Hilman <khilman@kernel.org> wrote:
> Kevin Hilman <khilman@kernel.org> writes:
>
> [...]
>
>> Trying $SUBJECT series on top of kukjin's for-next is working fine, but
>> I'm still not able to make it work on linux-next, with or without the
>> CLK_IGNORE_UNUSED patch.
>
> Nevermind, turns out I didn't apply the CLK_IGNORE_UNUSED PATCH.  If I
> actually apply it, I have it working on top of linux-next.  However, it
> seems to have some issues with the nonboot CPUs resuming:
>

Did you have this issue both on top of kukjin's for-next and
linux-next or only on the later?
Could you please share your tree so I can give a try on my each Pit?

> [   11.319833] Enabling non-boot CPUs ...
> [   12.319134] CPU1: failed to come online
> [   12.319235] Error taking CPU1 up: -5
> [   13.319137] CPU2: failed to come online
> [   13.319209] Error taking CPU2 up: -5
> [   14.319133] CPU3: failed to come online
> [   14.319224] Error taking CPU3 up: -5
>
> Are you guys seeing all the non-boot CPUs coming up?  They fail to come
> online, but the /sys/devices/.../cpu?/online reports that they are
> online, which means the next attempt to hotplug them will probably BUG().
>

Maybe a silly question but are you using the last version (v9) [0] of
Abhilash's "ARM: EXYNOS: Use MCPM call-backs to support S2R on
Exynos5420" patch?

I had the same issue than you when testing with his v8 version because
there was a mistake on rebasing where the CPU power down logic was in
exynos_cpu_power_up() instead of exynos_cpu_power_down().

> Also, If I turn off the switcher (enabled by default exynos_defconfig),
> resume still has problems bringing all the nonboot CPUs online, and then
> has a bunch of I2C errors[1].
>
> And one more..., if I try enabling CPUidle[1] with exynos_defconfig, S2R
> causes a reboot (seems to be on resume.)
>

I didn't try CPUidle and I don't remember seeing the I2C errors but
maybe I just didn't notice. I'll re-test and see if it behaves the
same on my Exynos5420 machine.

> Kevin
>
>
> [1]
> [   47.644273] cros-ec-spi spi2.0: EC failed to respond in time
> [   47.648535] cros-ec-spi spi2.0: spi transfer failed: -110
> [   47.653866] tps65090-charger tps65090-charger: tps65090_charger_isr(): Error in reading reg 0xa
>
> [2]
> CONFIG_CPU_IDLE=y
> CONFIG_ARM_BIG_LITTLE_CPUIDLE=y
> CONFIG_ARM_EXYNOS_CPUIDLE=n
>

Best regards,
Javier

[0]: http://www.spinics.net/lists/linux-samsung-soc/msg37647.html