[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

A series of patches that add support for GPIO maps that have holes in
them.  That is, even though a client driver has N consecutive GPIOs,
some are just unavailable for whatever reason, and the hardware should
not be accessed for those GPIOs.

Frankly, I like V5 of this patchset better, because it uses an
existing API (gpiochip_add_pin_range) and is less intrusive.

v7: fixed missing signed-off-by in patch #1

Timur Tabi (4):
  [v2] Revert "gpio: set up initial state from .get_direction()"
  gpiolib: add bitmask for valid GPIO lines
  [v6] pinctrl: qcom: disable GPIO groups with no pins
  [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

 drivers/gpio/gpiolib.c                 |  74 +++++++++--------
 drivers/pinctrl/qcom/pinctrl-msm.c     |  48 +++++++++--
 drivers/pinctrl/qcom/pinctrl-msm.h     |   2 +
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 145 +++++++++++++++++++++++++--------
 include/linux/gpio/driver.h            |   2 +
 5 files changed, 197 insertions(+), 74 deletions(-)

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 1/4] [v2] Revert "gpio: set up initial state from .get_direction()"

[Timur Tabi]

This reverts commit 72d3200061776264941be1b5a9bb8e926b3b30a5.

We cannot blindly query the direction of all GPIOs when the pins are
first registered.  The get_direction callback normally triggers a
read/write to hardware, but we shouldn't be touching the hardware for
an individual GPIO until after it's been properly claimed.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/gpio/gpiolib.c | 31 +++++++------------------------
 1 file changed, 7 insertions(+), 24 deletions(-)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index eb80dac4e26a..60553af4c004 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1221,31 +1221,14 @@ int gpiochip_add_data(struct gpio_chip *chip, void *data)
 		struct gpio_desc *desc = &gdev->descs[i];
 
 		desc->gdev = gdev;
-		/*
-		 * REVISIT: most hardware initializes GPIOs as inputs
-		 * (often with pullups enabled) so power usage is
-		 * minimized. Linux code should set the gpio direction
-		 * first thing; but until it does, and in case
-		 * chip->get_direction is not set, we may expose the
-		 * wrong direction in sysfs.
-		 */
-
-		if (chip->get_direction) {
-			/*
-			 * If we have .get_direction, set up the initial
-			 * direction flag from the hardware.
-			 */
-			int dir = chip->get_direction(chip, i);
 
-			if (!dir)
-				set_bit(FLAG_IS_OUT, &desc->flags);
-		} else if (!chip->direction_input) {
-			/*
-			 * If the chip lacks the .direction_input callback
-			 * we logically assume all lines are outputs.
-			 */
-			set_bit(FLAG_IS_OUT, &desc->flags);
-		}
+		/* REVISIT: most hardware initializes GPIOs as inputs (often
+		 * with pullups enabled) so power usage is minimized. Linux
+		 * code should set the gpio direction first thing; but until
+		 * it does, and in case chip->get_direction is not set, we may
+		 * expose the wrong direction in sysfs.
+		 */
+		desc->flags = !chip->direction_input ? (1 << FLAG_IS_OUT) : 0;
 	}
 
 #ifdef CONFIG_PINCTRL
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 2/4] gpiolib: add bitmask for valid GPIO lines

[Timur Tabi]

Add support for specifying that some GPIOs within a range are unavailable.
Some systems have a sparse list of GPIOs, where a range of GPIOs is
specified (usually 0 to n-1), but some subset within that range is
absent or unavailable for whatever reason.

To support this, allow drivers to specify a bitmask of GPIOs that
are present or absent.  Gpiolib will then block access to those that
are absent.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/gpio/gpiolib.c      | 43 +++++++++++++++++++++++++++++++++++--------
 include/linux/gpio/driver.h |  2 ++
 2 files changed, 37 insertions(+), 8 deletions(-)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 60553af4c004..c32387936cdd 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1481,22 +1481,36 @@ static struct gpio_chip *find_chip_by_name(const char *name)
 
 static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
 {
-	if (!gpiochip->irq_need_valid_mask)
-		return 0;
+	if (gpiochip->irq_need_valid_mask) {
+		gpiochip->irq_valid_mask =
+			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
+				sizeof(long), GFP_KERNEL);
+		if (!gpiochip->irq_valid_mask)
+			return -ENOMEM;
 
-	gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
-					   sizeof(long), GFP_KERNEL);
-	if (!gpiochip->irq_valid_mask)
-		return -ENOMEM;
+		/* Assume by default all GPIOs are valid */
+		bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
+	}
 
-	/* Assume by default all GPIOs are valid */
-	bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
+	if (gpiochip->line_need_valid_mask) {
+		gpiochip->line_valid_mask =
+			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
+				sizeof(long), GFP_KERNEL);
+		if (!gpiochip->line_valid_mask)
+			return -ENOMEM;
+
+		/* Assume by default all GPIOs are valid */
+		bitmap_fill(gpiochip->line_valid_mask, gpiochip->ngpio);
+	}
 
 	return 0;
 }
 
 static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
 {
+	kfree(gpiochip->line_valid_mask);
+	gpiochip->line_valid_mask = NULL;
+
 	kfree(gpiochip->irq_valid_mask);
 	gpiochip->irq_valid_mask = NULL;
 }
@@ -1510,6 +1524,15 @@ static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
 	return test_bit(offset, gpiochip->irq_valid_mask);
 }
 
+static bool gpiochip_irqchip_line_valid(const struct gpio_chip *gpiochip,
+					unsigned int offset)
+{
+	/* No mask means all valid */
+	if (likely(!gpiochip->line_valid_mask))
+		return true;
+	return test_bit(offset, gpiochip->line_valid_mask);
+}
+
 /**
  * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
  * @gpiochip: the gpiochip to set the irqchip chain to
@@ -3320,6 +3343,10 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
 		return desc;
 	}
 
+	/* Make sure the GPIO is valid before we request it. */
+	if (!gpiochip_irqchip_line_valid(desc->gdev->chip, idx))
+		return ERR_PTR(-EACCES);
+
 	status = gpiod_request(desc, con_id);
 	if (status < 0)
 		return ERR_PTR(status);
diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
index 424e5139ff10..853828ccabc8 100644
--- a/include/linux/gpio/driver.h
+++ b/include/linux/gpio/driver.h
@@ -173,6 +173,8 @@ struct gpio_chip {
 	bool			irq_nested;
 	bool			irq_need_valid_mask;
 	unsigned long		*irq_valid_mask;
+	bool			line_need_valid_mask;
+	unsigned long		*line_valid_mask;
 	struct lock_class_key	*lock_key;
 #endif
 
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
each group to support have only one pin (npins == 1).

We can support "sparse" GPIO maps if we allow for some groups to have zero
pins (npins == 0).  These pins are "hidden" from the rest of the driver
and gpiolib.

A new boolean 'sparse' indicates whether the GPIO map is sparse.  If any
GPIO has an 'npins' value of 0, then 'sparse' must be set to True.

Most access to unavailable GPIOs can be blocked via the gpio_chip.request
function.  The one exception is when gpiochip_add_data() scans all of
the GPIOs without "requesting" them.  To cover this case,
msm_gpio_get_direction() separately checks if the GPIO is available.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 48 +++++++++++++++++++++++++++++++++-----
 drivers/pinctrl/qcom/pinctrl-msm.h |  2 ++
 2 files changed, 44 insertions(+), 6 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index ff491da64dab..66c68a314ca9 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -507,6 +507,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -516,7 +521,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -524,23 +529,36 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
 #define msm_gpio_dbg_show NULL
 #endif
 
+/*
+ * If the requested GPIO has no pins, then treat it as unavailable.
+ * Otherwise, call the standard request function.
+ */
+static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
+	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
+
+	if (!g->npins)
+		return -ENODEV;
+
+	return gpiochip_generic_request(chip, offset);
+}
+
 static const struct gpio_chip msm_gpio_template = {
 	.direction_input  = msm_gpio_direction_input,
 	.direction_output = msm_gpio_direction_output,
 	.get_direction    = msm_gpio_get_direction,
 	.get              = msm_gpio_get,
 	.set              = msm_gpio_set,
-	.request          = gpiochip_generic_request,
+	.request          = msm_gpio_request,
 	.free             = gpiochip_generic_free,
 	.dbg_show         = msm_gpio_dbg_show,
 };
@@ -813,6 +831,8 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 	struct gpio_chip *chip;
 	int ret;
 	unsigned ngpio = pctrl->soc->ngpios;
+	const struct msm_pingroup *groups = pctrl->soc->groups;
+	unsigned int i;
 
 	if (WARN_ON(ngpio > MAX_NR_GPIO))
 		return -EINVAL;
@@ -825,13 +845,29 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
 	chip->owner = THIS_MODULE;
 	chip->of_node = pctrl->dev->of_node;
 
+	/* If the GPIO map is sparse, then we need to disable specific IRQs */
+	if (pctrl->soc->sparse) {
+		chip->irq_need_valid_mask = true;
+		chip->line_need_valid_mask = true;
+	}
+
 	ret = gpiochip_add_data(&pctrl->chip, pctrl);
 	if (ret) {
 		dev_err(pctrl->dev, "Failed register gpiochip\n");
 		return ret;
 	}
 
-	ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
+	if (chip->line_need_valid_mask) {
+		for (i = 0; i < ngpio; i++)
+			if (!groups[i].npins) {
+				clear_bit(i, pctrl->chip.irq_valid_mask);
+				clear_bit(i, pctrl->chip.line_valid_mask);
+			}
+	}
+
+	ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
+				     0, 0, ngpio);
+
 	if (ret) {
 		dev_err(pctrl->dev, "Failed to add pin range\n");
 		gpiochip_remove(&pctrl->chip);
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.h b/drivers/pinctrl/qcom/pinctrl-msm.h
index 9b9feea540ff..70762bcb84cb 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.h
+++ b/drivers/pinctrl/qcom/pinctrl-msm.h
@@ -107,6 +107,7 @@ struct msm_pingroup {
  * @ngroups:	    The numbmer of entries in @groups.
  * @ngpio:	    The number of pingroups the driver should expose as GPIOs.
  * @pull_no_keeper: The SoC does not support keeper bias.
+ * @sparse:         The GPIO map is sparse (some GPIOs have npins == 0)
  */
 struct msm_pinctrl_soc_data {
 	const struct pinctrl_pin_desc *pins;
@@ -117,6 +118,7 @@ struct msm_pinctrl_soc_data {
 	unsigned ngroups;
 	unsigned ngpios;
 	bool pull_no_keeper;
+	bool sparse;
 };
 
 int msm_pinctrl_probe(struct platform_device *pdev,
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 4/4] [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios".  This property is an array of
specific GPIOs that are accessible.  When an older kernel boots on
newer (restricted) firmware, it will fail to probe.

To implement the sparse GPIO map, we register all of the GPIOs, but set
the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
driver will block those unavailable GPIOs from being accessed.

To allow newer kernels to support older firmware, the driver retains
support for QCOM8001.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 145 +++++++++++++++++++++++++--------
 1 file changed, 109 insertions(+), 36 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c3e18b..37f746f6eb8c 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -38,68 +38,147 @@
 /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
 #define NAME_SIZE	8
 
+enum {
+	QDF2XXX_V1,
+	QDF2XXX_V2,
+};
+
+static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
+	{"QCOM8001", QDF2XXX_V1},
+	{"QCOM8002", QDF2XXX_V2},
+	{},
+};
+MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
+
 static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 {
+	const struct acpi_device_id *id =
+		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
 	struct pinctrl_pin_desc *pins;
 	struct msm_pingroup *groups;
 	char (*names)[NAME_SIZE];
 	unsigned int i;
 	u32 num_gpios;
+	unsigned int avail_gpios; /* The number of GPIOs we support */
+	u16 *gpios; /* An array of supported GPIOs */
 	int ret;
 
 	/* Query the number of GPIOs from ACPI */
 	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
 	if (ret < 0) {
-		dev_warn(&pdev->dev, "missing num-gpios property\n");
+		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
 		return ret;
 	}
-
 	if (!num_gpios || num_gpios > MAX_GPIOS) {
-		dev_warn(&pdev->dev, "invalid num-gpios property\n");
+		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
 		return -ENODEV;
 	}
 
+	/*
+	 * The QCOM8001 HID contains only the number of GPIOs, and assumes
+	 * that all of them are available. avail_gpios is the same as num_gpios.
+	 *
+	 * The QCOM8002 HID introduces the 'gpios' DSD, which lists
+	 * specific GPIOs that the driver is allowed to access.
+	 *
+	 * The make the common code simpler, in both cases we create an
+	 * array of GPIOs that are accessible.  So for QCOM8001, that would
+	 * be all of the GPIOs.
+	 */
+	if (id->driver_data == QDF2XXX_V1) {
+		avail_gpios = num_gpios;
+
+		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
+				     GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		for (i = 0; i < avail_gpios; i++)
+			gpios[i] = i;
+	} else {
+		/* The number of GPIOs in the approved list */
+		ret = device_property_read_u16_array(&pdev->dev, "gpios",
+						     NULL, 0);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "missing 'num-gpios' property\n");
+			return ret;
+		}
+		if (!ret || ret > MAX_GPIOS) {
+			dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+			return -ENODEV;
+		}
+		avail_gpios = ret;
+
+		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
+				     GFP_KERNEL);
+		if (!gpios)
+			return -ENOMEM;
+
+		ret = device_property_read_u16_array(&pdev->dev, "gpios", gpios,
+						     avail_gpios);
+		if (ret < 0) {
+			dev_err(&pdev->dev, "could not read list of GPIOs\n");
+			return ret;
+		}
+
+		/*
+		 * Because we have a specific list of GPIOs, the GPIO map
+		 * is 'sparse'.
+		 */
+		qdf2xxx_pinctrl.sparse = true;
+	}
+
 	pins = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
 	groups = devm_kcalloc(&pdev->dev, num_gpios,
 		sizeof(struct msm_pingroup), GFP_KERNEL);
-	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
 
 	if (!pins || !groups || !names)
 		return -ENOMEM;
 
+	/*
+	 * Initialize the array.  GPIOs not listed in the 'gpios' array
+	 * still need a number, but nothing else.
+	 */
 	for (i = 0; i < num_gpios; i++) {
-		snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
 		pins[i].number = i;
-		pins[i].name = names[i];
-
-		groups[i].npins = 1;
-		groups[i].name = names[i];
 		groups[i].pins = &pins[i].number;
+	}
 
-		groups[i].ctl_reg = 0x10000 * i;
-		groups[i].io_reg = 0x04 + 0x10000 * i;
-		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
-		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
-		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
-		groups[i].mux_bit = 2;
-		groups[i].pull_bit = 0;
-		groups[i].drv_bit = 6;
-		groups[i].oe_bit = 9;
-		groups[i].in_bit = 0;
-		groups[i].out_bit = 1;
-		groups[i].intr_enable_bit = 0;
-		groups[i].intr_status_bit = 0;
-		groups[i].intr_target_bit = 5;
-		groups[i].intr_target_kpss_val = 1;
-		groups[i].intr_raw_status_bit = 4;
-		groups[i].intr_polarity_bit = 1;
-		groups[i].intr_detection_bit = 2;
-		groups[i].intr_detection_width = 2;
+	/* Populate the entries that are meant to be exposes as GPIOs. */
+	for (i = 0; i < avail_gpios; i++) {
+		unsigned int gpio = gpios[i];
+
+		groups[gpio].npins = 1;
+		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+		pins[gpio].name = names[i];
+		groups[gpio].name = names[i];
+
+		groups[gpio].ctl_reg = 0x10000 * gpio;
+		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+		groups[gpio].mux_bit = 2;
+		groups[gpio].pull_bit = 0;
+		groups[gpio].drv_bit = 6;
+		groups[gpio].oe_bit = 9;
+		groups[gpio].in_bit = 0;
+		groups[gpio].out_bit = 1;
+		groups[gpio].intr_enable_bit = 0;
+		groups[gpio].intr_status_bit = 0;
+		groups[gpio].intr_target_bit = 5;
+		groups[gpio].intr_target_kpss_val = 1;
+		groups[gpio].intr_raw_status_bit = 4;
+		groups[gpio].intr_polarity_bit = 1;
+		groups[gpio].intr_detection_bit = 2;
+		groups[gpio].intr_detection_width = 2;
 	}
 
+	devm_kfree(&pdev->dev, gpios);
+
 	qdf2xxx_pinctrl.pins = pins;
 	qdf2xxx_pinctrl.groups = groups;
 	qdf2xxx_pinctrl.npins = num_gpios;
@@ -109,12 +188,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
 	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
 }
 
-static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
-	{"QCOM8001"},
-	{},
-};
-MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
-
 static struct platform_driver qdf2xxx_pinctrl_driver = {
 	.driver = {
 		.name = "qdf2xxx-pinctrl",
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

On 11/07/2017 05:07 PM, Timur Tabi wrote:
> A series of patches that add support for GPIO maps that have holes in
> them.  That is, even though a client driver has N consecutive GPIOs,
> some are just unavailable for whatever reason, and the hardware should
> not be accessed for those GPIOs.

Any chance of these patches going into 4.15?  I've been making lots of 
changes, but I haven't gotten a lot of feedback.  I still think that v7 
is more intrusive and risky than v5, with no real benefit.  But at this 
point, I just want something to be merged so that I stop thinking about it.



-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[Linus Walleij]

On Mon, Nov 13, 2017 at 8:19 PM, Timur Tabi <timur@codeaurora.org> wrote:

> Any chance of these patches going into 4.15?

Sadly no. The merge window is open.

>  I've been making lots of
> changes, but I haven't gotten a lot of feedback.  I still think that v7 is
> more intrusive and risky than v5, with no real benefit.  But at this point,
> I just want something to be merged so that I stop thinking about it.

I am waiting for feedback from the maintainer(s) mainly Bj?rn.

There are only so many people I really trust with reviewing
qualcomm pinctrl code: Bj?rn and Stephen mainly.
Especially for the core of the driver.

>From what I have understood Qualcomm has one finger constantly
on the fast-forward button for upstreaming right now, which I think
is good (everyone should have!) but the limited number of trusted
maintainers of core infrastructure code makes bottlenecks form
around these drivers where review is really needed and deep queues
of patches form. Sorry.

If the manpower shortage persists maybe we can seek some
review from other major contributors to these drivers?
Varadarajan and Neil for example?

Yours,
Linus Walleij

[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

On 11/13/2017 03:49 PM, Linus Walleij wrote:
> 
>  From what I have understood Qualcomm has one finger constantly
> on the fast-forward button for upstreaming right now, which I think
> is good (everyone should have!) but the limited number of trusted
> maintainers of core infrastructure code makes bottlenecks form
> around these drivers where review is really needed and deep queues
> of patches form. Sorry.

That's one of the reasons why I prefer v5 of my patch instead of v7.  v5 
does not touch the core.  It's much less intrusive and has no risk of 
breaking other drivers.  I can't say that about v7.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[Linus Walleij]

On Mon, Nov 13, 2017 at 10:53 PM, Timur Tabi <timur@codeaurora.org> wrote:
> On 11/13/2017 03:49 PM, Linus Walleij wrote:
>>
>>
>>  From what I have understood Qualcomm has one finger constantly
>> on the fast-forward button for upstreaming right now, which I think
>> is good (everyone should have!) but the limited number of trusted
>> maintainers of core infrastructure code makes bottlenecks form
>> around these drivers where review is really needed and deep queues
>> of patches form. Sorry.
>
>
> That's one of the reasons why I prefer v5 of my patch instead of v7.  v5
> does not touch the core.  It's much less intrusive and has no risk of
> breaking other drivers.  I can't say that about v7.

The more intrusive design is on my request so I will look at it in detail
ASAP. I took a quick look and liked what I saw, I just need to make
sure about the details. Also it'd be nice to have a nod from Bj?rn.

The main reason for some of the work is ACPI, am I right?

Timur could you look quickly at the series posted by Andy Shevchenko
(6 patches prefixed gpiolib: acpi: ) for augmenting ACPI GPIOs in the core?
Especially patch 5 and 6 which introduce the ability to add quirks in the
core.

I'd like to get some ARM-based people to look at it to make sure we
those systems can also quirk their GPIOs if need be.

Yours,
Linus Walleij

Fwd: [PATCH 2/4] gpiolib: add bitmask for valid GPIO lines

[Varadarajan Narayanan]

Timur,

> Add support for specifying that some GPIOs within a range are unavailable.
> Some systems have a sparse list of GPIOs, where a range of GPIOs is
> specified (usually 0 to n-1), but some subset within that range is
> absent or unavailable for whatever reason.
>
> To support this, allow drivers to specify a bitmask of GPIOs that
> are present or absent.  Gpiolib will then block access to those that
> are absent.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/gpio/gpiolib.c      | 43 +++++++++++++++++++++++++++++++++++--------
>  include/linux/gpio/driver.h |  2 ++
>  2 files changed, 37 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index 60553af4c004..c32387936cdd 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1481,22 +1481,36 @@ static struct gpio_chip *find_chip_by_name(const char *name)
>
>  static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
>  {
> -	if (!gpiochip->irq_need_valid_mask)
> -		return 0;
> +	if (gpiochip->irq_need_valid_mask) {
> +		gpiochip->irq_valid_mask =
> +			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> +				sizeof(long), GFP_KERNEL);

Since 'irq_valid_mask' is getting filled below wouldn't a kmalloc suffice?

> +		if (!gpiochip->irq_valid_mask)
> +			return -ENOMEM;
>
> -	gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> -					   sizeof(long), GFP_KERNEL);
> -	if (!gpiochip->irq_valid_mask)
> -		return -ENOMEM;
> +		/* Assume by default all GPIOs are valid */
> +		bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
> +	}
>
> -	/* Assume by default all GPIOs are valid */
> -	bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
> +	if (gpiochip->line_need_valid_mask) {
> +		gpiochip->line_valid_mask =
> +			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> +				sizeof(long), GFP_KERNEL);

Since 'line_valid_mask' is getting filled below wouldn't a kmalloc suffice?

Thanks
Varada

> +		if (!gpiochip->line_valid_mask)
> +			return -ENOMEM;
> +
> +		/* Assume by default all GPIOs are valid */
> +		bitmap_fill(gpiochip->line_valid_mask, gpiochip->ngpio);
> +	}
>
>  	return 0;
>  }
>
>  static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
>  {
> +	kfree(gpiochip->line_valid_mask);
> +	gpiochip->line_valid_mask = NULL;
> +
>  	kfree(gpiochip->irq_valid_mask);
>  	gpiochip->irq_valid_mask = NULL;
>  }
> @@ -1510,6 +1524,15 @@ static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
>  	return test_bit(offset, gpiochip->irq_valid_mask);
>  }
>
> +static bool gpiochip_irqchip_line_valid(const struct gpio_chip *gpiochip,
> +					unsigned int offset)
> +{
> +	/* No mask means all valid */
> +	if (likely(!gpiochip->line_valid_mask))
> +		return true;
> +	return test_bit(offset, gpiochip->line_valid_mask);
> +}
> +
>  /**
>   * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
>   * @gpiochip: the gpiochip to set the irqchip chain to
> @@ -3320,6 +3343,10 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
>  		return desc;
>  	}
>
> +	/* Make sure the GPIO is valid before we request it. */
> +	if (!gpiochip_irqchip_line_valid(desc->gdev->chip, idx))
> +		return ERR_PTR(-EACCES);
> +
>  	status = gpiod_request(desc, con_id);
>  	if (status < 0)
>  		return ERR_PTR(status);
> diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
> index 424e5139ff10..853828ccabc8 100644
> --- a/include/linux/gpio/driver.h
> +++ b/include/linux/gpio/driver.h
> @@ -173,6 +173,8 @@ struct gpio_chip {
>  	bool			irq_nested;
>  	bool			irq_need_valid_mask;
>  	unsigned long		*irq_valid_mask;
> +	bool			line_need_valid_mask;
> +	unsigned long		*line_valid_mask;
>  	struct lock_class_key	*lock_key;
>  #endif
>
> --
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
> ---
> This email has been checked for viruses by Avast antivirus software.
> https://www.avast.com/antivirus
>

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Fwd: [PATCH 4/4] [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Varadarajan Narayanan]

Timur,

> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM.  To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios".  This property is an array of
> specific GPIOs that are accessible.  When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
>
> To implement the sparse GPIO map, we register all of the GPIOs, but set
> the pin count for the unavailable GPIOs to zero.  The pinctrl-msm
> driver will block those unavailable GPIOs from being accessed.
>
> To allow newer kernels to support older firmware, the driver retains
> support for QCOM8001.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>  drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 145 +++++++++++++++++++++++++--------
>  1 file changed, 109 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> index bb3ce5c3e18b..37f746f6eb8c 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> @@ -38,68 +38,147 @@
>  /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
>  #define NAME_SIZE	8
>
> +enum {
> +	QDF2XXX_V1,
> +	QDF2XXX_V2,
> +};
> +
> +static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
> +	{"QCOM8001", QDF2XXX_V1},
> +	{"QCOM8002", QDF2XXX_V2},
> +	{},
> +};
> +MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
> +
>  static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>  {
> +	const struct acpi_device_id *id =
> +		acpi_match_device(qdf2xxx_acpi_ids, &pdev->dev);
>  	struct pinctrl_pin_desc *pins;
>  	struct msm_pingroup *groups;
>  	char (*names)[NAME_SIZE];
>  	unsigned int i;
>  	u32 num_gpios;
> +	unsigned int avail_gpios; /* The number of GPIOs we support */
> +	u16 *gpios; /* An array of supported GPIOs */
>  	int ret;
>
>  	/* Query the number of GPIOs from ACPI */
>  	ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
>  	if (ret < 0) {
> -		dev_warn(&pdev->dev, "missing num-gpios property\n");
> +		dev_err(&pdev->dev, "missing 'num-gpios' property\n");
>  		return ret;
>  	}
> -
>  	if (!num_gpios || num_gpios > MAX_GPIOS) {
> -		dev_warn(&pdev->dev, "invalid num-gpios property\n");
> +		dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
>  		return -ENODEV;
>  	}
>
> +	/*
> +	 * The QCOM8001 HID contains only the number of GPIOs, and assumes
> +	 * that all of them are available. avail_gpios is the same as num_gpios.
> +	 *
> +	 * The QCOM8002 HID introduces the 'gpios' DSD, which lists
> +	 * specific GPIOs that the driver is allowed to access.
> +	 *
> +	 * The make the common code simpler, in both cases we create an
> +	 * array of GPIOs that are accessible.  So for QCOM8001, that would
> +	 * be all of the GPIOs.
> +	 */
> +	if (id->driver_data == QDF2XXX_V1) {
> +		avail_gpios = num_gpios;
> +
> +		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
> +				     GFP_KERNEL);

Wouldn't kmalloc suffice since the array gets initialized just below.

> +		if (!gpios)
> +			return -ENOMEM;
> +
> +		for (i = 0; i < avail_gpios; i++)
> +			gpios[i] = i;
> +	} else {
> +		/* The number of GPIOs in the approved list */
> +		ret = device_property_read_u16_array(&pdev->dev, "gpios",
> +						     NULL, 0);
> +		if (ret < 0) {
> +			dev_err(&pdev->dev, "missing 'num-gpios' property\n");
> +			return ret;
> +		}
> +		if (!ret || ret > MAX_GPIOS) {

Instead of ret > MAX_GPIOS, should we check for ret > num_gpios?

> +			dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
> +			return -ENODEV;
> +		}

In both the above error messages 'num-gpios' should be 'gpios'

> +		avail_gpios = ret;
> +
> +		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
> +				     GFP_KERNEL);

devm_kmalloc?

Thanks
Varada

> +		if (!gpios)
> +			return -ENOMEM;
> +
> +		ret = device_property_read_u16_array(&pdev->dev, "gpios", gpios,
> +						     avail_gpios);
> +		if (ret < 0) {
> +			dev_err(&pdev->dev, "could not read list of GPIOs\n");
> +			return ret;
> +		}
> +
> +		/*
> +		 * Because we have a specific list of GPIOs, the GPIO map
> +		 * is 'sparse'.
> +		 */
> +		qdf2xxx_pinctrl.sparse = true;
> +	}
> +
>  	pins = devm_kcalloc(&pdev->dev, num_gpios,
>  		sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
>  	groups = devm_kcalloc(&pdev->dev, num_gpios,
>  		sizeof(struct msm_pingroup), GFP_KERNEL);
> -	names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
> +	names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
>
>  	if (!pins || !groups || !names)
>  		return -ENOMEM;
>
> +	/*
> +	 * Initialize the array.  GPIOs not listed in the 'gpios' array
> +	 * still need a number, but nothing else.
> +	 */
>  	for (i = 0; i < num_gpios; i++) {
> -		snprintf(names[i], NAME_SIZE, "gpio%u", i);
> -
>  		pins[i].number = i;
> -		pins[i].name = names[i];
> -
> -		groups[i].npins = 1;
> -		groups[i].name = names[i];
>  		groups[i].pins = &pins[i].number;
> +	}
>
> -		groups[i].ctl_reg = 0x10000 * i;
> -		groups[i].io_reg = 0x04 + 0x10000 * i;
> -		groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
> -		groups[i].intr_status_reg = 0x0c + 0x10000 * i;
> -		groups[i].intr_target_reg = 0x08 + 0x10000 * i;
> -
> -		groups[i].mux_bit = 2;
> -		groups[i].pull_bit = 0;
> -		groups[i].drv_bit = 6;
> -		groups[i].oe_bit = 9;
> -		groups[i].in_bit = 0;
> -		groups[i].out_bit = 1;
> -		groups[i].intr_enable_bit = 0;
> -		groups[i].intr_status_bit = 0;
> -		groups[i].intr_target_bit = 5;
> -		groups[i].intr_target_kpss_val = 1;
> -		groups[i].intr_raw_status_bit = 4;
> -		groups[i].intr_polarity_bit = 1;
> -		groups[i].intr_detection_bit = 2;
> -		groups[i].intr_detection_width = 2;
> +	/* Populate the entries that are meant to be exposes as GPIOs. */
> +	for (i = 0; i < avail_gpios; i++) {
> +		unsigned int gpio = gpios[i];
> +
> +		groups[gpio].npins = 1;
> +		snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
> +		pins[gpio].name = names[i];
> +		groups[gpio].name = names[i];
> +
> +		groups[gpio].ctl_reg = 0x10000 * gpio;
> +		groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
> +		groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
> +		groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
> +		groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
> +
> +		groups[gpio].mux_bit = 2;
> +		groups[gpio].pull_bit = 0;
> +		groups[gpio].drv_bit = 6;
> +		groups[gpio].oe_bit = 9;
> +		groups[gpio].in_bit = 0;
> +		groups[gpio].out_bit = 1;
> +		groups[gpio].intr_enable_bit = 0;
> +		groups[gpio].intr_status_bit = 0;
> +		groups[gpio].intr_target_bit = 5;
> +		groups[gpio].intr_target_kpss_val = 1;
> +		groups[gpio].intr_raw_status_bit = 4;
> +		groups[gpio].intr_polarity_bit = 1;
> +		groups[gpio].intr_detection_bit = 2;
> +		groups[gpio].intr_detection_width = 2;
>  	}
>
> +	devm_kfree(&pdev->dev, gpios);
> +
>  	qdf2xxx_pinctrl.pins = pins;
>  	qdf2xxx_pinctrl.groups = groups;
>  	qdf2xxx_pinctrl.npins = num_gpios;
> @@ -109,12 +188,6 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
>  	return msm_pinctrl_probe(pdev, &qdf2xxx_pinctrl);
>  }
>
> -static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
> -	{"QCOM8001"},
> -	{},
> -};
> -MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
> -
>  static struct platform_driver qdf2xxx_pinctrl_driver = {
>  	.driver = {
>  		.name = "qdf2xxx-pinctrl",
> --
> Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
> Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
> Code Aurora Forum, a Linux Foundation Collaborative Project.
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> "QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
>
> ---
> This email has been checked for viruses by Avast antivirus software.
> https://www.avast.com/antivirus
>

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Fwd: [PATCH 2/4] gpiolib: add bitmask for valid GPIO lines

[Andy Shevchenko]

On Wed, 2017-11-15 at 11:58 +0530, Varadarajan Narayanan wrote:

> > +	if (gpiochip->irq_need_valid_mask) {
> > +		gpiochip->irq_valid_mask =
> > +			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> > +				sizeof(long), GFP_KERNEL);
> 
> Since 'irq_valid_mask' is getting filled below wouldn't a kmalloc
> suffice?

I suppose you meant kmalloc_array.
Anyway, it's a separate change if you wish, because Timur didn't change
the original approach here.

> > +		if (!gpiochip->irq_valid_mask)
> > +			return -ENOMEM;
> > 


> > +		/* Assume by default all GPIOs are valid */
> > +		bitmap_fill(gpiochip->irq_valid_mask, gpiochip-
> > >ngpio);
> > +	}
> > 


> > +	if (gpiochip->line_need_valid_mask) {
> > +		gpiochip->line_valid_mask =
> > +			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> > +				sizeof(long), GFP_KERNEL);
> 
> Since 'line_valid_mask' is getting filled below wouldn't a kmalloc
> suffice?

This one just mimics previous, so, see above.

-- 
Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Intel Finland Oy

[PATCH 0/4] [v7] pinctrl: qcom: add support for sparse GPIOs

[Timur Tabi]

On 11/14/2017 04:03 AM, Linus Walleij wrote:
> The more intrusive design is on my request so I will look at it in detail
> ASAP. I took a quick look and liked what I saw, I just need to make
> sure about the details. Also it'd be nice to have a nod from Bj?rn.
> 
> The main reason for some of the work is ACPI, am I right?

Yes.  We don't have a nice hierarchical tree that lists the individual 
pins and their purposes.  We just have a dumb list of GPIOs.

> Timur could you look quickly at the series posted by Andy Shevchenko
> (6 patches prefixed gpiolib: acpi: ) for augmenting ACPI GPIOs in the core?
> Especially patch 5 and 6 which introduce the ability to add quirks in the
> core.

So this is something that I've never really understood with 
gpiolib-acpi.  I don't think this file is used with the pin control driver.

We do have GpioInt and GpioIo statements in our GPIO table, but they 
don't appear to be using the TLMM (our GPIO / pin control device)

For example:

GpioInt(Level, ActiveHigh, Exclusive, PullNone, , "\\_SB.TCS0.QIC5") {10}

The \\_SB.TCS0 device is NOT the TLMM.  It's our "irq combiner" which 
has something to do with performance measurement.  I think the

I don't think Andy's patch set has anything to do with my patches.  My 
patches just try to register a GPIO device, whereas the gpiolib-acpi 
patches are about ACPI nodes performing gpio-like operations.


> I'd like to get some ARM-based people to look at it to make sure we
> those systems can also quirk their GPIOs if need be.

My patches aren't about a quirk.  All I'm trying to do is registers 
specific GPIOs rather than one giant block of them.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

Fwd: [PATCH 4/4] [v3] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

[Timur Tabi]

On 11/15/2017 12:47 AM, Varadarajan Narayanan wrote:
>> +	if (id->driver_data == QDF2XXX_V1) {
>> +		avail_gpios = num_gpios;
>> +
>> +		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
>> +				     GFP_KERNEL);
> Wouldn't kmalloc suffice since the array gets initialized just below.

Sure.

>> +		if (!gpios)
>> +			return -ENOMEM;
>> +
>> +		for (i = 0; i < avail_gpios; i++)
>> +			gpios[i] = i;
>> +	} else {
>> +		/* The number of GPIOs in the approved list */
>> +		ret = device_property_read_u16_array(&pdev->dev, "gpios",
>> +						     NULL, 0);
>> +		if (ret < 0) {
>> +			dev_err(&pdev->dev, "missing 'num-gpios' property\n");
>> +			return ret;
>> +		}
>> +		if (!ret || ret > MAX_GPIOS) {
> Instead of ret > MAX_GPIOS, should we check for ret > num_gpios?

Yes.

> 
>> +			dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
>> +			return -ENODEV;
>> +		}
> In both the above error messages 'num-gpios' should be 'gpios'

Thanks, I not sure how that got messed up.

> 
>> +		avail_gpios = ret;
>> +
>> +		gpios = devm_kcalloc(&pdev->dev, avail_gpios, sizeof(gpios[0]),
>> +				     GFP_KERNEL);
> devm_kmalloc?

Ok.

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Fwd: [PATCH 2/4] gpiolib: add bitmask for valid GPIO lines

[Timur Tabi]

On 11/15/2017 05:38 AM, Andy Shevchenko wrote:
> I suppose you meant kmalloc_array.
> Anyway, it's a separate change if you wish, because Timur didn't change
> the original approach here.

Unfortunately for me, all of the irq stuff has moved into its own 
structure in 4.15, so I need to rewrite all this code anyway.  I'll drop 
the use of kcalloc.

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[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 11/07, Timur Tabi wrote:
> pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
> each group to support have only one pin (npins == 1).
> 
> We can support "sparse" GPIO maps if we allow for some groups to have zero
> pins (npins == 0).  These pins are "hidden" from the rest of the driver
> and gpiolib.
> 
> A new boolean 'sparse' indicates whether the GPIO map is sparse.  If any
> GPIO has an 'npins' value of 0, then 'sparse' must be set to True.
> 
> Most access to unavailable GPIOs can be blocked via the gpio_chip.request
> function.  The one exception is when gpiochip_add_data() scans all of

If patch 1 is applied is this statement still true?

> the GPIOs without "requesting" them.  To cover this case,

s/GPIOs/GPIOs for their direction/ perhaps?

> msm_gpio_get_direction() separately checks if the GPIO is available.
> 
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[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 11/16/17 8:43 PM, Stephen Boyd wrote:
>> Most access to unavailable GPIOs can be blocked via the gpio_chip.request
>> function.  The one exception is when gpiochip_add_data() scans all of

> If patch 1 is applied is this statement still true?

Nope.

>> the GPIOs without "requesting" them.  To cover this case,
> s/GPIOs/GPIOs for their direction/ perhaps?

Ok.

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[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 11/16, Timur Tabi wrote:
> On 11/16/17 8:43 PM, Stephen Boyd wrote:
> >>Most access to unavailable GPIOs can be blocked via the gpio_chip.request
> >>function.  The one exception is when gpiochip_add_data() scans all of
> 
> >If patch 1 is applied is this statement still true?
> 
> Nope.
> 

Ok. So what's the point of this patch then? Put another way, is
there some path that doesn't request the gpio still even with
patch 1 applied?

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[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 11/17/2017 11:46 AM, Stephen Boyd wrote:
> On 11/16, Timur Tabi wrote:
>> On 11/16/17 8:43 PM, Stephen Boyd wrote:
>>>> Most access to unavailable GPIOs can be blocked via the gpio_chip.request
>>>> function.  The one exception is when gpiochip_add_data() scans all of
>>
>>> If patch 1 is applied is this statement still true?
>>
>> Nope.
>>
> 
> Ok. So what's the point of this patch then? Put another way, is
> there some path that doesn't request the gpio still even with
> patch 1 applied?

This patch is how the pinctrl-msm driver actually reports the sparse 
GPIO map.

Patch 1 prevents gpiolib from accessing GPIOs that haven't been properly 
requested.

Patch 2 adds an infrastructure for sparse GPIO maps

Patch 3 updates pinctrl-msm to use that expose that new infrastructure

Patch 4 updates pinctrl-qdf2xxx to work with the new feature in pinctrl-msm


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[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Stephen Boyd]

On 11/17, Timur Tabi wrote:
> On 11/17/2017 11:46 AM, Stephen Boyd wrote:
> >On 11/16, Timur Tabi wrote:
> >>On 11/16/17 8:43 PM, Stephen Boyd wrote:
> >>>>Most access to unavailable GPIOs can be blocked via the gpio_chip.request
> >>>>function.  The one exception is when gpiochip_add_data() scans all of
> >>
> >>>If patch 1 is applied is this statement still true?
> >>
> >>Nope.
> >>
> >
> >Ok. So what's the point of this patch then? Put another way, is
> >there some path that doesn't request the gpio still even with
> >patch 1 applied?
> 
> This patch is how the pinctrl-msm driver actually reports the sparse
> GPIO map.
> 
> Patch 1 prevents gpiolib from accessing GPIOs that haven't been
> properly requested.
> 
> Patch 2 adds an infrastructure for sparse GPIO maps
> 
> Patch 3 updates pinctrl-msm to use that expose that new infrastructure
> 
> Patch 4 updates pinctrl-qdf2xxx to work with the new feature in pinctrl-msm
> 

Ok. What path doesn't request the gpio though? If we don't have a
path that fails to request the gpio before using it then I don't
see the need for this patch.

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[PATCH 3/4] [v6] pinctrl: qcom: disable GPIO groups with no pins

[Timur Tabi]

On 11/17/2017 03:42 PM, Stephen Boyd wrote:
>> Patch 1 prevents gpiolib from accessing GPIOs that haven't been
>> properly requested.
>>
>> Patch 2 adds an infrastructure for sparse GPIO maps
>>
>> Patch 3 updates pinctrl-msm to use that expose that new infrastructure
>>
>> Patch 4 updates pinctrl-qdf2xxx to work with the new feature in pinctrl-msm
>>
> Ok. What path doesn't request the gpio though? If we don't have a
> path that fails to request the gpio before using it then I don't
> see the need for this patch.

Sorry, I don't understand your question.  Patches 2-4 are all about 
creating a sparse GPIO map.  All patch 1 does is stop initializing all 
the GPIOs with an initial direction.

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[PATCH 2/4] gpiolib: add bitmask for valid GPIO lines

[Archit Taneja]

Hi,

On 11/08/2017 04:37 AM, Timur Tabi wrote:
> Add support for specifying that some GPIOs within a range are unavailable.
> Some systems have a sparse list of GPIOs, where a range of GPIOs is
> specified (usually 0 to n-1), but some subset within that range is
> absent or unavailable for whatever reason.
> 
> To support this, allow drivers to specify a bitmask of GPIOs that
> are present or absent.  Gpiolib will then block access to those that
> are absent.
> 
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
>   drivers/gpio/gpiolib.c      | 43 +++++++++++++++++++++++++++++++++++--------
>   include/linux/gpio/driver.h |  2 ++
>   2 files changed, 37 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
> index 60553af4c004..c32387936cdd 100644
> --- a/drivers/gpio/gpiolib.c
> +++ b/drivers/gpio/gpiolib.c
> @@ -1481,22 +1481,36 @@ static struct gpio_chip *find_chip_by_name(const char *name)
>   
>   static int gpiochip_irqchip_init_valid_mask(struct gpio_chip *gpiochip)
>   {
> -	if (!gpiochip->irq_need_valid_mask)
> -		return 0;
> +	if (gpiochip->irq_need_valid_mask) {
> +		gpiochip->irq_valid_mask =
> +			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> +				sizeof(long), GFP_KERNEL);
> +		if (!gpiochip->irq_valid_mask)
> +			return -ENOMEM;
>   
> -	gpiochip->irq_valid_mask = kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> -					   sizeof(long), GFP_KERNEL);
> -	if (!gpiochip->irq_valid_mask)
> -		return -ENOMEM;
> +		/* Assume by default all GPIOs are valid */
> +		bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
> +	}
>   
> -	/* Assume by default all GPIOs are valid */
> -	bitmap_fill(gpiochip->irq_valid_mask, gpiochip->ngpio);
> +	if (gpiochip->line_need_valid_mask) {
> +		gpiochip->line_valid_mask =
> +			kcalloc(BITS_TO_LONGS(gpiochip->ngpio),
> +				sizeof(long), GFP_KERNEL);
> +		if (!gpiochip->line_valid_mask)
> +			return -ENOMEM;
> +
> +		/* Assume by default all GPIOs are valid */
> +		bitmap_fill(gpiochip->line_valid_mask, gpiochip->ngpio);
> +	}
>   
>   	return 0;
>   }
>   
>   static void gpiochip_irqchip_free_valid_mask(struct gpio_chip *gpiochip)
>   {
> +	kfree(gpiochip->line_valid_mask);
> +	gpiochip->line_valid_mask = NULL;
> +
>   	kfree(gpiochip->irq_valid_mask);
>   	gpiochip->irq_valid_mask = NULL;
>   }
> @@ -1510,6 +1524,15 @@ static bool gpiochip_irqchip_irq_valid(const struct gpio_chip *gpiochip,
>   	return test_bit(offset, gpiochip->irq_valid_mask);
>   }
>   
> +static bool gpiochip_irqchip_line_valid(const struct gpio_chip *gpiochip,
> +					unsigned int offset)
> +{
> +	/* No mask means all valid */
> +	if (likely(!gpiochip->line_valid_mask))
> +		return true;
> +	return test_bit(offset, gpiochip->line_valid_mask);
> +}
> +
>   /**
>    * gpiochip_set_cascaded_irqchip() - connects a cascaded irqchip to a gpiochip
>    * @gpiochip: the gpiochip to set the irqchip chain to
> @@ -3320,6 +3343,10 @@ struct gpio_desc *__must_check gpiod_get_index(struct device *dev,
>   		return desc;
>   	}
>   
> +	/* Make sure the GPIO is valid before we request it. */
> +	if (!gpiochip_irqchip_line_valid(desc->gdev->chip, idx))
> +		return ERR_PTR(-EACCES);

We're hitting an issue here ^ when a consumer calls the devm_gpiod_get() API. This API
internally sets idx in gpiod_get_index to always 0. For example, in the call sequence
below, the idx argument to gpiochip_irqchip_line_valid is always 0:

devm_gpiod_get(dev, con_id, flags)
    devm_gpiod_get_index(dev, con_id, 0, flags)
       gpiod_get_index(dev, con_id, 0, flags)
          if (!gpiochip_irqchip_line_valid(desc->gdev->chip, 0))
              return ERR_PTR(-EACCES);

Therefore, with these patches, if we create a sparse gpio map, and the
0th gpio is set to "not accessible", all gpio requests end up failing with EACCESS
because idx is always passed as 0.

In gpiochip_irqchip_line_valid, shouldn't we test the nth bit (that corresponds to
this gpio_desc) in chip->line_valid_mask instead of idx passed above, which is always
0?

Thanks,
Archit


> +
>   	status = gpiod_request(desc, con_id);
>   	if (status < 0)
>   		return ERR_PTR(status);
> diff --git a/include/linux/gpio/driver.h b/include/linux/gpio/driver.h
> index 424e5139ff10..853828ccabc8 100644
> --- a/include/linux/gpio/driver.h
> +++ b/include/linux/gpio/driver.h
> @@ -173,6 +173,8 @@ struct gpio_chip {
>   	bool			irq_nested;
>   	bool			irq_need_valid_mask;
>   	unsigned long		*irq_valid_mask;
> +	bool			line_need_valid_mask;
> +	unsigned long		*line_valid_mask;
>   	struct lock_class_key	*lock_key;
>   #endif
>   
> 

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[PATCH 2/4] gpiolib: add bitmask for valid GPIO lines

[Timur Tabi]

On 12/01/2017 05:38 AM, Archit Taneja wrote:
> 
> We're hitting an issue here ^ when a consumer calls the devm_gpiod_get() 
> API. This API
> internally sets idx in gpiod_get_index to always 0. For example, in the 
> call sequence
> below, the idx argument to gpiochip_irqchip_line_valid is always 0:
> 
> devm_gpiod_get(dev, con_id, flags)
>  ?? devm_gpiod_get_index(dev, con_id, 0, flags)
>  ????? gpiod_get_index(dev, con_id, 0, flags)
>  ???????? if (!gpiochip_irqchip_line_valid(desc->gdev->chip, 0))
>  ???????????? return ERR_PTR(-EACCES);
> 
> Therefore, with these patches, if we create a sparse gpio map, and the
> 0th gpio is set to "not accessible", all gpio requests end up failing 
> with EACCESS
> because idx is always passed as 0.

Ok, I can see the problem, but I don't know how to fix it.

struct gpio_desc *__must_check devm_gpiod_get(struct device *dev,
					      const char *con_id,
					      enum gpiod_flags flags)
{
	return devm_gpiod_get_index(dev, con_id, 0, flags);
}

I thought that by putting the check for "availability" inside of the 
GPIO request, it would handle all situations where a client (whether 
kernel or user-space) tries to access a specific GPIO.

However, this doesn't work with [devm_]gpiod_get.  This function 
attempts to claim the entire GPIO block by claiming only the first GPIO.

This is straining my understanding of gpiolib.  Maybe we need to do 
something like this:

struct gpio_desc *__must_check gpiod_get(struct device *dev, const char 
*con_id,
					 enum gpiod_flags flags)
{
	return gpiod_get_index(dev, con_id, -1, flags);
}

Where idx == -1 is a special-case for gpiod_get_index() where it returns 
the gpio_desc without actually requesting it?

> In gpiochip_irqchip_line_valid, shouldn't we test the nth bit (that 
> corresponds to
> this gpio_desc) in chip->line_valid_mask instead of idx passed above, 
> which is always
> 0?

The code has changed upstream, so I need to refactor that function.  But 
I think it's already testing the nth bit:

static bool gpiochip_irqchip_line_valid(const struct gpio_chip gpiochip,
					unsigned int offset)
{
	/* No mask means all valid */
	if (likely(!gpiochip->line_valid_mask))
		return true;
	return test_bit(offset, gpiochip->line_valid_mask);

'offset' is the nth bit.

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