* [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change
@ 2017-04-05 12:50 Icenowy Zheng
2017-04-05 12:50 ` [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Icenowy Zheng
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Icenowy Zheng @ 2017-04-05 12:50 UTC (permalink / raw)
To: linux-arm-kernel
This patchset contains devicetree parts of the EHCI0/OHCI0 controllers
on A64 SoC.
The first patch is a devicetree binding change, which has been planned
for 4.12; however, as Maxime Ripard suggested, it should go in 4.11
as it's part of the device's description.
The second patch added pmu0 regs and EHCI/OHCI controllers for USB0.
The third patch enabled EHCI0/OHCI0 for Pine64 board.
This patchset should go in 4.11 as Maxime Ripard suggested.
Icenowy Zheng (3):
dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++
3 files changed, 33 insertions(+)
--
2.12.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
2017-04-05 12:50 [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change Icenowy Zheng
@ 2017-04-05 12:50 ` Icenowy Zheng
2017-04-05 12:58 ` Kishon Vijay Abraham I
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
2017-04-05 12:50 ` [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64 Icenowy Zheng
2 siblings, 1 reply; 7+ messages in thread
From: Icenowy Zheng @ 2017-04-05 12:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Icenowy Zheng <icenowy@aosc.xyz>
Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.
When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Kishon, could you push this to 4.11?
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
index e42334258185..005bc22938ff 100644
--- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
+++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
@@ -15,6 +15,7 @@ Required properties:
- reg : a list of offset + length pairs
- reg-names :
* "phy_ctrl"
+ * "pmu0" for H3, V3s and A64
* "pmu1"
* "pmu2" for sun4i, sun6i or sun7i
- #phy-cells : from the generic phy bindings, must be 1
--
2.12.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
2017-04-05 12:50 [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change Icenowy Zheng
2017-04-05 12:50 ` [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Icenowy Zheng
@ 2017-04-05 12:50 ` Icenowy Zheng
2017-04-05 13:05 ` Maxime Ripard
2017-04-05 12:50 ` [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64 Icenowy Zheng
2 siblings, 1 reply; 7+ messages in thread
From: Icenowy Zheng @ 2017-04-05 12:50 UTC (permalink / raw)
To: linux-arm-kernel
As we added USB0 route auto switching support for A64, add related
device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
pmu0 memory area for PHY).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1c64ea2d23f9..a8916df99048 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -179,8 +179,10 @@
usbphy: phy at 01c19400 {
compatible = "allwinner,sun50i-a64-usb-phy";
reg = <0x01c19400 0x14>,
+ <0x01c1a800 0x4>,
<0x01c1b800 0x4>;
reg-names = "phy_ctrl",
+ "pmu0",
"pmu1";
clocks = <&ccu CLK_USB_PHY0>,
<&ccu CLK_USB_PHY1>;
@@ -194,6 +196,28 @@
#phy-cells = <1>;
};
+ ehci0: usb at 01c1a000 {
+ compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
+ reg = <0x01c1a000 0x100>;
+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_BUS_EHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>,
+ <&ccu RST_BUS_EHCI0>;
+ status = "disabled";
+ };
+
+ ohci0: usb at 01c1a400 {
+ compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
+ reg = <0x01c1a400 0x100>;
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_OHCI0>,
+ <&ccu CLK_USB_OHCI0>;
+ resets = <&ccu RST_BUS_OHCI0>;
+ status = "disabled";
+ };
+
ehci1: usb at 01c1b000 {
compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
reg = <0x01c1b000 0x100>;
--
2.12.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64
2017-04-05 12:50 [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change Icenowy Zheng
2017-04-05 12:50 ` [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Icenowy Zheng
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
@ 2017-04-05 12:50 ` Icenowy Zheng
2 siblings, 0 replies; 7+ messages in thread
From: Icenowy Zheng @ 2017-04-05 12:50 UTC (permalink / raw)
To: linux-arm-kernel
The upper USB port of Pine64 board is connected to the SoC's USB0 port,
which can now switch from the MUSB controller to the EHCI/OHCI pair.
Enable the EHCI/OHCI pair in the Pine64 device tree.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index c680ed385da3..4782add50b94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -66,6 +66,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -91,6 +95,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
--
2.12.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
2017-04-05 12:50 ` [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Icenowy Zheng
@ 2017-04-05 12:58 ` Kishon Vijay Abraham I
2017-04-05 16:13 ` Chen-Yu Tsai
0 siblings, 1 reply; 7+ messages in thread
From: Kishon Vijay Abraham I @ 2017-04-05 12:58 UTC (permalink / raw)
To: linux-arm-kernel
On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote:
> From: Icenowy Zheng <icenowy@aosc.xyz>
>
> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>
> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>
> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> Acked-by: Chen-Yu Tsai <wens@csie.org>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
>
> Kishon, could you push this to 4.11?
Is this for the patch titled "phy: sun4i-usb: add support for V3s USB PHY" that
was added during the last merge window.
this patch looks simpler enough to be merged in this -rc cycle. However it
depends on Greg KH.
Thanks
Kishon
>
> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> index e42334258185..005bc22938ff 100644
> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
> @@ -15,6 +15,7 @@ Required properties:
> - reg : a list of offset + length pairs
> - reg-names :
> * "phy_ctrl"
> + * "pmu0" for H3, V3s and A64
> * "pmu1"
> * "pmu2" for sun4i, sun6i or sun7i
> - #phy-cells : from the generic phy bindings, must be 1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
@ 2017-04-05 13:05 ` Maxime Ripard
0 siblings, 0 replies; 7+ messages in thread
From: Maxime Ripard @ 2017-04-05 13:05 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Apr 05, 2017 at 08:50:52PM +0800, Icenowy Zheng wrote:
> As we added USB0 route auto switching support for A64, add related
> device tree parts to the A64 DTSI file (EHCI0/OHCI0 controllers and the
> pmu0 memory area for PHY).
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 1c64ea2d23f9..a8916df99048 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -179,8 +179,10 @@
> usbphy: phy at 01c19400 {
> compatible = "allwinner,sun50i-a64-usb-phy";
> reg = <0x01c19400 0x14>,
> + <0x01c1a800 0x4>,
> <0x01c1b800 0x4>;
> reg-names = "phy_ctrl",
> + "pmu0",
Again, this needs to be split apart, and sent for 4.11.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
2017-04-05 12:58 ` Kishon Vijay Abraham I
@ 2017-04-05 16:13 ` Chen-Yu Tsai
0 siblings, 0 replies; 7+ messages in thread
From: Chen-Yu Tsai @ 2017-04-05 16:13 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Apr 5, 2017 at 8:58 PM, Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
>
> On Wednesday 05 April 2017 06:20 PM, Icenowy Zheng wrote:
>> From: Icenowy Zheng <icenowy@aosc.xyz>
>>
>> Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
>> controllers: one is MUSB and the other is a EHCI/OHCI pair.
>>
>> When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
>> tweak, like other EHCI/OHCI pairs in Allwinner SoCs.
>>
>> Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.
>>
>> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
>> Acked-by: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> ---
>>
>> Kishon, could you push this to 4.11?
>
> Is this for the patch titled "phy: sun4i-usb: add support for V3s USB PHY" that
> was added during the last merge window.
Yes. In fact, as the description suggests, this also applies retroactively to
H3 and A64, which were added in the following commits:
4.9 732e35da7b4a ("dt: bindings: add bindings for Allwinner A64 usb phy")
4.5 626a630e003c ("phy-sun4i-usb: Add support for the host usb-phys found
on the H3 SoC")
Though this was missed at the time the binding was added.
ChenYu
> this patch looks simpler enough to be merged in this -rc cycle. However it
> depends on Greg KH.
>
> Thanks
> Kishon
>
>>
>> Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> index e42334258185..005bc22938ff 100644
>> --- a/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt
>> @@ -15,6 +15,7 @@ Required properties:
>> - reg : a list of offset + length pairs
>> - reg-names :
>> * "phy_ctrl"
>> + * "pmu0" for H3, V3s and A64
>> * "pmu1"
>> * "pmu2" for sun4i, sun6i or sun7i
>> - #phy-cells : from the generic phy bindings, must be 1
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2017-04-05 16:13 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
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2017-04-05 12:50 [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change Icenowy Zheng
2017-04-05 12:50 ` [PATCH 1/3] dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64 Icenowy Zheng
2017-04-05 12:58 ` Kishon Vijay Abraham I
2017-04-05 16:13 ` Chen-Yu Tsai
2017-04-05 12:50 ` [PATCH 2/3] arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts Icenowy Zheng
2017-04-05 13:05 ` Maxime Ripard
2017-04-05 12:50 ` [PATCH 3/3] arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64 Icenowy Zheng
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