* [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
@ 2016-08-10 5:31 Jisheng Zhang
2016-08-10 5:31 ` [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
2016-08-10 5:31 ` [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
0 siblings, 2 replies; 6+ messages in thread
From: Jisheng Zhang @ 2016-08-10 5:31 UTC (permalink / raw)
To: linux-arm-kernel
patch1 is a trivial clean up: move the parameters for wait for link
into the core pcie-designware.c
Since link may be UP but still in link training, if so, we can't think
the link is up and operating correctly. So patch2 teaches
dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
Since v1:
- add Joao's Ack
- rebased on v4.8-rc1
Jisheng Zhang (2):
PCI: designware: mv parameters for wait for link into
pcie-designware.c
PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
drivers/pci/host/pcie-designware.c | 11 +++++++++--
drivers/pci/host/pcie-designware.h | 5 -----
2 files changed, 9 insertions(+), 7 deletions(-)
--
2.8.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c
2016-08-10 5:31 [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
@ 2016-08-10 5:31 ` Jisheng Zhang
2016-08-14 16:01 ` Pratyush Anand
2016-08-10 5:31 ` [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
1 sibling, 1 reply; 6+ messages in thread
From: Jisheng Zhang @ 2016-08-10 5:31 UTC (permalink / raw)
To: linux-arm-kernel
These parameters are only used in the core pcie-designware.c, let's
move them to the core driver.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
drivers/pci/host/pcie-designware.c | 5 +++++
drivers/pci/host/pcie-designware.h | 5 -----
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 12afce1..24a16dd 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -75,6 +75,11 @@
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
+/* Parameters for the waiting for link up routine */
+#define LINK_WAIT_MAX_RETRIES 10
+#define LINK_WAIT_USLEEP_MIN 90000
+#define LINK_WAIT_USLEEP_MAX 100000
+
static struct pci_ops dw_pcie_ops;
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
index f437f9b..384e79b 100644
--- a/drivers/pci/host/pcie-designware.h
+++ b/drivers/pci/host/pcie-designware.h
@@ -22,11 +22,6 @@
#define MAX_MSI_IRQS 32
#define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
-/* Parameters for the waiting for link up routine */
-#define LINK_WAIT_MAX_RETRIES 10
-#define LINK_WAIT_USLEEP_MIN 90000
-#define LINK_WAIT_USLEEP_MAX 100000
-
struct pcie_port {
struct device *dev;
u8 root_bus_nr;
--
2.8.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
2016-08-10 5:31 [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-08-10 5:31 ` [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
@ 2016-08-10 5:31 ` Jisheng Zhang
2016-08-14 16:00 ` Pratyush Anand
1 sibling, 1 reply; 6+ messages in thread
From: Jisheng Zhang @ 2016-08-10 5:31 UTC (permalink / raw)
To: linux-arm-kernel
The link may be UP but still in link training. In this case, we can't
think the link is up and operating correctly. So we need to teach
dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
This patch also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that
it's consistent with other MACROS.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
---
drivers/pci/host/pcie-designware.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 24a16dd..6cc21bb 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -73,7 +73,8 @@
/* PCIe Port Logic registers */
#define PLR_OFFSET 0x700
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
+#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES 10
@@ -417,7 +418,8 @@ int dw_pcie_link_up(struct pcie_port *pp)
return pp->ops->link_up(pp);
val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
- return val & PCIE_PHY_DEBUG_R1_LINK_UP;
+ return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+ (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
}
static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
--
2.8.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
2016-08-10 5:31 ` [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
@ 2016-08-14 16:00 ` Pratyush Anand
0 siblings, 0 replies; 6+ messages in thread
From: Pratyush Anand @ 2016-08-14 16:00 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 10, 2016 at 11:01 AM, Jisheng Zhang <jszhang@marvell.com> wrote:
> The link may be UP but still in link training. In this case, we can't
> think the link is up and operating correctly. So we need to teach
> dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
>
I have no more access of designware PCIe specification now. Since Joao
has acked it, so I would consider that
PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit exists in older core as well.
If it is there then you have my Acked-by too.
~Pratyush
> This patch also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that
> it's consistent with other MACROS.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
> Acked-by: Joao Pinto <jpinto@synopsys.com>
> ---
> drivers/pci/host/pcie-designware.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 24a16dd..6cc21bb 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -73,7 +73,8 @@
> /* PCIe Port Logic registers */
> #define PLR_OFFSET 0x700
> #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
> -#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
> +#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
> +#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
>
> /* Parameters for the waiting for link up routine */
> #define LINK_WAIT_MAX_RETRIES 10
> @@ -417,7 +418,8 @@ int dw_pcie_link_up(struct pcie_port *pp)
> return pp->ops->link_up(pp);
>
> val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
> - return val & PCIE_PHY_DEBUG_R1_LINK_UP;
> + return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
> + (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
> }
>
> static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
> --
> 2.8.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c
2016-08-10 5:31 ` [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
@ 2016-08-14 16:01 ` Pratyush Anand
0 siblings, 0 replies; 6+ messages in thread
From: Pratyush Anand @ 2016-08-14 16:01 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Aug 10, 2016 at 11:01 AM, Jisheng Zhang <jszhang@marvell.com> wrote:
> These parameters are only used in the core pcie-designware.c, let's
> move them to the core driver.
>
> Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
> ---
> drivers/pci/host/pcie-designware.c | 5 +++++
> drivers/pci/host/pcie-designware.h | 5 -----
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
> index 12afce1..24a16dd 100644
> --- a/drivers/pci/host/pcie-designware.c
> +++ b/drivers/pci/host/pcie-designware.c
> @@ -75,6 +75,11 @@
> #define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
> #define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
>
> +/* Parameters for the waiting for link up routine */
> +#define LINK_WAIT_MAX_RETRIES 10
> +#define LINK_WAIT_USLEEP_MIN 90000
> +#define LINK_WAIT_USLEEP_MAX 100000
> +
> static struct pci_ops dw_pcie_ops;
>
> int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
> diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h
> index f437f9b..384e79b 100644
> --- a/drivers/pci/host/pcie-designware.h
> +++ b/drivers/pci/host/pcie-designware.h
> @@ -22,11 +22,6 @@
> #define MAX_MSI_IRQS 32
> #define MAX_MSI_CTRLS (MAX_MSI_IRQS / 32)
>
> -/* Parameters for the waiting for link up routine */
> -#define LINK_WAIT_MAX_RETRIES 10
> -#define LINK_WAIT_USLEEP_MIN 90000
> -#define LINK_WAIT_USLEEP_MAX 100000
> -
> struct pcie_port {
> struct device *dev;
> u8 root_bus_nr;
> --
> 2.8.1
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit
2016-08-10 10:07 [PATCH v2 0/2] " Jisheng Zhang
@ 2016-08-10 10:07 ` Jisheng Zhang
0 siblings, 0 replies; 6+ messages in thread
From: Jisheng Zhang @ 2016-08-10 10:07 UTC (permalink / raw)
To: linux-arm-kernel
The link may be UP but still in link training. In this case, we can't
think the link is up and operating correctly. So we need to teach
dw_pcie_link_up() beware of the PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING bit.
This patch also rewrite PCIE_PHY_DEBUG_R1_LINK_UP definition so that
it's consistent with other MACROS.
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Joao Pinto <jpinto@synopsys.com>
---
drivers/pci/host/pcie-designware.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 24a16dd..6cc21bb 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -73,7 +73,8 @@
/* PCIe Port Logic registers */
#define PLR_OFFSET 0x700
#define PCIE_PHY_DEBUG_R1 (PLR_OFFSET + 0x2c)
-#define PCIE_PHY_DEBUG_R1_LINK_UP 0x00000010
+#define PCIE_PHY_DEBUG_R1_LINK_UP (0x1 << 4)
+#define PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING (0x1 << 29)
/* Parameters for the waiting for link up routine */
#define LINK_WAIT_MAX_RETRIES 10
@@ -417,7 +418,8 @@ int dw_pcie_link_up(struct pcie_port *pp)
return pp->ops->link_up(pp);
val = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1);
- return val & PCIE_PHY_DEBUG_R1_LINK_UP;
+ return ((val & PCIE_PHY_DEBUG_R1_LINK_UP) &&
+ (!(val & PCIE_PHY_DEBUG_R1_LINK_IN_TRAINING)));
}
static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
--
2.8.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2016-08-14 16:01 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2016-08-10 5:31 [PATCH v2 0/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-08-10 5:31 ` [PATCH v2 1/2] PCI: designware: mv parameters for wait for link into pcie-designware.c Jisheng Zhang
2016-08-14 16:01 ` Pratyush Anand
2016-08-10 5:31 ` [PATCH v2 2/2] PCI: designware: let dw_pcie_link_up() beware of LTSSM training bit Jisheng Zhang
2016-08-14 16:00 ` Pratyush Anand
2016-08-10 10:07 [PATCH v2 0/2] " Jisheng Zhang
2016-08-10 10:07 ` [PATCH v2 2/2] " Jisheng Zhang
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