* [PATCH 1/2] dt-bindings: arm-smmu: Fix json-schema for Tegra
@ 2021-12-01 15:57 Jon Hunter
2021-12-01 15:57 ` [PATCH 2/2] arm64: tegra: Add ISO SMMU controller for Tegra194 Jon Hunter
2021-12-06 20:03 ` [PATCH 1/2] dt-bindings: arm-smmu: Fix json-schema for Tegra Rob Herring
0 siblings, 2 replies; 3+ messages in thread
From: Jon Hunter @ 2021-12-01 15:57 UTC (permalink / raw)
To: Will Deacon, Joerg Roedel, Rob Herring, Thierry Reding
Cc: linux-arm-kernel, iommu, devicetree, linux-tegra, Jon Hunter
The dt_binding_check currently issues the following warnings for the
Tegra186 and Tegra194 SMMUs ...
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml: iommu@12000000:
'nvidia,memory-controller' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/iommu/arm,smmu.yaml
DTC arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml
CHECK arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml
Add the missing 'nvidia,memory-controller' property to fix the above
warning.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
index f66a3effba73..5dce07b12cd7 100644
--- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
+++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml
@@ -155,6 +155,10 @@ properties:
power-domains:
maxItems: 1
+ nvidia,memory-controller:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle of the memory controller node
+
required:
- compatible
- reg
--
2.25.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/2] arm64: tegra: Add ISO SMMU controller for Tegra194
2021-12-01 15:57 [PATCH 1/2] dt-bindings: arm-smmu: Fix json-schema for Tegra Jon Hunter
@ 2021-12-01 15:57 ` Jon Hunter
2021-12-06 20:03 ` [PATCH 1/2] dt-bindings: arm-smmu: Fix json-schema for Tegra Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Jon Hunter @ 2021-12-01 15:57 UTC (permalink / raw)
To: Will Deacon, Joerg Roedel, Rob Herring, Thierry Reding
Cc: linux-arm-kernel, iommu, devicetree, linux-tegra, Jon Hunter
The display controllers are attached to a separate ARM SMMU instance
that is dedicated to servicing isochronous memory clients. Add this ISO
instance of the ARM SMMU to device tree.
Please note that the display controllers are not hooked up to this SMMU
yet, because we are still missing a means to transition framebuffers
used by the bootloader to the kernel.
This based upon an initial patch by Thierry Reding <treding@nvidia.com>.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 76 ++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d78c9ed08c47..496e31b5c637 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1474,6 +1474,82 @@ pmc: pmc@c360000 {
interrupt-controller;
};
+ iommu@10000000 {
+ compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
+ reg = <0x10000000 0x800000>;
+ interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
+ stream-match-mask = <0x7f80>;
+ #global-interrupts = <1>;
+ #iommu-cells = <1>;
+
+ nvidia,memory-controller = <&mc>;
+ status = "okay";
+ };
+
smmu: iommu@12000000 {
compatible = "nvidia,tegra194-smmu", "nvidia,smmu-500";
reg = <0x12000000 0x800000>,
--
2.25.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 1/2] dt-bindings: arm-smmu: Fix json-schema for Tegra
2021-12-01 15:57 [PATCH 1/2] dt-bindings: arm-smmu: Fix json-schema for Tegra Jon Hunter
2021-12-01 15:57 ` [PATCH 2/2] arm64: tegra: Add ISO SMMU controller for Tegra194 Jon Hunter
@ 2021-12-06 20:03 ` Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Rob Herring @ 2021-12-06 20:03 UTC (permalink / raw)
To: Jon Hunter
Cc: Will Deacon, Joerg Roedel, Thierry Reding, linux-arm-kernel,
iommu, devicetree, linux-tegra
On Wed, Dec 1, 2021 at 9:57 AM Jon Hunter <jonathanh@nvidia.com> wrote:
>
> The dt_binding_check currently issues the following warnings for the
dtbs_check
> Tegra186 and Tegra194 SMMUs ...
>
> arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dt.yaml: iommu@12000000:
> 'nvidia,memory-controller' does not match any of the regexes: 'pinctrl-[0-9]+'
> From schema: Documentation/devicetree/bindings/iommu/arm,smmu.yaml
> DTC arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml
> CHECK arch/arm64/boot/dts/nvidia/tegra186-p3509-0000+p3636-0001.dt.yaml
>
> Add the missing 'nvidia,memory-controller' property to fix the above
> warning.
Thierry sent the same change, but made it required. That's not a
compatible change, but could be justified. Please sort out which one
you need applied.
Rob
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^ permalink raw reply [flat|nested] 3+ messages in thread
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