* [PATCH v6 00/10] Host1x context isolation support
@ 2022-06-21 15:10 Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 01/10] iommu/arm-smmu: Attach to host1x context device bus Mikko Perttunen
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
-------------
Merging notes
-------------
The changes to DT bindings should be applied on top of Thierry's patch
'dt-bindings: display: tegra: Convert to json-schema'.
The change to the arm-smmu driver should be omitted if Robin Murphy's
IOMMU bus cleanup series is merged.
***
New in v6:
Rebased on 5.19-rc3 (-next is too broken)
Added patch to fix TRANSCFG offset on NVDEC.
***
***
New in v5:
Rebased
Renamed host1x_context to host1x_memory_context
Small change in DRM side client driver ops to reduce churn with some
upcoming changes
Add NVDEC support
***
***
New in v4:
Addressed review comments. See individual patches.
***
***
New in v3:
Added device tree bindings for new property.
***
***
New in v2:
Added support for Tegra194
Use standard iommu-map property instead of custom mechanism
***
This series adds support for Host1x 'context isolation'. Since
when programming engines through Host1x, userspace can program in
any addresses it wants, we need some way to isolate the engines'
memory spaces. Traditionally this has either been done imperfectly
with a single shared IOMMU domain, or by copying and verifying the
programming command stream at submit time (Host1x firewall).
Since Tegra186 there is a privileged (only usable by kernel)
Host1x opcode that allows setting the stream ID sent by the engine
to the SMMU. So, by allocating a number of context banks and stream
IDs for this purpose, and using this opcode at the beginning of
each job, we can implement isolation. Due to the limited number of
context banks only each process gets its own context, and not
each channel.
This feature also allows sharing engines among multiple VMs when
used with Host1x's hardware virtualization support - up to 8 VMs
can be configured with a subset of allowed stream IDs, enforced
at hardware level.
To implement this, this series adds a new host1x context bus, which
will contain the 'struct device's corresponding to each context
bank / stream ID, changes to device tree and SMMU code to allow
registering the devices and using the bus, as well as the Host1x
stream ID programming code and support in TegraDRM.
Thanks,
Mikko
Mikko Perttunen (9):
iommu/arm-smmu: Attach to host1x context device bus
dt-bindings: host1x: Add iommu-map property
gpu: host1x: Add context device management code
gpu: host1x: Program context stream ID on submission
arm64: tegra: Add Host1x context stream IDs on Tegra186+
drm/tegra: falcon: Set DMACTX field on DMA transactions
drm/tegra: nvdec: Fix TRANSCFG register offset
drm/tegra: Support context isolation
drm/tegra: Implement stream ID related callbacks on engines
Thierry Reding (1):
dt-bindings: display: tegra: Convert to json-schema
.../display/tegra/nvidia,tegra114-mipi.txt | 41 --
.../display/tegra/nvidia,tegra114-mipi.yaml | 74 ++
.../display/tegra/nvidia,tegra124-dpaux.yaml | 149 ++++
.../display/tegra/nvidia,tegra124-sor.yaml | 206 ++++++
.../display/tegra/nvidia,tegra124-vic.yaml | 71 ++
.../display/tegra/nvidia,tegra186-dc.yaml | 85 +++
.../tegra/nvidia,tegra186-display.yaml | 310 ++++++++
.../tegra/nvidia,tegra186-dsi-padctl.yaml | 45 ++
.../display/tegra/nvidia,tegra20-dc.yaml | 181 +++++
.../display/tegra/nvidia,tegra20-dsi.yaml | 159 +++++
.../display/tegra/nvidia,tegra20-epp.yaml | 70 ++
.../display/tegra/nvidia,tegra20-gr2d.yaml | 73 ++
.../display/tegra/nvidia,tegra20-gr3d.yaml | 214 ++++++
.../display/tegra/nvidia,tegra20-hdmi.yaml | 126 ++++
.../display/tegra/nvidia,tegra20-host1x.txt | 675 ------------------
.../display/tegra/nvidia,tegra20-host1x.yaml | 352 +++++++++
.../display/tegra/nvidia,tegra20-isp.yaml | 67 ++
.../display/tegra/nvidia,tegra20-mpe.yaml | 73 ++
.../display/tegra/nvidia,tegra20-tvo.yaml | 58 ++
.../display/tegra/nvidia,tegra20-vi.yaml | 163 +++++
.../display/tegra/nvidia,tegra210-csi.yaml | 52 ++
.../pinctrl/nvidia,tegra124-dpaux-padctl.txt | 59 --
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 11 +
drivers/gpu/drm/tegra/drm.h | 11 +
drivers/gpu/drm/tegra/falcon.c | 8 +
drivers/gpu/drm/tegra/falcon.h | 1 +
drivers/gpu/drm/tegra/nvdec.c | 13 +-
drivers/gpu/drm/tegra/submit.c | 48 +-
drivers/gpu/drm/tegra/uapi.c | 43 +-
drivers/gpu/drm/tegra/vic.c | 67 +-
drivers/gpu/host1x/Makefile | 1 +
drivers/gpu/host1x/context.c | 160 +++++
drivers/gpu/host1x/context.h | 27 +
drivers/gpu/host1x/dev.c | 12 +-
drivers/gpu/host1x/dev.h | 2 +
drivers/gpu/host1x/hw/channel_hw.c | 52 +-
drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +
drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +
drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 +
include/linux/host1x.h | 26 +
41 files changed, 3037 insertions(+), 792 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
create mode 100644 drivers/gpu/host1x/context.c
create mode 100644 drivers/gpu/host1x/context.h
--
2.36.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v6 01/10] iommu/arm-smmu: Attach to host1x context device bus
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 03/10] dt-bindings: host1x: Add iommu-map property Mikko Perttunen
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
Set itself as the IOMMU for the host1x context device bus, containing
"dummy" devices used for Host1x context isolation.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
This patch should only be applied if Robin Murphy's IOMMU bus
refactoring series doesn't get merged in time.
---
drivers/iommu/arm/arm-smmu/arm-smmu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c
index 2ed3594f384e..74c4357f850b 100644
--- a/drivers/iommu/arm/arm-smmu/arm-smmu.c
+++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c
@@ -39,6 +39,7 @@
#include <linux/amba/bus.h>
#include <linux/fsl/mc.h>
+#include <linux/host1x_context_bus.h>
#include "arm-smmu.h"
@@ -2056,8 +2057,20 @@ static int arm_smmu_bus_init(struct iommu_ops *ops)
goto err_reset_pci_ops;
}
#endif
+#ifdef CONFIG_TEGRA_HOST1X_CONTEXT_BUS
+ if (!iommu_present(&host1x_context_device_bus_type)) {
+ err = bus_set_iommu(&host1x_context_device_bus_type, ops);
+ if (err)
+ goto err_reset_fsl_mc_ops;
+ }
+#endif
+
return 0;
+err_reset_fsl_mc_ops: __maybe_unused;
+#ifdef CONFIG_FSL_MC_BUS
+ bus_set_iommu(&fsl_mc_bus_type, NULL);
+#endif
err_reset_pci_ops: __maybe_unused;
#ifdef CONFIG_PCI
bus_set_iommu(&pci_bus_type, NULL);
--
2.36.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 03/10] dt-bindings: host1x: Add iommu-map property
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 01/10] iommu/arm-smmu: Attach to host1x context device bus Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 04/10] gpu: host1x: Add context device management code Mikko Perttunen
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen, Rob Herring
From: Mikko Perttunen <mperttunen@nvidia.com>
Add schema information for specifying context stream IDs. This uses
the standard iommu-map property.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v3:
* New patch
v4:
* Remove memory-contexts subnode.
---
.../bindings/display/tegra/nvidia,tegra20-host1x.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
index 4fd513efb0f7..0adeb03b9e3a 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
@@ -144,6 +144,11 @@ allOf:
reset-names:
maxItems: 1
+ iommu-map:
+ description: Specification of stream IDs available for memory context device
+ use. Should be a mapping of IDs 0..n to IOMMU entries corresponding to
+ usable stream IDs.
+
required:
- reg-names
--
2.36.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 04/10] gpu: host1x: Add context device management code
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 01/10] iommu/arm-smmu: Attach to host1x context device bus Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 03/10] dt-bindings: host1x: Add iommu-map property Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-22 7:24 ` kernel test robot
2022-07-05 2:57 ` kernel test robot
2022-06-21 15:10 ` [PATCH v6 05/10] gpu: host1x: Program context stream ID on submission Mikko Perttunen
` (6 subsequent siblings)
9 siblings, 2 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
Add code to register context devices from device tree, allocate them
out and manage their refcounts.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v2:
* Directly set DMA mask instead of inheriting from Host1x.
* Use iommu-map instead of custom DT property.
v4:
* Use u64 instead of dma_addr_t for DMA mask
* Use unsigned ints for indexes and adjust error handling flow
* Parse iommu-map property at top level host1x DT node
* Use separate DMA mask per device
* Export symbols as GPL
v5:
* Rename host1x_context to host1x_memory_context
---
drivers/gpu/host1x/Makefile | 1 +
drivers/gpu/host1x/context.c | 160 +++++++++++++++++++++++++++++++++++
drivers/gpu/host1x/context.h | 27 ++++++
drivers/gpu/host1x/dev.c | 12 ++-
drivers/gpu/host1x/dev.h | 2 +
include/linux/host1x.h | 18 ++++
6 files changed, 219 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/host1x/context.c
create mode 100644 drivers/gpu/host1x/context.h
diff --git a/drivers/gpu/host1x/Makefile b/drivers/gpu/host1x/Makefile
index c891a3e33844..8a65e13d113a 100644
--- a/drivers/gpu/host1x/Makefile
+++ b/drivers/gpu/host1x/Makefile
@@ -10,6 +10,7 @@ host1x-y = \
debug.o \
mipi.o \
fence.o \
+ context.o \
hw/host1x01.o \
hw/host1x02.o \
hw/host1x04.o \
diff --git a/drivers/gpu/host1x/context.c b/drivers/gpu/host1x/context.c
new file mode 100644
index 000000000000..d7d95b69a72a
--- /dev/null
+++ b/drivers/gpu/host1x/context.c
@@ -0,0 +1,160 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2021, NVIDIA Corporation.
+ */
+
+#include <linux/device.h>
+#include <linux/kref.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/pid.h>
+#include <linux/slab.h>
+
+#include "context.h"
+#include "dev.h"
+
+int host1x_memory_context_list_init(struct host1x *host1x)
+{
+ struct host1x_memory_context_list *cdl = &host1x->context_list;
+ struct device_node *node = host1x->dev->of_node;
+ struct host1x_memory_context *ctx;
+ unsigned int i;
+ int err;
+
+ cdl->devs = NULL;
+ cdl->len = 0;
+ mutex_init(&cdl->lock);
+
+ err = of_property_count_u32_elems(node, "iommu-map");
+ if (err < 0)
+ return 0;
+
+ cdl->devs = kcalloc(err, sizeof(*cdl->devs), GFP_KERNEL);
+ if (!cdl->devs)
+ return -ENOMEM;
+ cdl->len = err / 4;
+
+ for (i = 0; i < cdl->len; i++) {
+ struct iommu_fwspec *fwspec;
+
+ ctx = &cdl->devs[i];
+
+ ctx->host = host1x;
+
+ device_initialize(&ctx->dev);
+
+ /*
+ * Due to an issue with T194 NVENC, only 38 bits can be used.
+ * Anyway, 256GiB of IOVA ought to be enough for anyone.
+ */
+ ctx->dma_mask = DMA_BIT_MASK(38);
+ ctx->dev.dma_mask = &ctx->dma_mask;
+ ctx->dev.coherent_dma_mask = ctx->dma_mask;
+ dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
+ ctx->dev.bus = &host1x_context_device_bus_type;
+ ctx->dev.parent = host1x->dev;
+
+ dma_set_max_seg_size(&ctx->dev, UINT_MAX);
+
+ err = device_add(&ctx->dev);
+ if (err) {
+ dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
+ goto del_devices;
+ }
+
+ err = of_dma_configure_id(&ctx->dev, node, true, &i);
+ if (err) {
+ dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
+ i, err);
+ device_del(&ctx->dev);
+ goto del_devices;
+ }
+
+ fwspec = dev_iommu_fwspec_get(&ctx->dev);
+ if (!fwspec) {
+ dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
+ device_del(&ctx->dev);
+ goto del_devices;
+ }
+
+ ctx->stream_id = fwspec->ids[0] & 0xffff;
+ }
+
+ return 0;
+
+del_devices:
+ while (i--)
+ device_del(&cdl->devs[i].dev);
+
+ kfree(cdl->devs);
+ cdl->len = 0;
+
+ return err;
+}
+
+void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl)
+{
+ unsigned int i;
+
+ for (i = 0; i < cdl->len; i++)
+ device_del(&cdl->devs[i].dev);
+
+ kfree(cdl->devs);
+ cdl->len = 0;
+}
+
+struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+ struct pid *pid)
+{
+ struct host1x_memory_context_list *cdl = &host1x->context_list;
+ struct host1x_memory_context *free = NULL;
+ int i;
+
+ if (!cdl->len)
+ return ERR_PTR(-EOPNOTSUPP);
+
+ mutex_lock(&cdl->lock);
+
+ for (i = 0; i < cdl->len; i++) {
+ struct host1x_memory_context *cd = &cdl->devs[i];
+
+ if (cd->owner == pid) {
+ refcount_inc(&cd->ref);
+ mutex_unlock(&cdl->lock);
+ return cd;
+ } else if (!cd->owner && !free) {
+ free = cd;
+ }
+ }
+
+ if (!free) {
+ mutex_unlock(&cdl->lock);
+ return ERR_PTR(-EBUSY);
+ }
+
+ refcount_set(&free->ref, 1);
+ free->owner = get_pid(pid);
+
+ mutex_unlock(&cdl->lock);
+
+ return free;
+}
+EXPORT_SYMBOL_GPL(host1x_memory_context_alloc);
+
+void host1x_memory_context_get(struct host1x_memory_context *cd)
+{
+ refcount_inc(&cd->ref);
+}
+EXPORT_SYMBOL_GPL(host1x_memory_context_get);
+
+void host1x_memory_context_put(struct host1x_memory_context *cd)
+{
+ struct host1x_memory_context_list *cdl = &cd->host->context_list;
+
+ if (refcount_dec_and_mutex_lock(&cd->ref, &cdl->lock)) {
+ put_pid(cd->owner);
+ cd->owner = NULL;
+ mutex_unlock(&cdl->lock);
+ }
+}
+EXPORT_SYMBOL_GPL(host1x_memory_context_put);
diff --git a/drivers/gpu/host1x/context.h b/drivers/gpu/host1x/context.h
new file mode 100644
index 000000000000..db8ff0a1f4f3
--- /dev/null
+++ b/drivers/gpu/host1x/context.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Host1x context devices
+ *
+ * Copyright (c) 2020, NVIDIA Corporation.
+ */
+
+#ifndef __HOST1X_CONTEXT_H
+#define __HOST1X_CONTEXT_H
+
+#include <linux/mutex.h>
+#include <linux/refcount.h>
+
+struct host1x;
+
+extern struct bus_type host1x_context_device_bus_type;
+
+struct host1x_memory_context_list {
+ struct mutex lock;
+ struct host1x_memory_context *devs;
+ unsigned int len;
+};
+
+int host1x_memory_context_list_init(struct host1x *host1x);
+void host1x_memory_context_list_free(struct host1x_memory_context_list *cdl);
+
+#endif
diff --git a/drivers/gpu/host1x/dev.c b/drivers/gpu/host1x/dev.c
index 80c685ab3e30..89cc79a48eab 100644
--- a/drivers/gpu/host1x/dev.c
+++ b/drivers/gpu/host1x/dev.c
@@ -28,6 +28,7 @@
#include "bus.h"
#include "channel.h"
+#include "context.h"
#include "debug.h"
#include "dev.h"
#include "intr.h"
@@ -503,10 +504,16 @@ static int host1x_probe(struct platform_device *pdev)
goto iommu_exit;
}
+ err = host1x_memory_context_list_init(host);
+ if (err) {
+ dev_err(&pdev->dev, "failed to initialize context list\n");
+ goto free_channels;
+ }
+
err = host1x_syncpt_init(host);
if (err) {
dev_err(&pdev->dev, "failed to initialize syncpts\n");
- goto free_channels;
+ goto free_contexts;
}
err = host1x_intr_init(host, syncpt_irq);
@@ -550,6 +557,8 @@ static int host1x_probe(struct platform_device *pdev)
host1x_intr_deinit(host);
deinit_syncpt:
host1x_syncpt_deinit(host);
+free_contexts:
+ host1x_memory_context_list_free(&host->context_list);
free_channels:
host1x_channel_list_free(&host->channel_list);
iommu_exit:
@@ -571,6 +580,7 @@ static int host1x_remove(struct platform_device *pdev)
host1x_intr_deinit(host);
host1x_syncpt_deinit(host);
+ host1x_memory_context_list_free(&host->context_list);
host1x_channel_list_free(&host->channel_list);
host1x_iommu_exit(host);
host1x_bo_cache_destroy(&host->cache);
diff --git a/drivers/gpu/host1x/dev.h b/drivers/gpu/host1x/dev.h
index ca4b082f0cd4..7552a4554534 100644
--- a/drivers/gpu/host1x/dev.h
+++ b/drivers/gpu/host1x/dev.h
@@ -14,6 +14,7 @@
#include "cdma.h"
#include "channel.h"
+#include "context.h"
#include "intr.h"
#include "job.h"
#include "syncpt.h"
@@ -141,6 +142,7 @@ struct host1x {
struct mutex syncpt_mutex;
struct host1x_channel_list channel_list;
+ struct host1x_memory_context_list context_list;
struct dentry *debugfs;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index c0bf4e581fe9..3f368fdb8445 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -446,4 +446,22 @@ int tegra_mipi_disable(struct tegra_mipi_device *device);
int tegra_mipi_start_calibration(struct tegra_mipi_device *device);
int tegra_mipi_finish_calibration(struct tegra_mipi_device *device);
+/* host1x memory contexts */
+
+struct host1x_memory_context {
+ struct host1x *host;
+
+ refcount_t ref;
+ struct pid *owner;
+
+ struct device dev;
+ u64 dma_mask;
+ u32 stream_id;
+};
+
+struct host1x_memory_context *host1x_memory_context_alloc(struct host1x *host1x,
+ struct pid *pid);
+void host1x_memory_context_get(struct host1x_memory_context *cd);
+void host1x_memory_context_put(struct host1x_memory_context *cd);
+
#endif
--
2.36.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 05/10] gpu: host1x: Program context stream ID on submission
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
` (2 preceding siblings ...)
2022-06-21 15:10 ` [PATCH v6 04/10] gpu: host1x: Add context device management code Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 06/10] arm64: tegra: Add Host1x context stream IDs on Tegra186+ Mikko Perttunen
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
Add code to do stream ID switching at the beginning of a job. The
stream ID is switched to the stream ID specified by the context
passed in the job structure.
Before switching the stream ID, an OP_DONE wait is done on the
channel's engine to ensure that there is no residual ongoing
work that might do DMA using the new stream ID.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5:
* Add fallback stream ID. Not used yet, will be needed for
full featured opcode sequence.
* Rename host1x_context to host1x_memory_context
v4:
* Rename job->context to job->memory_context for clarity
---
drivers/gpu/host1x/hw/channel_hw.c | 52 +++++++++++++++++++++--
drivers/gpu/host1x/hw/host1x06_hardware.h | 10 +++++
drivers/gpu/host1x/hw/host1x07_hardware.h | 10 +++++
include/linux/host1x.h | 8 ++++
4 files changed, 76 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/host1x/hw/channel_hw.c b/drivers/gpu/host1x/hw/channel_hw.c
index 6b40e9af1e88..f84caf06621a 100644
--- a/drivers/gpu/host1x/hw/channel_hw.c
+++ b/drivers/gpu/host1x/hw/channel_hw.c
@@ -180,6 +180,45 @@ static void host1x_enable_gather_filter(struct host1x_channel *ch)
#endif
}
+static void host1x_channel_program_engine_streamid(struct host1x_job *job)
+{
+#if HOST1X_HW >= 6
+ u32 fence;
+
+ if (!job->memory_context)
+ return;
+
+ fence = host1x_syncpt_incr_max(job->syncpt, 1);
+
+ /* First, increment a syncpoint on OP_DONE condition.. */
+
+ host1x_cdma_push(&job->channel->cdma,
+ host1x_opcode_nonincr(HOST1X_UCLASS_INCR_SYNCPT, 1),
+ HOST1X_UCLASS_INCR_SYNCPT_INDX_F(job->syncpt->id) |
+ HOST1X_UCLASS_INCR_SYNCPT_COND_F(1));
+
+ /* Wait for syncpoint to increment */
+
+ host1x_cdma_push(&job->channel->cdma,
+ host1x_opcode_setclass(HOST1X_CLASS_HOST1X,
+ host1x_uclass_wait_syncpt_r(), 1),
+ host1x_class_host_wait_syncpt(job->syncpt->id, fence));
+
+ /*
+ * Now that we know the engine is idle, return to class and
+ * change stream ID.
+ */
+
+ host1x_cdma_push(&job->channel->cdma,
+ host1x_opcode_setclass(job->class, 0, 0),
+ HOST1X_OPCODE_NOP);
+
+ host1x_cdma_push(&job->channel->cdma,
+ host1x_opcode_setpayload(job->memory_context->stream_id),
+ host1x_opcode_setstreamid(job->engine_streamid_offset / 4));
+#endif
+}
+
static int channel_submit(struct host1x_job *job)
{
struct host1x_channel *ch = job->channel;
@@ -236,18 +275,23 @@ static int channel_submit(struct host1x_job *job)
if (sp->base)
synchronize_syncpt_base(job);
- syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
-
host1x_hw_syncpt_assign_to_channel(host, sp, ch);
- job->syncpt_end = syncval;
-
/* add a setclass for modules that require it */
if (job->class)
host1x_cdma_push(&ch->cdma,
host1x_opcode_setclass(job->class, 0, 0),
HOST1X_OPCODE_NOP);
+ /*
+ * Ensure engine DMA is idle and set new stream ID. May increment
+ * syncpt max.
+ */
+ host1x_channel_program_engine_streamid(job);
+
+ syncval = host1x_syncpt_incr_max(sp, user_syncpt_incrs);
+ job->syncpt_end = syncval;
+
submit_gathers(job, syncval - user_syncpt_incrs);
/* end CDMA submit & stash pinned hMems into sync queue */
diff --git a/drivers/gpu/host1x/hw/host1x06_hardware.h b/drivers/gpu/host1x/hw/host1x06_hardware.h
index 01a142a09800..5d515745eee7 100644
--- a/drivers/gpu/host1x/hw/host1x06_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x06_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
}
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+ return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+ return (9 << 28) | payload;
+}
+
static inline u32 host1x_opcode_gather_wide(unsigned count)
{
return (12 << 28) | count;
diff --git a/drivers/gpu/host1x/hw/host1x07_hardware.h b/drivers/gpu/host1x/hw/host1x07_hardware.h
index e6582172ebfd..82c0cc9bb0b5 100644
--- a/drivers/gpu/host1x/hw/host1x07_hardware.h
+++ b/drivers/gpu/host1x/hw/host1x07_hardware.h
@@ -127,6 +127,16 @@ static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
}
+static inline u32 host1x_opcode_setstreamid(unsigned streamid)
+{
+ return (7 << 28) | streamid;
+}
+
+static inline u32 host1x_opcode_setpayload(unsigned payload)
+{
+ return (9 << 28) | payload;
+}
+
static inline u32 host1x_opcode_gather_wide(unsigned count)
{
return (12 << 28) | count;
diff --git a/include/linux/host1x.h b/include/linux/host1x.h
index 3f368fdb8445..3c5f1c23bd63 100644
--- a/include/linux/host1x.h
+++ b/include/linux/host1x.h
@@ -327,6 +327,14 @@ struct host1x_job {
/* Whether host1x-side firewall should be ran for this job or not */
bool enable_firewall;
+
+ /* Options for configuring engine data stream ID */
+ /* Context device to use for job */
+ struct host1x_memory_context *memory_context;
+ /* Stream ID to use if context isolation is disabled (!memory_context) */
+ u32 engine_fallback_streamid;
+ /* Engine offset to program stream ID to */
+ u32 engine_streamid_offset;
};
struct host1x_job *host1x_job_alloc(struct host1x_channel *ch,
--
2.36.1
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 06/10] arm64: tegra: Add Host1x context stream IDs on Tegra186+
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
` (3 preceding siblings ...)
2022-06-21 15:10 ` [PATCH v6 05/10] gpu: host1x: Program context stream ID on submission Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 07/10] drm/tegra: falcon: Set DMACTX field on DMA transactions Mikko Perttunen
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
Add Host1x context stream IDs on systems that support Host1x context
isolation. Host1x and attached engines can use these stream IDs to
allow isolation between memory used by different processes.
The specified stream IDs must match those configured by the hypervisor,
if one is present.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v2:
* Added context devices on T194.
* Use iommu-map instead of custom property.
v4:
* Remove memory-contexts subnode.
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 11 +++++++++++
arch/arm64/boot/dts/nvidia/tegra194.dtsi | 11 +++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 0e9afc3e2f26..5f560f13ed93 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1461,6 +1461,17 @@ host1x@13e00000 {
iommus = <&smmu TEGRA186_SID_HOST1X>;
+ /* Context isolation domains */
+ iommu-map = <
+ 0 &smmu TEGRA186_SID_HOST1X_CTX0 1
+ 1 &smmu TEGRA186_SID_HOST1X_CTX1 1
+ 2 &smmu TEGRA186_SID_HOST1X_CTX2 1
+ 3 &smmu TEGRA186_SID_HOST1X_CTX3 1
+ 4 &smmu TEGRA186_SID_HOST1X_CTX4 1
+ 5 &smmu TEGRA186_SID_HOST1X_CTX5 1
+ 6 &smmu TEGRA186_SID_HOST1X_CTX6 1
+ 7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
+
dpaux1: dpaux@15040000 {
compatible = "nvidia,tegra186-dpaux";
reg = <0x15040000 0x10000>;
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d1f8248c00f4..613fd71dec25 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1769,6 +1769,17 @@ host1x@13e00000 {
interconnect-names = "dma-mem";
iommus = <&smmu TEGRA194_SID_HOST1X>;
+ /* Context isolation domains */
+ iommu-map = <
+ 0 &smmu TEGRA194_SID_HOST1X_CTX0 1
+ 1 &smmu TEGRA194_SID_HOST1X_CTX1 1
+ 2 &smmu TEGRA194_SID_HOST1X_CTX2 1
+ 3 &smmu TEGRA194_SID_HOST1X_CTX3 1
+ 4 &smmu TEGRA194_SID_HOST1X_CTX4 1
+ 5 &smmu TEGRA194_SID_HOST1X_CTX5 1
+ 6 &smmu TEGRA194_SID_HOST1X_CTX6 1
+ 7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
+
nvdec@15140000 {
compatible = "nvidia,tegra194-nvdec";
reg = <0x15140000 0x00040000>;
--
2.36.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 07/10] drm/tegra: falcon: Set DMACTX field on DMA transactions
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
` (4 preceding siblings ...)
2022-06-21 15:10 ` [PATCH v6 06/10] arm64: tegra: Add Host1x context stream IDs on Tegra186+ Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 08/10] drm/tegra: nvdec: Fix TRANSCFG register offset Mikko Perttunen
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
The DMACTX field determines which context, as specified in the
TRANSCFG register, is used. While during boot it doesn't matter
which is used, later on it matters and this value is reused by
the firmware.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
drivers/gpu/drm/tegra/falcon.c | 8 ++++++++
drivers/gpu/drm/tegra/falcon.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers/gpu/drm/tegra/falcon.c b/drivers/gpu/drm/tegra/falcon.c
index 3762d87759d9..c0d85463eb1a 100644
--- a/drivers/gpu/drm/tegra/falcon.c
+++ b/drivers/gpu/drm/tegra/falcon.c
@@ -48,6 +48,14 @@ static int falcon_copy_chunk(struct falcon *falcon,
if (target == FALCON_MEMORY_IMEM)
cmd |= FALCON_DMATRFCMD_IMEM;
+ /*
+ * Use second DMA context (i.e. the one for firmware). Strictly
+ * speaking, at this point both DMA contexts point to the firmware
+ * stream ID, but this register's value will be reused by the firmware
+ * for later DMA transactions, so we need to use the correct value.
+ */
+ cmd |= FALCON_DMATRFCMD_DMACTX(1);
+
falcon_writel(falcon, offset, FALCON_DMATRFMOFFS);
falcon_writel(falcon, base, FALCON_DMATRFFBOFFS);
falcon_writel(falcon, cmd, FALCON_DMATRFCMD);
diff --git a/drivers/gpu/drm/tegra/falcon.h b/drivers/gpu/drm/tegra/falcon.h
index c56ee32d92ee..1955cf11a8a6 100644
--- a/drivers/gpu/drm/tegra/falcon.h
+++ b/drivers/gpu/drm/tegra/falcon.h
@@ -50,6 +50,7 @@
#define FALCON_DMATRFCMD_IDLE (1 << 1)
#define FALCON_DMATRFCMD_IMEM (1 << 4)
#define FALCON_DMATRFCMD_SIZE_256B (6 << 8)
+#define FALCON_DMATRFCMD_DMACTX(v) (((v) & 0x7) << 12)
#define FALCON_DMATRFFBOFFS 0x0000111c
--
2.36.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 08/10] drm/tegra: nvdec: Fix TRANSCFG register offset
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
` (5 preceding siblings ...)
2022-06-21 15:10 ` [PATCH v6 07/10] drm/tegra: falcon: Set DMACTX field on DMA transactions Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 09/10] drm/tegra: Support context isolation Mikko Perttunen
` (2 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
NVDEC's TRANSCFG register is at a different offset than VIC.
This becomes a problem now when context isolation is enabled and
the reset value of the register is no longer sufficient.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v6:
* New patch
---
drivers/gpu/drm/tegra/nvdec.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 79e1e88203cf..386f9b2e78c4 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -21,6 +21,8 @@
#include "falcon.h"
#include "vic.h"
+#define NVDEC_TFBIF_TRANSCFG 0x2c44
+
struct nvdec_config {
const char *firmware;
unsigned int version;
@@ -63,7 +65,7 @@ static int nvdec_boot(struct nvdec *nvdec)
u32 value;
value = TRANSCFG_ATT(1, TRANSCFG_SID_FALCON) | TRANSCFG_ATT(0, TRANSCFG_SID_HW);
- nvdec_writel(nvdec, value, VIC_TFBIF_TRANSCFG);
+ nvdec_writel(nvdec, value, NVDEC_TFBIF_TRANSCFG);
if (spec->num_ids > 0) {
value = spec->ids[0] & 0xffff;
--
2.36.1
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 09/10] drm/tegra: Support context isolation
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
` (6 preceding siblings ...)
2022-06-21 15:10 ` [PATCH v6 08/10] drm/tegra: nvdec: Fix TRANSCFG register offset Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 10/10] drm/tegra: Implement stream ID related callbacks on engines Mikko Perttunen
[not found] ` <20220621151022.1416300-3-cyndis@kapsi.fi>
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
For engines that support context isolation, allocate a context when
opening a channel, and set up stream ID offset and context fields
when submitting a job.
As of this commit, the stream ID offset and fallback stream ID
are not used when context isolation is disabled. However, with
upcoming patches that enable a full featured job opcode sequence,
these will be necessary.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5:
* On supporting engines, always program stream ID offset and
new fallback stream ID.
* Rename host1x_context to host1x_memory_context
v4:
* Separate error and output values in get_streamid_offset API
* Improve error handling
* Rename job->context to job->memory_context for clarity
---
drivers/gpu/drm/tegra/drm.h | 3 +++
drivers/gpu/drm/tegra/submit.c | 48 +++++++++++++++++++++++++++++++++-
drivers/gpu/drm/tegra/uapi.c | 43 ++++++++++++++++++++++++++++--
3 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index fc0a19554eac..2acc8f2948ad 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -80,6 +80,7 @@ struct tegra_drm_context {
/* Only used by new UAPI. */
struct xarray mappings;
+ struct host1x_memory_context *memory_context;
};
struct tegra_drm_client_ops {
@@ -91,6 +92,8 @@ struct tegra_drm_client_ops {
int (*submit)(struct tegra_drm_context *context,
struct drm_tegra_submit *args, struct drm_device *drm,
struct drm_file *file);
+ int (*get_streamid_offset)(struct tegra_drm_client *client, u32 *offset);
+ int (*can_use_memory_ctx)(struct tegra_drm_client *client, bool *supported);
};
int tegra_drm_submit(struct tegra_drm_context *context,
diff --git a/drivers/gpu/drm/tegra/submit.c b/drivers/gpu/drm/tegra/submit.c
index 6d6dd8c35475..b24738bdf3df 100644
--- a/drivers/gpu/drm/tegra/submit.c
+++ b/drivers/gpu/drm/tegra/submit.c
@@ -498,6 +498,9 @@ static void release_job(struct host1x_job *job)
struct tegra_drm_submit_data *job_data = job->user_data;
u32 i;
+ if (job->memory_context)
+ host1x_memory_context_put(job->memory_context);
+
for (i = 0; i < job_data->num_used_mappings; i++)
tegra_drm_mapping_put(job_data->used_mappings[i].mapping);
@@ -588,11 +591,51 @@ int tegra_drm_ioctl_channel_submit(struct drm_device *drm, void *data,
goto put_job;
}
+ if (context->client->ops->get_streamid_offset) {
+ err = context->client->ops->get_streamid_offset(
+ context->client, &job->engine_streamid_offset);
+ if (err) {
+ SUBMIT_ERR(context, "failed to get streamid offset: %d", err);
+ goto unpin_job;
+ }
+ }
+
+ if (context->memory_context && context->client->ops->can_use_memory_ctx) {
+ bool supported;
+
+ err = context->client->ops->can_use_memory_ctx(context->client, &supported);
+ if (err) {
+ SUBMIT_ERR(context, "failed to detect if engine can use memory context: %d", err);
+ goto unpin_job;
+ }
+
+ if (supported) {
+ job->memory_context = context->memory_context;
+ host1x_memory_context_get(job->memory_context);
+ }
+ } else if (context->client->ops->get_streamid_offset) {
+#ifdef CONFIG_IOMMU_API
+ struct iommu_fwspec *spec;
+
+ /*
+ * Job submission will need to temporarily change stream ID,
+ * so need to tell it what to change it back to.
+ */
+ spec = dev_iommu_fwspec_get(context->client->base.dev);
+ if (spec && spec->num_ids > 0)
+ job->engine_fallback_streamid = spec->ids[0] & 0xffff;
+ else
+ job->engine_fallback_streamid = 0x7f;
+#else
+ job->engine_fallback_streamid = 0x7f;
+#endif
+ }
+
/* Boot engine. */
err = pm_runtime_resume_and_get(context->client->base.dev);
if (err < 0) {
SUBMIT_ERR(context, "could not power up engine: %d", err);
- goto unpin_job;
+ goto put_memory_context;
}
job->user_data = job_data;
@@ -627,6 +670,9 @@ int tegra_drm_ioctl_channel_submit(struct drm_device *drm, void *data,
goto put_job;
+put_memory_context:
+ if (job->memory_context)
+ host1x_memory_context_put(job->memory_context);
unpin_job:
host1x_job_unpin(job);
put_job:
diff --git a/drivers/gpu/drm/tegra/uapi.c b/drivers/gpu/drm/tegra/uapi.c
index 9ab9179d2026..a98239cb0e29 100644
--- a/drivers/gpu/drm/tegra/uapi.c
+++ b/drivers/gpu/drm/tegra/uapi.c
@@ -33,6 +33,9 @@ static void tegra_drm_channel_context_close(struct tegra_drm_context *context)
struct tegra_drm_mapping *mapping;
unsigned long id;
+ if (context->memory_context)
+ host1x_memory_context_put(context->memory_context);
+
xa_for_each(&context->mappings, id, mapping)
tegra_drm_mapping_put(mapping);
@@ -72,6 +75,7 @@ static struct tegra_drm_client *tegra_drm_find_client(struct tegra_drm *tegra, u
int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_file *file)
{
+ struct host1x *host = tegra_drm_to_host1x(drm->dev_private);
struct tegra_drm_file *fpriv = file->driver_priv;
struct tegra_drm *tegra = drm->dev_private;
struct drm_tegra_channel_open *args = data;
@@ -102,10 +106,36 @@ int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_
}
}
+ /* Only allocate context if the engine supports context isolation. */
+ if (device_iommu_mapped(client->base.dev) && client->ops->can_use_memory_ctx) {
+ bool supported;
+
+ err = client->ops->can_use_memory_ctx(client, &supported);
+ if (err)
+ goto put_channel;
+
+ if (supported)
+ context->memory_context = host1x_memory_context_alloc(
+ host, get_task_pid(current, PIDTYPE_TGID));
+
+ if (IS_ERR(context->memory_context)) {
+ if (PTR_ERR(context->memory_context) != -EOPNOTSUPP) {
+ err = PTR_ERR(context->memory_context);
+ goto put_channel;
+ } else {
+ /*
+ * OK, HW does not support contexts or contexts
+ * are disabled.
+ */
+ context->memory_context = NULL;
+ }
+ }
+ }
+
err = xa_alloc(&fpriv->contexts, &args->context, context, XA_LIMIT(1, U32_MAX),
GFP_KERNEL);
if (err < 0)
- goto put_channel;
+ goto put_memctx;
context->client = client;
xa_init_flags(&context->mappings, XA_FLAGS_ALLOC1);
@@ -118,6 +148,9 @@ int tegra_drm_ioctl_channel_open(struct drm_device *drm, void *data, struct drm_
return 0;
+put_memctx:
+ if (context->memory_context)
+ host1x_memory_context_put(context->memory_context);
put_channel:
host1x_channel_put(context->channel);
free:
@@ -156,6 +189,7 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
struct tegra_drm_mapping *mapping;
struct tegra_drm_context *context;
enum dma_data_direction direction;
+ struct device *mapping_dev;
int err = 0;
if (args->flags & ~DRM_TEGRA_CHANNEL_MAP_READ_WRITE)
@@ -177,6 +211,11 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
kref_init(&mapping->ref);
+ if (context->memory_context)
+ mapping_dev = &context->memory_context->dev;
+ else
+ mapping_dev = context->client->base.dev;
+
mapping->bo = tegra_gem_lookup(file, args->handle);
if (!mapping->bo) {
err = -EINVAL;
@@ -201,7 +240,7 @@ int tegra_drm_ioctl_channel_map(struct drm_device *drm, void *data, struct drm_f
goto put_gem;
}
- mapping->map = host1x_bo_pin(context->client->base.dev, mapping->bo, direction, NULL);
+ mapping->map = host1x_bo_pin(mapping_dev, mapping->bo, direction, NULL);
if (IS_ERR(mapping->map)) {
err = PTR_ERR(mapping->map);
goto put_gem;
--
2.36.1
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v6 10/10] drm/tegra: Implement stream ID related callbacks on engines
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
` (7 preceding siblings ...)
2022-06-21 15:10 ` [PATCH v6 09/10] drm/tegra: Support context isolation Mikko Perttunen
@ 2022-06-21 15:10 ` Mikko Perttunen
[not found] ` <20220621151022.1416300-3-cyndis@kapsi.fi>
9 siblings, 0 replies; 14+ messages in thread
From: Mikko Perttunen @ 2022-06-21 15:10 UTC (permalink / raw)
To: thierry.reding, jonathanh, joro, will, robin.murphy, robh+dt,
krzysztof.kozlowski
Cc: linux-tegra, dri-devel, iommu, linux-kernel, devicetree,
linux-arm-kernel, Mikko Perttunen
From: Mikko Perttunen <mperttunen@nvidia.com>
Implement the get_streamid_offset and can_use_memory_ctx callbacks
required for supporting context isolation. Since old firmware on VIC
cannot support context isolation without hacks that we don't want to
implement, check the firmware binary to see if context isolation
should be enabled.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
---
v5:
* Split into two callbacks
* Add NVDEC support
v4:
* Add locking in vic_load_firmware
* Return -EOPNOTSUPP if context isolation is not available
* Update for changed get_streamid_offset declaration
* Add comment noting that vic_load_firmware is safe to call
without the hardware being powered on
Implement context isolation related callbacks in VIC, NVDEC
---
drivers/gpu/drm/tegra/drm.h | 8 +++++
drivers/gpu/drm/tegra/nvdec.c | 9 +++++
drivers/gpu/drm/tegra/vic.c | 67 ++++++++++++++++++++++++++++++-----
3 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/tegra/drm.h b/drivers/gpu/drm/tegra/drm.h
index 2acc8f2948ad..845e60f144c7 100644
--- a/drivers/gpu/drm/tegra/drm.h
+++ b/drivers/gpu/drm/tegra/drm.h
@@ -100,6 +100,14 @@ int tegra_drm_submit(struct tegra_drm_context *context,
struct drm_tegra_submit *args, struct drm_device *drm,
struct drm_file *file);
+static inline int
+tegra_drm_get_streamid_offset_thi(struct tegra_drm_client *client, u32 *offset)
+{
+ *offset = 0x30;
+
+ return 0;
+}
+
struct tegra_drm_client {
struct host1x_client base;
struct list_head list;
diff --git a/drivers/gpu/drm/tegra/nvdec.c b/drivers/gpu/drm/tegra/nvdec.c
index 386f9b2e78c4..a84f61709679 100644
--- a/drivers/gpu/drm/tegra/nvdec.c
+++ b/drivers/gpu/drm/tegra/nvdec.c
@@ -306,10 +306,19 @@ static void nvdec_close_channel(struct tegra_drm_context *context)
host1x_channel_put(context->channel);
}
+static int nvdec_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
+{
+ *supported = true;
+
+ return 0;
+}
+
static const struct tegra_drm_client_ops nvdec_ops = {
.open_channel = nvdec_open_channel,
.close_channel = nvdec_close_channel,
.submit = tegra_drm_submit,
+ .get_streamid_offset = tegra_drm_get_streamid_offset_thi,
+ .can_use_memory_ctx = nvdec_can_use_memory_ctx,
};
#define NVIDIA_TEGRA_210_NVDEC_FIRMWARE "nvidia/tegra210/nvdec.bin"
diff --git a/drivers/gpu/drm/tegra/vic.c b/drivers/gpu/drm/tegra/vic.c
index f56f5921a8c2..c5526bda88d6 100644
--- a/drivers/gpu/drm/tegra/vic.c
+++ b/drivers/gpu/drm/tegra/vic.c
@@ -38,6 +38,8 @@ struct vic {
struct clk *clk;
struct reset_control *rst;
+ bool can_use_context;
+
/* Platform configuration */
const struct vic_config *config;
};
@@ -229,28 +231,38 @@ static int vic_load_firmware(struct vic *vic)
{
struct host1x_client *client = &vic->client.base;
struct tegra_drm *tegra = vic->client.drm;
+ static DEFINE_MUTEX(lock);
+ u32 fce_bin_data_offset;
dma_addr_t iova;
size_t size;
void *virt;
int err;
- if (vic->falcon.firmware.virt)
- return 0;
+ mutex_lock(&lock);
+
+ if (vic->falcon.firmware.virt) {
+ err = 0;
+ goto unlock;
+ }
err = falcon_read_firmware(&vic->falcon, vic->config->firmware);
if (err < 0)
- return err;
+ goto unlock;
size = vic->falcon.firmware.size;
if (!client->group) {
virt = dma_alloc_coherent(vic->dev, size, &iova, GFP_KERNEL);
- if (!virt)
- return -ENOMEM;
+ if (!virt) {
+ err = -ENOMEM;
+ goto unlock;
+ }
} else {
virt = tegra_drm_alloc(tegra, size, &iova);
- if (IS_ERR(virt))
- return PTR_ERR(virt);
+ if (IS_ERR(virt)) {
+ err = PTR_ERR(virt);
+ goto unlock;
+ }
}
vic->falcon.firmware.virt = virt;
@@ -277,7 +289,28 @@ static int vic_load_firmware(struct vic *vic)
vic->falcon.firmware.phys = phys;
}
- return 0;
+ /*
+ * Check if firmware is new enough to not require mapping firmware
+ * to data buffer domains.
+ */
+ fce_bin_data_offset = *(u32 *)(virt + VIC_UCODE_FCE_DATA_OFFSET);
+
+ if (!vic->config->supports_sid) {
+ vic->can_use_context = false;
+ } else if (fce_bin_data_offset != 0x0 && fce_bin_data_offset != 0xa5a5a5a5) {
+ /*
+ * Firmware will access FCE through STREAMID0, so context
+ * isolation cannot be used.
+ */
+ vic->can_use_context = false;
+ dev_warn_once(vic->dev, "context isolation disabled due to old firmware\n");
+ } else {
+ vic->can_use_context = true;
+ }
+
+unlock:
+ mutex_unlock(&lock);
+ return err;
cleanup:
if (!client->group)
@@ -285,6 +318,7 @@ static int vic_load_firmware(struct vic *vic)
else
tegra_drm_free(tegra, size, virt, iova);
+ mutex_unlock(&lock);
return err;
}
@@ -358,10 +392,27 @@ static void vic_close_channel(struct tegra_drm_context *context)
host1x_channel_put(context->channel);
}
+static int vic_can_use_memory_ctx(struct tegra_drm_client *client, bool *supported)
+{
+ struct vic *vic = to_vic(client);
+ int err;
+
+ /* This doesn't access HW so it's safe to call without powering up. */
+ err = vic_load_firmware(vic);
+ if (err < 0)
+ return err;
+
+ *supported = vic->can_use_context;
+
+ return 0;
+}
+
static const struct tegra_drm_client_ops vic_ops = {
.open_channel = vic_open_channel,
.close_channel = vic_close_channel,
.submit = tegra_drm_submit,
+ .get_streamid_offset = tegra_drm_get_streamid_offset_thi,
+ .can_use_memory_ctx = vic_can_use_memory_ctx,
};
#define NVIDIA_TEGRA_124_VIC_FIRMWARE "nvidia/tegra124/vic03_ucode.bin"
--
2.36.1
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v6 04/10] gpu: host1x: Add context device management code
2022-06-21 15:10 ` [PATCH v6 04/10] gpu: host1x: Add context device management code Mikko Perttunen
@ 2022-06-22 7:24 ` kernel test robot
2022-07-05 2:57 ` kernel test robot
1 sibling, 0 replies; 14+ messages in thread
From: kernel test robot @ 2022-06-22 7:24 UTC (permalink / raw)
To: Mikko Perttunen, thierry.reding, jonathanh, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski
Cc: llvm, kbuild-all, devicetree, linux-kernel, dri-devel,
Mikko Perttunen, iommu, linux-tegra, linux-arm-kernel
Hi Mikko,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on tegra/for-next linus/master v5.19-rc3]
[cannot apply to tegra-drm/drm/tegra/for-next next-20220621]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/Host1x-context-isolation-support/20220621-231339
base: git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-randconfig-r021-20220622 (https://download.01.org/0day-ci/archive/20220622/202206221557.laES8yNQ-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 8b8d126598ce7bd5243da7f94f69fa1104288bee)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/2501beeae7469b805f9f624049fd56643cf6e18e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Mikko-Perttunen/Host1x-context-isolation-support/20220621-231339
git checkout 2501beeae7469b805f9f624049fd56643cf6e18e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/host1x/
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> drivers/gpu/host1x/context.c:80:28: error: no member named 'ids' in 'struct iommu_fwspec'
ctx->stream_id = fwspec->ids[0] & 0xffff;
~~~~~~ ^
1 error generated.
vim +80 drivers/gpu/host1x/context.c
15
16 int host1x_memory_context_list_init(struct host1x *host1x)
17 {
18 struct host1x_memory_context_list *cdl = &host1x->context_list;
19 struct device_node *node = host1x->dev->of_node;
20 struct host1x_memory_context *ctx;
21 unsigned int i;
22 int err;
23
24 cdl->devs = NULL;
25 cdl->len = 0;
26 mutex_init(&cdl->lock);
27
28 err = of_property_count_u32_elems(node, "iommu-map");
29 if (err < 0)
30 return 0;
31
32 cdl->devs = kcalloc(err, sizeof(*cdl->devs), GFP_KERNEL);
33 if (!cdl->devs)
34 return -ENOMEM;
35 cdl->len = err / 4;
36
37 for (i = 0; i < cdl->len; i++) {
38 struct iommu_fwspec *fwspec;
39
40 ctx = &cdl->devs[i];
41
42 ctx->host = host1x;
43
44 device_initialize(&ctx->dev);
45
46 /*
47 * Due to an issue with T194 NVENC, only 38 bits can be used.
48 * Anyway, 256GiB of IOVA ought to be enough for anyone.
49 */
50 ctx->dma_mask = DMA_BIT_MASK(38);
51 ctx->dev.dma_mask = &ctx->dma_mask;
52 ctx->dev.coherent_dma_mask = ctx->dma_mask;
53 dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
54 ctx->dev.bus = &host1x_context_device_bus_type;
55 ctx->dev.parent = host1x->dev;
56
57 dma_set_max_seg_size(&ctx->dev, UINT_MAX);
58
59 err = device_add(&ctx->dev);
60 if (err) {
61 dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
62 goto del_devices;
63 }
64
65 err = of_dma_configure_id(&ctx->dev, node, true, &i);
66 if (err) {
67 dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
68 i, err);
69 device_del(&ctx->dev);
70 goto del_devices;
71 }
72
73 fwspec = dev_iommu_fwspec_get(&ctx->dev);
74 if (!fwspec) {
75 dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
76 device_del(&ctx->dev);
77 goto del_devices;
78 }
79
> 80 ctx->stream_id = fwspec->ids[0] & 0xffff;
81 }
82
83 return 0;
84
85 del_devices:
86 while (i--)
87 device_del(&cdl->devs[i].dev);
88
89 kfree(cdl->devs);
90 cdl->len = 0;
91
92 return err;
93 }
94
--
0-DAY CI Kernel Test Service
https://01.org/lkp
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v6 02/10] dt-bindings: display: tegra: Convert to json-schema
[not found] ` <20220621151022.1416300-3-cyndis@kapsi.fi>
@ 2022-06-24 17:26 ` Rob Herring
2022-06-27 13:33 ` Rob Herring
0 siblings, 1 reply; 14+ messages in thread
From: Rob Herring @ 2022-06-24 17:26 UTC (permalink / raw)
To: Mikko Perttunen
Cc: devicetree, robin.murphy, joro, iommu, Thierry Reding, robh+dt,
linux-arm-kernel, linux-tegra, linux-kernel, jonathanh, will,
krzysztof.kozlowski, dri-devel, thierry.reding
On Tue, 21 Jun 2022 18:10:14 +0300, Mikko Perttunen wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Convert the Tegra host1x controller bindings from the free-form text
> format to json-schema.
>
> This also adds the missing display-hub DT bindings that were not
> previously documented.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Thierry Reding <treding@nvidia.com>
> ---
> .../display/tegra/nvidia,tegra114-mipi.txt | 41 --
> .../display/tegra/nvidia,tegra114-mipi.yaml | 74 ++
> .../display/tegra/nvidia,tegra124-dpaux.yaml | 149 ++++
> .../display/tegra/nvidia,tegra124-sor.yaml | 206 ++++++
> .../display/tegra/nvidia,tegra124-vic.yaml | 71 ++
> .../display/tegra/nvidia,tegra186-dc.yaml | 85 +++
> .../tegra/nvidia,tegra186-display.yaml | 310 ++++++++
> .../tegra/nvidia,tegra186-dsi-padctl.yaml | 45 ++
> .../display/tegra/nvidia,tegra20-dc.yaml | 181 +++++
> .../display/tegra/nvidia,tegra20-dsi.yaml | 159 +++++
> .../display/tegra/nvidia,tegra20-epp.yaml | 70 ++
> .../display/tegra/nvidia,tegra20-gr2d.yaml | 73 ++
> .../display/tegra/nvidia,tegra20-gr3d.yaml | 214 ++++++
> .../display/tegra/nvidia,tegra20-hdmi.yaml | 126 ++++
> .../display/tegra/nvidia,tegra20-host1x.txt | 675 ------------------
> .../display/tegra/nvidia,tegra20-host1x.yaml | 347 +++++++++
> .../display/tegra/nvidia,tegra20-isp.yaml | 67 ++
> .../display/tegra/nvidia,tegra20-mpe.yaml | 73 ++
> .../display/tegra/nvidia,tegra20-tvo.yaml | 58 ++
> .../display/tegra/nvidia,tegra20-vi.yaml | 163 +++++
> .../display/tegra/nvidia,tegra210-csi.yaml | 52 ++
> .../pinctrl/nvidia,tegra124-dpaux-padctl.txt | 59 --
> 22 files changed, 2523 insertions(+), 775 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
> create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
> delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml: allOf:1:if:not:properties: {'contains': {'const': 'nvidia,panel'}} should not be valid under {'$ref': '#/definitions/sub-schemas'}
hint: A json-schema keyword was found instead of a DT property name.
from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml: ignoring, error in schema: allOf: 1: if: not: properties
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.example.dtb: gr3d@54180000: resets: [[4294967295, 24]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.example.dtb: gr3d@54180000: reset-names: ['3d'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr2d@54140000: resets: [[4294967295, 21]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr2d@54140000: reset-names: ['2d'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr3d@54180000: resets: [[4294967295, 24]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr3d@54180000: reset-names: ['3d'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.example.dtb:0:0: /example-0/sor@54540000: failed to match any schema with compatible: ['nvidia,tegra210-sor']
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.example.dtb: gr2d@54140000: resets: [[4294967295, 21]] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.example.dtb: gr2d@54140000: reset-names: ['2d'] is too short
From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
doc reference errors (make refcheckdocs):
MAINTAINERS: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
MAINTAINERS: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v6 02/10] dt-bindings: display: tegra: Convert to json-schema
2022-06-24 17:26 ` [PATCH v6 02/10] dt-bindings: display: tegra: Convert to json-schema Rob Herring
@ 2022-06-27 13:33 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2022-06-27 13:33 UTC (permalink / raw)
To: Mikko Perttunen
Cc: devicetree, Robin Murphy, Joerg Roedel, Linux IOMMU,
Thierry Reding, linux-arm-kernel, linux-tegra, linux-kernel,
Jon Hunter, Will Deacon, Krzysztof Kozlowski, dri-devel,
Thierry Reding
On Fri, Jun 24, 2022 at 11:26 AM Rob Herring <robh@kernel.org> wrote:
>
> On Tue, 21 Jun 2022 18:10:14 +0300, Mikko Perttunen wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > Convert the Tegra host1x controller bindings from the free-form text
> > format to json-schema.
> >
> > This also adds the missing display-hub DT bindings that were not
> > previously documented.
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > .../display/tegra/nvidia,tegra114-mipi.txt | 41 --
> > .../display/tegra/nvidia,tegra114-mipi.yaml | 74 ++
> > .../display/tegra/nvidia,tegra124-dpaux.yaml | 149 ++++
> > .../display/tegra/nvidia,tegra124-sor.yaml | 206 ++++++
> > .../display/tegra/nvidia,tegra124-vic.yaml | 71 ++
> > .../display/tegra/nvidia,tegra186-dc.yaml | 85 +++
> > .../tegra/nvidia,tegra186-display.yaml | 310 ++++++++
> > .../tegra/nvidia,tegra186-dsi-padctl.yaml | 45 ++
> > .../display/tegra/nvidia,tegra20-dc.yaml | 181 +++++
> > .../display/tegra/nvidia,tegra20-dsi.yaml | 159 +++++
> > .../display/tegra/nvidia,tegra20-epp.yaml | 70 ++
> > .../display/tegra/nvidia,tegra20-gr2d.yaml | 73 ++
> > .../display/tegra/nvidia,tegra20-gr3d.yaml | 214 ++++++
> > .../display/tegra/nvidia,tegra20-hdmi.yaml | 126 ++++
> > .../display/tegra/nvidia,tegra20-host1x.txt | 675 ------------------
> > .../display/tegra/nvidia,tegra20-host1x.yaml | 347 +++++++++
> > .../display/tegra/nvidia,tegra20-isp.yaml | 67 ++
> > .../display/tegra/nvidia,tegra20-mpe.yaml | 73 ++
> > .../display/tegra/nvidia,tegra20-tvo.yaml | 58 ++
> > .../display/tegra/nvidia,tegra20-vi.yaml | 163 +++++
> > .../display/tegra/nvidia,tegra210-csi.yaml | 52 ++
> > .../pinctrl/nvidia,tegra124-dpaux-padctl.txt | 59 --
> > 22 files changed, 2523 insertions(+), 775 deletions(-)
> > delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.txt
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-mipi.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-dpaux.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-vic.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dc.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dc.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-dsi.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-hdmi.yaml
> > delete mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-tvo.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml
> > create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml
> > delete mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra124-dpaux-padctl.txt
> >
>
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
>
> yamllint warnings/errors:
>
> dtschema/dtc warnings/errors:
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml: allOf:1:if:not:properties: {'contains': {'const': 'nvidia,panel'}} should not be valid under {'$ref': '#/definitions/sub-schemas'}
> hint: A json-schema keyword was found instead of a DT property name.
> from schema $id: http://devicetree.org/meta-schemas/keywords.yaml#
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.yaml: ignoring, error in schema: allOf: 1: if: not: properties
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.example.dtb: gr3d@54180000: resets: [[4294967295, 24]] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.example.dtb: gr3d@54180000: reset-names: ['3d'] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr2d@54140000: resets: [[4294967295, 21]] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr2d@54140000: reset-names: ['2d'] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr3d@54180000: resets: [[4294967295, 24]] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.example.dtb: gr3d@54180000: reset-names: ['3d'] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr3d.yaml
> Documentation/devicetree/bindings/display/tegra/nvidia,tegra124-sor.example.dtb:0:0: /example-0/sor@54540000: failed to match any schema with compatible: ['nvidia,tegra210-sor']
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.example.dtb: gr2d@54140000: resets: [[4294967295, 21]] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
> /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.example.dtb: gr2d@54140000: reset-names: ['2d'] is too short
> From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-gr2d.yaml
>
> doc reference errors (make refcheckdocs):
> MAINTAINERS: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
> MAINTAINERS: Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
>
> See https://patchwork.ozlabs.org/patch/
>
> This check can fail if there are any dependencies. The base for a patch
> series is generally the most recent rc1.
>
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
>
> pip3 install dtschema --upgrade
>
> Please check and re-submit.
Now failing in linux-next. Please fix.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v6 04/10] gpu: host1x: Add context device management code
2022-06-21 15:10 ` [PATCH v6 04/10] gpu: host1x: Add context device management code Mikko Perttunen
2022-06-22 7:24 ` kernel test robot
@ 2022-07-05 2:57 ` kernel test robot
1 sibling, 0 replies; 14+ messages in thread
From: kernel test robot @ 2022-07-05 2:57 UTC (permalink / raw)
To: Mikko Perttunen, thierry.reding, jonathanh, joro, will,
robin.murphy, robh+dt, krzysztof.kozlowski
Cc: kbuild-all, devicetree, linux-kernel, dri-devel, Mikko Perttunen,
iommu, linux-tegra, linux-arm-kernel
Hi Mikko,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on drm/drm-next]
[also build test ERROR on tegra/for-next linus/master v5.19-rc5]
[cannot apply to tegra-drm/drm/tegra/for-next next-20220704]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Mikko-Perttunen/Host1x-context-isolation-support/20220621-231339
base: git://anongit.freedesktop.org/drm/drm drm-next
config: arm-randconfig-r005-20220703 (https://download.01.org/0day-ci/archive/20220705/202207051045.JWeVR4tW-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/2501beeae7469b805f9f624049fd56643cf6e18e
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Mikko-Perttunen/Host1x-context-isolation-support/20220621-231339
git checkout 2501beeae7469b805f9f624049fd56643cf6e18e
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
drivers/gpu/host1x/context.c: In function 'host1x_memory_context_list_init':
>> drivers/gpu/host1x/context.c:80:40: error: 'struct iommu_fwspec' has no member named 'ids'
80 | ctx->stream_id = fwspec->ids[0] & 0xffff;
| ^~
vim +80 drivers/gpu/host1x/context.c
15
16 int host1x_memory_context_list_init(struct host1x *host1x)
17 {
18 struct host1x_memory_context_list *cdl = &host1x->context_list;
19 struct device_node *node = host1x->dev->of_node;
20 struct host1x_memory_context *ctx;
21 unsigned int i;
22 int err;
23
24 cdl->devs = NULL;
25 cdl->len = 0;
26 mutex_init(&cdl->lock);
27
28 err = of_property_count_u32_elems(node, "iommu-map");
29 if (err < 0)
30 return 0;
31
32 cdl->devs = kcalloc(err, sizeof(*cdl->devs), GFP_KERNEL);
33 if (!cdl->devs)
34 return -ENOMEM;
35 cdl->len = err / 4;
36
37 for (i = 0; i < cdl->len; i++) {
38 struct iommu_fwspec *fwspec;
39
40 ctx = &cdl->devs[i];
41
42 ctx->host = host1x;
43
44 device_initialize(&ctx->dev);
45
46 /*
47 * Due to an issue with T194 NVENC, only 38 bits can be used.
48 * Anyway, 256GiB of IOVA ought to be enough for anyone.
49 */
50 ctx->dma_mask = DMA_BIT_MASK(38);
51 ctx->dev.dma_mask = &ctx->dma_mask;
52 ctx->dev.coherent_dma_mask = ctx->dma_mask;
53 dev_set_name(&ctx->dev, "host1x-ctx.%d", i);
54 ctx->dev.bus = &host1x_context_device_bus_type;
55 ctx->dev.parent = host1x->dev;
56
57 dma_set_max_seg_size(&ctx->dev, UINT_MAX);
58
59 err = device_add(&ctx->dev);
60 if (err) {
61 dev_err(host1x->dev, "could not add context device %d: %d\n", i, err);
62 goto del_devices;
63 }
64
65 err = of_dma_configure_id(&ctx->dev, node, true, &i);
66 if (err) {
67 dev_err(host1x->dev, "IOMMU configuration failed for context device %d: %d\n",
68 i, err);
69 device_del(&ctx->dev);
70 goto del_devices;
71 }
72
73 fwspec = dev_iommu_fwspec_get(&ctx->dev);
74 if (!fwspec) {
75 dev_err(host1x->dev, "Context device %d has no IOMMU!\n", i);
76 device_del(&ctx->dev);
77 goto del_devices;
78 }
79
> 80 ctx->stream_id = fwspec->ids[0] & 0xffff;
81 }
82
83 return 0;
84
85 del_devices:
86 while (i--)
87 device_del(&cdl->devs[i].dev);
88
89 kfree(cdl->devs);
90 cdl->len = 0;
91
92 return err;
93 }
94
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-07-05 3:00 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-06-21 15:10 [PATCH v6 00/10] Host1x context isolation support Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 01/10] iommu/arm-smmu: Attach to host1x context device bus Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 03/10] dt-bindings: host1x: Add iommu-map property Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 04/10] gpu: host1x: Add context device management code Mikko Perttunen
2022-06-22 7:24 ` kernel test robot
2022-07-05 2:57 ` kernel test robot
2022-06-21 15:10 ` [PATCH v6 05/10] gpu: host1x: Program context stream ID on submission Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 06/10] arm64: tegra: Add Host1x context stream IDs on Tegra186+ Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 07/10] drm/tegra: falcon: Set DMACTX field on DMA transactions Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 08/10] drm/tegra: nvdec: Fix TRANSCFG register offset Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 09/10] drm/tegra: Support context isolation Mikko Perttunen
2022-06-21 15:10 ` [PATCH v6 10/10] drm/tegra: Implement stream ID related callbacks on engines Mikko Perttunen
[not found] ` <20220621151022.1416300-3-cyndis@kapsi.fi>
2022-06-24 17:26 ` [PATCH v6 02/10] dt-bindings: display: tegra: Convert to json-schema Rob Herring
2022-06-27 13:33 ` Rob Herring
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