[PATCH 0/6] ARM: dts: imx cleanups

[PATCH 0/6] ARM: dts: imx cleanups

[Uwe Kleine-König]

Hello Shawn,

I put the patches I sent in the last time in a single series here because they
conflict each other. IMHO this is merge window material because according to the
documentation writing to reserved bits doesn't have an effect and the other patches
are non-critical, too. It also splits the fec gpio patch I sent before in two as
the first submission contained some unrelated changes as was pointed out by Fabio.

The first patch was trimmed to use diff -b. This has the downside that it's not
possible to apply. But this way it makes it to the list at least.

You can also pull the series from

	git://git.kleine-koenig.org/git/linux.git imx-dt-cleanups

(which then obviously contains the full 1st patch) based on v4.7-rc6.

Best regards
Uwe

Uwe Kleine-K?nig (6):
  ARM: dts: drop function device nodes for pinctrl-imx nodes
  ARM: dts: imx25: don't configure reserved pad settings
  ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value
  ARM: dts: imx6q: don't configure reserved pad settings
  ARM: dts: imx: fix polarity of fec reset gpios
  ARM: dts: imx6-wandboard: substitute NO_PAD_CTL by the respective
    reset value

 arch/arm/boot/dts/imx1-ads.dts                     | 100 ++--
 arch/arm/boot/dts/imx1-apf9328.dts                 |  92 ++--
 arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi       |  38 +-
 .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts  |   6 +-
 .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts  | 134 +++---
 arch/arm/boot/dts/imx25-karo-tx25.dts              |  55 +--
 arch/arm/boot/dts/imx25-pdk.dts                    | 192 ++++----
 arch/arm/boot/dts/imx27-apf27.dts                  |  56 ++-
 arch/arm/boot/dts/imx27-apf27dev.dts               | 194 ++++----
 arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi       | 228 +++++-----
 .../boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts  | 194 ++++----
 arch/arm/boot/dts/imx27-pdk.dts                    | 132 +++---
 arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts   |  92 ++--
 arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi  |  78 ++--
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts     | 206 +++++----
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi    | 154 ++++---
 arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi       |  62 ++-
 .../boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts  |  88 ++--
 arch/arm/boot/dts/imx35-pdk.dts                    |  36 +-
 arch/arm/boot/dts/imx50-evk.dts                    |  67 +--
 arch/arm/boot/dts/imx51-apf51.dts                  |  58 ++-
 arch/arm/boot/dts/imx51-apf51dev.dts               | 176 ++++---
 arch/arm/boot/dts/imx51-babbage.dts                | 418 +++++++++--------
 arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts   |  78 ++--
 arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi  | 266 ++++++-----
 arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi       |  68 ++-
 .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts  | 192 ++++----
 arch/arm/boot/dts/imx53-ard.dts                    | 116 +++--
 arch/arm/boot/dts/imx53-m53.dtsi                   |  64 ++-
 arch/arm/boot/dts/imx53-m53evk.dts                 | 268 ++++++-----
 arch/arm/boot/dts/imx53-mba53.dts                  | 116 +++--
 arch/arm/boot/dts/imx53-qsb-common.dtsi            | 246 +++++-----
 arch/arm/boot/dts/imx53-qsrb.dts                   |  10 +-
 arch/arm/boot/dts/imx53-smd.dts                    | 198 ++++----
 arch/arm/boot/dts/imx53-tqma53.dtsi                | 246 +++++-----
 arch/arm/boot/dts/imx53-tx53-x03x.dts              | 112 +++--
 arch/arm/boot/dts/imx53-tx53-x13x.dts              |  74 ++-
 arch/arm/boot/dts/imx53-tx53.dtsi                  | 438 +++++++++---------
 arch/arm/boot/dts/imx53-voipac-bsb.dts             | 106 +++--
 arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi        | 126 +++--
 arch/arm/boot/dts/imx6dl-riotboard.dts             | 362 ++++++++-------
 arch/arm/boot/dts/imx6q-arm2.dts                   | 198 ++++----
 arch/arm/boot/dts/imx6q-ba16.dtsi                  |  24 +-
 arch/arm/boot/dts/imx6q-cm-fx6.dts                 |  94 ++--
 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts            | 234 +++++-----
 arch/arm/boot/dts/imx6q-evi.dts                    |  26 +-
 arch/arm/boot/dts/imx6q-gk802.dts                  |  92 ++--
 arch/arm/boot/dts/imx6q-gw5400-a.dts               | 217 +++++----
 arch/arm/boot/dts/imx6q-marsboard.dts              |  25 +-
 arch/arm/boot/dts/imx6q-novena.dts                 |  14 +-
 arch/arm/boot/dts/imx6q-sbc6x.dts                  |  82 ++--
 arch/arm/boot/dts/imx6q-tbs2910.dts                |  24 +-
 arch/arm/boot/dts/imx6qdl-apalis.dtsi              |  24 +-
 arch/arm/boot/dts/imx6qdl-apf6.dtsi                | 112 +++--
 arch/arm/boot/dts/imx6qdl-apf6dev.dtsi             | 306 +++++++------
 arch/arm/boot/dts/imx6qdl-aristainetos.dtsi        | 406 ++++++++---------
 arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi       |   2 +-
 arch/arm/boot/dts/imx6qdl-cubox-i.dtsi             | 136 +++---
 arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi       | 176 ++++---
 arch/arm/boot/dts/imx6qdl-gw51xx.dtsi              | 238 +++++-----
 arch/arm/boot/dts/imx6qdl-gw52xx.dtsi              | 348 +++++++-------
 arch/arm/boot/dts/imx6qdl-gw53xx.dtsi              | 334 +++++++-------
 arch/arm/boot/dts/imx6qdl-gw54xx.dtsi              | 356 +++++++--------
 arch/arm/boot/dts/imx6qdl-gw551x.dtsi              | 162 ++++---
 arch/arm/boot/dts/imx6qdl-gw552x.dtsi              | 154 ++++---
 arch/arm/boot/dts/imx6qdl-hummingboard.dtsi        | 152 +++----
 arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi           |  24 +-
 arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi     |  86 ++--
 arch/arm/boot/dts/imx6qdl-microsom.dtsi            |  98 ++--
 arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi           | 378 ++++++++-------
 arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi       | 506 ++++++++++-----------
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi          | 400 ++++++++--------
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi       | 288 ++++++------
 arch/arm/boot/dts/imx6qdl-rex.dtsi                 | 264 ++++++-----
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           | 412 +++++++++--------
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi           | 360 ++++++++-------
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi             | 296 ++++++------
 arch/arm/boot/dts/imx6qdl-tx6.dtsi                 |   2 +-
 arch/arm/boot/dts/imx6qdl-udoo.dtsi                | 186 ++++----
 arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi     |  32 +-
 arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi     |  34 +-
 arch/arm/boot/dts/imx6qdl-wandboard.dtsi           | 193 ++++----
 arch/arm/boot/dts/imx6qp-sabreauto.dts             |  40 +-
 arch/arm/boot/dts/imx6qp-sabresd.dts               |  56 ++-
 arch/arm/boot/dts/imx6sl-evk.dts                   | 460 ++++++++++---------
 arch/arm/boot/dts/imx6sl-warp.dts                  | 208 +++++----
 arch/arm/boot/dts/imx6sx-sabreauto.dts             | 134 +++---
 arch/arm/boot/dts/imx6sx-sdb.dtsi                  | 482 ++++++++++----------
 arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts       |   2 +-
 arch/arm/boot/dts/imx6ul-tx6ul.dtsi                |   4 +-
 arch/arm/boot/dts/imx7d-sdb.dts                    | 351 +++++++-------
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi          |  10 +-
 arch/arm/boot/dts/vf-colibri.dtsi                  | 334 +++++++-------
 arch/arm/boot/dts/vf500-colibri.dtsi               |  44 +-
 arch/arm/boot/dts/vf610-cosmic.dts                 |  60 ++-
 arch/arm/boot/dts/vf610-twr.dts                    | 228 +++++-----
 arch/arm/boot/dts/vf610m4-colibri.dts              |  16 +-
 arch/arm/boot/dts/vf610m4-cosmic.dts               |  12 +-
 98 files changed, 7851 insertions(+), 8027 deletions(-)

-- 
2.8.1

[PATCH 1/6] ARM: dts: drop function device nodes for pinctrl-imx nodes

[Uwe Kleine-König]

From: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>

Since commit v4.2-rc1~128^2~88 ("pinctrl: imx: Allow parsing DT without
function nodes") the imx pinctrl driver supports the more sensible
format without function device nodes. It's time to switch all
devicetrees to this easier format.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
Hello,

note this patch probably doesn't apply as I replaced the full diff
by the output of diff -b because it's easier to review this way and would be
blocked by the ML anyhow.

 arch/arm/boot/dts/imx1-ads.dts                     | 100 ++--
 arch/arm/boot/dts/imx1-apf9328.dts                 |  92 ++--
 arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi       |  38 +-
 .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts  |   6 +-
 .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts  | 134 +++---
 arch/arm/boot/dts/imx25-pdk.dts                    | 190 ++++----
 arch/arm/boot/dts/imx27-apf27.dts                  |  56 ++-
 arch/arm/boot/dts/imx27-apf27dev.dts               | 194 ++++----
 arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi       | 228 +++++-----
 .../boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts  | 194 ++++----
 arch/arm/boot/dts/imx27-pdk.dts                    | 132 +++---
 arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts   |  92 ++--
 arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi  |  78 ++--
 arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts     | 206 +++++----
 arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi    | 154 ++++---
 arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi       |  62 ++-
 .../boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts  |  88 ++--
 arch/arm/boot/dts/imx35-pdk.dts                    |  36 +-
 arch/arm/boot/dts/imx50-evk.dts                    |  62 ++-
 arch/arm/boot/dts/imx51-apf51.dts                  |  56 ++-
 arch/arm/boot/dts/imx51-apf51dev.dts               | 176 ++++---
 arch/arm/boot/dts/imx51-babbage.dts                | 418 +++++++++--------
 arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts   |  78 ++--
 arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi  | 266 ++++++-----
 arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi       |  68 ++-
 .../boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts  | 192 ++++----
 arch/arm/boot/dts/imx53-ard.dts                    | 116 +++--
 arch/arm/boot/dts/imx53-m53.dtsi                   |  64 ++-
 arch/arm/boot/dts/imx53-m53evk.dts                 | 268 ++++++-----
 arch/arm/boot/dts/imx53-mba53.dts                  | 114 +++--
 arch/arm/boot/dts/imx53-qsb-common.dtsi            | 244 +++++-----
 arch/arm/boot/dts/imx53-qsrb.dts                   |  10 +-
 arch/arm/boot/dts/imx53-smd.dts                    | 196 ++++----
 arch/arm/boot/dts/imx53-tqma53.dtsi                | 246 +++++-----
 arch/arm/boot/dts/imx53-tx53-x03x.dts              | 112 +++--
 arch/arm/boot/dts/imx53-tx53-x13x.dts              |  74 ++-
 arch/arm/boot/dts/imx53-tx53.dtsi                  | 436 +++++++++---------
 arch/arm/boot/dts/imx53-voipac-bsb.dts             | 106 +++--
 arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi        | 124 +++--
 arch/arm/boot/dts/imx6dl-riotboard.dts             | 360 ++++++++-------
 arch/arm/boot/dts/imx6q-arm2.dts                   | 198 ++++----
 arch/arm/boot/dts/imx6q-cm-fx6.dts                 |  94 ++--
 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts            | 232 +++++-----
 arch/arm/boot/dts/imx6q-gk802.dts                  |  92 ++--
 arch/arm/boot/dts/imx6q-gw5400-a.dts               | 215 +++++----
 arch/arm/boot/dts/imx6q-marsboard.dts              |   1 -
 arch/arm/boot/dts/imx6q-sbc6x.dts                  |  82 ++--
 arch/arm/boot/dts/imx6qdl-apf6.dtsi                | 112 +++--
 arch/arm/boot/dts/imx6qdl-apf6dev.dtsi             | 306 +++++++------
 arch/arm/boot/dts/imx6qdl-aristainetos.dtsi        | 404 ++++++++--------
 arch/arm/boot/dts/imx6qdl-cubox-i.dtsi             | 136 +++---
 arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi       | 176 ++++---
 arch/arm/boot/dts/imx6qdl-gw51xx.dtsi              | 238 +++++-----
 arch/arm/boot/dts/imx6qdl-gw52xx.dtsi              | 348 +++++++-------
 arch/arm/boot/dts/imx6qdl-gw53xx.dtsi              | 334 +++++++-------
 arch/arm/boot/dts/imx6qdl-gw54xx.dtsi              | 356 +++++++--------
 arch/arm/boot/dts/imx6qdl-gw551x.dtsi              | 162 ++++---
 arch/arm/boot/dts/imx6qdl-gw552x.dtsi              | 154 ++++---
 arch/arm/boot/dts/imx6qdl-hummingboard.dtsi        | 152 +++----
 arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi     |  84 ++--
 arch/arm/boot/dts/imx6qdl-microsom.dtsi            |  98 ++--
 arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi           | 378 ++++++++-------
 arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi       | 506 ++++++++++-----------
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi          | 398 ++++++++--------
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi       | 288 ++++++------
 arch/arm/boot/dts/imx6qdl-rex.dtsi                 | 264 ++++++-----
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi           | 412 +++++++++--------
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi           | 360 ++++++++-------
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi             | 294 ++++++------
 arch/arm/boot/dts/imx6qdl-udoo.dtsi                | 186 ++++----
 arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi     |  32 +-
 arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi     |  32 +-
 arch/arm/boot/dts/imx6qdl-wandboard.dtsi           | 191 ++++----
 arch/arm/boot/dts/imx6qp-sabreauto.dts             |  40 +-
 arch/arm/boot/dts/imx6qp-sabresd.dts               |  56 ++-
 arch/arm/boot/dts/imx6sl-evk.dts                   | 460 ++++++++++---------
 arch/arm/boot/dts/imx6sl-warp.dts                  | 208 +++++----
 arch/arm/boot/dts/imx6sx-sabreauto.dts             | 134 +++---
 arch/arm/boot/dts/imx6sx-sdb.dtsi                  | 482 ++++++++++----------
 arch/arm/boot/dts/imx7d-sdb.dts                    | 351 +++++++-------
 arch/arm/boot/dts/vf-colibri-eval-v3.dtsi          |  10 +-
 arch/arm/boot/dts/vf-colibri.dtsi                  | 334 +++++++-------
 arch/arm/boot/dts/vf500-colibri.dtsi               |  44 +-
 arch/arm/boot/dts/vf610-cosmic.dts                 |  60 ++-
 arch/arm/boot/dts/vf610-twr.dts                    | 228 +++++-----
 arch/arm/boot/dts/vf610m4-colibri.dts              |  16 +-
 arch/arm/boot/dts/vf610m4-cosmic.dts               |  12 +-
 87 files changed, 7717 insertions(+), 7899 deletions(-)

diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
index af4eee5794aa..c4883138e79d 100644
--- a/arch/arm/boot/dts/imx1-ads.dts
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -93,7 +93,6 @@
 };
 
 &iomuxc {
-	imx1-ads {
 	pinctrl_cspi1: cspi1grp {
 		fsl,pins = <
 			MX1_PAD_SPI1_MISO__SPI1_MISO	0x0
@@ -148,5 +147,4 @@
 			MX1_PAD_LBA__LBA		0x0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx1-apf9328.dts b/arch/arm/boot/dts/imx1-apf9328.dts
index 07d92fb40e6f..d30ed3b90603 100644
--- a/arch/arm/boot/dts/imx1-apf9328.dts
+++ b/arch/arm/boot/dts/imx1-apf9328.dts
@@ -74,7 +74,6 @@
 };
 
 &iomuxc {
-	imx1-apf9328 {
 	pinctrl_eth: ethgrp {
 		fsl,pins = <
 			MX1_PAD_SIM_SVEN__GPIO2_14	0x0
@@ -125,5 +124,4 @@
 			MX1_PAD_LBA__LBA		0x0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
index d6f27641c0ef..f024a84bd37b 100644
--- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -41,7 +41,6 @@
 };
 
 &iomuxc {
-	imx25-eukrea-cpuimx25 {
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
 			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
@@ -62,7 +61,6 @@
 			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
index 68d0834a2d1e..184778f4335f 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
@@ -58,11 +58,9 @@
 };
 
 &iomuxc {
-	imx25-eukrea-mbimxsd25-baseboard-cmo-qvga {
 	pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
 		fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
 	};
-	};
 };
 
 &lcdc {
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index cda6907a27b9..9efcdad20e73 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -76,7 +76,6 @@
 };
 
 &iomuxc {
-	imx25-eukrea-mbimxsd25-baseboard {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
@@ -150,7 +149,6 @@
 			MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
 		>;
 	};
-	};
 };
 
 &ssi1 {
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 9351296356dc..8b00cfca18ea 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -145,7 +145,6 @@
 };
 
 &iomuxc {
-	imx25-pdk {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX25_PAD_RW__AUD4_TXFS			0xe0
@@ -248,7 +247,6 @@
 			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
 		>;
 	};
-	};
 };
 
 &lcdc {
diff --git a/arch/arm/boot/dts/imx27-apf27.dts b/arch/arm/boot/dts/imx27-apf27.dts
index 73aae4f5e539..7037777646d1 100644
--- a/arch/arm/boot/dts/imx27-apf27.dts
+++ b/arch/arm/boot/dts/imx27-apf27.dts
@@ -36,7 +36,6 @@
 };
 
 &iomuxc {
-	imx27-apf27 {
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
 			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
@@ -66,7 +65,6 @@
 			MX27_PAD_UART1_RXD__UART1_RXD 0x0
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index bba3f41b89ef..cda7b3ee21bc 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -137,7 +137,6 @@
 };
 
 &iomuxc {
-	imx27-apf27dev {
 	pinctrl_cspi1: cspi1grp {
 		fsl,pins = <
 			MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
@@ -247,7 +246,6 @@
 	pinctrl_sdhc2_cd: sdhc2cdgrp {
 		fsl,pins = <MX27_PAD_TOUT__GPIO3_14 0x0>;
 	};
-	};
 };
 
 &sdhci2 {
diff --git a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
index e2242638ea0b..a1d1b138974f 100644
--- a/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
+++ b/arch/arm/boot/dts/imx27-eukrea-cpuimx27.dtsi
@@ -166,7 +166,6 @@
 };
 
 &iomuxc {
-	imx27-eukrea-cpuimx27 {
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
 			MX27_PAD_SD3_CMD__FEC_TXD0		0x0
@@ -292,5 +291,4 @@
 			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7	0x0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
index 2ab65fc4c1e1..585699775f24 100644
--- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -161,7 +161,6 @@
 };
 
 &iomuxc {
-	imx27-eukrea-cpuimx27-baseboard {
 	pinctrl_cspi1: cspi1grp {
 		fsl,pins = <
 			MX27_PAD_CSPI1_MISO__CSPI1_MISO	0x0
@@ -269,5 +268,4 @@
 			MX27_PAD_UART3_RTS__UART3_RTS	0x0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index 49450dbbcab8..b82432357621 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -122,7 +122,6 @@
 };
 
 &iomuxc {
-	imx27-pdk {
 	pinctrl_cspi2: cspi2grp {
 		fsl,pins = <
 			MX27_PAD_CSPI2_MISO__CSPI2_MISO 0x0
@@ -193,5 +192,4 @@
 			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
index 7c869fe3c30b..ef5370d7bbf9 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-rdk.dts
@@ -78,7 +78,6 @@
 };
 
 &iomuxc {
-	imx27-phycard-s-rdk {
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
 			MX27_PAD_I2C2_SDA__I2C2_SDA 0x0
@@ -130,7 +129,6 @@
 			MX27_PAD_UART3_RTS__UART3_RTS 0x0
 		>;
 	};
-	};
 };
 
 &owire {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
index 1b6248079682..27315828f534 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -48,7 +48,6 @@
 };
 
 &iomuxc {
-	imx27-phycard-s-som {
 	pinctrl_fec1: fec1grp {
 		fsl,pins = <
 			MX27_PAD_SD3_CMD__FEC_TXD0 0x0
@@ -90,7 +89,6 @@
 			MX27_PAD_NFWE_B__NFWE_B 0x0
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index 538568b0de26..133c511f27bb 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -100,7 +100,6 @@
 };
 
 &iomuxc {
-	imx27_phycore_rdk {
 	pinctrl_csien: csiengrp {
 		fsl,pins = <
 			MX27_PAD_USB_OC_B__GPIO2_24 0x0
@@ -213,7 +212,6 @@
 			MX27_PAD_SD1_D1__GPIO5_19	0x0 /* CAN IRQ */
 		>;
 	};
-	};
 };
 
 &owire {
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index b4e955e3be8d..49b0e30cafc8 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -211,7 +211,6 @@
 };
 
 &iomuxc {
-	imx27_phycore_som {
 	pinctrl_cspi1: cspi1grp {
 		fsl,pins = <
 			MX27_PAD_CSPI1_MISO__CSPI1_MISO 0x0
@@ -295,7 +294,6 @@
 			MX27_PAD_USBOTG_DATA7__USBOTG_DATA7 0x0
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
index 9c2b715ab8bf..4524391cd5bc 100644
--- a/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
+++ b/arch/arm/boot/dts/imx35-eukrea-cpuimx35.dtsi
@@ -51,7 +51,6 @@
 };
 
 &iomuxc {
-	imx35-eukrea {
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
 			MX35_PAD_FEC_TX_CLK__FEC_TX_CLK		0x80000000
@@ -85,7 +84,6 @@
 	pinctrl_tsc2007_1: tsc2007grp-1 {
 		fsl,pins = <MX35_PAD_ATA_DA2__GPIO3_2 0x80000000>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
index 4727bbb804e1..3f41b13cbfd4 100644
--- a/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
+++ b/arch/arm/boot/dts/imx35-eukrea-mbimxsd35-baseboard.dts
@@ -77,7 +77,6 @@
 };
 
 &iomuxc {
-	imx35-eukrea {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS	0x80000000
@@ -128,7 +127,6 @@
 			MX35_PAD_CTS2__UART2_CTS		0x1c5
 		>;
 	};
-	};
 };
 
 &ssi1 {
diff --git a/arch/arm/boot/dts/imx35-pdk.dts b/arch/arm/boot/dts/imx35-pdk.dts
index 8d715523708f..369016f78a98 100644
--- a/arch/arm/boot/dts/imx35-pdk.dts
+++ b/arch/arm/boot/dts/imx35-pdk.dts
@@ -30,7 +30,6 @@
 };
 
 &iomuxc {
-	imx35-pdk {
 	pinctrl_esdhc1: esdhc1grp {
 		fsl,pins = <
 			MX35_PAD_SD1_CMD__ESDHC1_CMD		0x80000000
@@ -50,7 +49,6 @@
 			MX35_PAD_RTS1__UART1_RTS		0x1c5
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 27d763c7a307..04cefa7c950f 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -59,7 +59,6 @@
 };
 
 &iomuxc {
-	imx50-evk {
 	pinctrl_cspi: cspigrp {
 		fsl,pins = <
 			MX50_PAD_CSPI_SCLK__CSPI_SCLK		0x00
@@ -93,7 +92,6 @@
 			MX50_PAD_UART1_CTS__UART1_CTS		0x1e4
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index e88b2a6be079..aa5861610834 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -42,7 +42,6 @@
 };
 
 &iomuxc {
-	imx51-apf51 {
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
 			MX51_PAD_DI_GP3__FEC_TX_ER		0x80000000
@@ -72,7 +71,6 @@
 			MX51_PAD_UART3_TXD__UART3_TXD		0x1c5
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 0f3fe29b816e..d43843220c9a 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -121,7 +121,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx51-apf51dev {
 	pinctrl_backlight: bl1grp {
 		fsl,pins = <
 			MX51_PAD_DI1_D1_CS__GPIO3_4 0x1F5
@@ -217,7 +216,6 @@
 			MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
 		>;
 	};
-	};
 };
 
 &ipu_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 018d24eb9965..636a61491e5f 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -422,7 +422,6 @@
 };
 
 &iomuxc {
-	imx51-babbage {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX51_PAD_AUD3_BB_TXD__AUD3_TXD		0x80000000
@@ -651,5 +650,4 @@
 			MX51_PAD_GPIO1_7__GPIO1_7		0x85
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
index 1db517d3d497..b72b63406a47 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-jsk.dts
@@ -60,7 +60,6 @@
 };
 
 &iomuxc {
-	imx51-digi-connectcore-jsk {
 	pinctrl_owire: owiregrp {
 		fsl,pins = <
 			MX51_PAD_OWIRE_LINE__OWIRE_LINE		0x40000000
@@ -104,5 +103,4 @@
 			MX51_PAD_USBH1_STP__USBH1_STP		0x1e5
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index 16fc69c69ab2..deb6b560cb85 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -231,7 +231,6 @@
 };
 
 &iomuxc {
-	imx51-digi-connectcore-som {
 	pinctrl_ecspi1: ecspi1grp {
 		fsl,pins = <
 			MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
@@ -373,5 +372,4 @@
 			MX51_PAD_EIM_CS5__EIM_CS5		0x80000000 /* CS5 */
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
index 63164266af83..5aa9e95e2ba0 100644
--- a/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
+++ b/arch/arm/boot/dts/imx51-eukrea-cpuimx51.dtsi
@@ -56,7 +56,6 @@
 };
 
 &iomuxc {
-	imx51-eukrea {
 	pinctrl_tsc2007_1: tsc2007grp-1 {
 		fsl,pins = <
 			MX51_PAD_GPIO_NAND__GPIO_NAND 0x1f5
@@ -93,7 +92,6 @@
 			MX51_PAD_SD2_CLK__I2C1_SDA		0x400001ed
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index d270df3e5891..7002a66d51e0 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -139,7 +139,6 @@
 };
 
 &iomuxc {
-	imx51-eukrea {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX51_PAD_AUD3_BB_TXD__AUD3_TXD		0x80000000
@@ -250,7 +249,6 @@
 			MX51_PAD_EIM_CS3__GPIO2_28 0x1f5
 		>;
 	};
-	};
 };
 
 &ssi2 {
diff --git a/arch/arm/boot/dts/imx53-ard.dts b/arch/arm/boot/dts/imx53-ard.dts
index 4486bc47d140..f41e6f91b0c3 100644
--- a/arch/arm/boot/dts/imx53-ard.dts
+++ b/arch/arm/boot/dts/imx53-ard.dts
@@ -112,7 +112,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-ard {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX53_PAD_GPIO_1__GPIO1_1             0x80000000
@@ -173,7 +172,6 @@
 			MX53_PAD_PATA_DMACK__UART1_RXD_MUX	0x1e4
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx53-m53.dtsi b/arch/arm/boot/dts/imx53-m53.dtsi
index 87a7fc709c2d..443f6eccace8 100644
--- a/arch/arm/boot/dts/imx53-m53.dtsi
+++ b/arch/arm/boot/dts/imx53-m53.dtsi
@@ -93,7 +93,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-m53evk {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK	0x80000000
@@ -128,7 +127,6 @@
 			MX53_PAD_PATA_DATA7__EMI_NANDF_D_7	0xa4
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index dcee1e0f968f..bd33bd60ebc8 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -169,7 +169,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-m53evk {
 	pinctrl_usb: usbgrp {
 		fsl,pins = <
 			MX53_PAD_GPIO_2__GPIO1_2		0x80000000
@@ -318,7 +317,6 @@
 			MX53_PAD_PATA_DA_2__UART3_RTS		0x1e4
 		>;
 	};
-	};
 };
 
 &ipu_di1_disp1 {
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 2e44d2aba14e..fa6438141747 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -89,7 +89,6 @@
 };
 
 &iomuxc {
-	lvds1 {
 	pinctrl_lvds1_1: lvds1-grp1 {
 		fsl,pins = <
 			MX53_PAD_LVDS0_TX3_P__LDB_LVDS0_TX3 0x80000000
@@ -109,9 +108,7 @@
 			MX53_PAD_LVDS1_TX0_P__LDB_LVDS1_TX0 0x80000000
 		>;
 	};
-	};
 
-	disp1 {
 	pinctrl_disp1_1: disp1-grp1 {
 		fsl,pins = <
 			MX53_PAD_EIM_A16__IPU_DI1_DISP_CLK 0x80000000 /* DISP1_CLK */
@@ -144,9 +141,7 @@
 			MX53_PAD_EIM_DA9__IPU_DISP1_DAT_0  0x80000000
 		>;
 	};
-	};
 
-	tve {
 	pinctrl_vga_sync_1: vgasync-grp1 {
 		fsl,pins = <
 			/* VGA_VSYNC, HSYNC with max drive strength */
@@ -154,7 +149,6 @@
 			MX53_PAD_EIM_DA15__IPU_DI1_PIN4	   0xe6
 		>;
 	};
-	};
 };
 
 &ipu_di1_disp1 {
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index c05e7cfd0cbc..baebcd3a0515 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -157,7 +157,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-qsb {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000
@@ -290,7 +289,6 @@
 			MX53_PAD_CSI0_DAT11__UART1_RXD_MUX	0x1e4
 		>;
 	};
-	};
 };
 
 &tve {
diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index 96d7eede412e..0bda292893e0 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -20,13 +20,11 @@
 };
 
 &iomuxc {
-	imx53-qsrb {
 	pinctrl_pmic: pmicgrp {
 		fsl,pins = <
 			MX53_PAD_CSI0_DAT5__GPIO5_23	0x1e4 /* IRQ */
 		>;
 	};
-	};
 };
 
 &i2c1 {
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 542ab9e697fb..105b5e0972ff 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -104,7 +104,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-smd {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX53_PAD_PATA_DATA14__GPIO2_14 0x80000000
@@ -213,7 +212,6 @@
 			MX53_PAD_PATA_DA_2__UART3_RTS		0x1e4
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index e03373a58760..244842e8152a 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -74,7 +74,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-tqma53 {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			 MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x80000000 /* SSI_MCLK */
@@ -212,7 +211,6 @@
 			MX53_PAD_PATA_CS_1__UART3_RXD_MUX	0x1e4
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index 0ecb43d88522..bc799aa896b3 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -236,7 +236,6 @@
 };
 
 &iomuxc {
-	imx53-tx53-x03x {
 	pinctrl_edt_ft5x06_1: edt-ft5x06grp-1 {
 		fsl,pins = <
 			MX53_PAD_NANDF_CS2__GPIO6_15 0x1f0 /* Interrupt */
@@ -296,7 +295,6 @@
 			MX53_PAD_EIM_D26__GPIO3_26 0x1f0 /* Interrupt */
 		>;
 	};
-	};
 };
 
 &ipu_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx53-tx53-x13x.dts b/arch/arm/boot/dts/imx53-tx53-x13x.dts
index 3cf682a681f4..73487c4b49b0 100644
--- a/arch/arm/boot/dts/imx53-tx53-x13x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x13x.dts
@@ -131,7 +131,6 @@
 };
 
 &iomuxc {
-	imx53-tx53-x13x {
 	pinctrl_i2c2: i2c2-grp1 {
 		fsl,pins = <
 			MX53_PAD_KEY_ROW3__I2C2_SDA		0xc0000000
@@ -174,7 +173,6 @@
 			MX53_PAD_EIM_D23__GPIO3_23 0x1f0 /* Interrupt */
 		>;
 	};
-	};
 };
 
 &ldb {
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index bd3dfefa5778..13deaa664eb8 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -234,7 +234,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-tx53 {
 	pinctrl_hog: hoggrp {
 		/* pins not in use by any device on the Starterkit board series */
 		fsl,pins = <
@@ -475,7 +474,6 @@
 			MX53_PAD_GPIO_8__GPIO1_8 0x100 /* OC */
 		>;
 	};
-	};
 };
 
 &ipu {
diff --git a/arch/arm/boot/dts/imx53-voipac-bsb.dts b/arch/arm/boot/dts/imx53-voipac-bsb.dts
index fc51b87ad208..bf06e659436f 100644
--- a/arch/arm/boot/dts/imx53-voipac-bsb.dts
+++ b/arch/arm/boot/dts/imx53-voipac-bsb.dts
@@ -48,7 +48,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-voipac {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			/* SD2_CD */
@@ -107,7 +106,6 @@
 			MX53_PAD_GPIO_6__I2C3_SDA		0xc0000000
 		>;
 	};
-	};
 };
 
 &audmux {
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
index ba689fbd0e41..1ad10374b3c5 100644
--- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -55,7 +55,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx53-voipac {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			/* Make DA9053 regulator functional */
@@ -123,7 +122,6 @@
 			MX53_PAD_PATA_DATA7__EMI_NANDF_D_7	0xa4
 		>;
 	};
-	};
 };
 
 &ecspi1 {
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index bfbed52ce1bd..2309b050525f 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -331,7 +331,6 @@
 &iomuxc {
 	pinctrl-names = "default";
 
-	imx6-riotboard {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
@@ -534,5 +533,4 @@
 			MX6QDL_PAD_NANDF_ALE__GPIO6_IO08	0x17059	/* SD4 RST (eMMC) */
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index d6515f7a56c4..1ef2ca4251b0 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -68,7 +68,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6q-arm2 {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_EIM_D25__GPIO3_IO25 0x80000000
@@ -176,7 +175,6 @@
 			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
 		>;
 	};
-	};
 };
 
 &fec {
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index 99b46f8030ad..21c513f6980e 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -47,7 +47,6 @@
 };
 
 &iomuxc {
-	imx6q-cm-fx6 {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
 			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
@@ -97,7 +96,6 @@
 			MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA	0x1b0b1
 		>;
 	};
-	};
 };
 
 &uart4 {
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 364578d707a5..84046ad7ab16 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -298,7 +298,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6q-dmo-edmqmx6 {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
@@ -430,7 +429,6 @@
 			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
 		>;
 	};
-	};
 };
 
 &pcie {
diff --git a/arch/arm/boot/dts/imx6q-gk802.dts b/arch/arm/boot/dts/imx6q-gk802.dts
index b715deb4ea46..46a6a7d2df34 100644
--- a/arch/arm/boot/dts/imx6q-gk802.dts
+++ b/arch/arm/boot/dts/imx6q-gk802.dts
@@ -80,7 +80,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6q-gk802 {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			/* Recovery button, active-low */
@@ -132,7 +131,6 @@
 			MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
 		>;
 	};
-	};
 };
 
 &uart2 {
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 0511137d1e23..2e40c7e2f870 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -398,8 +398,6 @@
 };
 
 &iomuxc {
-	imx6q-gw5400-a {
-
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
@@ -520,5 +518,4 @@
 			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index 3f8013c85fb9..bc22cc31119c 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -228,7 +228,6 @@
 };
 
 &iomuxc {
-
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index 86cf09364664..60277d75b207 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -26,7 +26,6 @@
 };
 
 &iomuxc {
-	imx6q-sbc6x {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
@@ -71,7 +70,6 @@
 			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx6qdl-apf6.dtsi b/arch/arm/boot/dts/imx6qdl-apf6.dtsi
index 1ebf29f43a24..82387f72005f 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6.dtsi
@@ -94,7 +94,6 @@
 };
 
 &iomuxc {
-	apf6 {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
@@ -154,5 +153,4 @@
 			MX6QDL_PAD_SD3_DAT7__SD3_DATA7	0x17059
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index 865c9a264a43..e289a30b7872 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -302,7 +302,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_gpios>;
 
-	apf6dev {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC  0x1b0b0
@@ -475,5 +474,4 @@
 			MX6QDL_PAD_CSI0_DAT17__GPIO6_IO03 0x1b0b0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index ecbc6eba6a2c..f7e6803992ee 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -189,7 +189,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog &pinctrl_gpio>;
 
-	imx6qdl-aristainetos {
 	pinctrl_aristainetos_usbh1_vbus: aristainetos-usbh1-vbus {
 		fsl,pins = <MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x130b0>;
 	};
@@ -414,5 +413,4 @@
 			MX6QDL_PAD_KEY_COL1__GPIO4_IO08 0x1b0b0
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
index ff41f83551de..a238420015cb 100644
--- a/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
@@ -146,7 +146,6 @@
 };
 
 &iomuxc {
-	cubox_i {
 	pinctrl_cubox_i_hdmi: cubox-i-hdmi {
 		fsl,pins = <
 			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
@@ -227,7 +226,6 @@
 			MX6QDL_PAD_EIM_DA8__GPIO3_IO08	0x17059
 		>;
 	};
-	};
 };
 
 &pwm1 {
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
index da1341d47b14..80682d506f8f 100644
--- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -55,7 +55,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-dfi-fs700-m60 {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x80000000
@@ -152,7 +151,6 @@
 			MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x80000000 /* SPI NOR chipselect */
 		>;
 	};
-	};
 };
 
 &i2c2 {
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 9d7ab6cdc9a6..5e829c650a56 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -229,7 +229,6 @@
 };
 
 &iomuxc {
-	imx6qdl-gw51xx {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
 			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
@@ -364,5 +363,4 @@
 			MX6QDL_PAD_EIM_D22__GPIO3_IO22		0x1b0b0 /* OTG_PWR_EN */
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 7191b84770b9..78b53ff4aa17 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -354,7 +354,6 @@
 };
 
 &iomuxc {
-	imx6qdl-gw52xx {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
@@ -549,5 +548,4 @@
 			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 40d06b09deba..8788afc25709 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -352,7 +352,6 @@
 };
 
 &iomuxc {
-	imx6qdl-gw53xx {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
@@ -539,5 +538,4 @@
 			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index d6dbe2a88ee6..8ceaf527b58e 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -454,7 +454,6 @@
 };
 
 &iomuxc {
-	imx6qdl-gw54xx {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_SD2_DAT0__AUD4_RXD		0x130b0
@@ -654,5 +653,4 @@
 			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x170f9
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
index 118bea524dab..51307ae3dbc0 100644
--- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi
@@ -240,7 +240,6 @@
 };
 
 &iomuxc {
-	imx6qdl-gw51xx {
 	pinctrl_flexcan1: flexcan1grp {
 		fsl,pins = <
 			MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b1
@@ -333,5 +332,4 @@
 			MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
index f27f184558fb..623b6e6037b5 100644
--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
@@ -198,7 +198,6 @@
 };
 
 &iomuxc {
-	imx6qdl-gw552x {
 	pinctrl_gpio_leds: gpioledsgrp {
 		fsl,pins = <
 			MX6QDL_PAD_KEY_COL0__GPIO4_IO06		0x1b0b0
@@ -286,5 +285,4 @@
 			MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA	0x1b0b1
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
index d6c2358ffad4..3c5f268b6c37 100644
--- a/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
@@ -157,7 +157,6 @@
 };
 
 &iomuxc {
-	hummingboard {
 	pinctrl_hummingboard_flexcan1: hummingboard-flexcan1 {
 		fsl,pins = <
 			MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x80000000
@@ -247,7 +246,6 @@
 			MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
 		>;
 	};
-	};
 };
 
 &pcie {
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index 469ef58ce4bc..631fa6eacc79 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -51,7 +51,6 @@
 };
 
 &iomuxc {
-	enet {
 	pinctrl_microsom_enet_ar8035: microsom-enet-ar8035 {
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b8b0
@@ -95,5 +94,4 @@
 			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x03000
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-microsom.dtsi b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
index 86460e46d055..d26626c842c4 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom.dtsi
@@ -74,7 +74,6 @@
 };
 
 &iomuxc {
-	microsom {
 	pinctrl_microsom_brcm_bt: microsom-brcm-bt {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00	0x40013070
@@ -130,7 +129,6 @@
 			MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index e456b5cc1b03..1a4a244c31f9 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -317,7 +317,6 @@
 	pinctrl-0 = <&pinctrl_j10>;
 	pinctrl-1 = <&pinctrl_j28>;
 
-	imx6dl-nit6xlite {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
@@ -529,7 +528,6 @@
 			MX6QDL_PAD_SD3_DAT5__GPIO7_IO00		0x1b0b0
 		>;
 	};
-	};
 };
 
 &ldb {
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index 657da6b6ccd2..762b2a934978 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -446,7 +446,6 @@
 };
 
 &iomuxc {
-	imx6q-nitrogen6_max {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
@@ -727,7 +726,6 @@
 			MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT	0x000b0
 		>;
 	};
-	};
 };
 
 &ipu1_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index 73915db704a0..c9a337deb7cd 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -348,7 +348,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6q-nitrogen6x {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			/* SGTL5000 sys_mclk */
@@ -568,7 +567,6 @@
 			MX6QDL_PAD_SD1_CLK__OSC32K_32K_OUT	0x000b0
 		>;
 	};
-	};
 };
 
 &ipu1_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index d6d98d426384..afffd1b0f158 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -208,7 +208,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6q-phytec-pfla02 {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x80000000
@@ -369,7 +368,6 @@
 			MX6QDL_PAD_DISP0_DAT19__AUD5_RXD	0x130b0
 		>;
 	};
-	};
 };
 
 &pcie {
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index cacf5933707d..f8d49899f6e8 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -155,7 +155,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-rex {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			/* SGTL5000 sys_mclk */
@@ -302,7 +301,6 @@
 			MX6QDL_PAD_NANDF_D1__GPIO2_IO01		0x1f0b0
 		>;
 	};
-	};
 };
 
 &ssi1 {
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d354d406954d..cab748c7483f 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -317,7 +317,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-sabreauto {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
@@ -541,7 +540,6 @@
 			MX6QDL_PAD_EIM_DA0__EIM_AD00		0xb0b1
 		>;
 	};
-	};
 };
 
 &ldb {
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index c47fe6c79b36..9b9999499930 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -314,7 +314,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6q-sabrelite {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			/* SGTL5000 sys_mclk */
@@ -513,7 +512,6 @@
 			MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0	/* CD */
 		>;
 	};
-	};
 };
 
 &ipu1_di0_disp0 {
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 5248e7bd2b06..7ab9249b6144 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -343,7 +343,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-sabresd {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x1b0b0
@@ -501,15 +500,12 @@
 			MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
 		>;
 	};
-	};
 
-	gpio_leds {
 	pinctrl_gpio_leds: gpioledsgrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
 		>;
 	};
-	};
 };
 
 &ldb {
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index 3bee2f910067..42caca66ef04 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -129,7 +129,6 @@
 };
 
 &iomuxc {
-	imx6q-udoo {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
 			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
@@ -233,7 +232,6 @@
 			MX6QDL_PAD_EIM_EB2__GPIO2_IO30		0x1b0b0
 		>;
 	};
-	};
 };
 
 &ldb {
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
index ef7fa62b9898..d92c5a4f07d9 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
@@ -14,7 +14,6 @@
 &iomuxc {
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-wandboard {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* GPIO_0_CLKO */
@@ -31,7 +30,6 @@
 			MX6QDL_PAD_EIM_DA15__GPIO3_IO15		0x80000000	/* BT_HOST_WAKE */				
 		>;
 	};
-	};
 };
 
 &usdhc2 {
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
index 8d893a78cdf0..ca4bfb2aa218 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
@@ -14,7 +14,6 @@
 &iomuxc {
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6qdl-wandboard {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* GPIO_0_CLKO */
@@ -31,7 +30,6 @@
 			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x80000000	/* RGMII_nRST */
 		>;
 	};
-	};
 };
 
 &usdhc2 {
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index 8e7c40e114dd..dff0eab40f79 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -94,8 +94,6 @@
 &iomuxc {
 	pinctrl-names = "default";
 
-	imx6qdl-wandboard {
-
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
@@ -201,7 +199,6 @@
 			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
 		>;
 	};
-	};
 };
 
 &fec {
diff --git a/arch/arm/boot/dts/imx6qp-sabreauto.dts b/arch/arm/boot/dts/imx6qp-sabreauto.dts
index 5ce3840d83d3..05490830b9eb 100644
--- a/arch/arm/boot/dts/imx6qp-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6qp-sabreauto.dts
@@ -60,7 +60,6 @@
 };
 
 &iomuxc {
-	imx6qdl-sabreauto {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
 			MX6QDL_PAD_KEY_COL1__ENET_MDIO          0x1b0b0
@@ -81,7 +80,6 @@
 			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 		>;
 	};
-	};
 };
 
 &pcie {
diff --git a/arch/arm/boot/dts/imx6qp-sabresd.dts b/arch/arm/boot/dts/imx6qp-sabresd.dts
index b23458062f5e..acf4f9ac064c 100644
--- a/arch/arm/boot/dts/imx6qp-sabresd.dts
+++ b/arch/arm/boot/dts/imx6qp-sabresd.dts
@@ -55,7 +55,6 @@
 };
 
 &iomuxc {
-	imx6qdl-sabresd {
 	pinctrl_usdhc2: usdhc2grp {
 		fsl,pins = <
 			MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
@@ -85,7 +84,6 @@
 			MX6QDL_PAD_SD3_DAT7__SD3_DATA7		0x17059
 		>;
 	};
-	};
 };
 
 &pcie {
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index be118820e9f7..57e5de05b28a 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -272,7 +272,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx6sl-evk {
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6SL_PAD_KEY_ROW7__GPIO4_IO07    0x17059
@@ -525,7 +524,6 @@
 			MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x170f9
 		>;
 	};
-	};
 };
 
 &kpp {
diff --git a/arch/arm/boot/dts/imx6sl-warp.dts b/arch/arm/boot/dts/imx6sl-warp.dts
index 058bcdceb81a..3513170eea8d 100644
--- a/arch/arm/boot/dts/imx6sl-warp.dts
+++ b/arch/arm/boot/dts/imx6sl-warp.dts
@@ -124,7 +124,6 @@
 };
 
 &iomuxc {
-	imx6sl-warp {
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX6SL_PAD_UART1_RXD__UART1_RX_DATA	0x41b0b1
@@ -229,5 +228,4 @@
 			MX6SL_PAD_SD3_DAT3__SD3_DATA3		0x4170f9
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 96ea936eeeb0..5ebd53682b3f 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -69,7 +69,6 @@
 };
 
 &iomuxc {
-	imx6x-sabreauto {
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
 			MX6SX_PAD_GPIO1_IO04__UART1_TX		0x1b0b1
@@ -142,5 +141,4 @@
 			MX6SX_PAD_KEY_COL1__GPIO2_IO_11		0x17059
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dtsi b/arch/arm/boot/dts/imx6sx-sdb.dtsi
index e5eafe4d9a70..ce77e5b65217 100644
--- a/arch/arm/boot/dts/imx6sx-sdb.dtsi
+++ b/arch/arm/boot/dts/imx6sx-sdb.dtsi
@@ -323,7 +323,6 @@
 };
 
 &iomuxc {
-	imx6x-sdb {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
 			MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC	0x130b0
@@ -588,5 +587,4 @@
 			MX6SX_PAD_SD4_DATA6__GPIO6_IO_20	0x17059 /* WP */
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index b267f79e3059..b38c643ba8d2 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -318,7 +318,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_hog>;
 
-	imx7d-sdb {
 	pinctrl_enet1: enet1grp {
 		fsl,pins = <
 			MX7D_PAD_GPIO1_IO10__ENET1_MDIO			0x3
@@ -511,6 +510,4 @@
 			MX7D_PAD_SD3_STROBE__SD3_STROBE		0x1b
 		>;
 	};
-
-	};
 };
diff --git a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
index a8a8e434fb27..b3160b4449b7 100644
--- a/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
+++ b/arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
@@ -167,11 +167,9 @@
 };
 
 &iomuxc {
-	vf610-colibri {
 	pinctrl_can_int: can_int {
 		fsl,pins = <
 			VF610_PAD_PTB21__GPIO_43	0x22ed
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/vf-colibri.dtsi b/arch/arm/boot/dts/vf-colibri.dtsi
index b7417094dc11..7c9895e75a79 100644
--- a/arch/arm/boot/dts/vf-colibri.dtsi
+++ b/arch/arm/boot/dts/vf-colibri.dtsi
@@ -199,7 +199,6 @@
 };
 
 &iomuxc {
-	vf610-colibri {
 	pinctrl_flexcan0: can0grp {
 		fsl,pins = <
 			VF610_PAD_PTB14__CAN0_RX	0x31F1
@@ -367,5 +366,4 @@
 			VF610_PAD_PTD4__GPIO_83			0x22ed
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/vf500-colibri.dtsi b/arch/arm/boot/dts/vf500-colibri.dtsi
index 1a8a0efa19a6..22bf1a42d7b2 100644
--- a/arch/arm/boot/dts/vf500-colibri.dtsi
+++ b/arch/arm/boot/dts/vf500-colibri.dtsi
@@ -75,7 +75,6 @@
 };
 
 &iomuxc {
-	vf610-colibri {
 	pinctrl_touchctrl_idle: touchctrl_idle {
 		fsl,pins = <
 			VF610_PAD_PTA18__GPIO_8		0x006d
@@ -100,5 +99,4 @@
 			VF610_PAD_PTA11__GPIO_4		0x22e9
 			>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/vf610-cosmic.dts b/arch/arm/boot/dts/vf610-cosmic.dts
index 5447f2594659..6248f838866d 100644
--- a/arch/arm/boot/dts/vf610-cosmic.dts
+++ b/arch/arm/boot/dts/vf610-cosmic.dts
@@ -50,7 +50,6 @@
 };
 
 &iomuxc {
-	vf610-cosmic {
 	pinctrl_esdhc1: esdhc1grp {
 		fsl,pins = <
 			VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
@@ -83,7 +82,6 @@
 			VF610_PAD_PTB5__UART1_RX		0x21a1
 		>;
 	};
-	};
 };
 
 &uart1 {
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index cdc100732514..821b0ae367b2 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -209,7 +209,6 @@
 };
 
 &iomuxc {
-	vf610-twr {
 	pinctrl_adc0_ad5: adc0ad5grp {
 		fsl,pins = <
 			VF610_PAD_PTC30__ADC0_SE5		0xa1
@@ -334,7 +333,6 @@
 			VF610_PAD_PTB7__UART2_RX		0x21a1
 		>;
 	};
-	};
 };
 
 &nfc {
diff --git a/arch/arm/boot/dts/vf610m4-colibri.dts b/arch/arm/boot/dts/vf610m4-colibri.dts
index 2931a80caccb..7f55a32b4d94 100644
--- a/arch/arm/boot/dts/vf610m4-colibri.dts
+++ b/arch/arm/boot/dts/vf610m4-colibri.dts
@@ -86,7 +86,6 @@
 };
 
 &iomuxc {
-	vf610-colibri {
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
 			VF610_PAD_PTD0__UART2_TX		0x21a2
@@ -95,5 +94,4 @@
 			VF610_PAD_PTD3__UART2_CTS		0x21a1
 		>;
 	};
-	};
 };
diff --git a/arch/arm/boot/dts/vf610m4-cosmic.dts b/arch/arm/boot/dts/vf610m4-cosmic.dts
index 8944a2d2054c..ad08fe083d4b 100644
--- a/arch/arm/boot/dts/vf610m4-cosmic.dts
+++ b/arch/arm/boot/dts/vf610m4-cosmic.dts
@@ -79,12 +79,10 @@
 };
 
 &iomuxc {
-	vf610-cosmic {
 	pinctrl_uart3: uart3grp {
 		fsl,pins = <
 			VF610_PAD_PTA20__UART3_TX		0x21a2
 			VF610_PAD_PTA21__UART3_RX		0x21a1
 		>;
 	};
-	};
 };

[PATCH 2/6] ARM: dts: imx25: don't configure reserved pad settings

[Uwe Kleine-König]

From: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>

Two dts files specified reserved bits in their pad setting value for
some pins. This commit just unsets the reserved bits, which matches the
hardware behaviour when writing a 1 to a reserved bit.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
 .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts  | 24 +++++++++++-----------
 arch/arm/boot/dts/imx25-pdk.dts                    | 16 +++++++--------
 2 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 9efcdad20e73..1a4b08df061c 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -78,10 +78,10 @@
 &iomuxc {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
-			MX25_PAD_KPP_COL3__AUD5_TXFS		0xe0
-			MX25_PAD_KPP_COL2__AUD5_TXC		0xe0
-			MX25_PAD_KPP_COL1__AUD5_RXD		0xe0
-			MX25_PAD_KPP_COL0__AUD5_TXD		0xe0
+			MX25_PAD_KPP_COL3__AUD5_TXFS		0x000000a0
+			MX25_PAD_KPP_COL2__AUD5_TXC		0x000000a0
+			MX25_PAD_KPP_COL1__AUD5_RXD		0x000000a0
+			MX25_PAD_KPP_COL0__AUD5_TXD		0x000000a0
 		>;
 	};
 
@@ -106,10 +106,10 @@
 
 	pinctrl_lcdc: lcdcgrp {
 		fsl,pins = <
-			MX25_PAD_LD0__LD0			0x1
-			MX25_PAD_LD1__LD1			0x1
+			MX25_PAD_LD0__LD0			0x0
+			MX25_PAD_LD1__LD1			0x0
 			MX25_PAD_LD2__LD2			0x1
-			MX25_PAD_LD3__LD3			0x1
+			MX25_PAD_LD3__LD3			0x0
 			MX25_PAD_LD4__LD4			0x1
 			MX25_PAD_LD5__LD5			0x1
 			MX25_PAD_LD6__LD6			0x1
@@ -120,10 +120,10 @@
 			MX25_PAD_LD11__LD11			0x1
 			MX25_PAD_LD12__LD12			0x1
 			MX25_PAD_LD13__LD13			0x1
-			MX25_PAD_LD14__LD14			0x1
-			MX25_PAD_LD15__LD15			0x1
-			MX25_PAD_GPIO_E__LD16			0x1
-			MX25_PAD_GPIO_F__LD17			0x1
+			MX25_PAD_LD14__LD14			0x0
+			MX25_PAD_LD15__LD15			0x0
+			MX25_PAD_GPIO_E__LD16			0x0
+			MX25_PAD_GPIO_F__LD17			0x0
 			MX25_PAD_HSYNC__HSYNC			0x80000000
 			MX25_PAD_VSYNC__VSYNC			0x80000000
 			MX25_PAD_LSCLK__LSCLK			0x80000000
@@ -137,7 +137,7 @@
 			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
 			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
 			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
-			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
+			MX25_PAD_UART1_RXD__UART1_RXD		0x00000080
 		>;
 	};
 
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 8b00cfca18ea..c823e45a7a01 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -147,10 +147,10 @@
 &iomuxc {
 	pinctrl_audmux: audmuxgrp {
 		fsl,pins = <
-			MX25_PAD_RW__AUD4_TXFS			0xe0
-			MX25_PAD_OE__AUD4_TXC			0xe0
-			MX25_PAD_EB0__AUD4_TXD			0xe0
-			MX25_PAD_EB1__AUD4_RXD			0xe0
+			MX25_PAD_RW__AUD4_TXFS			0x80
+			MX25_PAD_OE__AUD4_TXC			0x80
+			MX25_PAD_EB0__AUD4_TXD			0x80
+			MX25_PAD_EB1__AUD4_RXD			0x80
 		>;
 	};
 
@@ -227,10 +227,10 @@
 			MX25_PAD_LD11__LD11		0xe0
 			MX25_PAD_LD12__LD12		0xe0
 			MX25_PAD_LD13__LD13		0xe0
-			MX25_PAD_LD14__LD14		0xe0
+			MX25_PAD_LD14__LD14		0xa0
 			MX25_PAD_LD15__LD15		0xe0
-			MX25_PAD_GPIO_E__LD16		0xe0
-			MX25_PAD_GPIO_F__LD17		0xe0
+			MX25_PAD_GPIO_E__LD16		0xa0
+			MX25_PAD_GPIO_F__LD17		0xa0
 			MX25_PAD_HSYNC__HSYNC		0xe0
 			MX25_PAD_VSYNC__VSYNC		0xe0
 			MX25_PAD_LSCLK__LSCLK		0xe0
@@ -244,7 +244,7 @@
 			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
 			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
 			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
-			MX25_PAD_UART1_RXD__UART1_RXD		0xc0
+			MX25_PAD_UART1_RXD__UART1_RXD		0x80
 		>;
 	};
 };
-- 
2.8.1

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

From: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>

When 0x80000000 (aka NO_PAD_CTL) is used as pad config value, the
SW_PAD_CTL register isn't modified. Instead be more explicit here and
specify the reset default value.

If the machines don't depend on bootloader modifications to these
registers (and the tables in the reference manual are right) this commit
doesn't result in different behaviour of the affected machines.

Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>
---
 arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi       | 18 +++----
 .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts  |  2 +-
 .../boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts  | 24 ++++-----
 arch/arm/boot/dts/imx25-karo-tx25.dts              | 50 +++++++++---------
 arch/arm/boot/dts/imx25-pdk.dts                    | 60 +++++++++++-----------
 5 files changed, 77 insertions(+), 77 deletions(-)

diff --git a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
index f024a84bd37b..5ba6351d55cf 100644
--- a/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
+++ b/arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi
@@ -43,22 +43,22 @@
 &iomuxc {
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
-			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
+			MX25_PAD_FEC_MDC__FEC_MDC		0x00000060
 			MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
-			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
-			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
-			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
-			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
-			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
-			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x00000060
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x00000060
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x00000060
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x000000c1
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x000000c0
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x000000c0
 			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
 		>;
 	};
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
-			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x000000a8
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x000000a8
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
index 184778f4335f..f773690da909 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts
@@ -59,7 +59,7 @@
 
 &iomuxc {
 	pinctrl_reg_lcd_3v3: reg_lcd_3v3 {
-		fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x80000000>;
+		fsl,pins = <MX25_PAD_PWM__GPIO_1_26 0x000000c0>;
 	};
 };
 
diff --git a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
index 1a4b08df061c..d6681966ee9c 100644
--- a/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
+++ b/arch/arm/boot/dts/imx25-eukrea-mbimxsd25-baseboard.dts
@@ -97,11 +97,11 @@
 	};
 
 	pinctrl_gpiokeys: gpiokeysgrp {
-		fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x80000000>;
+		fsl,pins = <MX25_PAD_VSTBY_ACK__GPIO_3_18 0x00000080>;
 	};
 
 	pinctrl_gpioled: gpioledgrp {
-		fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x80000000>;
+		fsl,pins = <MX25_PAD_POWER_FAIL__GPIO_3_19 0x00000080>;
 	};
 
 	pinctrl_lcdc: lcdcgrp {
@@ -124,11 +124,11 @@
 			MX25_PAD_LD15__LD15			0x0
 			MX25_PAD_GPIO_E__LD16			0x0
 			MX25_PAD_GPIO_F__LD17			0x0
-			MX25_PAD_HSYNC__HSYNC			0x80000000
-			MX25_PAD_VSYNC__VSYNC			0x80000000
-			MX25_PAD_LSCLK__LSCLK			0x80000000
-			MX25_PAD_OE_ACD__OE_ACD			0x80000000
-			MX25_PAD_CONTRAST__CONTRAST		0x80000000
+			MX25_PAD_HSYNC__HSYNC			0x00000060
+			MX25_PAD_VSYNC__VSYNC			0x00000060
+			MX25_PAD_LSCLK__LSCLK			0x00000061
+			MX25_PAD_OE_ACD__OE_ACD			0x00000060
+			MX25_PAD_CONTRAST__CONTRAST		0x00000060
 		>;
 	};
 
@@ -136,17 +136,17 @@
 		fsl,pins = <
 			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
 			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
-			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
+			MX25_PAD_UART1_TXD__UART1_TXD		0x00000020
 			MX25_PAD_UART1_RXD__UART1_RXD		0x00000080
 		>;
 	};
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-			MX25_PAD_UART2_RXD__UART2_RXD		0x80000000
-			MX25_PAD_UART2_TXD__UART2_TXD		0x80000000
-			MX25_PAD_UART2_RTS__UART2_RTS		0x80000000
-			MX25_PAD_UART2_CTS__UART2_CTS		0x80000000
+			MX25_PAD_UART2_RXD__UART2_RXD		0x000000e0
+			MX25_PAD_UART2_TXD__UART2_TXD		0x00000060
+			MX25_PAD_UART2_RTS__UART2_RTS		0x000000e0
+			MX25_PAD_UART2_CTS__UART2_CTS		0x00000060
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index 9b31faa96377..c622c342efa0 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -44,46 +44,46 @@
 &iomuxc {
 	pinctrl_uart1: uart1grp {
 		fsl,pins = <
-			MX25_PAD_UART1_TXD__UART1_TXD 0x80000000
-			MX25_PAD_UART1_RXD__UART1_RXD 0x80000000
-			MX25_PAD_UART1_CTS__UART1_CTS 0x80000000
-			MX25_PAD_UART1_RTS__UART1_RTS 0x80000000
+			MX25_PAD_UART1_TXD__UART1_TXD 0x00000020
+			MX25_PAD_UART1_RXD__UART1_RXD 0x000000a0
+			MX25_PAD_UART1_CTS__UART1_CTS 0x00000060
+			MX25_PAD_UART1_RTS__UART1_RTS 0x000000e0
 		>;
 	};
 
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
-			MX25_PAD_D11__GPIO_4_9		0x80000000 /* FEC PHY power on pin */
-			MX25_PAD_D13__GPIO_4_7		0x80000000 /* FEC reset */
-			MX25_PAD_FEC_MDC__FEC_MDC	0x80000000
-			MX25_PAD_FEC_MDIO__FEC_MDIO	0x80000000
-			MX25_PAD_FEC_TDATA0__FEC_TDATA0	0x80000000
-			MX25_PAD_FEC_TDATA1__FEC_TDATA1	0x80000000
-			MX25_PAD_FEC_TX_EN__FEC_TX_EN	0x80000000
-			MX25_PAD_FEC_RDATA0__FEC_RDATA0	0x80000000
-			MX25_PAD_FEC_RDATA1__FEC_RDATA1	0x80000000
-			MX25_PAD_FEC_RX_DV__FEC_RX_DV	0x80000000
-			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK	0x80000000
+			MX25_PAD_D11__GPIO_4_9		0x00000021 /* FEC PHY power on pin */
+			MX25_PAD_D13__GPIO_4_7		0x000000a1 /* FEC reset */
+			MX25_PAD_FEC_MDC__FEC_MDC	0x00000060
+			MX25_PAD_FEC_MDIO__FEC_MDIO	0x000001f0
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0	0x00000060
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1	0x00000060
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN	0x00000060
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0	0x000000c1
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1	0x000000c0
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV	0x000000c0
+			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK	0x000000c0
 		>;
 	};
 
 	pinctrl_nfc: nfcgrp {
 		fsl,pins = <
-			MX25_PAD_NF_CE0__NF_CE0		0x80000000
+			MX25_PAD_NF_CE0__NF_CE0		0x00000001
 			MX25_PAD_NFWE_B__NFWE_B		0x80000000
 			MX25_PAD_NFRE_B__NFRE_B		0x80000000
 			MX25_PAD_NFALE__NFALE		0x80000000
 			MX25_PAD_NFCLE__NFCLE		0x80000000
 			MX25_PAD_NFWP_B__NFWP_B		0x80000000
-			MX25_PAD_NFRB__NFRB		0x80000000
-			MX25_PAD_D7__D7			0x80000000
-			MX25_PAD_D6__D6			0x80000000
-			MX25_PAD_D5__D5			0x80000000
-			MX25_PAD_D4__D4			0x80000000
-			MX25_PAD_D3__D3			0x80000000
-			MX25_PAD_D2__D2			0x80000000
-			MX25_PAD_D1__D1			0x80000000
-			MX25_PAD_D0__D0			0x80000000
+			MX25_PAD_NFRB__NFRB		0x00000080
+			MX25_PAD_D7__D7			0x00000000
+			MX25_PAD_D6__D6			0x00000000
+			MX25_PAD_D5__D5			0x00000000
+			MX25_PAD_D4__D4			0x00000000
+			MX25_PAD_D3__D3			0x00000000
+			MX25_PAD_D2__D2			0x00000000
+			MX25_PAD_D1__D1			0x00000000
+			MX25_PAD_D0__D0			0x00000000
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index c823e45a7a01..643d083951ef 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -158,56 +158,56 @@
 		fsl,pins = <
 			MX25_PAD_GPIO_A__CAN1_TX		0x0
 			MX25_PAD_GPIO_B__CAN1_RX		0x0
-			MX25_PAD_D14__GPIO_4_6 			0x80000000
+			MX25_PAD_D14__GPIO_4_6 			0x000000a1
 		>;
 	};
 
 	pinctrl_esdhc1: esdhc1grp {
 		fsl,pins = <
-			MX25_PAD_SD1_CMD__SD1_CMD		0x80000000
-			MX25_PAD_SD1_CLK__SD1_CLK		0x80000000
-			MX25_PAD_SD1_DATA0__SD1_DATA0		0x80000000
-			MX25_PAD_SD1_DATA1__SD1_DATA1		0x80000000
-			MX25_PAD_SD1_DATA2__SD1_DATA2		0x80000000
-			MX25_PAD_SD1_DATA3__SD1_DATA3		0x80000000
-			MX25_PAD_A14__GPIO_2_0			0x80000000
-			MX25_PAD_A15__GPIO_2_1			0x80000000
+			MX25_PAD_SD1_CMD__SD1_CMD		0x000000d1
+			MX25_PAD_SD1_CLK__SD1_CLK		0x000000d1
+			MX25_PAD_SD1_DATA0__SD1_DATA0		0x000000d1
+			MX25_PAD_SD1_DATA1__SD1_DATA1		0x000000d1
+			MX25_PAD_SD1_DATA2__SD1_DATA2		0x000000d1
+			MX25_PAD_SD1_DATA3__SD1_DATA3		0x000000d1
+			MX25_PAD_A14__GPIO_2_0			0x00000080
+			MX25_PAD_A15__GPIO_2_1			0x00000080
 		>;
 	};
 
 	pinctrl_fec: fecgrp {
 		fsl,pins = <
-			MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
+			MX25_PAD_FEC_MDC__FEC_MDC		0x00000060
 			MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
-			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
-			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
-			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
-			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
-			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
-			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
-			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
-			MX25_PAD_A17__GPIO_2_3			0x80000000
-			MX25_PAD_D12__GPIO_4_8			0x80000000
+			MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x00000060
+			MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x00000060
+			MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x00000060
+			MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x000000c1
+			MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x000000c0
+			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x000000c0
+			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x000001c0
+			MX25_PAD_A17__GPIO_2_3			0x00000000
+			MX25_PAD_D12__GPIO_4_8			0x000000a1
 		>;
 	};
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
-			MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x000000a8
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x000000a8
 		>;
 	};
 
 	pinctrl_kpp: kppgrp {
 		fsl,pins = <
-			MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
-			MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
-			MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
-			MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
-			MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
-			MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
-			MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
-			MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
+			MX25_PAD_KPP_ROW0__KPP_ROW0		0x000000a0
+			MX25_PAD_KPP_ROW1__KPP_ROW1		0x000000a0
+			MX25_PAD_KPP_ROW2__KPP_ROW2		0x000000e0
+			MX25_PAD_KPP_ROW3__KPP_ROW3		0x000000e0
+			MX25_PAD_KPP_COL0__KPP_COL0		0x000000a8
+			MX25_PAD_KPP_COL1__KPP_COL1		0x000000a8
+			MX25_PAD_KPP_COL2__KPP_COL2		0x000000a8
+			MX25_PAD_KPP_COL3__KPP_COL3		0x000000a8
 		>;
 	};
 
@@ -243,7 +243,7 @@
 		fsl,pins = <
 			MX25_PAD_UART1_RTS__UART1_RTS		0xe0
 			MX25_PAD_UART1_CTS__UART1_CTS		0xe0
-			MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
+			MX25_PAD_UART1_TXD__UART1_TXD		0x00000020
 			MX25_PAD_UART1_RXD__UART1_RXD		0x80
 		>;
 	};
-- 
2.8.1

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Sun, Jul 10, 2016 at 7:07 AM, Uwe Kleine-K?nig <uwe@kleine-koenig.org> wrote:

>  arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi       | 18 +++----
>  .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts  |  2 +-
> diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
> index c823e45a7a01..643d083951ef 100644
> --- a/arch/arm/boot/dts/imx25-pdk.dts
> +++ b/arch/arm/boot/dts/imx25-pdk.dts

>         pinctrl_fec: fecgrp {
>                 fsl,pins = <
> -                       MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
> +                       MX25_PAD_FEC_MDC__FEC_MDC               0x00000060
>                         MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
> -                       MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
> -                       MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
> -                       MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
> -                       MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
> -                       MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
> -                       MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
> -                       MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
> -                       MX25_PAD_A17__GPIO_2_3                  0x80000000
> -                       MX25_PAD_D12__GPIO_4_8                  0x80000000
> +                       MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x00000060
> +                       MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x00000060
> +                       MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x00000060
> +                       MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x000000c1
> +                       MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x000000c0
> +                       MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x000000c0
> +                       MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x000001c0
> +                       MX25_PAD_A17__GPIO_2_3                  0x00000000
> +                       MX25_PAD_D12__GPIO_4_8                  0x000000a1

Looking at the mx25pdk U-boot source code we see that FEC pins are not
configured as per the default power-on reset values, so this changes
the behavior.

>         pinctrl_i2c1: i2c1grp {
>                 fsl,pins = <
> -                       MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
> -                       MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
> +                       MX25_PAD_I2C1_CLK__I2C1_CLK             0x000000a8
> +                       MX25_PAD_I2C1_DAT__I2C1_DAT             0x000000a8

Same happens with I2C pins.

To stay in the safe side I would only change the pins that have GPIO
functionality in this patch.

Then we could later change each 0x80000000 occurrance by replacing it
with the actual PAD register value instead of the power on defaults.

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

Hello Fabio,

On Sun, Jul 10, 2016 at 04:10:12PM -0300, Fabio Estevam wrote:
> On Sun, Jul 10, 2016 at 7:07 AM, Uwe Kleine-K?nig <uwe@kleine-koenig.org> wrote:
> 
> >  arch/arm/boot/dts/imx25-eukrea-cpuimx25.dtsi       | 18 +++----
> >  .../imx25-eukrea-mbimxsd25-baseboard-cmo-qvga.dts  |  2 +-
> > diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
> > index c823e45a7a01..643d083951ef 100644
> > --- a/arch/arm/boot/dts/imx25-pdk.dts
> > +++ b/arch/arm/boot/dts/imx25-pdk.dts
> 
> >         pinctrl_fec: fecgrp {
> >                 fsl,pins = <
> > -                       MX25_PAD_FEC_MDC__FEC_MDC               0x80000000
> > +                       MX25_PAD_FEC_MDC__FEC_MDC               0x00000060
> >                         MX25_PAD_FEC_MDIO__FEC_MDIO             0x400001e0
> > -                       MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x80000000
> > -                       MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x80000000
> > -                       MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x80000000
> > -                       MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x80000000
> > -                       MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x80000000
> > -                       MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x80000000
> > -                       MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x1c0
> > -                       MX25_PAD_A17__GPIO_2_3                  0x80000000
> > -                       MX25_PAD_D12__GPIO_4_8                  0x80000000
> > +                       MX25_PAD_FEC_TDATA0__FEC_TDATA0         0x00000060
> > +                       MX25_PAD_FEC_TDATA1__FEC_TDATA1         0x00000060
> > +                       MX25_PAD_FEC_TX_EN__FEC_TX_EN           0x00000060
> > +                       MX25_PAD_FEC_RDATA0__FEC_RDATA0         0x000000c1
> > +                       MX25_PAD_FEC_RDATA1__FEC_RDATA1         0x000000c0
> > +                       MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x000000c0
> > +                       MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x000001c0
> > +                       MX25_PAD_A17__GPIO_2_3                  0x00000000
> > +                       MX25_PAD_D12__GPIO_4_8                  0x000000a1
> 
> Looking at the mx25pdk U-boot source code we see that FEC pins are not
> configured as per the default power-on reset values, so this changes
> the behavior.
> 
> >         pinctrl_i2c1: i2c1grp {
> >                 fsl,pins = <
> > -                       MX25_PAD_I2C1_CLK__I2C1_CLK             0x80000000
> > -                       MX25_PAD_I2C1_DAT__I2C1_DAT             0x80000000
> > +                       MX25_PAD_I2C1_CLK__I2C1_CLK             0x000000a8
> > +                       MX25_PAD_I2C1_DAT__I2C1_DAT             0x000000a8
> 
> Same happens with I2C pins.
> 
> To stay in the safe side I would only change the pins that have GPIO
> functionality in this patch.
> 
> Then we could later change each 0x80000000 occurrance by replacing it
> with the actual PAD register value instead of the power on defaults.

Why later?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Mon, Jul 11, 2016 at 4:37 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:

>> Then we could later change each 0x80000000 occurrance by replacing it
>> with the actual PAD register value instead of the power on defaults.
>
> Why later?

I was not sure if you had access to all these mx25 boards to verify
the real values used on the pin configurations. I don't have access to
mx25pdk today, but I can access it later this week.

Thanks

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

On Mon, Jul 11, 2016 at 07:56:15AM -0300, Fabio Estevam wrote:
> Hi Uwe,
> 
> On Mon, Jul 11, 2016 at 4:37 AM, Uwe Kleine-K?nig
> <u.kleine-koenig@pengutronix.de> wrote:
> 
> >> Then we could later change each 0x80000000 occurrance by replacing it
> >> with the actual PAD register value instead of the power on defaults.
> >
> > Why later?
> 
> I was not sure if you had access to all these mx25 boards to verify
> the real values used on the pin configurations. I don't have access to
> mx25pdk today, but I can access it later this week.

I don't have access to these, but I took a look in the U-boot sources.

So on top of my patch I'd suggest the following change:

diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index cf41b726e2de..08caba550ee6 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -171,7 +171,7 @@
 			MX25_PAD_SD1_DATA2__SD1_DATA2		0x000000d1
 			MX25_PAD_SD1_DATA3__SD1_DATA3		0x000000d1
 			MX25_PAD_A14__GPIO_2_0			0x00000080
-			MX25_PAD_A15__GPIO_2_1			0x00000080
+			MX25_PAD_A15__GPIO_2_1			0x00000000
 		>;
 	};
 
@@ -187,14 +187,14 @@
 			MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x000000c0
 			MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x000001c0
 			MX25_PAD_A17__GPIO_2_3			0x00000000
-			MX25_PAD_D12__GPIO_4_8			0x000000a1
+			MX25_PAD_D12__GPIO_4_8			0x00000000
 		>;
 	};
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-			MX25_PAD_I2C1_CLK__I2C1_CLK		0x000000a8
-			MX25_PAD_I2C1_DAT__I2C1_DAT		0x000000a8
+			MX25_PAD_I2C1_CLK__I2C1_CLK		0x000001e8
+			MX25_PAD_I2C1_DAT__I2C1_DAT		0x000001e8
 		>;
 	};
 
Did I miss anything?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Tue, Jul 12, 2016 at 4:38 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:

> I don't have access to these, but I took a look in the U-boot sources.
>
> So on top of my patch I'd suggest the following change:
>
> diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
> index cf41b726e2de..08caba550ee6 100644
> --- a/arch/arm/boot/dts/imx25-pdk.dts
> +++ b/arch/arm/boot/dts/imx25-pdk.dts
> @@ -171,7 +171,7 @@
>                         MX25_PAD_SD1_DATA2__SD1_DATA2           0x000000d1
>                         MX25_PAD_SD1_DATA3__SD1_DATA3           0x000000d1
>                         MX25_PAD_A14__GPIO_2_0                  0x00000080
> -                       MX25_PAD_A15__GPIO_2_1                  0x00000080
> +                       MX25_PAD_A15__GPIO_2_1                  0x00000000
>                 >;
>         };
>
> @@ -187,14 +187,14 @@
>                         MX25_PAD_FEC_RX_DV__FEC_RX_DV           0x000000c0
>                         MX25_PAD_FEC_TX_CLK__FEC_TX_CLK         0x000001c0
>                         MX25_PAD_A17__GPIO_2_3                  0x00000000
> -                       MX25_PAD_D12__GPIO_4_8                  0x000000a1
> +                       MX25_PAD_D12__GPIO_4_8                  0x00000000
>                 >;
>         };
>
>         pinctrl_i2c1: i2c1grp {
>                 fsl,pins = <
> -                       MX25_PAD_I2C1_CLK__I2C1_CLK             0x000000a8
> -                       MX25_PAD_I2C1_DAT__I2C1_DAT             0x000000a8
> +                       MX25_PAD_I2C1_CLK__I2C1_CLK             0x000001e8
> +                       MX25_PAD_I2C1_DAT__I2C1_DAT             0x000001e8
>                 >;
>         };
>
> Did I miss anything?

I will try to get access to a mx25pdk and will confirm soon. Thanks

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Tue, Jul 12, 2016 at 12:15 PM, Fabio Estevam <festevam@gmail.com> wrote:

> I will try to get access to a mx25pdk and will confirm soon. Thanks

Please find attached the patch after reading all the PAD_CTL
registers. Feel free to submit it as part of your series.
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[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

Hello Fabio,

On Tue, Jul 12, 2016 at 03:32:54PM -0300, Fabio Estevam wrote:
> On Tue, Jul 12, 2016 at 12:15 PM, Fabio Estevam <festevam@gmail.com> wrote:
> 
> > I will try to get access to a mx25pdk and will confirm soon. Thanks
> 
> Please find attached the patch after reading all the PAD_CTL
> registers. Feel free to submit it as part of your series.

> From a2b9e24841909868803576c68c2d2b064a00d4a9 Mon Sep 17 00:00:00 2001
> From: Fabio Estevam <fabio.estevam@nxp.com>
> Date: Tue, 12 Jul 2016 15:19:02 -0300
> Subject: [PATCH] ARM: dts: imx25-pdk: Explicitly setup PAD config in dts
> 
> When passing 0x80000000 as the PAD_CTL config value, the kernel does
> not touch the PAD_CTL egisters and use the value that comes from the
> bootloader.
> 
> Instead of relying on the bootloader it is better to have the kernel
> to explicitly configure the PAD_CTL registers.
> 
> Modified each 0x80000000 occurrance by reading the real PAD_CTL
> registers values in the bootloader and putting in the dts.
> 
> Also tested by booting the resulting dtb.
> 
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
> ---
>  arch/arm/boot/dts/imx25-pdk.dts | 58 ++++++++++++++++++++---------------------
>  1 file changed, 29 insertions(+), 29 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
> index 7029210..e997e2b 100644
> --- a/arch/arm/boot/dts/imx25-pdk.dts
> +++ b/arch/arm/boot/dts/imx25-pdk.dts
> @@ -159,56 +159,56 @@
>  			fsl,pins = <
>  				MX25_PAD_GPIO_A__CAN1_TX		0x0
>  				MX25_PAD_GPIO_B__CAN1_RX		0x0
> -				MX25_PAD_D14__GPIO_4_6 			0x80000000
> +				MX25_PAD_D14__GPIO_4_6 			0xa1
>  			>;
>  		};
>  
>  		pinctrl_esdhc1: esdhc1grp {
>  			fsl,pins = <
> -				MX25_PAD_SD1_CMD__SD1_CMD		0x80000000
> -				MX25_PAD_SD1_CLK__SD1_CLK		0x80000000
> -				MX25_PAD_SD1_DATA0__SD1_DATA0		0x80000000
> -				MX25_PAD_SD1_DATA1__SD1_DATA1		0x80000000
> -				MX25_PAD_SD1_DATA2__SD1_DATA2		0x80000000
> -				MX25_PAD_SD1_DATA3__SD1_DATA3		0x80000000
> -				MX25_PAD_A14__GPIO_2_0			0x80000000
> -				MX25_PAD_A15__GPIO_2_1			0x80000000
> +				MX25_PAD_SD1_CMD__SD1_CMD		0xe1
> +				MX25_PAD_SD1_CLK__SD1_CLK		0xd1
> +				MX25_PAD_SD1_DATA0__SD1_DATA0		0xe1
> +				MX25_PAD_SD1_DATA1__SD1_DATA1		0xd1
> +				MX25_PAD_SD1_DATA2__SD1_DATA2		0xd1
> +				MX25_PAD_SD1_DATA3__SD1_DATA3		0xe1
> +				MX25_PAD_A14__GPIO_2_0			0x80
> +				MX25_PAD_A15__GPIO_2_1			0x00
>  			>;
>  		};
>  
>  		pinctrl_fec: fecgrp {
>  			fsl,pins = <
> -				MX25_PAD_FEC_MDC__FEC_MDC		0x80000000
> +				MX25_PAD_FEC_MDC__FEC_MDC		0x00
>  				MX25_PAD_FEC_MDIO__FEC_MDIO		0x400001e0
> -				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x80000000
> -				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x80000000
> -				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x80000000
> -				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0x80000000
> -				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0x80000000
> -				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0x80000000
> +				MX25_PAD_FEC_TDATA0__FEC_TDATA0		0x00
> +				MX25_PAD_FEC_TDATA1__FEC_TDATA1		0x00
> +				MX25_PAD_FEC_TX_EN__FEC_TX_EN		0x00
> +				MX25_PAD_FEC_RDATA0__FEC_RDATA0		0xc0
> +				MX25_PAD_FEC_RDATA1__FEC_RDATA1		0xc0
> +				MX25_PAD_FEC_RX_DV__FEC_RX_DV		0xc0
>  				MX25_PAD_FEC_TX_CLK__FEC_TX_CLK		0x1c0
> -				MX25_PAD_A17__GPIO_2_3			0x80000000
> -				MX25_PAD_D12__GPIO_4_8			0x80000000
> +				MX25_PAD_A17__GPIO_2_3			0x00
> +				MX25_PAD_D12__GPIO_4_8			0x00
>  			>;
>  		};
>  
>  		pinctrl_i2c1: i2c1grp {
>  			fsl,pins = <
> -				MX25_PAD_I2C1_CLK__I2C1_CLK		0x80000000
> -				MX25_PAD_I2C1_DAT__I2C1_DAT		0x80000000
> +				MX25_PAD_I2C1_CLK__I2C1_CLK		0xa8
> +				MX25_PAD_I2C1_DAT__I2C1_DAT		0xa8
>  			>;
>  		};
>  
>  		pinctrl_kpp: kppgrp {
>  			fsl,pins = <
> -				MX25_PAD_KPP_ROW0__KPP_ROW0	0x80000000
> -				MX25_PAD_KPP_ROW1__KPP_ROW1	0x80000000
> -				MX25_PAD_KPP_ROW2__KPP_ROW2	0x80000000
> -				MX25_PAD_KPP_ROW3__KPP_ROW3	0x80000000
> -				MX25_PAD_KPP_COL0__KPP_COL0	0x80000000
> -				MX25_PAD_KPP_COL1__KPP_COL1	0x80000000
> -				MX25_PAD_KPP_COL2__KPP_COL2	0x80000000
> -				MX25_PAD_KPP_COL3__KPP_COL3	0x80000000
> +				MX25_PAD_KPP_ROW0__KPP_ROW0	0xa0
> +				MX25_PAD_KPP_ROW1__KPP_ROW1	0xa0
> +				MX25_PAD_KPP_ROW2__KPP_ROW2	0xe0
> +				MX25_PAD_KPP_ROW3__KPP_ROW3	0xe0
> +				MX25_PAD_KPP_COL0__KPP_COL0	0xa8
> +				MX25_PAD_KPP_COL1__KPP_COL1	0xa8
> +				MX25_PAD_KPP_COL2__KPP_COL2	0xa8
> +				MX25_PAD_KPP_COL3__KPP_COL3	0xa8
>  			>;
>  		};
>  
> @@ -244,7 +244,7 @@
>  			fsl,pins = <
>  				MX25_PAD_UART1_RTS__UART1_RTS		0xe0
>  				MX25_PAD_UART1_CTS__UART1_CTS		0xe0
> -				MX25_PAD_UART1_TXD__UART1_TXD		0x80000000
> +				MX25_PAD_UART1_TXD__UART1_TXD		0x00
>  				MX25_PAD_UART1_RXD__UART1_RXD		0xc0

Are you sure here? According to the reference manual bit 0x40 of
IOMUXC_SW_PAD_CTL_PAD_UART1_RXD isn't valid. And my i.mx25 based machine
agrees:

	barebox at imx25:/ mw 0x43fac368 0xc0
	barebox at imx25:/ md 0x43fac368+4
	43fac368: 00000080                                           ....

(This entry was fixed in my series to 0x80.) So you only checked the
NO_PAD_CTL values, right?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Tue, Jul 12, 2016 at 4:15 PM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:

>> @@ -244,7 +244,7 @@
>>                       fsl,pins = <
>>                               MX25_PAD_UART1_RTS__UART1_RTS           0xe0
>>                               MX25_PAD_UART1_CTS__UART1_CTS           0xe0
>> -                             MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
>> +                             MX25_PAD_UART1_TXD__UART1_TXD           0x00
>>                               MX25_PAD_UART1_RXD__UART1_RXD           0xc0
>
> Are you sure here? According to the reference manual bit 0x40 of
> IOMUXC_SW_PAD_CTL_PAD_UART1_RXD isn't valid. And my i.mx25 based machine
> agrees:
>
>         barebox at imx25:/ mw 0x43fac368 0xc0
>         barebox at imx25:/ md 0x43fac368+4
>         43fac368: 00000080

Let me double check it when I get access to this board again.
                                           ....
>
> (This entry was fixed in my series to 0x80.) So you only checked the
> NO_PAD_CTL values, right?

Yes, I only checked the NO_PAD_CTL values.

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

On Tue, Jul 12, 2016 at 5:30 PM, Fabio Estevam <festevam@gmail.com> wrote:
> Hi Uwe,
>
> On Tue, Jul 12, 2016 at 4:15 PM, Uwe Kleine-K?nig
> <u.kleine-koenig@pengutronix.de> wrote:
>
>>> @@ -244,7 +244,7 @@
>>>                       fsl,pins = <
>>>                               MX25_PAD_UART1_RTS__UART1_RTS           0xe0
>>>                               MX25_PAD_UART1_CTS__UART1_CTS           0xe0
>>> -                             MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
>>> +                             MX25_PAD_UART1_TXD__UART1_TXD           0x00
>>>                               MX25_PAD_UART1_RXD__UART1_RXD           0xc0
>>
>> Are you sure here? According to the reference manual bit 0x40 of
>> IOMUXC_SW_PAD_CTL_PAD_UART1_RXD isn't valid. And my i.mx25 based machine
>> agrees:
>>
>>         barebox at imx25:/ mw 0x43fac368 0xc0
>>         barebox at imx25:/ md 0x43fac368+4
>>         43fac368: 00000080
>
> Let me double check it when I get access to this board again.

Sorry, I misread.

You were referring to MX25_PAD_UART1_RXD__UART1_RXD, not
MX25_PAD_UART1_TXD__UART1_TXD.

I didn't touch MX25_PAD_UART1_RXD__UART1_RXD, so your series does the
right thing for this pad (put it at 0x80).

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

Hello Fabio,

On Tue, Jul 12, 2016 at 05:40:13PM -0300, Fabio Estevam wrote:
> On Tue, Jul 12, 2016 at 5:30 PM, Fabio Estevam <festevam@gmail.com> wrote:
> > On Tue, Jul 12, 2016 at 4:15 PM, Uwe Kleine-K?nig
> > <u.kleine-koenig@pengutronix.de> wrote:
> >
> >>> @@ -244,7 +244,7 @@
> >>>                       fsl,pins = <
> >>>                               MX25_PAD_UART1_RTS__UART1_RTS           0xe0
> >>>                               MX25_PAD_UART1_CTS__UART1_CTS           0xe0
> >>> -                             MX25_PAD_UART1_TXD__UART1_TXD           0x80000000
> >>> +                             MX25_PAD_UART1_TXD__UART1_TXD           0x00
> >>>                               MX25_PAD_UART1_RXD__UART1_RXD           0xc0
> >>
> >> Are you sure here? According to the reference manual bit 0x40 of
> >> IOMUXC_SW_PAD_CTL_PAD_UART1_RXD isn't valid. And my i.mx25 based machine
> >> agrees:
> >>
> >>         barebox at imx25:/ mw 0x43fac368 0xc0
> >>         barebox at imx25:/ md 0x43fac368+4
> >>         43fac368: 00000080
> >
> > Let me double check it when I get access to this board again.
> 
> Sorry, I misread.
> 
> You were referring to MX25_PAD_UART1_RXD__UART1_RXD, not
> MX25_PAD_UART1_TXD__UART1_TXD.
> 
> I didn't touch MX25_PAD_UART1_RXD__UART1_RXD, so your series does the
> right thing for this pad (put it at 0x80).

OK.

Which U-Boot did you test? Mainline or the vendor variant?

Can you provide the output of

	md 0x43fac000+0x584

in U-Boot (which for sure has a different syntax that I don't know) and
from Linux

	memtool md 0x43fac000+0x584

(or whatever different tool you prefer to do the same).

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Wed, Jul 13, 2016 at 3:25 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:

> Which U-Boot did you test? Mainline or the vendor variant?

U-boot mainline.

> Can you provide the output of
>
>         md 0x43fac000+0x584
>
> in U-Boot (which for sure has a different syntax that I don't know) and
> from Linux
>
>         memtool md 0x43fac000+0x584
>
> (or whatever different tool you prefer to do the same).

Sure, I will run such tests when I get access to the board again tomorrow.

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Wed, Jul 13, 2016 at 3:25 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:

> Which U-Boot did you test? Mainline or the vendor variant?
>
> Can you provide the output of
>
>         md 0x43fac000+0x584

Here it goes:
=> md.l 0x43fac584 1
43fac584: 00000000                               ....

>
> in U-Boot (which for sure has a different syntax that I don't know) and
> from Linux
>
>         memtool md 0x43fac000+0x584

The memtool utility version I have is broken for mx25, so I can't dump
this register easily in Linux.

Regards,

Fabio Estevam

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

Hello Fabio,

On Thu, Jul 14, 2016 at 02:04:14PM -0300, Fabio Estevam wrote:
> On Wed, Jul 13, 2016 at 3:25 AM, Uwe Kleine-K?nig
> <u.kleine-koenig@pengutronix.de> wrote:
> 
> > Which U-Boot did you test? Mainline or the vendor variant?

I assume the vendor variant, because your patch doesn't match what I saw
in U-Boot mainline.

> > Can you provide the output of
> >
> >         md 0x43fac000+0x584
> 
> Here it goes:
> => md.l 0x43fac584 1
> 43fac584: 00000000                               ....

I guess your tool (U-Boot?) would generate the output I want with:

	md.l 0x43fac000 353

(i.e. 353 32bit words, that are all the iomux registers)

> > in U-Boot (which for sure has a different syntax that I don't know) and
> > from Linux
> >
> >         memtool md 0x43fac000+0x584
> 
> The memtool utility version I have is broken for mx25, so I can't dump
> this register easily in Linux.

Which version do you have? How is it broken? Did you configure AIPS to
allow non-privileged access to the peripherals? Our internal
documentation tells you have to set (in the boot loader) the following
registers to 0:

	0x43f00020 0x43f00024 0x43f00028 0x43f0002c
	0x43f00040 0x43f00044 0x43f00048 0x43f0004c 0x43f00050

After that memtool works fine for me in Linux.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Fabio Estevam]

Hi Uwe,

On Thu, Jul 14, 2016 at 3:34 PM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:

> I assume the vendor variant, because your patch doesn't match what I saw
> in U-Boot mainline.

I am running U-boot 2016.07 from mainline.

> I guess your tool (U-Boot?) would generate the output I want with:
>
>         md.l 0x43fac000 353
>
> (i.e. 353 32bit words, that are all the iomux registers)

Here it goes:

=> md.l 0x43fac000 0x161
43fac000: 00000000 00000000 00000000 00000000    ................
43fac010: 00000000 00000015 00000000 00000015    ................
43fac020: 00000000 00000000 00000000 00000000    ................
43fac030: 00000000 00000000 00000000 00000000    ................
43fac040: 00000000 00000000 00000000 00000000    ................
43fac050: 00000000 00000000 00000000 00000000    ................
43fac060: 00000000 00000000 00000000 00000000    ................
43fac070: 00000000 00000000 00000000 00000000    ................
43fac080: 00000000 00000000 00000000 00000000    ................
43fac090: 00000000 00000005 00000000 00000000    ................
43fac0a0: 00000000 00000000 00000000 00000000    ................
43fac0b0: 00000000 00000000 00000000 00000000    ................
43fac0c0: 00000000 00000000 00000000 00000000    ................
43fac0d0: 00000000 00000000 00000000 00000000    ................
43fac0e0: 00000000 00000000 00000000 00000000    ................
43fac0f0: 00000000 00000000 00000000 00000000    ................
43fac100: 00000000 00000000 00000000 00000000    ................
43fac110: 00000000 00000000 00000000 00000000    ................
43fac120: 00000000 00000000 00000000 00000000    ................
43fac130: 00000000 00000000 00000000 00000000    ................
43fac140: 00000000 00000000 00000000 00000000    ................
43fac150: 00000010 00000010 00000000 00000000    ................
43fac160: 00000000 00000000 00000000 00000000    ................
43fac170: 00000010 00000010 00000010 00000010    ................
43fac180: 00000000 00000000 00000000 00000005    ................
43fac190: 00000010 00000010 00000010 00000010    ................
43fac1a0: 00000010 00000010 00000000 00000000    ................
43fac1b0: 00000000 00000000 00000000 00000000    ................
43fac1c0: 00000000 00000000 00000010 00000010    ................
43fac1d0: 00000010 00000010 00000010 00000010    ................
43fac1e0: 00000010 00000010 00000010 00000000    ................
43fac1f0: 00000000 00000000 00000000 00000000    ................
43fac200: 00000000 00000000 00000000 00000000    ................
43fac210: 00000000 00000000 00000000 00000000    ................
43fac220: 00000000 00000000 00000000 00000080    ................
43fac230: 00000080 00000000 00000000 00000000    ................
43fac240: 00000000 00000000 00000000 00000000    ................
43fac250: 00000000 00000000 00000000 00000000    ................
43fac260: 00000000 00002001 00002001 00000001    ..... ... ......
43fac270: 00002080 00000000 00000000 00000080    . ..............
43fac280: 000000a1 000000a1 000000a1 00000000    ................
43fac290: 00000021 000000a1 000000a1 000000a1    !...............
43fac2a0: 00000000 00000000 00000000 00000000    ................
43fac2b0: 00000000 00000000 00000000 00000000    ................
43fac2c0: 00000060 00000060 00000060 00000060    `...`...`...`...
43fac2d0: 00000060 00000060 00000060 00000060    `...`...`...`...
43fac2e0: 00000060 00000160 00000060 00000060    `...`...`...`...
43fac2f0: 00000060 00000060 00000020 00000060    `...`... ...`...
43fac300: 00000060 00000060 00000061 00000060    `...`...a...`...
43fac310: 00000060 000000c0 000000a1 000000a0    `...............
43fac320: 000001a1 000000a0 000000a0 000001a0    ................
43fac330: 000000a0 000000a0 00000061 000000a0    ........a.......
43fac340: 000000a0 000001a0 000000a8 000000a8    ................
43fac350: 000000a0 000000a0 000000e0 000000a0    ................
43fac360: 000000a0 000000a0 000000a0 00000000    ................
43fac370: 00000000 000000e0 000000e0 00000060    ............`...
43fac380: 000000e1 00000060 000000e1 000000d1    ....`...........
43fac390: 000000e1 000000d1 000000d1 000000e1    ................
43fac3a0: 000000a0 000000a0 000000e0 000000e0    ................
43fac3b0: 000000a8 000000a8 000000a8 000000a8    ................
43fac3c0: 00000000 000001f0 00000000 00000000    ................
43fac3d0: 00000000 000000c0 000000c0 000000c0    ................
43fac3e0: 000001c0 00000062 00000002 00000000    ....b...........
43fac3f0: 00000040 000000c0 000000c0 00000020    @........... ...
43fac400: 000000a8 00000020 00000000 00000080    .... ...........
43fac410: 00000080 00000004 00000000 00000000    ................
43fac420: 00000000 00000002 00000000 00000002    ................
43fac430: 00000002 00000000 00000000 00000002    ................
43fac440: 00000000 00000000 00000000 00000000    ................
43fac450: 00000000 00001000 00000000 00000000    ................
43fac460: 00000000 00000000 00000000 00000000    ................
43fac470: 00000000 00000000 00000000 00000000    ................
43fac480: 00000000 00000000 00000000 00000000    ................
43fac490: 00000000 00000000 00000000 00000000    ................
43fac4a0: 00000000 00000000 00000000 00000000    ................
43fac4b0: 00000000 00000000 00000000 00000000    ................
43fac4c0: 00000000 00000000 00000000 00000000    ................
43fac4d0: 00000000 00000000 00000000 00000000    ................
43fac4e0: 00000000 00000000 00000000 00000000    ................
43fac4f0: 00000000 00000000 00000000 00000000    ................
43fac500: 00000000 00000000 00000000 00000000    ................
43fac510: 00000000 00000000 00000000 00000000    ................
43fac520: 00000000 00000000 00000000 00000000    ................
43fac530: 00000000 00000000 00000000 00000000    ................
43fac540: 00000000 00000000 00000000 00000000    ................
43fac550: 00000000 00000000 00000000 00000000    ................
43fac560: 00000000 00000000 00000000 00000000    ................
43fac570: 00000000 00000000 00000000 00000000    ................
43fac580: 00000000

>> The memtool utility version I have is broken for mx25, so I can't dump
>> this register easily in Linux.
>
> Which version do you have? How is it broken? Did you configure AIPS to

The problem is that all IOMUX registers were returning the same
incorrect values with memtool on mx25.

> allow non-privileged access to the peripherals? Our internal
> documentation tells you have to set (in the boot loader) the following
> registers to 0:
>
>         0x43f00020 0x43f00024 0x43f00028 0x43f0002c
>         0x43f00040 0x43f00044 0x43f00048 0x43f0004c 0x43f00050
>
> After that memtool works fine for me in Linux.

I will give this a try, thanks.

[PATCH 3/6] ARM: dts: imx25: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

Hello Fabio,

On Thu, Jul 14, 2016 at 04:16:59PM -0300, Fabio Estevam wrote:
> I am running U-boot 2016.07 from mainline.

hmm, ok.

> > I guess your tool (U-Boot?) would generate the output I want with:
> >
> >         md.l 0x43fac000 353
> >
> > (i.e. 353 32bit words, that are all the iomux registers)
> 
> Here it goes:
> 
> [...]

Thanks, will take a look.

> >> The memtool utility version I have is broken for mx25, so I can't dump
> >> this register easily in Linux.
> >
> > Which version do you have? How is it broken? Did you configure AIPS to
> 
> The problem is that all IOMUX registers were returning the same
> incorrect values with memtool on mx25.

Yeah, that's the effect when the AIPS access control registers are not
setup correctly.

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-K?nig            |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |

[PATCH 4/6] ARM: dts: imx6q: don't configure reserved pad settings

[Uwe Kleine-König]

Several dts files set a bit in the SPEED field for pads
RGMII_{R,T}{XC,D0,D1,D2,D3,X_CTL}, but that doesn't exist. Writing there
doesn't have an effect and the bit reads as zero.

Signed-off-by: Uwe Kleine-K?nig <uwe@kleine-koenig.org>
---
 arch/arm/boot/dts/imx6dl-riotboard.dts       | 22 +++++++++++-----------
 arch/arm/boot/dts/imx6q-arm2.dts             | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-ba16.dtsi            | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-cm-fx6.dts           | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts      | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-evi.dts              | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-gw5400-a.dts         | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-marsboard.dts        | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-novena.dts           | 12 ++++++------
 arch/arm/boot/dts/imx6q-sbc6x.dts            | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6q-tbs2910.dts          | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-apalis.dtsi        | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-gw51xx.dtsi        | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-gw52xx.dtsi        | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-gw53xx.dtsi        | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-gw54xx.dtsi        | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi     | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi     | 12 ++++++------
 arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi    | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-rex.dtsi           | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-sabreauto.dtsi     | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-sabrelite.dtsi     | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi       | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-udoo.dtsi          | 24 ++++++++++++------------
 arch/arm/boot/dts/imx6qdl-wandboard.dtsi     | 24 ++++++++++++------------
 28 files changed, 323 insertions(+), 323 deletions(-)

diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 2309b050525f..34a8927b6206 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -374,18 +374,18 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1		/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0		/* AR8035 pin strapping: IO voltage: pull up */
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x130b0		/* AR8035 pin strapping: PHYADDR#0: pull down */
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x130b0		/* AR8035 pin strapping: PHYADDR#1: pull down */
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0		/* AR8035 pin strapping: MODE#1: pull up */
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0		/* AR8035 pin strapping: MODE#3: pull up */
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030		/* AR8035 pin strapping: IO voltage: pull up */
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030		/* AR8035 pin strapping: PHYADDR#0: pull down */
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030		/* AR8035 pin strapping: PHYADDR#1: pull down */
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030		/* AR8035 pin strapping: MODE#1: pull up */
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030		/* AR8035 pin strapping: MODE#3: pull up */
 			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0		/* AR8035 pin strapping: MODE#0: pull down */
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8	/* GPIO16 -> AR8035 25MHz */
 			MX6QDL_PAD_EIM_D31__GPIO3_IO31		0x130b0		/* RGMII_nRST */
diff --git a/arch/arm/boot/dts/imx6q-arm2.dts b/arch/arm/boot/dts/imx6q-arm2.dts
index 1ef2ca4251b0..fb922559bbb5 100644
--- a/arch/arm/boot/dts/imx6q-arm2.dts
+++ b/arch/arm/boot/dts/imx6q-arm2.dts
@@ -78,19 +78,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 		>;
 	};
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index f7e17e2004ac..e75db4eb1c38 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -448,19 +448,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 			/* FEC Reset */
 			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28     0x1b0b0
 			/* AR8033 Interrupt */
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index 21c513f6980e..63f0550f78e8 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -49,18 +49,18 @@
 &iomuxc {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 84046ad7ab16..63bf517ad568 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -323,18 +323,18 @@
 
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 4fa56019225e..9647c099acc6 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -303,19 +303,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x4001b0a8
 			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0
 		>;
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 2e40c7e2f870..bb7067e9e32e 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -419,18 +419,18 @@
 
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index bc22cc31119c..9d9febb5d03f 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -251,26 +251,26 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			/* AR8035 CLK_25M --> ENET_REF_CLK (V22) */
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x0a0b1
 			/* AR8035 pin strapping: IO voltage: pull up */
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
 			/* AR8035 pin strapping: PHYADDR#0: pull down */
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x130b0
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x13030
 			/* AR8035 pin strapping: PHYADDR#1: pull down */
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x130b0
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x13030
 			/* AR8035 pin strapping: MODE#1: pull up */
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
 			/* AR8035 pin strapping: MODE#3: pull up */
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
 			/* AR8035 pin strapping: MODE#0: pull down */
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x130b0
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
 			/* GPIO16 -> AR8035 25MHz */
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
 			/* RGMII_nRST */
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 5acd0c63b33b..1723e89e3acc 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -549,12 +549,12 @@
 			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b028
 			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b028
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
 			/* Ethernet reset */
 			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x1b0b1
diff --git a/arch/arm/boot/dts/imx6q-sbc6x.dts b/arch/arm/boot/dts/imx6q-sbc6x.dts
index 60277d75b207..8e275a9ac5f4 100644
--- a/arch/arm/boot/dts/imx6q-sbc6x.dts
+++ b/arch/arm/boot/dts/imx6q-sbc6x.dts
@@ -30,19 +30,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
 		>;
 	};
diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts
index 1926b1348a62..d67576f0d9fc 100644
--- a/arch/arm/boot/dts/imx6q-tbs2910.dts
+++ b/arch/arm/boot/dts/imx6q-tbs2910.dts
@@ -284,19 +284,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK      0x4001b0a8
 			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25    0x1b059
 		>;
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 922b1dd06fda..0a75d610bf1d 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -586,19 +586,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			/* Ethernet PHY reset */
 			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
 			/* Ethernet PHY interrupt */
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
index 80682d506f8f..fc4f6459d0fa 100644
--- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -66,18 +66,18 @@
 
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
index 5e829c650a56..bdb07b99291c 100644
--- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi
@@ -231,18 +231,18 @@
 &iomuxc {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 78b53ff4aa17..4a1eb96b9595 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -375,18 +375,18 @@
 
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
index 8788afc25709..0de81cf0ed7a 100644
--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
@@ -364,18 +364,18 @@
 
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
index 8ceaf527b58e..ff2bc7eca88d 100644
--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
@@ -466,18 +466,18 @@
 
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
index f8d945a56525..d5c3aa88adbe 100644
--- a/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-icore-rqs.dtsi
@@ -254,19 +254,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO       0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC         0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC       0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0       0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1       0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2       0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3       0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK  0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC       0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0       0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1       0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2       0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3       0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
 			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN     0x1b0b0
 		>;
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 1a4a244c31f9..7b7629091a02 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -359,12 +359,12 @@
 			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
 			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			/* Phy reset */
 			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x0f0b0
 			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index 762b2a934978..94f4aeaad099 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -482,19 +482,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			/* Phy reset */
 			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x0f0b0
 			MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28	0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index c9a337deb7cd..dcfdb2c24e62 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -392,19 +392,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			/* Phy reset */
 			MX6QDL_PAD_ENET_RXD0__GPIO1_IO27	0x000b0
 			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index afffd1b0f158..31d01e44f3b8 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -230,19 +230,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN	0x1b0b0
 		>;
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index f8d49899f6e8..c50a7b77e366 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -195,19 +195,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
 			/* Phy reset */
 			MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x000b0
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index cab748c7483f..ef1b1fbdeb9a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -343,19 +343,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_KEY_COL2__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 		>;
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 9b9999499930..0c0b5448a536 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -357,19 +357,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x100b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x100b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x100b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x100b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x100b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x100b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			/* Phy reset */
 			MX6QDL_PAD_EIM_D23__GPIO3_IO23		0x000b0
 			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 7ab9249b6144..53e6df5a5f6a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -379,19 +379,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
 		>;
 	};
diff --git a/arch/arm/boot/dts/imx6qdl-udoo.dtsi b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
index 42caca66ef04..0f1db99274be 100644
--- a/arch/arm/boot/dts/imx6qdl-udoo.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-udoo.dtsi
@@ -131,18 +131,18 @@
 &iomuxc {
 	pinctrl_enet: enetgrp {
 		fsl,pins = <
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index dff0eab40f79..cc845026cd60 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -107,19 +107,19 @@
 		fsl,pins = <
 			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
 			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
-			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
-			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
-			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
-			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
-			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
-			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b030
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b030
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b030
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b030
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b030
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b030
 			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
-			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
-			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
-			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
-			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
-			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
-			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
 			MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
 			MX6QDL_PAD_GPIO_6__ENET_IRQ		0x000b1
 		>;
-- 
2.8.1

[PATCH 5/6] ARM: dts: imx: fix polarity of fec reset gpios

[Uwe Kleine-König]

The fec driver ignores the polarity flags of the references in
phy-reset-gpios and assumes them to be active low unlesss there is a
property phy-reset-active-high.

So fix all device trees that specify (maybe implicitly) an active high
gpio without the phy-reset-active-high property.

Signed-off-by: Uwe Kleine-K?nig <uwe@kleine-koenig.org>
---
 arch/arm/boot/dts/imx25-karo-tx25.dts          | 5 ++++-
 arch/arm/boot/dts/imx25-pdk.dts                | 2 +-
 arch/arm/boot/dts/imx50-evk.dts                | 5 ++++-
 arch/arm/boot/dts/imx51-apf51.dts              | 2 +-
 arch/arm/boot/dts/imx53-mba53.dts              | 2 +-
 arch/arm/boot/dts/imx53-qsb-common.dtsi        | 2 +-
 arch/arm/boot/dts/imx53-smd.dts                | 2 +-
 arch/arm/boot/dts/imx53-tx53.dtsi              | 2 +-
 arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi    | 2 +-
 arch/arm/boot/dts/imx6dl-riotboard.dts         | 2 +-
 arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts        | 2 +-
 arch/arm/boot/dts/imx6q-evi.dts                | 2 +-
 arch/arm/boot/dts/imx6q-gw5400-a.dts           | 2 +-
 arch/arm/boot/dts/imx6q-novena.dts             | 2 +-
 arch/arm/boot/dts/imx6qdl-aristainetos.dtsi    | 2 +-
 arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi   | 2 +-
 arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi | 2 +-
 arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi      | 2 +-
 arch/arm/boot/dts/imx6qdl-sabresd.dtsi         | 2 +-
 arch/arm/boot/dts/imx6qdl-tx6.dtsi             | 2 +-
 arch/arm/boot/dts/imx6qdl-wandboard.dtsi       | 2 +-
 arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts   | 2 +-
 arch/arm/boot/dts/imx6ul-tx6ul.dtsi            | 4 ++--
 23 files changed, 30 insertions(+), 24 deletions(-)

diff --git a/arch/arm/boot/dts/imx25-karo-tx25.dts b/arch/arm/boot/dts/imx25-karo-tx25.dts
index c622c342efa0..901ef21a38d8 100644
--- a/arch/arm/boot/dts/imx25-karo-tx25.dts
+++ b/arch/arm/boot/dts/imx25-karo-tx25.dts
@@ -10,6 +10,9 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
 #include "imx25.dtsi"
 
 / {
@@ -97,7 +100,7 @@
 &fec {
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
-	phy-reset-gpios = <&gpio3 7 0>;
+	phy-reset-gpios = <&gpio3 7 GPIO_ACTIVE_LOW>;
 	phy-mode = "rmii";
 	phy-supply = <&reg_fec_phy>;
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx25-pdk.dts b/arch/arm/boot/dts/imx25-pdk.dts
index 643d083951ef..cf41b726e2de 100644
--- a/arch/arm/boot/dts/imx25-pdk.dts
+++ b/arch/arm/boot/dts/imx25-pdk.dts
@@ -125,7 +125,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-supply = <&reg_fec_3v3>;
-	phy-reset-gpios = <&gpio4 8 0>;
+	phy-reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 04cefa7c950f..29706cf4b5ef 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -12,6 +12,9 @@
  */
 
 /dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+
 #include "imx50.dtsi"
 
 / {
@@ -54,7 +57,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio4 12 0>;
+	phy-reset-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx51-apf51.dts b/arch/arm/boot/dts/imx51-apf51.dts
index aa5861610834..2ed675a8e4bf 100644
--- a/arch/arm/boot/dts/imx51-apf51.dts
+++ b/arch/arm/boot/dts/imx51-apf51.dts
@@ -36,7 +36,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "mii";
-	phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
 	phy-reset-duration = <1>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index fa6438141747..2099861d6013 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -189,7 +189,7 @@
 };
 
 &fec {
-	phy-reset-gpios = <&gpio7 6 0>;
+	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx53-qsb-common.dtsi b/arch/arm/boot/dts/imx53-qsb-common.dtsi
index baebcd3a0515..da481610a8b4 100644
--- a/arch/arm/boot/dts/imx53-qsb-common.dtsi
+++ b/arch/arm/boot/dts/imx53-qsb-common.dtsi
@@ -342,7 +342,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio7 6 0>;
+	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 105b5e0972ff..5f8ecbe1b65b 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -272,6 +272,6 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio7 6 0>;
+	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index 13deaa664eb8..f4a47aec9ecb 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -202,7 +202,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 	phy-handle = <&phy0>;
 	mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
index 1ad10374b3c5..fbdd38f0fca0 100644
--- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -136,7 +136,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_fec>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio4 2 0>;
+	phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts
index 34a8927b6206..d11fd9607f01 100644
--- a/arch/arm/boot/dts/imx6dl-riotboard.dts
+++ b/arch/arm/boot/dts/imx6dl-riotboard.dts
@@ -94,7 +94,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio3 31 0>;
+	phy-reset-gpios = <&gpio3 31 GPIO_ACTIVE_LOW>;
 	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 63bf517ad568..5571e07cb276 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -119,7 +119,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio1 25 0>;
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 	phy-supply = <&vgen2_1v2_eth>;
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 9647c099acc6..b25284e35047 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -138,7 +138,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio1 25 0>;
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index bb7067e9e32e..706422ac46f9 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -155,7 +155,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii-id";
-	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 1723e89e3acc..a8cae9b30d76 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -218,7 +218,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet_novena>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
 	rxc-skew-ps = <3000>;
 	rxdv-skew-ps = <0>;
 	txc-skew-ps = <3000>;
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index f7e6803992ee..534494f82745 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -119,7 +119,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
index 7d81100e7d47..13da8623f595 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
@@ -323,7 +323,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>;
 	txd0-skew-ps = <0>;
 	txd1-skew-ps = <0>;
 	txd2-skew-ps = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
index 631fa6eacc79..d073796a9d0b 100644
--- a/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
@@ -46,7 +46,7 @@
 	pinctrl-0 = <&pinctrl_microsom_enet_ar8035>;
 	phy-mode = "rgmii";
 	phy-reset-duration = <2>;
-	phy-reset-gpios = <&gpio4 15 0>;
+	phy-reset-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index dcfdb2c24e62..329b36c44c54 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -272,7 +272,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio1 27 0>;
+	phy-reset-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
 	txen-skew-ps = <0>;
 	txc-skew-ps = <3000>;
 	rxdv-skew-ps = <0>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 53e6df5a5f6a..dde6337102f1 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -179,7 +179,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio1 25 0>;
+	phy-reset-gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
 	status = "okay";
 };
 
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 39b85aef93e1..41dc9ad56180 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -250,7 +250,7 @@
 		 <&clks IMX6QDL_CLK_ENET_REF>;
 	clock-names = "ipg", "ahb", "ptp", "enet_out";
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>;
 	phy-handle = <&etnphy>;
 	phy-supply = <&reg_3v3_etn>;
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
index cc845026cd60..3590080a4f44 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard.dtsi
@@ -205,7 +205,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet>;
 	phy-mode = "rgmii";
-	phy-reset-gpios = <&gpio3 29 0>;
+	phy-reset-gpios = <&gpio3 29 GPIO_ACTIVE_LOW>;
 	interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
 			      <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
index d25899b71575..0c380df39ae3 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
+++ b/arch/arm/boot/dts/imx6ul-tx6ul-mainboard.dts
@@ -78,7 +78,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2 &pinctrl_enet2_mdio &pinctrl_etnphy1_rst>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 	phy-supply = <&reg_3v3_etn>;
 	phy-handle = <&etnphy1>;
 	status = "okay";
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 437e9aad5920..5caf5534ea3d 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -309,7 +309,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio &pinctrl_etnphy0_rst>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio5 6 GPIO_ACTIVE_LOW>;
 	phy-supply = <&reg_3v3_etn>;
 	phy-handle = <&etnphy0>;
 	status = "okay";
@@ -344,7 +344,7 @@
 	pinctrl-names = "default";
 	pinctrl-0 = <&pinctrl_enet2 &pinctrl_etnphy1_rst>;
 	phy-mode = "rmii";
-	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
+	phy-reset-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
 	phy-supply = <&reg_3v3_etn>;
 	phy-handle = <&etnphy1>;
 	status = "disabled";
-- 
2.8.1

[PATCH 6/6] ARM: dts: imx6-wandboard: substitute NO_PAD_CTL by the respective reset value

[Uwe Kleine-König]

When 0x80000000 (aka NO_PAD_CTL) is used as pad config value, the
SW_PAD_CTL register isn't modified. Instead be more explicit here
and specify the reset default value.

If the machines don't depend on bootloader modifications to these
registers (and the tables in the reference manual are right) this commit
doesn't result in different behaviour of the affected machines.

Signed-off-by: Uwe Kleine-K?nig <uwe@kleine-koenig.org>
---
 arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi | 16 ++++++++--------
 arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi | 18 +++++++++---------
 2 files changed, 17 insertions(+), 17 deletions(-)

diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
index d92c5a4f07d9..73f31ede9aba 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revb1.dtsi
@@ -17,17 +17,17 @@
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* GPIO_0_CLKO */
-			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* uSDHC1 CD */
-			MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000	/* uSDHC3 CD */
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0		/* uSDHC1 CD */
+			MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x0b0b1		/* uSDHC3 CD */
 			MX6QDL_PAD_EIM_EB1__GPIO2_IO29		0x0f0b0		/* WL_REF_ON */
 			MX6QDL_PAD_EIM_A25__GPIO5_IO02		0x0f0b0		/* WL_RST_N */
 			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x000b0		/* WL_REG_ON */
-			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x80000000	/* WL_HOST_WAKE */
-			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000	/* WL_WAKE */
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x80000000	/* RGMII_nRST */
-			MX6QDL_PAD_EIM_DA13__GPIO3_IO13		0x80000000	/* BT_ON */
-			MX6QDL_PAD_EIM_DA14__GPIO3_IO14		0x80000000	/* BT_WAKE */
-			MX6QDL_PAD_EIM_DA15__GPIO3_IO15		0x80000000	/* BT_HOST_WAKE */				
+			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0		/* WL_HOST_WAKE */
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0		/* WL_WAKE */
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x1b0b0		/* RGMII_nRST */
+			MX6QDL_PAD_EIM_DA13__GPIO3_IO13		0x0b0b1		/* BT_ON */
+			MX6QDL_PAD_EIM_DA14__GPIO3_IO14		0x0b0b1		/* BT_WAKE */
+			MX6QDL_PAD_EIM_DA15__GPIO3_IO15		0x0b0b1		/* BT_HOST_WAKE */
 		>;
 	};
 };
diff --git a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
index ca4bfb2aa218..8a76601e931a 100644
--- a/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-wandboard-revc1.dtsi
@@ -1,4 +1,4 @@
-/*
+	/*
  * Copyright 2013 Freescale Semiconductor, Inc.
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
@@ -17,17 +17,17 @@
 	pinctrl_hog: hoggrp {
 		fsl,pins = <
 			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0		/* GPIO_0_CLKO */
-			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x80000000	/* uSDHC1 CD */
-			MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x80000000	/* uSDHC3 CD */
+			MX6QDL_PAD_GPIO_2__GPIO1_IO02		0x1b0b0		/* uSDHC1 CD */
+			MX6QDL_PAD_EIM_DA9__GPIO3_IO09		0x0b0b1		/* uSDHC3 CD */
 			MX6QDL_PAD_CSI0_DAT14__GPIO6_IO00	0x0f0b0		/* WIFI_ON (reset, active low) */
 			MX6QDL_PAD_ENET_RXD1__GPIO1_IO26	0x000b0		/* WL_REG_ON (unused) */
-			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x80000000	/* WL_HOST_WAKE, input */
+			MX6QDL_PAD_ENET_TXD1__GPIO1_IO29	0x1b0b0		/* WL_HOST_WAKE, input */
 			MX6QDL_PAD_CSI0_DAT13__GPIO5_IO31	0x0f0b0		/* GPIO5_IO31 (Wifi Power Enable) */
-			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x80000000	/* WL_WAKE (unused) */
-			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x80000000	/* BT_ON */
-			MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30	0x80000000	/* BT_WAKE */
-			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x80000000	/* BT_HOST_WAKE */
-			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x80000000	/* RGMII_nRST */
+			MX6QDL_PAD_ENET_TXD0__GPIO1_IO30	0x1b0b0		/* WL_WAKE (unused) */
+			MX6QDL_PAD_CSI0_VSYNC__GPIO5_IO21	0x1b0b0		/* BT_ON */
+			MX6QDL_PAD_CSI0_DAT12__GPIO5_IO30	0x1b0b0		/* BT_WAKE */
+			MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20	0x1b0b0		/* BT_HOST_WAKE */
+			MX6QDL_PAD_EIM_D29__GPIO3_IO29		0x1b0b0		/* RGMII_nRST */
 		>;
 	};
 };
-- 
2.8.1