[PATCH 0/4] misc: add ArmChina Zhouyi NPU driver

[PATCH 0/4] misc: add ArmChina Zhouyi NPU driver

[Dejia Shang]

Hi,

These 4 patches add supports to the ArmChina Zhouyi NPU IPs.

The Zhouyi NPUs (and software for it) are designed by Arm Technology (China) Co. Ltd.,
i.e. short for ArmChina, for edge AI computing devices in markets like smart home, auto,
IoT, mobile, etc. The brand name "Zhouyi" comes from a Chinese traditional classic about
changes and predictions. Currently two versions of Zhouyi IP (Z1 and Z2) are released,
and they are integrated into SoC chips Allwinner R329 and Siengine SE1000, respectively.

This driver supports the control of Zhouyi Z1 and Z2 NPUs. By using the user mode driver
APIs, application program can schedule AI inference tasks on Zhouyi NPUs efficiently. The
user mode part of this driver is opensourced now and anyone can fetch it from github:
https://github.com/dejsha01/armchina-zhouyi.

We found that a few days ago someone submitted a legacy version of Zhouyi NPU driver:
https://lore.kernel.org/lkml/20211126021904.32325-1-caihuoqing@baidu.com/#t.
We think that the current version in these 4 patches is better for upstreaming because
it contains bug-fixes and code optimizations compared with the legacy version,
and the corresponding user mode driver for this kernel driver is opensourced.

I would appricate any feedback, question or review :)

Thanks,
Dejia

Dejia Shang (4):
  misc: add ArmChina Zhouyi NPU driver
  Documentation: add sysfs entries for Zhouyi NPU
  dt-bindings: add vendor-prefix and documentation for Zhouyi NPU
  MAINTAINERS: add maintainer info. for Zhouyi NPU

 .../sysfs-devices-platform-armchina-npu       |  13 +
 .../bindings/misc/armchina,zhouyi-npu.yaml    |  57 ++
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |  10 +
 drivers/misc/Kconfig                          |   1 +
 drivers/misc/Makefile                         |   1 +
 drivers/misc/armchina-npu/Kconfig             |  15 +
 drivers/misc/armchina-npu/Makefile            |  11 +
 drivers/misc/armchina-npu/aipu.c              | 312 ++++++++
 drivers/misc/armchina-npu/aipu_core.c         | 418 ++++++++++
 drivers/misc/armchina-npu/aipu_core.h         | 100 +++
 drivers/misc/armchina-npu/aipu_io.c           |  74 ++
 drivers/misc/armchina-npu/aipu_io.h           |  27 +
 drivers/misc/armchina-npu/aipu_irq.c          | 113 +++
 drivers/misc/armchina-npu/aipu_irq.h          |  36 +
 drivers/misc/armchina-npu/aipu_job_manager.c  | 689 ++++++++++++++++
 drivers/misc/armchina-npu/aipu_job_manager.h  | 110 +++
 drivers/misc/armchina-npu/aipu_mm.c           | 740 ++++++++++++++++++
 drivers/misc/armchina-npu/aipu_mm.h           | 127 +++
 drivers/misc/armchina-npu/aipu_priv.c         | 280 +++++++
 drivers/misc/armchina-npu/aipu_priv.h         |  58 ++
 drivers/misc/armchina-npu/aipu_soc_default.c  |  82 ++
 drivers/misc/armchina-npu/config.h            |  12 +
 .../armchina-npu/include/armchina_aipu_soc.h  |  52 ++
 drivers/misc/armchina-npu/zhouyi/Makefile     |   4 +
 drivers/misc/armchina-npu/zhouyi/z1.c         | 244 ++++++
 drivers/misc/armchina-npu/zhouyi/z1.h         |  33 +
 drivers/misc/armchina-npu/zhouyi/z2.c         | 311 ++++++++
 drivers/misc/armchina-npu/zhouyi/z2.h         |  47 ++
 drivers/misc/armchina-npu/zhouyi/zhouyi.c     | 142 ++++
 drivers/misc/armchina-npu/zhouyi/zhouyi.h     |  73 ++
 include/uapi/misc/armchina_aipu.h             | 335 ++++++++
 32 files changed, 4529 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-armchina-npu
 create mode 100644 Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
 create mode 100644 drivers/misc/armchina-npu/Kconfig
 create mode 100644 drivers/misc/armchina-npu/Makefile
 create mode 100644 drivers/misc/armchina-npu/aipu.c
 create mode 100644 drivers/misc/armchina-npu/aipu_core.c
 create mode 100644 drivers/misc/armchina-npu/aipu_core.h
 create mode 100644 drivers/misc/armchina-npu/aipu_io.c
 create mode 100644 drivers/misc/armchina-npu/aipu_io.h
 create mode 100644 drivers/misc/armchina-npu/aipu_irq.c
 create mode 100644 drivers/misc/armchina-npu/aipu_irq.h
 create mode 100644 drivers/misc/armchina-npu/aipu_job_manager.c
 create mode 100644 drivers/misc/armchina-npu/aipu_job_manager.h
 create mode 100644 drivers/misc/armchina-npu/aipu_mm.c
 create mode 100644 drivers/misc/armchina-npu/aipu_mm.h
 create mode 100644 drivers/misc/armchina-npu/aipu_priv.c
 create mode 100644 drivers/misc/armchina-npu/aipu_priv.h
 create mode 100644 drivers/misc/armchina-npu/aipu_soc_default.c
 create mode 100644 drivers/misc/armchina-npu/config.h
 create mode 100644 drivers/misc/armchina-npu/include/armchina_aipu_soc.h
 create mode 100644 drivers/misc/armchina-npu/zhouyi/Makefile
 create mode 100644 drivers/misc/armchina-npu/zhouyi/z1.c
 create mode 100644 drivers/misc/armchina-npu/zhouyi/z1.h
 create mode 100644 drivers/misc/armchina-npu/zhouyi/z2.c
 create mode 100644 drivers/misc/armchina-npu/zhouyi/z2.h
 create mode 100644 drivers/misc/armchina-npu/zhouyi/zhouyi.c
 create mode 100644 drivers/misc/armchina-npu/zhouyi/zhouyi.h
 create mode 100644 include/uapi/misc/armchina_aipu.h

--
2.17.1

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[PATCH 2/4] Documentation: add sysfs entries for Zhouyi NPU

[Dejia Shang]

Zhouyi NPU driver provides sysfs interfaces for userspace to
check the status of NPU cores.

Signed-off-by: Dejia Shang <dejia.shang@armchina.com>
---
 .../ABI/testing/sysfs-devices-platform-armchina-npu | 13 +++++++++++++
 1 file changed, 13 insertions(+)
 create mode 100644 Documentation/ABI/testing/sysfs-devices-platform-armchina-npu

diff --git a/Documentation/ABI/testing/sysfs-devices-platform-armchina-npu b/Documentation/ABI/testing/sysfs-devices-platform-armchina-npu
new file mode 100644
index 000000000000..185819e0010c
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-devices-platform-armchina-npu
@@ -0,0 +1,13 @@
+What:           /sys/devices/platform/aipu<n>/disable
+Date:           December 2021
+KernelVersion:  5.16
+Contact:        Dejia Shang <dejia.shang@armchina.com>
+Description:
+                (RW) Read/Set the enable/disable status of the current Zhouyi NPU core
+
+What:           /sys/devices/platform/aipu<n>/ext_registers
+Date:           December 2021
+KernelVersion:  5.16
+Contact:        Dejia Shang <dejia.shang@armchina.com>
+Description:
+                (RO) List of Zhouyi NPU external registers and current values inside
--
2.17.1

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[PATCH 3/4] dt-bindings: add vendor-prefix and documentation for Zhouyi NPU

[Dejia Shang]

To enable this NPU IP in Arm-Linux system, SoC vendors should
write devicetree files as documented.

Signed-off-by: Dejia Shang <dejia.shang@armchina.com>
---
 .../bindings/misc/armchina,zhouyi-npu.yaml    | 57 +++++++++++++++++++
 .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
 2 files changed, 59 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml

diff --git a/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
new file mode 100644
index 000000000000..d3fdea101114
--- /dev/null
+++ b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/misc/armchina,zhouyi-npu.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: ArmChina Zhouyi NPU bindings
+
+maintainers:
+  - Dejia Shang <dejia.shang@armchina.com>
+
+description: |
+  Armchina AI accelerator IP - Zhouyi NPU
+
+properties:
+  compatible:
+    items:
+      - const: armchina,zhouyi-v1
+      - const: armchina,zhouyi-v2
+      - const: armchina,zhouyi
+
+  reg:
+    maxItems: 1
+
+  memory-region:
+    maxItems: 2
+
+  interrupts:
+    maxItems: 1
+
+required:
+  - compatible
+  - reg
+  - interrupts
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+    reserved-memory {
+                #address-cells = <2>;
+                #size-cells = <2>;
+                ranges;
+
+                aipu_ddr_reserved: aipu-shmem@0xA0000000 {
+                        compatible = "shared-dma-pool";
+                        no-map;
+                        reg = <0x0 0xA0000000 0x0 0x4000000>;
+                };
+    };
+
+    aipu0@0x64000000 {
+                compatible = "armchina,zhouyi";
+                reg = <0x0 0x64000000 0x0 0x1000>;
+                memory-region=<&aipu_ddr_reserved>;
+                interrupts = <0 168 1>;
+    };
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 66d6432fd781..4b1865d92455 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -123,6 +123,8 @@ patternProperties:
     description: ARM Ltd.
   "^armadeus,.*":
     description: ARMadeus Systems SARL
+  "^armchina,.*":
+    description: Arm Technology (China) Co., Ltd.
   "^arrow,.*":
     description: Arrow Electronics
   "^artesyn,.*":
--
2.17.1

IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

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[PATCH 4/4] MAINTAINERS: add maintainer info. for Zhouyi NPU

[Dejia Shang]

Zhouyi NPU IP and its SDK/driver are designed and maintained by
Arm Technology (China), i.e. ArmChina.

Signed-off-by: Dejia Shang <dejia.shang@armchina.com>
---
 MAINTAINERS | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5f040a502859..7bb01176e169 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1827,6 +1827,16 @@ L:       linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
 S:     Supported
 F:     drivers/net/ethernet/cavium/thunder/

+ARMCHINA NPU DRIVER
+M:     Dejia Shang <dejia.shang@armchina.com>
+M:     Toby Huang <toby.huang@armchina.com>
+L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+S:     Maintained
+F:     Documentation/ABI/testing/sysfs-devices-platform-armchina-npu
+F:     Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
+F:     drivers/misc/armchina-npu/
+F:     include/uapi/misc/armchina-aipu.h
+
 ARM/CIRRUS LOGIC BK3 MACHINE SUPPORT
 M:     Lukasz Majewski <lukma@denx.de>
 L:     linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.17.1

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Re: [PATCH 1/4] misc: add ArmChina Zhouyi NPU driver

[Greg KH]

On Wed, Dec 15, 2021 at 06:36:06PM +0800, Dejia Shang wrote:
> IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

Now deleted.

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Re: [PATCH 0/4] misc: add ArmChina Zhouyi NPU driver

[Greg KH]

On Wed, Dec 15, 2021 at 06:36:05PM +0800, Dejia Shang wrote:
> IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

Now deleted.

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Re: [PATCH 2/4] Documentation: add sysfs entries for Zhouyi NPU

[Greg KH]

On Wed, Dec 15, 2021 at 06:36:07PM +0800, Dejia Shang wrote:
> IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

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Re: [PATCH 3/4] dt-bindings: add vendor-prefix and documentation for Zhouyi NPU

[Greg KH]

On Wed, Dec 15, 2021 at 06:36:08PM +0800, Dejia Shang wrote:
> IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

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Re: [PATCH 4/4] MAINTAINERS: add maintainer info. for Zhouyi NPU

[Greg KH]

On Wed, Dec 15, 2021 at 06:36:09PM +0800, Dejia Shang wrote:
> IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

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Re: [PATCH 3/4] dt-bindings: add vendor-prefix and documentation for Zhouyi NPU

[Rob Herring]

On Wed, Dec 15, 2021 at 06:36:08PM +0800, Dejia Shang wrote:
> To enable this NPU IP in Arm-Linux system, SoC vendors should
> write devicetree files as documented.
> 
> Signed-off-by: Dejia Shang <dejia.shang@armchina.com>
> ---
>  .../bindings/misc/armchina,zhouyi-npu.yaml    | 57 +++++++++++++++++++
>  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
>  2 files changed, 59 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
> 
> diff --git a/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
> new file mode 100644
> index 000000000000..d3fdea101114
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/misc/armchina,zhouyi-npu.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: ArmChina Zhouyi NPU bindings
> +
> +maintainers:
> +  - Dejia Shang <dejia.shang@armchina.com>
> +
> +description: |
> +  Armchina AI accelerator IP - Zhouyi NPU
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: armchina,zhouyi-v1
> +      - const: armchina,zhouyi-v2
> +      - const: armchina,zhouyi

This says compatible must be a list of all 3 of these.

Where do v1 and v2 come from? We don't do version numbers in DT usually 
unless they correspond to h/w revision registers or h/w documentation. I 
would assume the h/w follows the Arm rXpY form?

> +
> +  reg:
> +    maxItems: 1
> +
> +  memory-region:
> +    maxItems: 2

What is each region?

This requires 2 entries, but the example only has 1.

> +
> +  interrupts:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +    reserved-memory {
> +                #address-cells = <2>;
> +                #size-cells = <2>;
> +                ranges;
> +
> +                aipu_ddr_reserved: aipu-shmem@0xA0000000 {

aipu-shmem@a0000000

> +                        compatible = "shared-dma-pool";
> +                        no-map;
> +                        reg = <0x0 0xA0000000 0x0 0x4000000>;
> +                };
> +    };
> +
> +    aipu0@0x64000000 {

Drop '0x'

> +                compatible = "armchina,zhouyi";
> +                reg = <0x0 0x64000000 0x0 0x1000>;
> +                memory-region=<&aipu_ddr_reserved>;
> +                interrupts = <0 168 1>;
> +    };
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index 66d6432fd781..4b1865d92455 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -123,6 +123,8 @@ patternProperties:
>      description: ARM Ltd.
>    "^armadeus,.*":
>      description: ARMadeus Systems SARL
> +  "^armchina,.*":
> +    description: Arm Technology (China) Co., Ltd.
>    "^arrow,.*":
>      description: Arrow Electronics
>    "^artesyn,.*":
> --
> 2.17.1
> 
> IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。
> 

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Re: [PATCH 3/4] dt-bindings: add vendor-prefix and documentation for Zhouyi NPU

[Dejia Shang]

> On Wed, Dec 15, 2021 at 06:36:08PM +0800, Dejia Shang wrote:
> > To enable this NPU IP in Arm-Linux system, SoC vendors should write
> > devicetree files as documented.
> >
> > Signed-off-by: Dejia Shang <dejia.shang@armchina.com>
> > ---
> >  .../bindings/misc/armchina,zhouyi-npu.yaml    | 57 +++++++++++++++++++
> >  .../devicetree/bindings/vendor-prefixes.yaml  |  2 +
> >  2 files changed, 59 insertions(+)
> >  create mode 100644
> > Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
> > b/Documentation/devicetree/bindings/misc/armchina,zhouyi-npu.yaml
> > new file mode 100644
> > index 000000000000..d3fdea101114
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/misc/armchina,zhouyi-
> npu.yaml
> > @@ -0,0 +1,57 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id: "http://devicetree.org/schemas/misc/armchina,zhouyi-npu.yaml#"
> > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> > +
> > +title: ArmChina Zhouyi NPU bindings
> > +
> > +maintainers:
> > +  - Dejia Shang <dejia.shang@armchina.com>
> > +
> > +description: |
> > +  Armchina AI accelerator IP - Zhouyi NPU
> > +
> > +properties:
> > +  compatible:
> > +    items:
> > +      - const: armchina,zhouyi-v1
> > +      - const: armchina,zhouyi-v2
> > +      - const: armchina,zhouyi
>
> This says compatible must be a list of all 3 of these.
>
> Where do v1 and v2 come from? We don't do version numbers in DT usually
> unless they correspond to h/w revision registers or h/w documentation. I
> would assume the h/w follows the Arm rXpY form?
>

Yes, the Zhouyi NPU h/w follows the Arm rXpY form but "zhouyi-v1" (z1) and "zhouyi-v2" (z2)
represent two generations of Zhouyi. They have different h/w architecture, revision registers
and documentation.

I think I can remove "armchina,zhouyi-v1" and "armchina,zhouyi-v2" because the driver does not
depend on them to tell the NPU arch.

> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  memory-region:
> > +    maxItems: 2
>
> What is each region?
>
> This requires 2 entries, but the example only has 1.
>

They are reserved regions in DDR and SoC SRAM, and the latter one is optional for a SoC.
Should I also add the second one into the example?

> > +
> > +  interrupts:
> > +    maxItems: 1
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupts
> > +
> > +examples:
> > +  - |
> > +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> > +
> > +    reserved-memory {
> > +                #address-cells = <2>;
> > +                #size-cells = <2>;
> > +                ranges;
> > +
> > +                aipu_ddr_reserved: aipu-shmem@0xA0000000 {
>
> aipu-shmem@a0000000

I will fix that.

>
> > +                        compatible = "shared-dma-pool";
> > +                        no-map;
> > +                        reg = <0x0 0xA0000000 0x0 0x4000000>;
> > +                };
> > +    };
> > +
> > +    aipu0@0x64000000 {
>
> Drop '0x'

I will fix that.

>
> > +                compatible = "armchina,zhouyi";
> > +                reg = <0x0 0x64000000 0x0 0x1000>;
> > +                memory-region=<&aipu_ddr_reserved>;
> > +                interrupts = <0 168 1>;
> > +    };
> > diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > index 66d6432fd781..4b1865d92455 100644
> > --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> > @@ -123,6 +123,8 @@ patternProperties:
> >      description: ARM Ltd.
> >    "^armadeus,.*":
> >      description: ARMadeus Systems SARL
> > +  "^armchina,.*":
> > +    description: Arm Technology (China) Co., Ltd.
> >    "^arrow,.*":
> >      description: Arrow Electronics
> >    "^artesyn,.*":
> > --
> > 2.17.1
> >

IMPORTANT NOTICE: The contents of this email and any attachments may be privileged and confidential. If you are not the intended recipient, please delete the email immediately. It is strictly prohibited to disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you. ©Arm Technology (China) Co., Ltd copyright and reserve all rights. 重要提示：本邮件（包括任何附件）可能含有专供明确的个人或目的使用的机密信息，并受法律保护。如果您并非该收件人，请立即删除此邮件。严禁通过任何渠道，以任何目的，向任何人披露、储存或复制邮件信息或者据此采取任何行动。感谢您的配合。 ©安谋科技（中国）有限公司 版权所有并保留一切权利。

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