From: Rob Herring <robh@kernel.org>
To: Aradhya Bhatia <a-bhatia1@ti.com>
Cc: Jyri Sarha <jyri.sarha@iki.fi>, Tomi Valkeinen <tomba@kernel.org>,
Vignesh Raghavendra <vigneshr@ti.com>, Nishanth Menon <nm@ti.com>,
DRI Development <dri-devel@lists.freedesktop.org>,
Devicetree <devicetree@vger.kernel.org>,
Linux ARM Kernel <linux-arm-kernel@lists.infradead.org>,
Linux Kernel <linux-kernel@vger.kernel.org>,
Nikhil Devshatwar <nikhil.nd@ti.com>
Subject: Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
Date: Tue, 19 Apr 2022 09:20:02 -0500 [thread overview]
Message-ID: <Yl7FEuHEy66KUc5F@robh.at.kernel.org> (raw)
In-Reply-To: <20220419070302.16502-2-a-bhatia1@ti.com>
On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
You've just broken the ABI.
New entries have to go on the end.
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
Once there is more than 1, we need to know what each entry is and the
order.
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
>
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next prev parent reply other threads:[~2022-04-19 15:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-19 7:03 [PATCH 0/2] Update register & interrupt info in am65x DSS Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti, am65x-dss: Add missing register & interrupt Aradhya Bhatia
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:40 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: " Nishanth Menon
2022-04-19 14:20 ` Rob Herring [this message]
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 21:30 ` Rob Herring
2022-04-19 7:03 ` [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Aradhya Bhatia
2022-04-19 12:06 ` [PATCH 0/2] Update register & interrupt info in am65x DSS Tomi Valkeinen
2022-04-19 17:29 ` Aradhya Bhatia
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