From: Jon Hunter <jonathanh@nvidia.com>
To: Robin Murphy <robin.murphy@arm.com>,
Jose Abreu <Jose.Abreu@synopsys.com>,
Lars Persson <lists@bofh.nu>,
Ilias Apalodimas <ilias.apalodimas@linaro.org>
Cc: Joao Pinto <Joao.Pinto@synopsys.com>,
Alexandre Torgue <alexandre.torgue@st.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
"netdev@vger.kernel.org" <netdev@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"David S . Miller" <davem@davemloft.net>,
Chen-Yu Tsai <wens@csie.org>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
linux-tegra <linux-tegra@vger.kernel.org>,
Giuseppe Cavallaro <peppe.cavallaro@st.com>,
"linux-stm32@st-md-mailman.stormreply.com"
<linux-stm32@st-md-mailman.stormreply.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool
Date: Tue, 23 Jul 2019 22:39:29 +0100 [thread overview]
Message-ID: <ae11deb4-abec-f0f9-312d-b11d72bc74cd@nvidia.com> (raw)
In-Reply-To: <3255edfa-4465-204b-4751-8d40c8fb1382@arm.com>
On 23/07/2019 14:19, Robin Murphy wrote:
...
>>> Do you know if the SMMU interrupts are working correctly? If not, it's
>>> possible that an incorrect address or mapping direction could lead to
>>> the DMA transaction just being silently terminated without any fault
>>> indication, which generally presents as inexplicable weirdness (I've
>>> certainly seen that on another platform with the mix of an unsupported
>>> interrupt controller and an 'imperfect' ethernet driver).
>>
>> If I simply remove the iommu node for the ethernet controller, then I
>> see lots of ...
>>
>> [ 6.296121] arm-smmu 12000000.iommu: Unexpected global fault, this
>> could be serious
>> [ 6.296125] arm-smmu 12000000.iommu: GFSR 0x00000002,
>> GFSYNR0 0x00000000, GFSYNR1 0x00000014, GFSYNR2 0x00000000
>>
>> So I assume that this is triggering the SMMU interrupt correctly.
>
> According to tegra186.dtsi it appears you're using the MMU-500 combined
> interrupt, so if global faults are being delivered then context faults
> *should* also, but I'd be inclined to try a quick hack of the relevant
> stmmac_desc_ops::set_addr callback to write some bogus unmapped address
> just to make sure arm_smmu_context_fault() then screams as expected, and
> we're not missing anything else.
I hacked the driver and forced the address to zero for a test and
in doing so I see ...
[ 10.440072] arm-smmu 12000000.iommu: Unhandled context fault: fsr=0x402, iova=0x00000000, fsynr=0x1c0011, cbfrsynra=0x14, cb=0
So looks like the interrupts are working AFAICT.
Cheers
Jon
--
nvpublic
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next prev parent reply other threads:[~2019-07-23 21:39 UTC|newest]
Thread overview: 86+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-03 10:37 [PATCH net-next 0/3] net: stmmac: Some performance improvements and a fix Jose Abreu
2019-07-03 10:37 ` [PATCH net-next 1/3] net: stmmac: Implement RX Coalesce Frames setting Jose Abreu
2019-07-03 20:41 ` Jakub Kicinski
2019-07-03 10:37 ` [PATCH net-next 2/3] net: stmmac: Fix descriptors address being in > 32 bits address space Jose Abreu
2019-07-03 10:37 ` [PATCH net-next 3/3] net: stmmac: Introducing support for Page Pool Jose Abreu
2019-07-03 10:40 ` Jose Abreu
2019-07-04 9:39 ` Jesper Dangaard Brouer
2019-07-04 14:45 ` Jose Abreu
2019-07-04 15:09 ` Jesper Dangaard Brouer
2019-07-04 15:18 ` Jose Abreu
2019-07-04 15:33 ` Jesper Dangaard Brouer
2019-07-04 9:48 ` Jesper Dangaard Brouer
2019-07-04 10:00 ` Jesper Dangaard Brouer
2019-07-04 10:13 ` Jose Abreu
2019-07-04 11:11 ` Ilias Apalodimas
2019-07-04 11:54 ` Jesper Dangaard Brouer
2019-07-04 12:04 ` Ilias Apalodimas
2019-07-04 12:59 ` Jose Abreu
2019-07-04 13:06 ` Ilias Apalodimas
2019-07-04 10:30 ` Ilias Apalodimas
2019-07-04 12:14 ` Arnd Bergmann
2019-07-04 12:49 ` Ilias Apalodimas
2019-07-17 18:58 ` Jon Hunter
2019-07-18 7:29 ` Jose Abreu
2019-07-18 7:48 ` Jose Abreu
2019-07-18 9:16 ` Jon Hunter
2019-07-19 7:51 ` Jose Abreu
2019-07-19 8:37 ` Jon Hunter
2019-07-19 8:44 ` Jose Abreu
2019-07-19 8:49 ` Jon Hunter
2019-07-19 10:25 ` Jose Abreu
2019-07-19 12:28 ` Jose Abreu
2019-07-19 13:33 ` Jon Hunter
2019-07-19 12:30 ` Jon Hunter
2019-07-19 12:32 ` Jose Abreu
[not found] ` <25512348-5b98-aeb7-a6fb-f90376e66a84@nvidia.com>
2019-07-22 7:23 ` Jose Abreu
2019-07-22 9:37 ` Jon Hunter
2019-07-22 9:47 ` Jose Abreu
2019-07-22 9:57 ` Jose Abreu
2019-07-22 10:27 ` Jon Hunter
2019-07-22 10:18 ` Ilias Apalodimas
2019-07-22 11:11 ` Lars Persson
2019-07-22 11:39 ` Jose Abreu
2019-07-22 12:05 ` Jon Hunter
2019-07-22 14:04 ` Jose Abreu
2019-07-23 8:14 ` Jose Abreu
2019-07-23 10:01 ` Jon Hunter
2019-07-23 10:07 ` Jose Abreu
2019-07-23 10:29 ` Robin Murphy
2019-07-23 11:22 ` Jose Abreu
2019-07-23 12:09 ` Jon Hunter
2019-07-23 13:19 ` Robin Murphy
2019-07-23 21:39 ` Jon Hunter [this message]
2019-07-24 10:03 ` Robin Murphy
2019-07-23 18:51 ` David Miller
2019-07-24 8:54 ` Ilias Apalodimas
2019-07-24 9:43 ` Jose Abreu
2019-07-24 9:53 ` Ilias Apalodimas
2019-07-24 10:04 ` Jose Abreu
2019-07-24 11:10 ` Jon Hunter
2019-07-24 11:34 ` Jose Abreu
2019-07-24 11:58 ` Jon Hunter
2019-07-25 7:44 ` Jose Abreu
2019-07-25 9:45 ` Jon Hunter
2019-07-25 11:39 ` Ilias Apalodimas
2019-07-23 10:38 ` Jon Hunter
2019-07-23 10:49 ` Jose Abreu
2019-07-23 11:58 ` Jon Hunter
2019-07-23 12:51 ` Jose Abreu
2019-07-23 13:34 ` Jon Hunter
2019-07-29 9:45 ` Mikko Perttunen
2019-07-25 13:20 ` Jon Hunter
2019-07-25 13:26 ` Jose Abreu
2019-07-25 14:25 ` Jon Hunter
2019-07-25 15:12 ` Jose Abreu
2019-07-26 14:11 ` Jon Hunter
2019-07-27 15:56 ` Jose Abreu
2019-07-29 8:16 ` Jose Abreu
2019-07-29 10:55 ` Jon Hunter
2019-07-29 11:29 ` Jose Abreu
2019-07-29 11:52 ` Robin Murphy
2019-07-29 14:08 ` Jose Abreu
2019-07-29 21:33 ` Jon Hunter
2019-07-30 9:39 ` Jose Abreu
2019-07-30 13:36 ` Jon Hunter
2019-07-30 13:58 ` Jose Abreu
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