* [PATCH 2/2] arm64: dts: imx8mn: specify dma-ranges
2021-05-04 8:20 [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges Lucas Stach
@ 2021-05-04 8:20 ` Lucas Stach
2021-05-04 9:06 ` Frieder Schrempf
2021-05-04 9:05 ` [PATCH 1/2] arm64: dts: imx8mm: " Frieder Schrempf
` (2 subsequent siblings)
3 siblings, 1 reply; 8+ messages in thread
From: Lucas Stach @ 2021-05-04 8:20 UTC (permalink / raw)
To: Shawn Guo
Cc: NXP Linux Team, linux-arm-kernel, Fabio Estevam,
Frieder Schrempf, kernel, patchwork-lst
DMA addressing capabilities on i.MX8MN are limited by the interconnect,
same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
the kernel know about this.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
index 16ea50089567..256e1dfb5db3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
@@ -245,6 +245,7 @@ soc@0 {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x0 0x0 0x3e000000>;
+ dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
nvmem-cells = <&imx8mn_uid>;
nvmem-cell-names = "soc_unique_id";
--
2.29.2
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] arm64: dts: imx8mn: specify dma-ranges
2021-05-04 8:20 ` [PATCH 2/2] arm64: dts: imx8mn: " Lucas Stach
@ 2021-05-04 9:06 ` Frieder Schrempf
0 siblings, 0 replies; 8+ messages in thread
From: Frieder Schrempf @ 2021-05-04 9:06 UTC (permalink / raw)
To: Lucas Stach, Shawn Guo
Cc: NXP Linux Team, linux-arm-kernel, Fabio Estevam, kernel, patchwork-lst
On 04.05.21 10:20, Lucas Stach wrote:
> DMA addressing capabilities on i.MX8MN are limited by the interconnect,
> same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> the kernel know about this.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mn.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> index 16ea50089567..256e1dfb5db3 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi
> @@ -245,6 +245,7 @@ soc@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x0 0x0 0x3e000000>;
> + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> nvmem-cells = <&imx8mn_uid>;
> nvmem-cell-names = "soc_unique_id";
>
>
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges
2021-05-04 8:20 [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges Lucas Stach
2021-05-04 8:20 ` [PATCH 2/2] arm64: dts: imx8mn: " Lucas Stach
@ 2021-05-04 9:05 ` Frieder Schrempf
2021-05-05 11:36 ` Adam Ford
2021-05-23 2:32 ` Shawn Guo
3 siblings, 0 replies; 8+ messages in thread
From: Frieder Schrempf @ 2021-05-04 9:05 UTC (permalink / raw)
To: Lucas Stach, Shawn Guo
Cc: NXP Linux Team, linux-arm-kernel, Fabio Estevam, kernel, patchwork-lst
On 04.05.21 10:20, Lucas Stach wrote:
> DMA addressing capabilities on i.MX8MM are limited by the interconnect,
> same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> the kernel know about this.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de>
With this applied the following errors don't occur anymore when using
the GPU with a board that has 4GB of RAM.
etnaviv-gpu 38000000.gpu: AXI bus error
etnaviv-gpu 38000000.gpu: MMU fault status 0x00000000
etnaviv-gpu 38000000.gpu: recover hung GPU!
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 6bf1d15ba16a..5bdc730f6132 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -261,6 +261,7 @@ soc@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x0 0x0 0x3e000000>;
> + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> nvmem-cells = <&imx8mm_uid>;
> nvmem-cell-names = "soc_unique_id";
>
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges
2021-05-04 8:20 [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges Lucas Stach
2021-05-04 8:20 ` [PATCH 2/2] arm64: dts: imx8mn: " Lucas Stach
2021-05-04 9:05 ` [PATCH 1/2] arm64: dts: imx8mm: " Frieder Schrempf
@ 2021-05-05 11:36 ` Adam Ford
2021-05-05 11:54 ` Lucas Stach
2021-05-23 2:32 ` Shawn Guo
3 siblings, 1 reply; 8+ messages in thread
From: Adam Ford @ 2021-05-05 11:36 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, NXP Linux Team, arm-soc, Fabio Estevam,
Frieder Schrempf, Sascha Hauer, patchwork-lst
On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> DMA addressing capabilities on i.MX8MM are limited by the interconnect,
> same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> the kernel know about this.
Can you point me to the section of the reference manual where this is
found? I'm guessing a similar thing would be applicable to the 8M
Nano as well, but I want to understand first.
thanks
adam
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> index 6bf1d15ba16a..5bdc730f6132 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> @@ -261,6 +261,7 @@ soc@0 {
> #address-cells = <1>;
> #size-cells = <1>;
> ranges = <0x0 0x0 0x0 0x3e000000>;
> + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> nvmem-cells = <&imx8mm_uid>;
> nvmem-cell-names = "soc_unique_id";
>
> --
> 2.29.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
_______________________________________________
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges
2021-05-05 11:36 ` Adam Ford
@ 2021-05-05 11:54 ` Lucas Stach
2021-05-05 12:08 ` Adam Ford
0 siblings, 1 reply; 8+ messages in thread
From: Lucas Stach @ 2021-05-05 11:54 UTC (permalink / raw)
To: Adam Ford
Cc: Shawn Guo, Frieder Schrempf, patchwork-lst, NXP Linux Team,
Sascha Hauer, Fabio Estevam, arm-soc
Am Mittwoch, dem 05.05.2021 um 06:36 -0500 schrieb Adam Ford:
> On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach@pengutronix.de> wrote:
> >
> > DMA addressing capabilities on i.MX8MM are limited by the interconnect,
> > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> > the kernel know about this.
>
> Can you point me to the section of the reference manual where this is
> found? I'm guessing a similar thing would be applicable to the 8M
> Nano as well, but I want to understand first.
The second patch in this series already fixes up the 8MN DT.
The relevant part of the RM is section 2.1.2 (Cortex-A53 memory map)
where you can see that the DDR above the 4GB mark is only accessible to
the A53 cluster, other DMA masters only have access to the 3GB located
below the 4GB mark.
Regards,
Lucas
> thanks
>
> adam
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > index 6bf1d15ba16a..5bdc730f6132 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > @@ -261,6 +261,7 @@ soc@0 {
> > #address-cells = <1>;
> > #size-cells = <1>;
> > ranges = <0x0 0x0 0x0 0x3e000000>;
> > + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> > nvmem-cells = <&imx8mm_uid>;
> > nvmem-cell-names = "soc_unique_id";
> >
> > --
> > 2.29.2
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges
2021-05-05 11:54 ` Lucas Stach
@ 2021-05-05 12:08 ` Adam Ford
0 siblings, 0 replies; 8+ messages in thread
From: Adam Ford @ 2021-05-05 12:08 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Frieder Schrempf, patchwork-lst, NXP Linux Team,
Sascha Hauer, Fabio Estevam, arm-soc
On Wed, May 5, 2021 at 6:54 AM Lucas Stach <l.stach@pengutronix.de> wrote:
>
> Am Mittwoch, dem 05.05.2021 um 06:36 -0500 schrieb Adam Ford:
> > On Tue, May 4, 2021 at 3:21 AM Lucas Stach <l.stach@pengutronix.de> wrote:
> > >
> > > DMA addressing capabilities on i.MX8MM are limited by the interconnect,
> > > same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> > > the kernel know about this.
> >
> > Can you point me to the section of the reference manual where this is
> > found? I'm guessing a similar thing would be applicable to the 8M
> > Nano as well, but I want to understand first.
>
> The second patch in this series already fixes up the 8MN DT.
Thanks, I didn't even notice there was a 2/2 patch. My mistake.
Sorry for the noise.
>
> The relevant part of the RM is section 2.1.2 (Cortex-A53 memory map)
> where you can see that the DDR above the 4GB mark is only accessible to
> the A53 cluster, other DMA masters only have access to the 3GB located
> below the 4GB mark.
Thanks for the clarification.
adam
>
> Regards,
> Lucas
>
> > thanks
> >
> > adam
> > >
> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mm.dtsi | 1 +
> > > 1 file changed, 1 insertion(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > index 6bf1d15ba16a..5bdc730f6132 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
> > > @@ -261,6 +261,7 @@ soc@0 {
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > > ranges = <0x0 0x0 0x0 0x3e000000>;
> > > + dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
> > > nvmem-cells = <&imx8mm_uid>;
> > > nvmem-cell-names = "soc_unique_id";
> > >
> > > --
> > > 2.29.2
> > >
> > >
> > > _______________________________________________
> > > linux-arm-kernel mailing list
> > > linux-arm-kernel@lists.infradead.org
> > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> >
>
>
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linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges
2021-05-04 8:20 [PATCH 1/2] arm64: dts: imx8mm: specify dma-ranges Lucas Stach
` (2 preceding siblings ...)
2021-05-05 11:36 ` Adam Ford
@ 2021-05-23 2:32 ` Shawn Guo
3 siblings, 0 replies; 8+ messages in thread
From: Shawn Guo @ 2021-05-23 2:32 UTC (permalink / raw)
To: Lucas Stach
Cc: NXP Linux Team, linux-arm-kernel, Fabio Estevam,
Frieder Schrempf, kernel, patchwork-lst
On Tue, May 04, 2021 at 10:20:51AM +0200, Lucas Stach wrote:
> DMA addressing capabilities on i.MX8MM are limited by the interconnect,
> same as on i.MX8MQ. Add dma-ranges to the the peripheral bus to let
> the kernel know about this.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Applied both, thanks.
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^ permalink raw reply [flat|nested] 8+ messages in thread