[PATCH 1/3] ARM: dts: NSP: Disable PL330 by default, add dma-coherent property

[PATCH 1/3] ARM: dts: NSP: Disable PL330 by default, add dma-coherent property

[Matthew Hagan]

Currently the PL330 is enabled by default. However if left in IDM reset, as is
the case with the Meraki and Synology NSP devices, the system will hang when
probing for the PL330's AMBA peripheral ID. We therefore should be able to
disable it in these cases.

The PL330 is also included among of the list of peripherals put into coherent
mode, so "dma-coherent" has been added here as well.

Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi     | 4 +++-
 arch/arm/boot/dts/bcm958522er.dts  | 4 ++++
 arch/arm/boot/dts/bcm958525er.dts  | 4 ++++
 arch/arm/boot/dts/bcm958525xmc.dts | 4 ++++
 arch/arm/boot/dts/bcm958622hr.dts  | 4 ++++
 arch/arm/boot/dts/bcm958623hr.dts  | 4 ++++
 arch/arm/boot/dts/bcm958625hr.dts  | 4 ++++
 arch/arm/boot/dts/bcm958625k.dts   | 4 ++++
 8 files changed, 31 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index da6d70f09ef1..920c0f561e5c 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -200,7 +200,7 @@ uart1: serial@400 {
 			status = "disabled";
 		};
 
-		dma@20000 {
+		dma: dma@20000 {
 			compatible = "arm,pl330", "arm,primecell";
 			reg = <0x20000 0x1000>;
 			interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
@@ -215,6 +215,8 @@ dma@20000 {
 			clocks = <&iprocslow>;
 			clock-names = "apb_pclk";
 			#dma-cells = <1>;
+			dma-coherent;
+			status = "disabled";
 		};
 
 		sdio: sdhci@21000 {
diff --git a/arch/arm/boot/dts/bcm958522er.dts b/arch/arm/boot/dts/bcm958522er.dts
index 8c388eb8a08f..7be4c4e628e0 100644
--- a/arch/arm/boot/dts/bcm958522er.dts
+++ b/arch/arm/boot/dts/bcm958522er.dts
@@ -58,6 +58,10 @@ gpio-restart {
 
 /* USB 3 support needed to be complete */
 
+&dma {
+	status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958525er.dts b/arch/arm/boot/dts/bcm958525er.dts
index c339771bb22e..515164dacc4d 100644
--- a/arch/arm/boot/dts/bcm958525er.dts
+++ b/arch/arm/boot/dts/bcm958525er.dts
@@ -58,6 +58,10 @@ gpio-restart {
 
 /* USB 3 support needed to be complete */
 
+&dma {
+        status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958525xmc.dts b/arch/arm/boot/dts/bcm958525xmc.dts
index 1c72ec8288de..09092bbd7b63 100644
--- a/arch/arm/boot/dts/bcm958525xmc.dts
+++ b/arch/arm/boot/dts/bcm958525xmc.dts
@@ -58,6 +58,10 @@ gpio-restart {
 
 /* XHCI support needed to be complete */
 
+&dma {
+        status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958622hr.dts b/arch/arm/boot/dts/bcm958622hr.dts
index 96a021cebd97..3c46f5003401 100644
--- a/arch/arm/boot/dts/bcm958622hr.dts
+++ b/arch/arm/boot/dts/bcm958622hr.dts
@@ -58,6 +58,10 @@ gpio-restart {
 
 /* USB 3 and SLIC support needed to be complete */
 
+&dma {
+        status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958623hr.dts b/arch/arm/boot/dts/bcm958623hr.dts
index b2c7f21d471e..6e5c580defe5 100644
--- a/arch/arm/boot/dts/bcm958623hr.dts
+++ b/arch/arm/boot/dts/bcm958623hr.dts
@@ -58,6 +58,10 @@ gpio-restart {
 
 /* USB 3 and SLIC support needed to be complete */
 
+&dma {
+        status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958625hr.dts b/arch/arm/boot/dts/bcm958625hr.dts
index 536fb24f38bb..0509c57a8366 100644
--- a/arch/arm/boot/dts/bcm958625hr.dts
+++ b/arch/arm/boot/dts/bcm958625hr.dts
@@ -69,6 +69,10 @@ &i2c0 {
 	status = "okay";
 };
 
+&dma {
+        status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
diff --git a/arch/arm/boot/dts/bcm958625k.dts b/arch/arm/boot/dts/bcm958625k.dts
index 3fcca12d83c2..1557491c1751 100644
--- a/arch/arm/boot/dts/bcm958625k.dts
+++ b/arch/arm/boot/dts/bcm958625k.dts
@@ -48,6 +48,10 @@ memory@60000000 {
 	};
 };
 
+&dma {
+        status = "okay";
+};
+
 &amac0 {
 	status = "okay";
 };
-- 
2.25.4


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[PATCH 2/3] ARM: dts: NSP: Correct amac_base lengths, mailbox reg and add amac3

[Matthew Hagan]

According to gmac/src/et/sys/et_linux.c, IORESOURCE_MEM end address for each
mac is IPROC_GMACx_REG_BASE+0xbff.

The FA2 mailbox is specified at 0x18025000 but should actually be 0x18025c00,
length 0x400 according to socregs_nsp.h and board_bu.c. amac3 is at 25000.

Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
 arch/arm/boot/dts/bcm-nsp.dtsi | 23 +++++++++++++++++------
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 920c0f561e5c..512720f39e04 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -47,6 +47,7 @@ aliases {
 		ethernet0 = &amac0;
 		ethernet1 = &amac1;
 		ethernet2 = &amac2;
+		ethernet3 = &amac3;
 	};
 
 	cpus {
@@ -231,7 +232,7 @@ sdio: sdhci@21000 {
 
 		amac0: ethernet@22000 {
 			compatible = "brcm,nsp-amac";
-			reg = <0x022000 0x1000>,
+			reg = <0x022000 0x0c00>,
 			      <0x110000 0x1000>;
 			reg-names = "amac_base", "idm_base";
 			interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
@@ -241,7 +242,7 @@ amac0: ethernet@22000 {
 
 		amac1: ethernet@23000 {
 			compatible = "brcm,nsp-amac";
-			reg = <0x023000 0x1000>,
+			reg = <0x023000 0x0c00>,
 			      <0x111000 0x1000>;
 			reg-names = "amac_base", "idm_base";
 			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
@@ -251,7 +252,7 @@ amac1: ethernet@23000 {
 
 		amac2: ethernet@24000 {
 			compatible = "brcm,nsp-amac";
-			reg = <0x024000 0x1000>,
+			reg = <0x024000 0x0c00>,
 			      <0x112000 0x1000>;
 			reg-names = "amac_base", "idm_base";
 			interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
@@ -259,10 +260,20 @@ amac2: ethernet@24000 {
 			status = "disabled";
 		};
 
-		mailbox: mailbox@25000 {
-			compatible = "brcm,iproc-fa2-mbox";
-			reg = <0x25000 0x445>;
+		amac3: ethernet@25000 {
+			compatible = "brcm,nsp-amac";
+			reg = <0x025000 0x0c00>,
+			      <0x113000 0x1000>;
+			reg-names = "amac_base", "idm_base";
 			interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			dma-coherent;
+			status = "disabled";
+		};
+
+		mailbox: mailbox@25c00 {
+			compatible = "brcm,iproc-fa2-mbox";
+			reg = <0x25c00 0x400>;
+			interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
 			#mbox-cells = <1>;
 			brcm,rx-status-len = <32>;
 			brcm,use-bcm-hdr;
-- 
2.25.4


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[PATCH 3/3] ARM: bcm: Select ARM_TIMER_SP804 for ARCH_BCM_NSP

[Matthew Hagan]

The NSP SoC includes an SP804 timer so should be enabled here.

Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
---
 arch/arm/mach-bcm/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 6aa938b949db..1df0ee01ee02 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -53,6 +53,7 @@ config ARCH_BCM_NSP
 	select ARM_ERRATA_754322
 	select ARM_ERRATA_775420
 	select ARM_ERRATA_764369 if SMP
+	select ARM_TIMER_SP804
 	select THERMAL
 	select THERMAL_OF
 	help
-- 
2.25.4


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Re: [PATCH 3/3] ARM: bcm: Select ARM_TIMER_SP804 for ARCH_BCM_NSP

[Florian Fainelli]

On 6/9/2020 9:58 AM, Matthew Hagan wrote:
> The NSP SoC includes an SP804 timer so should be enabled here.
> 
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>

Applied to soc/fixes with:

Fixes: a0efb0d28b77 ("ARM: dts: NSP: Add SP804 Support to DT")

Thanks
-- 
Florian

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Re: [PATCH 1/3] ARM: dts: NSP: Disable PL330 by default, add dma-coherent property

[Florian Fainelli]

On 6/9/2020 9:58 AM, Matthew Hagan wrote:
> Currently the PL330 is enabled by default. However if left in IDM reset, as is
> the case with the Meraki and Synology NSP devices, the system will hang when
> probing for the PL330's AMBA peripheral ID. We therefore should be able to
> disable it in these cases.
> 
> The PL330 is also included among of the list of peripherals put into coherent
> mode, so "dma-coherent" has been added here as well.
> 
> Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>

Applied to devicetree/fixes with:

Fixes: 5fa1026a3e4d ("ARM: dts: NSP: Add PL330 support")

Thanks!
-- 
Florian

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Re: [PATCH 2/3] ARM: dts: NSP: Correct amac_base lengths, mailbox reg and add amac3

[Florian Fainelli]

On 6/9/2020 9:58 AM, Matthew Hagan wrote:
> According to gmac/src/et/sys/et_linux.c, IORESOURCE_MEM end address for each
> mac is IPROC_GMACx_REG_BASE+0xbff.

The datasheet shows an entire GMAC to end at 0x1000 from its base offset
which is likely what was used to construct this DTS, I do not believe
this is a functional change, and if we look at the register details, the
last register starts at 0xb44 so 0xc00 is giving a little bit of
headroom. In practice it does not change anything since you are still
going to need a full 4KB page frame to map the registers.

> 
> The FA2 mailbox is specified at 0x18025000 but should actually be 0x18025c00,
> length 0x400 according to socregs_nsp.h and board_bu.c. amac3 is at 25000.

Yes, FA2 definitively start 0x18025c00, and ends 0x400 later, so I did
split this patch in three patches:

- one that fixes the FA2 base address, which can be queued to stable
kernel branches
- one that changes the AMAC register size
- one that adds the AMAC3

Such that the first patch can be queued for -stable fixes, whereas the
other two, not being functional changes are candidates for devicetree/next.

Result here:

https://github.com/Broadcom/stblinux/commits/devicetree/next

Thanks!
-- 
Florian

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Re: [PATCH 2/3] ARM: dts: NSP: Correct amac_base lengths, mailbox reg and add amac3

[Matthew Hagan]

On 14/06/2020 23:28, Florian Fainelli wrote:
> 
> 
> On 6/9/2020 9:58 AM, Matthew Hagan wrote:
>> According to gmac/src/et/sys/et_linux.c, IORESOURCE_MEM end address for each
>> mac is IPROC_GMACx_REG_BASE+0xbff.
> 
> The datasheet shows an entire GMAC to end at 0x1000 from its base offset
> which is likely what was used to construct this DTS, I do not believe
> this is a functional change, and if we look at the register details, the
> last register starts at 0xb44 so 0xc00 is giving a little bit of
> headroom. In practice it does not change anything since you are still
> going to need a full 4KB page frame to map the registers.
> 
>>
>> The FA2 mailbox is specified at 0x18025000 but should actually be 0x18025c00,
>> length 0x400 according to socregs_nsp.h and board_bu.c. amac3 is at 25000.
> 
> Yes, FA2 definitively start 0x18025c00, and ends 0x400 later, so I did
> split this patch in three patches:
> 
> - one that fixes the FA2 base address, which can be queued to stable
> kernel branches
> - one that changes the AMAC register size
> - one that adds the AMAC3

Since AMAC3 has been added with interrupt 150, should the mailbox
interrupt not also be incremented to 151?
> 
> Such that the first patch can be queued for -stable fixes, whereas the
> other two, not being functional changes are candidates for devicetree/next.
> 
> Result here:
> 
> https://github.com/Broadcom/stblinux/commits/devicetree/next
> 
> Thanks!
> 

Thanks,
Matthew

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Re: [PATCH 2/3] ARM: dts: NSP: Correct amac_base lengths, mailbox reg and add amac3

[Florian Fainelli]

On 6/16/2020 1:19 PM, Matthew Hagan wrote:
> 
> 
> On 14/06/2020 23:28, Florian Fainelli wrote:
>>
>>
>> On 6/9/2020 9:58 AM, Matthew Hagan wrote:
>>> According to gmac/src/et/sys/et_linux.c, IORESOURCE_MEM end address for each
>>> mac is IPROC_GMACx_REG_BASE+0xbff.
>>
>> The datasheet shows an entire GMAC to end at 0x1000 from its base offset
>> which is likely what was used to construct this DTS, I do not believe
>> this is a functional change, and if we look at the register details, the
>> last register starts at 0xb44 so 0xc00 is giving a little bit of
>> headroom. In practice it does not change anything since you are still
>> going to need a full 4KB page frame to map the registers.
>>
>>>
>>> The FA2 mailbox is specified at 0x18025000 but should actually be 0x18025c00,
>>> length 0x400 according to socregs_nsp.h and board_bu.c. amac3 is at 25000.
>>
>> Yes, FA2 definitively start 0x18025c00, and ends 0x400 later, so I did
>> split this patch in three patches:
>>
>> - one that fixes the FA2 base address, which can be queued to stable
>> kernel branches
>> - one that changes the AMAC register size
>> - one that adds the AMAC3
> 
> Since AMAC3 has been added with interrupt 150, should the mailbox
> interrupt not also be incremented to 151?

Yes indeed, now corrected:

https://github.com/Broadcom/stblinux/commit/ac4e106d8934a5894811fc263f4b03fc8ed0fb7a

(have not merged it back into devicetree/next yet)
-- 
Florian

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