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From: Suzuki K Poulose <>
Subject: Re: [PATCH 2/2] arm64: Expose PARange via ID_AA64MMFR0_EL1 and VARange via ID_AA64MMFR2_EL1
Date: Tue, 29 Jan 2019 10:14:47 +0000
Message-ID: <> (raw)
In-Reply-To: <>


On 28/01/2019 20:57, Bhupesh Sharma wrote:
> ARMv8.2 architecture hardware extensions can support
> upto 52-bit physical addresses (ARMv8.2-LPA) and 52-bit virtual
> addresses (ARMv8.2-LVA).
> User-space utilities like 'makedumpfile' can try and use the getauxval()
> function to retrieve the underlying PARange and VARange values
> supported.

Why do we need VARange here ? This value could be different from the
kernel VA. As for decoding the PTE, you could safely do the flip
of the upper byte by checking the page size of 64K.

What is the usecase for exposing the PARange ?

> An example implementation can be via the 'Appendix I: Example' shown
> in 'Documentation/arm64/cpu-feature-registers.txt'. A reference
> 'makedumpfile' implementation which uses a similar approach is
> available in [0].
> So, we expose these properties via 'FTR_NONSTRICT' and 'FTR_VISIBLE'
> settings for 'ID_AA64MMFR0_PARANGE_SHIFT' and 'ID_AA64MMFR2_LVA_SHIFT'.

What is the rationale behind changing the feature to NONSTRICT ?

> [0].

Btw, if you are not using a 64K page size, the usage of the lva support
feature could corrupt your PTE-> PHYS conversion, unless I am missing something.


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Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-28 20:57 [PATCH 0/2] arm64: Expose physical and virtual address capabilities to user-space Bhupesh Sharma
2019-01-28 20:57 ` [PATCH 1/2] arm64: Expose address bits (physical/virtual) via cpuinfo Bhupesh Sharma
2019-01-29 10:09   ` Suzuki K Poulose
2019-01-30 19:48     ` Bhupesh Sharma
2019-02-04 16:54       ` James Morse
2019-01-28 20:57 ` [PATCH 2/2] arm64: Expose PARange via ID_AA64MMFR0_EL1 and VARange via ID_AA64MMFR2_EL1 Bhupesh Sharma
2019-01-29 10:14   ` Suzuki K Poulose [this message]
2019-01-30 20:27     ` Bhupesh Sharma

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