[PATCH v3 0/9] Add support for Hikey 970 PCIe

[PATCH v3 0/9] Add support for Hikey 970 PCIe

[Mauro Carvalho Chehab]

As requested by Rob Herring, this series split the PHY part into a separate driver.
Then, it adds support for Kirin 970 on a single patch.

With this change, the PHY-specific device tree bindings for Kirin 960 moved
to its own PHY properties.

Manivannan,

Please notice that the last two patches are marked as co-developed:

	phy: hisilicon: add driver for Kirin 970 PCIe PHY
	arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware

The first one contains the code you submitted in the past adding
support for Kirin 970 at the pcie-kirin driver, modified by me and
moved to a separate driver.

The second one is the DTS file, also modified by me in order to split the PHY
properties from the PCIe ones.

Please send your SoB to confirm that both changes are OK for you.

Tested on Hikey970:

  $ lspci
  00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
  01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
  02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
  02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
  02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
  02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
  02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
  06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)

  $ ethtool enp6s0
  Settings for enp6s0:
	Supported ports: [ TP	 MII ]
	Supported link modes:   10baseT/Half 10baseT/Full
	                        100baseT/Half 100baseT/Full
	                        1000baseT/Half 1000baseT/Full
	Supported pause frame use: Symmetric Receive-only
	Supports auto-negotiation: Yes
	Supported FEC modes: Not reported
	Advertised link modes:  10baseT/Half 10baseT/Full
	                        100baseT/Half 100baseT/Full
	                        1000baseT/Half 1000baseT/Full
	Advertised pause frame use: Symmetric Receive-only
	Advertised auto-negotiation: Yes
	Advertised FEC modes: Not reported
	Link partner advertised link modes:  10baseT/Half 10baseT/Full
	                                     100baseT/Half 100baseT/Full
	Link partner advertised pause frame use: Symmetric Receive-only
	Link partner advertised auto-negotiation: Yes
	Link partner advertised FEC modes: Not reported
	Speed: 100Mb/s
	Duplex: Full
	Auto-negotiation: on
	master-slave cfg: preferred slave
	master-slave status: slave
	Port: Twisted Pair
	PHYAD: 0
	Transceiver: external
	MDI-X: Unknown
  netlink error: Operation not permitted
	Link detected: yes

Partially tested on Hikey 960[1]:

  $ lspci
  00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)

[1] The Hikey 960 doesn't come with any internal PCIe device.
    Its hardware supports just an external device via a M.2 slot that
    doesn't support SATA. I ordered a NVMe device to test, but the vendor
    is currently out of supply. It should take 4-5 weeks to arrive here. I'll
    run an extra test on it once it arrives.

Manivannan Sadhasivam (1):
  arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller
    hardware

Mauro Carvalho Chehab (8):
  dt-bindings: phy: add bindings for Hikey 960 PCIe PHY
  dt-bindings: phy: add bindings for Hikey 970 PCIe PHY
  dt-bindings: PCI: kirin: fix compatible string
  dt-bindings: PCI: kirin: drop PHY properties
  phy: hisilicon: add a PHY driver for Kirin 960
  PCI: kirin: drop the PHY logic from the driver
  PCI: kirin: use regmap for APB registers
  phy: hisilicon: add driver for Kirin 970 PCIe PHY

 .../devicetree/bindings/pci/kirin-pcie.txt    |  21 +-
 .../phy/hisilicon,phy-hi3660-pcie.yaml        |  82 ++
 .../phy/hisilicon,phy-hi3670-pcie.yaml        | 101 ++
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi     |  29 +-
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi     |  72 ++
 .../boot/dts/hisilicon/hikey970-pmic.dtsi     |   1 -
 drivers/pci/controller/dwc/pcie-kirin.c       | 298 ++----
 drivers/phy/hisilicon/Kconfig                 |  20 +
 drivers/phy/hisilicon/Makefile                |   2 +
 drivers/phy/hisilicon/phy-hi3660-pcie.c       | 325 +++++++
 drivers/phy/hisilicon/phy-hi3670-pcie.c       | 892 ++++++++++++++++++
 11 files changed, 1572 insertions(+), 271 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
 create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
 create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c

-- 
2.31.1



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[PATCH v3 6/9] PCI: kirin: drop the PHY logic from the driver

[Mauro Carvalho Chehab]

The pcie-kirin PCIe driver contains internally a PHY interface for
a Kirin 960. Drop it and add support for using the new PHY driver
for Kirin 960, updating DT accordingly.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 arch/arm64/boot/dts/hisilicon/hi3660.dtsi |  29 ++-
 drivers/pci/controller/dwc/pcie-kirin.c   | 252 +++-------------------
 2 files changed, 47 insertions(+), 234 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 53890e8052a7..07a616b352f5 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -1001,17 +1001,33 @@ spi3: spi@ff3b3000 {
 			status = "disabled";
 		};
 
+		pcie_phy: pcie-phy@f3f2000 {
+			compatible = "hisilicon,hi960-pcie-phy";
+			reg = <0x0 0xf3f20000 0x0 0x40000>;
+			reg-names = "phy";
+			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+				 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+				 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+			clock-names = "pcie_phy_ref", "pcie_aux",
+				      "pcie_apb_phy", "pcie_apb_sys",
+				      "pcie_aclk";
+			reset-gpios = <&gpio11 1 0 >;
+			#phy-cells = <0>;
+		};
+
 		pcie@f4000000 {
 			compatible = "hisilicon,kirin960-pcie";
 			reg = <0x0 0xf4000000 0x0 0x1000>,
 			      <0x0 0xff3fe000 0x0 0x1000>,
-			      <0x0 0xf3f20000 0x0 0x40000>,
 			      <0x0 0xf5000000 0x0 0x2000>;
-			reg-names = "dbi", "apb", "phy", "config";
+			reg-names = "dbi", "apb", "config";
 			bus-range = <0x0  0x1>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			device_type = "pci";
+			phys = <&pcie_phy>;
 			ranges = <0x02000000 0x0 0x00000000
 				  0x0 0xf6000000
 				  0x0 0x02000000>;
@@ -1028,15 +1044,6 @@ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
 					 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
 					<0x0 0 0 4
 					 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
-				 <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
-				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
-				 <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
-				 <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
-			clock-names = "pcie_phy_ref", "pcie_aux",
-				      "pcie_apb_phy", "pcie_apb_sys",
-				      "pcie_aclk";
-			reset-gpios = <&gpio11 1 0 >;
 		};
 
 		/* UFS */
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index 026fd1e42a55..a77bbecbf11f 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -9,7 +9,6 @@
  */
 
 #include <linux/compiler.h>
-#include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
@@ -21,6 +20,7 @@
 #include <linux/pci.h>
 #include <linux/pci_regs.h>
 #include <linux/platform_device.h>
+#include <linux/phy/phy.h>
 #include <linux/regmap.h>
 #include <linux/resource.h>
 #include <linux/types.h>
@@ -28,26 +28,17 @@
 
 #define to_kirin_pcie(x) dev_get_drvdata((x)->dev)
 
-#define REF_CLK_FREQ			100000000
-
 /* PCIe ELBI registers */
 #define SOC_PCIECTRL_CTRL0_ADDR		0x000
 #define SOC_PCIECTRL_CTRL1_ADDR		0x004
-#define SOC_PCIEPHY_CTRL2_ADDR		0x008
-#define SOC_PCIEPHY_CTRL3_ADDR		0x00c
 #define PCIE_ELBI_SLV_DBI_ENABLE	(0x1 << 21)
 
 /* info located in APB */
 #define PCIE_APP_LTSSM_ENABLE	0x01c
-#define PCIE_APB_PHY_CTRL0	0x0
-#define PCIE_APB_PHY_CTRL1	0x4
 #define PCIE_APB_PHY_STATUS0	0x400
 #define PCIE_LINKUP_ENABLE	(0x8020)
 #define PCIE_LTSSM_ENABLE_BIT	(0x1 << 11)
 #define PIPE_CLK_STABLE		(0x1 << 19)
-#define PHY_REF_PAD_BIT		(0x1 << 8)
-#define PHY_PWR_DOWN_BIT	(0x1 << 22)
-#define PHY_RST_ACK_BIT		(0x1 << 16)
 
 /* info located in sysctrl */
 #define SCTRL_PCIE_CMOS_OFFSET	0x60
@@ -60,36 +51,10 @@
 #define PCIE_DEBOUNCE_PARAM	0xF0F400
 #define PCIE_OE_BYPASS		(0x3 << 28)
 
-/* peri_crg ctrl */
-#define CRGCTRL_PCIE_ASSERT_OFFSET	0x88
-#define CRGCTRL_PCIE_ASSERT_BIT		0x8c000000
-
-/* Time for delay */
-#define REF_2_PERST_MIN		20000
-#define REF_2_PERST_MAX		25000
-#define PERST_2_ACCESS_MIN	10000
-#define PERST_2_ACCESS_MAX	12000
-#define LINK_WAIT_MIN		900
-#define LINK_WAIT_MAX		1000
-#define PIPE_CLK_WAIT_MIN	550
-#define PIPE_CLK_WAIT_MAX	600
-#define TIME_CMOS_MIN		100
-#define TIME_CMOS_MAX		105
-#define TIME_PHY_PD_MIN		10
-#define TIME_PHY_PD_MAX		11
-
 struct kirin_pcie {
 	struct dw_pcie	*pci;
+	struct phy	*phy;
 	void __iomem	*apb_base;
-	void __iomem	*phy_base;
-	struct regmap	*crgctrl;
-	struct regmap	*sysctrl;
-	struct clk	*apb_sys_clk;
-	struct clk	*apb_phy_clk;
-	struct clk	*phy_ref_clk;
-	struct clk	*pcie_aclk;
-	struct clk	*pcie_aux_clk;
-	int		gpio_id_reset;
 };
 
 /* Registers in PCIeCTRL */
@@ -104,46 +69,6 @@ static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
 	return readl(kirin_pcie->apb_base + reg);
 }
 
-/* Registers in PCIePHY */
-static inline void kirin_apb_phy_writel(struct kirin_pcie *kirin_pcie,
-					u32 val, u32 reg)
-{
-	writel(val, kirin_pcie->phy_base + reg);
-}
-
-static inline u32 kirin_apb_phy_readl(struct kirin_pcie *kirin_pcie, u32 reg)
-{
-	return readl(kirin_pcie->phy_base + reg);
-}
-
-static long kirin_pcie_get_clk(struct kirin_pcie *kirin_pcie,
-			       struct platform_device *pdev)
-{
-	struct device *dev = &pdev->dev;
-
-	kirin_pcie->phy_ref_clk = devm_clk_get(dev, "pcie_phy_ref");
-	if (IS_ERR(kirin_pcie->phy_ref_clk))
-		return PTR_ERR(kirin_pcie->phy_ref_clk);
-
-	kirin_pcie->pcie_aux_clk = devm_clk_get(dev, "pcie_aux");
-	if (IS_ERR(kirin_pcie->pcie_aux_clk))
-		return PTR_ERR(kirin_pcie->pcie_aux_clk);
-
-	kirin_pcie->apb_phy_clk = devm_clk_get(dev, "pcie_apb_phy");
-	if (IS_ERR(kirin_pcie->apb_phy_clk))
-		return PTR_ERR(kirin_pcie->apb_phy_clk);
-
-	kirin_pcie->apb_sys_clk = devm_clk_get(dev, "pcie_apb_sys");
-	if (IS_ERR(kirin_pcie->apb_sys_clk))
-		return PTR_ERR(kirin_pcie->apb_sys_clk);
-
-	kirin_pcie->pcie_aclk = devm_clk_get(dev, "pcie_aclk");
-	if (IS_ERR(kirin_pcie->pcie_aclk))
-		return PTR_ERR(kirin_pcie->pcie_aclk);
-
-	return 0;
-}
-
 static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
 				    struct platform_device *pdev)
 {
@@ -152,149 +77,18 @@ static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
 	if (IS_ERR(kirin_pcie->apb_base))
 		return PTR_ERR(kirin_pcie->apb_base);
 
-	kirin_pcie->phy_base =
-		devm_platform_ioremap_resource_byname(pdev, "phy");
-	if (IS_ERR(kirin_pcie->phy_base))
-		return PTR_ERR(kirin_pcie->phy_base);
-
-	kirin_pcie->crgctrl =
-		syscon_regmap_lookup_by_compatible("hisilicon,hi3660-crgctrl");
-	if (IS_ERR(kirin_pcie->crgctrl))
-		return PTR_ERR(kirin_pcie->crgctrl);
-
-	kirin_pcie->sysctrl =
-		syscon_regmap_lookup_by_compatible("hisilicon,hi3660-sctrl");
-	if (IS_ERR(kirin_pcie->sysctrl))
-		return PTR_ERR(kirin_pcie->sysctrl);
-
 	return 0;
 }
 
-static int kirin_pcie_phy_init(struct kirin_pcie *kirin_pcie)
-{
-	struct device *dev = kirin_pcie->pci->dev;
-	u32 reg_val;
-
-	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
-	reg_val &= ~PHY_REF_PAD_BIT;
-	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
-
-	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL0);
-	reg_val &= ~PHY_PWR_DOWN_BIT;
-	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL0);
-	usleep_range(TIME_PHY_PD_MIN, TIME_PHY_PD_MAX);
-
-	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_CTRL1);
-	reg_val &= ~PHY_RST_ACK_BIT;
-	kirin_apb_phy_writel(kirin_pcie, reg_val, PCIE_APB_PHY_CTRL1);
-
-	usleep_range(PIPE_CLK_WAIT_MIN, PIPE_CLK_WAIT_MAX);
-	reg_val = kirin_apb_phy_readl(kirin_pcie, PCIE_APB_PHY_STATUS0);
-	if (reg_val & PIPE_CLK_STABLE) {
-		dev_err(dev, "PIPE clk is not stable\n");
-		return -EINVAL;
-	}
-
-	return 0;
-}
-
-static void kirin_pcie_oe_enable(struct kirin_pcie *kirin_pcie)
-{
-	u32 val;
-
-	regmap_read(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, &val);
-	val |= PCIE_DEBOUNCE_PARAM;
-	val &= ~PCIE_OE_BYPASS;
-	regmap_write(kirin_pcie->sysctrl, SCTRL_PCIE_OE_OFFSET, val);
-}
-
-static int kirin_pcie_clk_ctrl(struct kirin_pcie *kirin_pcie, bool enable)
-{
-	int ret = 0;
-
-	if (!enable)
-		goto close_clk;
-
-	ret = clk_set_rate(kirin_pcie->phy_ref_clk, REF_CLK_FREQ);
-	if (ret)
-		return ret;
-
-	ret = clk_prepare_enable(kirin_pcie->phy_ref_clk);
-	if (ret)
-		return ret;
-
-	ret = clk_prepare_enable(kirin_pcie->apb_sys_clk);
-	if (ret)
-		goto apb_sys_fail;
-
-	ret = clk_prepare_enable(kirin_pcie->apb_phy_clk);
-	if (ret)
-		goto apb_phy_fail;
-
-	ret = clk_prepare_enable(kirin_pcie->pcie_aclk);
-	if (ret)
-		goto aclk_fail;
-
-	ret = clk_prepare_enable(kirin_pcie->pcie_aux_clk);
-	if (ret)
-		goto aux_clk_fail;
-
-	return 0;
-
-close_clk:
-	clk_disable_unprepare(kirin_pcie->pcie_aux_clk);
-aux_clk_fail:
-	clk_disable_unprepare(kirin_pcie->pcie_aclk);
-aclk_fail:
-	clk_disable_unprepare(kirin_pcie->apb_phy_clk);
-apb_phy_fail:
-	clk_disable_unprepare(kirin_pcie->apb_sys_clk);
-apb_sys_fail:
-	clk_disable_unprepare(kirin_pcie->phy_ref_clk);
-
-	return ret;
-}
-
 static int kirin_pcie_power_on(struct kirin_pcie *kirin_pcie)
 {
 	int ret;
 
-	/* Power supply for Host */
-	regmap_write(kirin_pcie->sysctrl,
-		     SCTRL_PCIE_CMOS_OFFSET, SCTRL_PCIE_CMOS_BIT);
-	usleep_range(TIME_CMOS_MIN, TIME_CMOS_MAX);
-	kirin_pcie_oe_enable(kirin_pcie);
-
-	ret = kirin_pcie_clk_ctrl(kirin_pcie, true);
+	ret = phy_init(kirin_pcie->phy);
 	if (ret)
 		return ret;
 
-	/* ISO disable, PCIeCtrl, PHY assert and clk gate clear */
-	regmap_write(kirin_pcie->sysctrl,
-		     SCTRL_PCIE_ISO_OFFSET, SCTRL_PCIE_ISO_BIT);
-	regmap_write(kirin_pcie->crgctrl,
-		     CRGCTRL_PCIE_ASSERT_OFFSET, CRGCTRL_PCIE_ASSERT_BIT);
-	regmap_write(kirin_pcie->sysctrl,
-		     SCTRL_PCIE_HPCLK_OFFSET, SCTRL_PCIE_HPCLK_BIT);
-
-	ret = kirin_pcie_phy_init(kirin_pcie);
-	if (ret)
-		goto close_clk;
-
-	/* perst assert Endpoint */
-	if (!gpio_request(kirin_pcie->gpio_id_reset, "pcie_perst")) {
-		usleep_range(REF_2_PERST_MIN, REF_2_PERST_MAX);
-		ret = gpio_direction_output(kirin_pcie->gpio_id_reset, 1);
-		if (ret)
-			goto close_clk;
-		usleep_range(PERST_2_ACCESS_MIN, PERST_2_ACCESS_MAX);
-
-		return 0;
-	}
-
-close_clk:
-	kirin_pcie_clk_ctrl(kirin_pcie, false);
-	return ret;
+	return phy_power_on(kirin_pcie->phy);
 }
 
 static void kirin_pcie_sideband_dbi_w_mode(struct kirin_pcie *kirin_pcie,
@@ -444,30 +238,41 @@ static int kirin_pcie_probe(struct platform_device *pdev)
 	pci->pp.ops = &kirin_pcie_host_ops;
 	kirin_pcie->pci = pci;
 
-	ret = kirin_pcie_get_clk(kirin_pcie, pdev);
-	if (ret)
-		return ret;
+	kirin_pcie->phy = devm_of_phy_get(dev, dev->of_node, NULL);
+	if (IS_ERR(kirin_pcie->phy))
+		return PTR_ERR(kirin_pcie->phy);
 
 	ret = kirin_pcie_get_resource(kirin_pcie, pdev);
 	if (ret)
 		return ret;
 
-	kirin_pcie->gpio_id_reset = of_get_named_gpio(dev->of_node,
-						      "reset-gpios", 0);
-	if (kirin_pcie->gpio_id_reset == -EPROBE_DEFER) {
-		return -EPROBE_DEFER;
-	} else if (!gpio_is_valid(kirin_pcie->gpio_id_reset)) {
-		dev_err(dev, "unable to get a valid gpio pin\n");
-		return -ENODEV;
-	}
-
 	ret = kirin_pcie_power_on(kirin_pcie);
 	if (ret)
 		return ret;
 
 	platform_set_drvdata(pdev, kirin_pcie);
 
-	return dw_pcie_host_init(&pci->pp);
+	ret = dw_pcie_host_init(&pci->pp);
+	if (ret) {
+		phy_power_off(kirin_pcie->phy);
+		goto err;
+	}
+
+	return 0;
+err:
+	phy_exit(kirin_pcie->phy);
+
+	return ret;
+}
+
+static int __exit kirin_pcie_remove(struct platform_device *pdev)
+{
+	struct kirin_pcie *kirin_pcie = platform_get_drvdata(pdev);
+
+	phy_power_off(kirin_pcie->phy);
+	phy_exit(kirin_pcie->phy);
+
+	return 0;
 }
 
 static const struct of_device_id kirin_pcie_match[] = {
@@ -477,6 +282,7 @@ static const struct of_device_id kirin_pcie_match[] = {
 
 static struct platform_driver kirin_pcie_driver = {
 	.probe			= kirin_pcie_probe,
+	.remove	        	= __exit_p(kirin_pcie_remove),
 	.driver			= {
 		.name			= "kirin-pcie",
 		.of_match_table = kirin_pcie_match,
-- 
2.31.1


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[PATCH v3 9/9] arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware

[Mauro Carvalho Chehab]

From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Add DTS bindings for the Hikey 970 board's PCIe hardware.

Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
 arch/arm64/boot/dts/hisilicon/hi3670.dtsi     | 72 +++++++++++++++++++
 .../boot/dts/hisilicon/hikey970-pmic.dtsi     |  1 -
 2 files changed, 72 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6476149d99e3..f54dab70f01b 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
 			#clock-cells = <1>;
 		};
 
+		pmctrl: pmctrl@fff31000 {
+			compatible = "hisilicon,hi3670-pmctrl", "syscon";
+			reg = <0x0 0xfff31000 0x0 0x1000>;
+			#clock-cells = <1>;
+		};
+
 		iomcu: iomcu@ffd7e000 {
 			compatible = "hisilicon,hi3670-iomcu", "syscon";
 			reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -660,6 +666,72 @@ gpio28: gpio@fff1d000 {
 			clock-names = "apb_pclk";
 		};
 
+		its_pcie: interrupt-controller@f4000000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0xf5100000 0x0 0x100000>;
+		};
+
+		pcie_phy: pcie-phy@fc000000 {
+			compatible = "hisilicon,hi970-pcie-phy";
+			reg = <0x0 0xfc000000 0x0 0x80000>;
+			reg-names = "phy";
+
+			phy-supply = <&ldo33>;
+
+			clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+				 <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+				 <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+				 <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+				 <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+			clock-names = "pcie_phy_ref", "pcie_aux",
+				      "pcie_apb_phy", "pcie_apb_sys",
+				      "pcie_aclk";
+
+			reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
+				      <&gpio3 1 0 >, <&gpio27 4 0 >;
+
+			clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >,
+				       <&gpio17 0 0 >;
+
+			/* vboost iboost pre post main */
+			hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF
+						       0xFFFFFFFF 0xFFFFFFFF
+						       0xFFFFFFFF>;
+
+			#phy-cells = <0>;
+		};
+
+		pcie@f4000000 {
+			compatible = "hisilicon,kirin970-pcie";
+			reg = <0x0 0xf4000000 0x0 0x1000000>,
+			      <0x0 0xfc180000 0x0 0x1000>,
+			      <0x0 0xf5000000 0x0 0x2000>;
+			reg-names = "dbi", "apb", "config";
+			bus-range = <0x0  0x1>;
+			msi-parent = <&its_pcie>;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			phys = <&pcie_phy>;
+			ranges = <0x02000000 0x0 0x00000000
+				  0x0 0xf6000000
+				  0x0 0x02000000>;
+			num-lanes = <1>;
+			#interrupt-cells = <1>;
+			interrupts = <0 283 4>;
+			interrupt-names = "msi";
+			interrupt-map-mask = <0 0 0 7>;
+			interrupt-map = <0x0 0 0 1
+					 &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 2
+					 &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 3
+					 &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+					<0x0 0 0 4
+					 &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
 		/* UFS */
 		ufs: ufs@ff3c0000 {
 			compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
index 48c739eacba0..03452e627641 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
@@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */
 					regulator-name = "ldo33";
 					regulator-min-microvolt = <2500000>;
 					regulator-max-microvolt = <3300000>;
-					regulator-boot-on;
 				};
 
 				ldo34: LDO34 { /* GPS AUX IN VDD */
-- 
2.31.1


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Re: [PATCH v3 0/9] Add support for Hikey 970 PCIe

[Manivannan Sadhasivam]

Hi Mauro,

On Fri, Jul 09, 2021 at 12:41:36PM +0200, Mauro Carvalho Chehab wrote:
> As requested by Rob Herring, this series split the PHY part into a separate driver.
> Then, it adds support for Kirin 970 on a single patch.
> 
> With this change, the PHY-specific device tree bindings for Kirin 960 moved
> to its own PHY properties.
> 
> Manivannan,
> 
> Please notice that the last two patches are marked as co-developed:
> 
> 	phy: hisilicon: add driver for Kirin 970 PCIe PHY
> 	arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware
> 
> The first one contains the code you submitted in the past adding
> support for Kirin 970 at the pcie-kirin driver, modified by me and
> moved to a separate driver.
> 
> The second one is the DTS file, also modified by me in order to split the PHY
> properties from the PCIe ones.
> 
> Please send your SoB to confirm that both changes are OK for you.
> 

I'm fine with the changes. The dts patch already has my s-o-b as you
preserved my authorship and I've sent my s-o-b for the driver patch.
I used my korg address for the driver patch but that's fine as all these
efforts were done in my spare time.

Thanks,
Mani

> Tested on Hikey970:
> 
>   $ lspci
>   00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
>   01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
>   06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
> 
>   $ ethtool enp6s0
>   Settings for enp6s0:
> 	Supported ports: [ TP	 MII ]
> 	Supported link modes:   10baseT/Half 10baseT/Full
> 	                        100baseT/Half 100baseT/Full
> 	                        1000baseT/Half 1000baseT/Full
> 	Supported pause frame use: Symmetric Receive-only
> 	Supports auto-negotiation: Yes
> 	Supported FEC modes: Not reported
> 	Advertised link modes:  10baseT/Half 10baseT/Full
> 	                        100baseT/Half 100baseT/Full
> 	                        1000baseT/Half 1000baseT/Full
> 	Advertised pause frame use: Symmetric Receive-only
> 	Advertised auto-negotiation: Yes
> 	Advertised FEC modes: Not reported
> 	Link partner advertised link modes:  10baseT/Half 10baseT/Full
> 	                                     100baseT/Half 100baseT/Full
> 	Link partner advertised pause frame use: Symmetric Receive-only
> 	Link partner advertised auto-negotiation: Yes
> 	Link partner advertised FEC modes: Not reported
> 	Speed: 100Mb/s
> 	Duplex: Full
> 	Auto-negotiation: on
> 	master-slave cfg: preferred slave
> 	master-slave status: slave
> 	Port: Twisted Pair
> 	PHYAD: 0
> 	Transceiver: external
> 	MDI-X: Unknown
>   netlink error: Operation not permitted
> 	Link detected: yes
> 
> Partially tested on Hikey 960[1]:
> 
>   $ lspci
>   00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
> 
> [1] The Hikey 960 doesn't come with any internal PCIe device.
>     Its hardware supports just an external device via a M.2 slot that
>     doesn't support SATA. I ordered a NVMe device to test, but the vendor
>     is currently out of supply. It should take 4-5 weeks to arrive here. I'll
>     run an extra test on it once it arrives.
> 
> Manivannan Sadhasivam (1):
>   arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller
>     hardware
> 
> Mauro Carvalho Chehab (8):
>   dt-bindings: phy: add bindings for Hikey 960 PCIe PHY
>   dt-bindings: phy: add bindings for Hikey 970 PCIe PHY
>   dt-bindings: PCI: kirin: fix compatible string
>   dt-bindings: PCI: kirin: drop PHY properties
>   phy: hisilicon: add a PHY driver for Kirin 960
>   PCI: kirin: drop the PHY logic from the driver
>   PCI: kirin: use regmap for APB registers
>   phy: hisilicon: add driver for Kirin 970 PCIe PHY
> 
>  .../devicetree/bindings/pci/kirin-pcie.txt    |  21 +-
>  .../phy/hisilicon,phy-hi3660-pcie.yaml        |  82 ++
>  .../phy/hisilicon,phy-hi3670-pcie.yaml        | 101 ++
>  arch/arm64/boot/dts/hisilicon/hi3660.dtsi     |  29 +-
>  arch/arm64/boot/dts/hisilicon/hi3670.dtsi     |  72 ++
>  .../boot/dts/hisilicon/hikey970-pmic.dtsi     |   1 -
>  drivers/pci/controller/dwc/pcie-kirin.c       | 298 ++----
>  drivers/phy/hisilicon/Kconfig                 |  20 +
>  drivers/phy/hisilicon/Makefile                |   2 +
>  drivers/phy/hisilicon/phy-hi3660-pcie.c       | 325 +++++++
>  drivers/phy/hisilicon/phy-hi3670-pcie.c       | 892 ++++++++++++++++++
>  11 files changed, 1572 insertions(+), 271 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
>  create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
>  create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
>  create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
> 
> -- 
> 2.31.1
> 
> 

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Re: [PATCH v3 0/9] Add support for Hikey 970 PCIe

[Bjorn Helgaas]

On Fri, Jul 09, 2021 at 12:41:36PM +0200, Mauro Carvalho Chehab wrote:
> ...
> Manivannan Sadhasivam (1):
>   arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller
>     hardware

FWIW, this didn't apply cleanly for me to v5.14-rc1.

> Mauro Carvalho Chehab (8):
>   dt-bindings: phy: add bindings for Hikey 960 PCIe PHY
>   dt-bindings: phy: add bindings for Hikey 970 PCIe PHY
>   dt-bindings: PCI: kirin: fix compatible string
>   dt-bindings: PCI: kirin: drop PHY properties
>   phy: hisilicon: add a PHY driver for Kirin 960

>   PCI: kirin: drop the PHY logic from the driver
>   PCI: kirin: use regmap for APB registers

If/when you repost this, please update these subject lines to match the
historical style:

  PCI: kirin: Drop PHY logic from the driver
  PCI: kirin: Use regmap for APB registers

Also, please update subject lines, commit logs, Kconfig menu and help
text, comments, etc throughout to capitalize "HiKey" and "HiSilicon"
as the vendor does.

>   phy: hisilicon: add driver for Kirin 970 PCIe PHY

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Re: [PATCH v3 0/9] Add support for Hikey 970 PCIe

[Mauro Carvalho Chehab]

Hi Bjorn,

Em Mon, 12 Jul 2021 11:52:21 -0500
Bjorn Helgaas <helgaas@kernel.org> escreveu:

> On Fri, Jul 09, 2021 at 12:41:36PM +0200, Mauro Carvalho Chehab wrote:
> > ...
> > Manivannan Sadhasivam (1):
> >   arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller
> >     hardware  
> 
> FWIW, this didn't apply cleanly for me to v5.14-rc1.

True. The last patch of this series:

	dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware

Depends on a patch that should be merged via another tree:

	https://lore.kernel.org/lkml/db5b33e4d0b239a7377e123b46f63b5640329021.1625477735.git.mchehab+huawei@kernel.org/

Such patch adds the DTS data required for the PMIC.

I guess I'll submit the series without this one. Once both series
get merged, I'll submit it in separate.

> 
> > Mauro Carvalho Chehab (8):
> >   dt-bindings: phy: add bindings for Hikey 960 PCIe PHY
> >   dt-bindings: phy: add bindings for Hikey 970 PCIe PHY
> >   dt-bindings: PCI: kirin: fix compatible string
> >   dt-bindings: PCI: kirin: drop PHY properties
> >   phy: hisilicon: add a PHY driver for Kirin 960  
> 
> >   PCI: kirin: drop the PHY logic from the driver
> >   PCI: kirin: use regmap for APB registers  
> 
> If/when you repost this, please update these subject lines to match the
> historical style:
> 
>   PCI: kirin: Drop PHY logic from the driver
>   PCI: kirin: Use regmap for APB registers
> 
> Also, please update subject lines, commit logs, Kconfig menu and help
> text, comments, etc throughout to capitalize "HiKey" and "HiSilicon"
> as the vendor does.

Ok.

> 
> >   phy: hisilicon: add driver for Kirin 970 PCIe PHY  



Thanks,
Mauro

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Re: [PATCH v3 0/9] Add support for Hikey 970 PCIe

[Mauro Carvalho Chehab]

Em Mon, 12 Jul 2021 13:49:44 +0530
Manivannan Sadhasivam <mani@kernel.org> escreveu:

> Hi Mauro,
> 
> On Fri, Jul 09, 2021 at 12:41:36PM +0200, Mauro Carvalho Chehab wrote:
> > As requested by Rob Herring, this series split the PHY part into a separate driver.
> > Then, it adds support for Kirin 970 on a single patch.
> > 
> > With this change, the PHY-specific device tree bindings for Kirin 960 moved
> > to its own PHY properties.
> > 
> > Manivannan,
> > 
> > Please notice that the last two patches are marked as co-developed:
> > 
> > 	phy: hisilicon: add driver for Kirin 970 PCIe PHY
> > 	arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller hardware
> > 
> > The first one contains the code you submitted in the past adding
> > support for Kirin 970 at the pcie-kirin driver, modified by me and
> > moved to a separate driver.
> > 
> > The second one is the DTS file, also modified by me in order to split the PHY
> > properties from the PCIe ones.
> > 
> > Please send your SoB to confirm that both changes are OK for you.
> >   
> 
> I'm fine with the changes. The dts patch already has my s-o-b as you
> preserved my authorship and I've sent my s-o-b for the driver patch.
> I used my korg address for the driver patch but that's fine as all these
> efforts were done in my spare time.

Thank you! Sent v4 with your SoB at the driver part. I'll submit
your DTS patch later on, as it depends on a patch adding DT for HiKey 970
PMIC, that should be merged via another tree.

Regards,
Mauro

> 
> Thanks,
> Mani
> 
> > Tested on Hikey970:
> > 
> >   $ lspci
> >   00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3670 (rev 01)
> >   01:00.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
> >   02:01.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
> >   02:04.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
> >   02:05.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
> >   02:07.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
> >   02:09.0 PCI bridge: PLX Technology, Inc. PEX 8606 6 Lane, 6 Port PCI Express Gen 2 (5.0 GT/s) Switch (rev ba)
> >   06:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8111/8168/8411 PCI Express Gigabit Ethernet Controller (rev 07)
> > 
> >   $ ethtool enp6s0
> >   Settings for enp6s0:
> > 	Supported ports: [ TP	 MII ]
> > 	Supported link modes:   10baseT/Half 10baseT/Full
> > 	                        100baseT/Half 100baseT/Full
> > 	                        1000baseT/Half 1000baseT/Full
> > 	Supported pause frame use: Symmetric Receive-only
> > 	Supports auto-negotiation: Yes
> > 	Supported FEC modes: Not reported
> > 	Advertised link modes:  10baseT/Half 10baseT/Full
> > 	                        100baseT/Half 100baseT/Full
> > 	                        1000baseT/Half 1000baseT/Full
> > 	Advertised pause frame use: Symmetric Receive-only
> > 	Advertised auto-negotiation: Yes
> > 	Advertised FEC modes: Not reported
> > 	Link partner advertised link modes:  10baseT/Half 10baseT/Full
> > 	                                     100baseT/Half 100baseT/Full
> > 	Link partner advertised pause frame use: Symmetric Receive-only
> > 	Link partner advertised auto-negotiation: Yes
> > 	Link partner advertised FEC modes: Not reported
> > 	Speed: 100Mb/s
> > 	Duplex: Full
> > 	Auto-negotiation: on
> > 	master-slave cfg: preferred slave
> > 	master-slave status: slave
> > 	Port: Twisted Pair
> > 	PHYAD: 0
> > 	Transceiver: external
> > 	MDI-X: Unknown
> >   netlink error: Operation not permitted
> > 	Link detected: yes
> > 
> > Partially tested on Hikey 960[1]:
> > 
> >   $ lspci
> >   00:00.0 PCI bridge: Huawei Technologies Co., Ltd. Device 3660 (rev 01)
> > 
> > [1] The Hikey 960 doesn't come with any internal PCIe device.
> >     Its hardware supports just an external device via a M.2 slot that
> >     doesn't support SATA. I ordered a NVMe device to test, but the vendor
> >     is currently out of supply. It should take 4-5 weeks to arrive here. I'll
> >     run an extra test on it once it arrives.
> > 
> > Manivannan Sadhasivam (1):
> >   arm64: dts: hisilicon: Add support for HiKey 970 PCIe controller
> >     hardware
> > 
> > Mauro Carvalho Chehab (8):
> >   dt-bindings: phy: add bindings for Hikey 960 PCIe PHY
> >   dt-bindings: phy: add bindings for Hikey 970 PCIe PHY
> >   dt-bindings: PCI: kirin: fix compatible string
> >   dt-bindings: PCI: kirin: drop PHY properties
> >   phy: hisilicon: add a PHY driver for Kirin 960
> >   PCI: kirin: drop the PHY logic from the driver
> >   PCI: kirin: use regmap for APB registers
> >   phy: hisilicon: add driver for Kirin 970 PCIe PHY
> > 
> >  .../devicetree/bindings/pci/kirin-pcie.txt    |  21 +-
> >  .../phy/hisilicon,phy-hi3660-pcie.yaml        |  82 ++
> >  .../phy/hisilicon,phy-hi3670-pcie.yaml        | 101 ++
> >  arch/arm64/boot/dts/hisilicon/hi3660.dtsi     |  29 +-
> >  arch/arm64/boot/dts/hisilicon/hi3670.dtsi     |  72 ++
> >  .../boot/dts/hisilicon/hikey970-pmic.dtsi     |   1 -
> >  drivers/pci/controller/dwc/pcie-kirin.c       | 298 ++----
> >  drivers/phy/hisilicon/Kconfig                 |  20 +
> >  drivers/phy/hisilicon/Makefile                |   2 +
> >  drivers/phy/hisilicon/phy-hi3660-pcie.c       | 325 +++++++
> >  drivers/phy/hisilicon/phy-hi3670-pcie.c       | 892 ++++++++++++++++++
> >  11 files changed, 1572 insertions(+), 271 deletions(-)
> >  create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3660-pcie.yaml
> >  create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
> >  create mode 100644 drivers/phy/hisilicon/phy-hi3660-pcie.c
> >  create mode 100644 drivers/phy/hisilicon/phy-hi3670-pcie.c
> > 
> > -- 
> > 2.31.1
> > 
> >   



Thanks,
Mauro

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