* [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work
@ 2021-07-29 11:56 Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Mauro Carvalho Chehab
2021-07-29 17:20 ` [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Rob Herring
0 siblings, 2 replies; 3+ messages in thread
From: Mauro Carvalho Chehab @ 2021-07-29 11:56 UTC (permalink / raw)
To: Rob Herring
Cc: linuxarm, mauro.chehab, Mauro Carvalho Chehab, Binghui Wang,
Gustavo Pimentel, Jingoo Han, Rob Herring, Xiaowei Song,
devicetree, linux-arm-kernel, linux-kernel, linux-pci, linux-phy
Hi Rob,
After our discussions, I'm opting to submit first the DT bindings for the
Kirin 970 PCIe support.
Patch 1 is there just because patch 2 needs. You already acked on it.
Patch 5 is also there just as an example of the entire stuff added to
the DTS file.
The core of this series are patches 2 to 4. They contain the conversion
of the kirin-pcie.txt file to the DT schema, and adds the needed
bindings.
Currently, it generates some warnings:
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short
Not sure how/where to fix those. Perhaps at the pci-bus.yaml?
Please review.
Thanks!
Mauro
Manivannan Sadhasivam (1):
arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller
hardware
Mauro Carvalho Chehab (4):
dt-bindings: PCI: kirin: Fix compatible string
dt-bindings: PCI: kirin: convert kirin-pcie.txt to yaml
dt-bindings: PCI: kirin: Add support for Kirin970
dt-bindings: phy: Add bindings for HiKey 970 PCIe PHY
.../bindings/pci/hisilicon,kirin-pcie.yaml | 145 ++++++++++++++++++
.../devicetree/bindings/pci/kirin-pcie.txt | 50 ------
.../devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
.../phy/hisilicon,phy-hi3670-pcie.yaml | 86 +++++++++++
MAINTAINERS | 2 +-
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 99 ++++++++++++
6 files changed, 332 insertions(+), 52 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
delete mode 100644 Documentation/devicetree/bindings/pci/kirin-pcie.txt
create mode 100644 Documentation/devicetree/bindings/phy/hisilicon,phy-hi3670-pcie.yaml
--
2.31.1
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^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware
2021-07-29 11:56 [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Mauro Carvalho Chehab
@ 2021-07-29 11:56 ` Mauro Carvalho Chehab
2021-07-29 17:20 ` [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Mauro Carvalho Chehab @ 2021-07-29 11:56 UTC (permalink / raw)
To: Rob Herring
Cc: linuxarm, mauro.chehab, Manivannan Sadhasivam, Rob Herring,
Wei Xu, devicetree, linux-arm-kernel, linux-kernel,
Mauro Carvalho Chehab
From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 99 +++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 20698cfd0637..2cf19c8960f3 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -176,6 +176,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -659,6 +665,99 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ its_pcie: interrupt-controller@f4000000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0xf5100000 0x0 0x100000>;
+ };
+
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xffffffff 0xffffffff
+ 0xffffffff 0xffffffff
+ 0xffffffff>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0x1>;
+ msi-parent = <&its_pcie>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ reset-gpios = <&gpio7 0 0 >;
+
+ pcie@4,0 { // Lane 4: M.2
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio7 1 0>;
+ clkreq-gpios = <&gpio27 3 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@5,0 { // Lane 5: Mini PCIe
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio7 2 0>;
+ clkreq-gpios = <&gpio17 0 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+
+ pcie@7,0 { // Lane 7: Ethernet
+ reg = <0 0 0 0 0>;
+ compatible = "pciclass,0604";
+ device_type = "pci";
+ reset-gpios = <&gpio7 3 0>;
+ clkreq-gpios = <&gpio20 0 0 >;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges;
+ };
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
--
2.31.1
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work
2021-07-29 11:56 [PATCH 0/5] DT schema changes for HiKey970 PCIe hardware to work Mauro Carvalho Chehab
2021-07-29 11:56 ` [PATCH 5/5] arm64: dts: HiSilicon: Add support for HiKey 970 PCIe controller hardware Mauro Carvalho Chehab
@ 2021-07-29 17:20 ` Rob Herring
1 sibling, 0 replies; 3+ messages in thread
From: Rob Herring @ 2021-07-29 17:20 UTC (permalink / raw)
To: Mauro Carvalho Chehab
Cc: Linuxarm, mauro.chehab, Binghui Wang, Gustavo Pimentel,
Jingoo Han, Xiaowei Song, devicetree, linux-arm-kernel,
linux-kernel, PCI, linux-phy
On Thu, Jul 29, 2021 at 5:56 AM Mauro Carvalho Chehab
<mchehab+huawei@kernel.org> wrote:
>
> Hi Rob,
>
> After our discussions, I'm opting to submit first the DT bindings for the
> Kirin 970 PCIe support.
>
> Patch 1 is there just because patch 2 needs. You already acked on it.
>
> Patch 5 is also there just as an example of the entire stuff added to
> the DTS file.
>
> The core of this series are patches 2 to 4. They contain the conversion
> of the kirin-pcie.txt file to the DT schema, and adds the needed
> bindings.
>
> Currently, it generates some warnings:
>
> Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@f5000000: pcie@4,0:compatible: None of ['pciclass,0604'] are valid under the given schema
> From schema: Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
This should be fixed now in dtschema master.
> Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.example.dt.yaml: pcie@4,0: reset-gpios: [[4294967295, 1, 0]] is too short
Your proposed change to pci-bus.yaml is wrong. It's requiring 4
entries. You need 'minItems: 1'.
Rob
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^ permalink raw reply [flat|nested] 3+ messages in thread
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