* [PATCH 1/5] arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes
2020-01-08 11:18 [PATCH 0/5] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
@ 2020-01-08 11:18 ` Roger Quadros
2020-01-08 11:18 ` [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux Roger Quadros
` (3 subsequent siblings)
4 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-01-08 11:18 UTC (permalink / raw)
To: t-kristo
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, kishon,
linux-arm-kernel, Roger Quadros
From: Kishon Vijay Abraham I <kishon@ti.com>
Add DT nodes for all instances of WIZ and SERDES modules.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 241 ++++++++++++++++++++++
1 file changed, 241 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 1e4c2b78d66d..24cb78db28e4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -4,6 +4,7 @@
*
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
+#include <dt-bindings/phy/phy.h>
&cbass_main {
msmc_ram: sram@70000000 {
@@ -225,6 +226,246 @@
pinctrl-single,function-mask = <0xffffffff>;
};
+ dummy_cmn_refclk: dummy_cmn_refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ dummy_cmn_refclk1: dummy_cmn_refclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ serdes_wiz0: wiz@5000000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
+ assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5000000 0x0 0x5000000 0x10000>;
+
+ wiz0_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 292 11>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ wiz0_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 292 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 292 0>;
+ };
+
+ wiz0_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 292 11>, <&k3_clks 292 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz0_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 292 11>;
+ };
+
+ wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz0_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz0_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz0_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes0: serdes@5000000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5000000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz0 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz1: wiz@5010000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 293 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 293 5>, <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 293 13>, <&k3_clks 293 0>;
+ assigned-clock-parents = <&k3_clks 293 17>, <&k3_clks 293 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5010000 0x0 0x5010000 0x10000>;
+
+ wiz1_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ wiz1_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 293 0>;
+ };
+
+ wiz1_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 293 13>, <&k3_clks 293 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz1_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 293 13>;
+ };
+
+ wiz1_cmn_refclk_dig_div: cmn-refclk-dig-div{
+ clocks = <&wiz1_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz1_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz1_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes1: serdes@5010000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5010000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz1 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz1_cmn_refclk_dig_div>, <&wiz1_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 294 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 294 5>, <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 294 11>, <&k3_clks 294 0>;
+ assigned-clock-parents = <&k3_clks 294 15>, <&k3_clks 294 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5020000 0x0 0x5020000 0x10000>;
+
+ wiz2_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 294 11>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 294 11>;
+ };
+
+ wiz2_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 294 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 294 0>;
+ };
+
+ wiz2_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 294 11>, <&k3_clks 294 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz2_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 294 11>;
+ };
+
+ wiz2_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz2_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz2_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz2_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5020000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz2 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz2_cmn_refclk_dig_div>, <&wiz2_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
+ serdes_wiz3: wiz@5030000 {
+ compatible = "ti,j721e-wiz-16g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 295 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 295 5>, <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 295 9>, <&k3_clks 295 0>;
+ assigned-clock-parents = <&k3_clks 295 13>, <&k3_clks 295 4>;
+ num-lanes = <2>;
+ #reset-cells = <1>;
+ ranges = <0x5030000 0x0 0x5030000 0x10000>;
+
+ wiz3_pll0_refclk: pll0-refclk {
+ clocks = <&k3_clks 295 9>, <&dummy_cmn_refclk>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_pll0_refclk>;
+ assigned-clock-parents = <&k3_clks 295 9>;
+ };
+
+ wiz3_pll1_refclk: pll1-refclk {
+ clocks = <&k3_clks 295 0>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_pll1_refclk>;
+ assigned-clock-parents = <&k3_clks 295 0>;
+ };
+
+ wiz3_refclk_dig: refclk-dig {
+ clocks = <&k3_clks 295 9>, <&k3_clks 295 0>, <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
+ #clock-cells = <0>;
+ assigned-clocks = <&wiz3_refclk_dig>;
+ assigned-clock-parents = <&k3_clks 295 9>;
+ };
+
+ wiz3_cmn_refclk_dig_div: cmn-refclk-dig-div {
+ clocks = <&wiz3_refclk_dig>;
+ #clock-cells = <0>;
+ };
+
+ wiz3_cmn_refclk1_dig_div: cmn-refclk1-dig-div {
+ clocks = <&wiz3_pll1_refclk>;
+ #clock-cells = <0>;
+ };
+
+ serdes3: serdes@5030000 {
+ compatible = "ti,sierra-phy-t0";
+ reg-names = "serdes";
+ reg = <0x5030000 0x10000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ resets = <&serdes_wiz3 0>;
+ reset-names = "sierra_reset";
+ clocks = <&wiz3_cmn_refclk_dig_div>, <&wiz3_cmn_refclk1_dig_div>;
+ clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
+ };
+ };
+
main_uart0: serial@2800000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x02800000 0x00 0x100>;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-01-08 11:18 [PATCH 0/5] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
2020-01-08 11:18 ` [PATCH 1/5] arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes Roger Quadros
@ 2020-01-08 11:18 ` Roger Quadros
2020-01-15 1:47 ` Rob Herring
2020-01-08 11:18 ` [PATCH 3/5] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX Roger Quadros
` (2 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Roger Quadros @ 2020-01-08 11:18 UTC (permalink / raw)
To: t-kristo
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, kishon,
linux-arm-kernel, Roger Quadros
From: Kishon Vijay Abraham I <kishon@ti.com>
Add serdes_ln_ctrl node used for selecting SERDES lane mux.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++
include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
2 files changed, 79 insertions(+)
create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 24cb78db28e4..6741c1e67f50 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -5,6 +5,8 @@
* Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
*/
#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/mux/mux-j721e-wiz.h>
&cbass_main {
msmc_ram: sram@70000000 {
@@ -19,6 +21,30 @@
};
};
+ scm_conf: scm_conf@100000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0 0x00100000 0 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x0 0x0 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: serdes_ln_ctrl@4080 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
+ <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
+ /* SERDES4 lane0/1/2/3 select */
+ idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+ <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+ <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
+ <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
new file mode 100644
index 000000000000..fd1c4ea9fc7f
--- /dev/null
+++ b/include/dt-bindings/mux/mux-j721e-wiz.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * This header provides constants for J721E WIZ.
+ */
+
+#ifndef _DT_BINDINGS_J721E_WIZ
+#define _DT_BINDINGS_J721E_WIZ
+
+#define SERDES0_LANE0_QSGMII_LANE1 0x0
+#define SERDES0_LANE0_PCIE0_LANE0 0x1
+#define SERDES0_LANE0_USB3_0_SWAP 0x2
+
+#define SERDES0_LANE1_QSGMII_LANE2 0x0
+#define SERDES0_LANE1_PCIE0_LANE1 0x1
+#define SERDES0_LANE1_USB3_0 0x2
+
+#define SERDES1_LANE0_QSGMII_LANE3 0x0
+#define SERDES1_LANE0_PCIE1_LANE0 0x1
+#define SERDES1_LANE0_USB3_1_SWAP 0x2
+#define SERDES1_LANE0_SGMII_LANE0 0x3
+
+#define SERDES1_LANE1_QSGMII_LANE4 0x0
+#define SERDES1_LANE1_PCIE1_LANE1 0x1
+#define SERDES1_LANE1_USB3_1 0x2
+#define SERDES1_LANE1_SGMII_LANE1 0x3
+
+#define SERDES2_LANE0_PCIE2_LANE0 0x1
+#define SERDES2_LANE0_SGMII_LANE0 0x3
+#define SERDES2_LANE0_USB3_1_SWAP 0x2
+
+#define SERDES2_LANE1_PCIE2_LANE1 0x1
+#define SERDES2_LANE1_USB3_1 0x2
+#define SERDES2_LANE1_SGMII_LANE1 0x3
+
+#define SERDES3_LANE0_PCIE3_LANE0 0x1
+#define SERDES3_LANE0_USB3_0_SWAP 0x2
+
+#define SERDES3_LANE1_PCIE3_LANE1 0x1
+#define SERDES3_LANE1_USB3_0 0x2
+
+#define SERDES4_LANE0_EDP_LANE0 0x0
+#define SERDES4_LANE0_QSGMII_LANE5 0x2
+
+#define SERDES4_LANE1_EDP_LANE1 0x0
+#define SERDES4_LANE1_QSGMII_LANE6 0x2
+
+#define SERDES4_LANE2_EDP_LANE2 0x0
+#define SERDES4_LANE2_QSGMII_LANE7 0x2
+
+#define SERDES4_LANE3_EDP_LANE3 0x0
+#define SERDES4_LANE3_QSGMII_LANE8 0x2
+
+#endif /* _DT_BINDINGS_J721E_WIZ */
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-01-08 11:18 ` [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux Roger Quadros
@ 2020-01-15 1:47 ` Rob Herring
2020-01-21 5:13 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-01-15 1:47 UTC (permalink / raw)
To: Roger Quadros
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, kishon,
t-kristo, linux-arm-kernel
On Wed, Jan 08, 2020 at 01:18:27PM +0200, Roger Quadros wrote:
> From: Kishon Vijay Abraham I <kishon@ti.com>
>
> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: Roger Quadros <rogerq@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++
> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
> 2 files changed, 79 insertions(+)
> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> index 24cb78db28e4..6741c1e67f50 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> @@ -5,6 +5,8 @@
> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
> */
> #include <dt-bindings/phy/phy.h>
> +#include <dt-bindings/mux/mux.h>
> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>
> &cbass_main {
> msmc_ram: sram@70000000 {
> @@ -19,6 +21,30 @@
> };
> };
>
> + scm_conf: scm_conf@100000 {
Don't use '_' in node names.
> + compatible = "syscon", "simple-mfd";
Needs a specific compatible especially since the child node doesn't have
one.
> + reg = <0 0x00100000 0 0x1c000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x00100000 0x1c000>;
> +
> + serdes_ln_ctrl: serdes_ln_ctrl@4080 {
'reg' is needed if there's a unit-address. If there's a register range
with only the mux controls, then add 'reg'.
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
> + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
> + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
> + /* SERDES4 lane0/1/2/3 select */
> + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
> + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
> + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
> + <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
> + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
> + };
> + };
> +
> gic500: interrupt-controller@1800000 {
> compatible = "arm,gic-v3";
> #address-cells = <2>;
> diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
> new file mode 100644
> index 000000000000..fd1c4ea9fc7f
> --- /dev/null
> +++ b/include/dt-bindings/mux/mux-j721e-wiz.h
> @@ -0,0 +1,53 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * This header provides constants for J721E WIZ.
> + */
> +
> +#ifndef _DT_BINDINGS_J721E_WIZ
> +#define _DT_BINDINGS_J721E_WIZ
> +
> +#define SERDES0_LANE0_QSGMII_LANE1 0x0
> +#define SERDES0_LANE0_PCIE0_LANE0 0x1
> +#define SERDES0_LANE0_USB3_0_SWAP 0x2
> +
> +#define SERDES0_LANE1_QSGMII_LANE2 0x0
> +#define SERDES0_LANE1_PCIE0_LANE1 0x1
> +#define SERDES0_LANE1_USB3_0 0x2
> +
> +#define SERDES1_LANE0_QSGMII_LANE3 0x0
> +#define SERDES1_LANE0_PCIE1_LANE0 0x1
> +#define SERDES1_LANE0_USB3_1_SWAP 0x2
> +#define SERDES1_LANE0_SGMII_LANE0 0x3
> +
> +#define SERDES1_LANE1_QSGMII_LANE4 0x0
> +#define SERDES1_LANE1_PCIE1_LANE1 0x1
> +#define SERDES1_LANE1_USB3_1 0x2
> +#define SERDES1_LANE1_SGMII_LANE1 0x3
> +
> +#define SERDES2_LANE0_PCIE2_LANE0 0x1
> +#define SERDES2_LANE0_SGMII_LANE0 0x3
> +#define SERDES2_LANE0_USB3_1_SWAP 0x2
> +
> +#define SERDES2_LANE1_PCIE2_LANE1 0x1
> +#define SERDES2_LANE1_USB3_1 0x2
> +#define SERDES2_LANE1_SGMII_LANE1 0x3
> +
> +#define SERDES3_LANE0_PCIE3_LANE0 0x1
> +#define SERDES3_LANE0_USB3_0_SWAP 0x2
> +
> +#define SERDES3_LANE1_PCIE3_LANE1 0x1
> +#define SERDES3_LANE1_USB3_0 0x2
> +
> +#define SERDES4_LANE0_EDP_LANE0 0x0
> +#define SERDES4_LANE0_QSGMII_LANE5 0x2
> +
> +#define SERDES4_LANE1_EDP_LANE1 0x0
> +#define SERDES4_LANE1_QSGMII_LANE6 0x2
> +
> +#define SERDES4_LANE2_EDP_LANE2 0x0
> +#define SERDES4_LANE2_QSGMII_LANE7 0x2
> +
> +#define SERDES4_LANE3_EDP_LANE3 0x0
> +#define SERDES4_LANE3_QSGMII_LANE8 0x2
> +
> +#endif /* _DT_BINDINGS_J721E_WIZ */
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-01-15 1:47 ` Rob Herring
@ 2020-01-21 5:13 ` Kishon Vijay Abraham I
2020-01-21 17:57 ` Rob Herring
0 siblings, 1 reply; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-01-21 5:13 UTC (permalink / raw)
To: Rob Herring, Roger Quadros
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, t-kristo,
linux-arm-kernel
Hi Rob,
On 15/01/20 7:17 AM, Rob Herring wrote:
> On Wed, Jan 08, 2020 at 01:18:27PM +0200, Roger Quadros wrote:
>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>
>> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>>
>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++
>> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
>> 2 files changed, 79 insertions(+)
>> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> index 24cb78db28e4..6741c1e67f50 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>> @@ -5,6 +5,8 @@
>> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
>> */
>> #include <dt-bindings/phy/phy.h>
>> +#include <dt-bindings/mux/mux.h>
>> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>>
>> &cbass_main {
>> msmc_ram: sram@70000000 {
>> @@ -19,6 +21,30 @@
>> };
>> };
>>
>> + scm_conf: scm_conf@100000 {
>
> Don't use '_' in node names.
Okay.
>
>> + compatible = "syscon", "simple-mfd";
>
> Needs a specific compatible especially since the child node doesn't have
> one.
Child node has "mmio-mux" as compatible no? Are you referring to
something else here?
>
>> + reg = <0 0x00100000 0 0x1c000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0x0 0x0 0x00100000 0x1c000>;
>> +
>> + serdes_ln_ctrl: serdes_ln_ctrl@4080 {
>
> 'reg' is needed if there's a unit-address. If there's a register range
> with only the mux controls, then add 'reg'.
Sure, will add.
Thanks
Kishon
>
>> + compatible = "mmio-mux";
>> + #mux-control-cells = <1>;
>> + mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
>> + <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
>> + <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
>> + <0x40b0 0x3>, <0x40b4 0x3>, /* SERDES3 lane0/1 select */
>> + <0x40c0 0x3>, <0x40c4 0x3>, <0x40c8 0x3>, <0x40cc 0x3>;
>> + /* SERDES4 lane0/1/2/3 select */
>> + idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
>> + <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
>> + <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
>> + <MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
>> + <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
>> + };
>> + };
>> +
>> gic500: interrupt-controller@1800000 {
>> compatible = "arm,gic-v3";
>> #address-cells = <2>;
>> diff --git a/include/dt-bindings/mux/mux-j721e-wiz.h b/include/dt-bindings/mux/mux-j721e-wiz.h
>> new file mode 100644
>> index 000000000000..fd1c4ea9fc7f
>> --- /dev/null
>> +++ b/include/dt-bindings/mux/mux-j721e-wiz.h
>> @@ -0,0 +1,53 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * This header provides constants for J721E WIZ.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_J721E_WIZ
>> +#define _DT_BINDINGS_J721E_WIZ
>> +
>> +#define SERDES0_LANE0_QSGMII_LANE1 0x0
>> +#define SERDES0_LANE0_PCIE0_LANE0 0x1
>> +#define SERDES0_LANE0_USB3_0_SWAP 0x2
>> +
>> +#define SERDES0_LANE1_QSGMII_LANE2 0x0
>> +#define SERDES0_LANE1_PCIE0_LANE1 0x1
>> +#define SERDES0_LANE1_USB3_0 0x2
>> +
>> +#define SERDES1_LANE0_QSGMII_LANE3 0x0
>> +#define SERDES1_LANE0_PCIE1_LANE0 0x1
>> +#define SERDES1_LANE0_USB3_1_SWAP 0x2
>> +#define SERDES1_LANE0_SGMII_LANE0 0x3
>> +
>> +#define SERDES1_LANE1_QSGMII_LANE4 0x0
>> +#define SERDES1_LANE1_PCIE1_LANE1 0x1
>> +#define SERDES1_LANE1_USB3_1 0x2
>> +#define SERDES1_LANE1_SGMII_LANE1 0x3
>> +
>> +#define SERDES2_LANE0_PCIE2_LANE0 0x1
>> +#define SERDES2_LANE0_SGMII_LANE0 0x3
>> +#define SERDES2_LANE0_USB3_1_SWAP 0x2
>> +
>> +#define SERDES2_LANE1_PCIE2_LANE1 0x1
>> +#define SERDES2_LANE1_USB3_1 0x2
>> +#define SERDES2_LANE1_SGMII_LANE1 0x3
>> +
>> +#define SERDES3_LANE0_PCIE3_LANE0 0x1
>> +#define SERDES3_LANE0_USB3_0_SWAP 0x2
>> +
>> +#define SERDES3_LANE1_PCIE3_LANE1 0x1
>> +#define SERDES3_LANE1_USB3_0 0x2
>> +
>> +#define SERDES4_LANE0_EDP_LANE0 0x0
>> +#define SERDES4_LANE0_QSGMII_LANE5 0x2
>> +
>> +#define SERDES4_LANE1_EDP_LANE1 0x0
>> +#define SERDES4_LANE1_QSGMII_LANE6 0x2
>> +
>> +#define SERDES4_LANE2_EDP_LANE2 0x0
>> +#define SERDES4_LANE2_QSGMII_LANE7 0x2
>> +
>> +#define SERDES4_LANE3_EDP_LANE3 0x0
>> +#define SERDES4_LANE3_QSGMII_LANE8 0x2
>> +
>> +#endif /* _DT_BINDINGS_J721E_WIZ */
>> --
>> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
>> Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
>>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-01-21 5:13 ` Kishon Vijay Abraham I
@ 2020-01-21 17:57 ` Rob Herring
2020-01-22 5:05 ` Kishon Vijay Abraham I
0 siblings, 1 reply; 10+ messages in thread
From: Rob Herring @ 2020-01-21 17:57 UTC (permalink / raw)
To: Kishon Vijay Abraham I
Cc: Nishanth Menon, devicetree, Vignesh R, Sekhar Nori, linux-kernel,
Tero Kristo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Roger Quadros
On Mon, Jan 20, 2020 at 11:10 PM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>
> Hi Rob,
>
> On 15/01/20 7:17 AM, Rob Herring wrote:
> > On Wed, Jan 08, 2020 at 01:18:27PM +0200, Roger Quadros wrote:
> >> From: Kishon Vijay Abraham I <kishon@ti.com>
> >>
> >> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
> >>
> >> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> >> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> >> Signed-off-by: Roger Quadros <rogerq@ti.com>
> >> ---
> >> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++
> >> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
> >> 2 files changed, 79 insertions(+)
> >> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
> >>
> >> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> >> index 24cb78db28e4..6741c1e67f50 100644
> >> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> >> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
> >> @@ -5,6 +5,8 @@
> >> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
> >> */
> >> #include <dt-bindings/phy/phy.h>
> >> +#include <dt-bindings/mux/mux.h>
> >> +#include <dt-bindings/mux/mux-j721e-wiz.h>
> >>
> >> &cbass_main {
> >> msmc_ram: sram@70000000 {
> >> @@ -19,6 +21,30 @@
> >> };
> >> };
> >>
> >> + scm_conf: scm_conf@100000 {
> >
> > Don't use '_' in node names.
>
> Okay.
> >
> >> + compatible = "syscon", "simple-mfd";
> >
> > Needs a specific compatible especially since the child node doesn't have
> > one.
>
> Child node has "mmio-mux" as compatible no? Are you referring to
> something else here?
I'm referring to exactly what I quoted, but that's also a generic
compatible, so you'd never be able to match any of this block to a
specific driver or handle any quirks.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread* Re: [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux
2020-01-21 17:57 ` Rob Herring
@ 2020-01-22 5:05 ` Kishon Vijay Abraham I
0 siblings, 0 replies; 10+ messages in thread
From: Kishon Vijay Abraham I @ 2020-01-22 5:05 UTC (permalink / raw)
To: Rob Herring
Cc: Nishanth Menon, devicetree, Vignesh R, Sekhar Nori, linux-kernel,
Tero Kristo,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
Roger Quadros
Rob,
On 21/01/20 11:27 PM, Rob Herring wrote:
> On Mon, Jan 20, 2020 at 11:10 PM Kishon Vijay Abraham I <kishon@ti.com> wrote:
>>
>> Hi Rob,
>>
>> On 15/01/20 7:17 AM, Rob Herring wrote:
>>> On Wed, Jan 08, 2020 at 01:18:27PM +0200, Roger Quadros wrote:
>>>> From: Kishon Vijay Abraham I <kishon@ti.com>
>>>>
>>>> Add serdes_ln_ctrl node used for selecting SERDES lane mux.
>>>>
>>>> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
>>>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>>>> Signed-off-by: Roger Quadros <rogerq@ti.com>
>>>> ---
>>>> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 26 +++++++++++
>>>> include/dt-bindings/mux/mux-j721e-wiz.h | 53 +++++++++++++++++++++++
>>>> 2 files changed, 79 insertions(+)
>>>> create mode 100644 include/dt-bindings/mux/mux-j721e-wiz.h
>>>>
>>>> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> index 24cb78db28e4..6741c1e67f50 100644
>>>> --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
>>>> @@ -5,6 +5,8 @@
>>>> * Copyright (C) 2016-2019 Texas Instruments Incorporated - http://www.ti.com/
>>>> */
>>>> #include <dt-bindings/phy/phy.h>
>>>> +#include <dt-bindings/mux/mux.h>
>>>> +#include <dt-bindings/mux/mux-j721e-wiz.h>
>>>>
>>>> &cbass_main {
>>>> msmc_ram: sram@70000000 {
>>>> @@ -19,6 +21,30 @@
>>>> };
>>>> };
>>>>
>>>> + scm_conf: scm_conf@100000 {
>>>
>>> Don't use '_' in node names.
>>
>> Okay.
>>>
>>>> + compatible = "syscon", "simple-mfd";
>>>
>>> Needs a specific compatible especially since the child node doesn't have
>>> one.
>>
>> Child node has "mmio-mux" as compatible no? Are you referring to
>> something else here?
>
> I'm referring to exactly what I quoted, but that's also a generic
> compatible, so you'd never be able to match any of this block to a
> specific driver or handle any quirks.
Okay, right now we didn't see the need for a specific compatible but I
guess that is necessary to make it more future proof. Will add a
specific compatible.
Thanks
Kishon
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/5] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX
2020-01-08 11:18 [PATCH 0/5] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
2020-01-08 11:18 ` [PATCH 1/5] arm64: dts: ti: k3-j721e-main: Add WIZ and SERDES PHY nodes Roger Quadros
2020-01-08 11:18 ` [PATCH 2/5] arm64: dts: ti: k3-j721e-main: Add serdes_ln_ctrl node to select SERDES lane mux Roger Quadros
@ 2020-01-08 11:18 ` Roger Quadros
2020-01-08 11:18 ` [PATCH 4/5] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0 Roger Quadros
2020-01-08 11:18 ` [PATCH 5/5] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line Roger Quadros
4 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-01-08 11:18 UTC (permalink / raw)
To: t-kristo
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, kishon,
linux-arm-kernel, Roger Quadros
The USB controllers can be connected to one of the 2 SERDESes
using a MUX. Add a MUX controller node fot that.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 6741c1e67f50..7c60f8ec6365 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -43,6 +43,13 @@
<MUX_IDLE_AS_IS>, <SERDES3_LANE1_USB3_0>,
<SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
};
+
+ usb_serdes_mux: mux-controller@4000 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4000 0x8000000>, /* USB0 to SERDES0/3 mux */
+ <0x4010 0x8000000>; /* USB1 to SERDES1/2 mux */
+ };
};
gic500: interrupt-controller@1800000 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/5] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0
2020-01-08 11:18 [PATCH 0/5] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
` (2 preceding siblings ...)
2020-01-08 11:18 ` [PATCH 3/5] arm64: dts: ti: k3-j721e-main.dtsi: Add USB to SERDES MUX Roger Quadros
@ 2020-01-08 11:18 ` Roger Quadros
2020-01-08 11:18 ` [PATCH 5/5] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line Roger Quadros
4 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-01-08 11:18 UTC (permalink / raw)
To: t-kristo
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, kishon,
linux-arm-kernel, Roger Quadros
USB0 supports super-speed mode on the EVM. Enable that.
On the EVM, USB0 uses SERDES3 for super-speed lane.
Since USB0 is a type-C port, it needs to support lane swapping
for cable flip support. This is provided using SERDES lane
swap feature. Provide the Type-C cable orientation GPIO
to the SERDES Wrapper driver.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
.../dts/ti/k3-j721e-common-proc-board.dts | 32 +++++++++++++++++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 2a3cd6174504..4d180887342c 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -59,6 +59,7 @@
main_usbss0_pins_default: main_usbss0_pins_default {
pinctrl-single,pins = <
J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
+ J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
>;
};
@@ -257,16 +258,43 @@
status = "disabled";
};
+&usb_serdes_mux {
+ idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
+};
+
+&serdes_ln_ctrl {
+ idle-states = <SERDES0_LANE0_PCIE0_LANE0>, <SERDES0_LANE1_PCIE0_LANE1>,
+ <SERDES1_LANE0_PCIE1_LANE0>, <SERDES1_LANE1_PCIE1_LANE1>,
+ <SERDES2_LANE0_PCIE2_LANE0>, <SERDES2_LANE1_PCIE2_LANE1>,
+ <SERDES3_LANE0_USB3_0_SWAP>, <SERDES3_LANE1_USB3_0>,
+ <SERDES4_LANE0_EDP_LANE0>, <SERDES4_LANE1_EDP_LANE1>, <SERDES4_LANE2_EDP_LANE2>, <SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz3 {
+ typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+};
+
+&serdes3 {
+ serdes3_usb_link: link@0 {
+ reg = <0>;
+ cdns,num-lanes = <2>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_USB3>;
+ resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
+ };
+};
+
&usbss0 {
pinctrl-names = "default";
pinctrl-0 = <&main_usbss0_pins_default>;
- ti,usb2-only;
ti,vbus-divider;
};
&usb0 {
dr_mode = "otg";
- maximum-speed = "high-speed";
+ maximum-speed = "super-speed";
+ phys = <&serdes3_usb_link>;
+ phy-names = "cdns3,usb3-phy";
};
&usbss1 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/5] arm64: dts: k3-j721e-proc-board: Add wait time for sampling Type-C DIR line
2020-01-08 11:18 [PATCH 0/5] arm64: ti: k3-j721e: Add SERDES PHY and USB3.0 support Roger Quadros
` (3 preceding siblings ...)
2020-01-08 11:18 ` [PATCH 4/5] arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0 Roger Quadros
@ 2020-01-08 11:18 ` Roger Quadros
4 siblings, 0 replies; 10+ messages in thread
From: Roger Quadros @ 2020-01-08 11:18 UTC (permalink / raw)
To: t-kristo
Cc: nm, devicetree, vigneshr, nsekhar, linux-kernel, kishon,
linux-arm-kernel, Roger Quadros
The Type-C compainon chip on the board needs ~133ms (tCCB_DEFAULT)
to debounce the CC lines in order to detect attach and plug orientation
and reflect the correct DIR status. [1]
Let's wait for 300ms before sampling the Type-C DIR line.
[1] http://www.ti.com/lit/ds/symlink/tusb321.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 4d180887342c..1dc6fdc86bc5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -272,6 +272,7 @@
&serdes_wiz3 {
typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
+ typec-dir-debounce-ms = <300>; /* TUSB321, tCCB_DEFAULT 133 ms */
};
&serdes3 {
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 10+ messages in thread