* [PATCH v3 3/3] arm64: dts: mediatek: mt8167: add some DRM nodes
2021-04-06 11:36 [PATCH v3 1/3] arm64: dts: mediatek: mt8167: add larb nodes Fabien Parent
2021-04-06 11:36 ` [PATCH v3 2/3] arm64: dts: mediatek: mt8167: add iommu node Fabien Parent
@ 2021-04-06 11:36 ` Fabien Parent
2021-05-12 16:20 ` Matthias Brugger
2021-04-06 13:13 ` [PATCH v3 1/3] arm64: dts: mediatek: mt8167: add larb nodes Matthias Brugger
2 siblings, 1 reply; 5+ messages in thread
From: Fabien Parent @ 2021-04-06 11:36 UTC (permalink / raw)
To: Rob Herring, Matthias Brugger
Cc: mkorpershoek, Fabien Parent, devicetree, linux-arm-kernel,
linux-mediatek, linux-kernel
Add all the DRM nodes required to get DSI to work on MT8167 SoC.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
---
Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2
V3:
* Removed unicode character in commit summary
V2:
* No changes
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 149 +++++++++++++++++++++++
1 file changed, 149 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 9029051624a6..17942095944e 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -16,6 +16,19 @@
/ {
compatible = "mediatek,mt8167";
+ aliases {
+ aal0 = &aal;
+ ccorr0 = &ccorr;
+ color0 = &color;
+ dither0 = &dither;
+ dsi0 = &dsi;
+ ovl0 = &ovl0;
+ pwm0 = &disp_pwm;
+ rdma0 = &rdma0;
+ rdma1 = &rdma1;
+ wdma0 = &wdma;
+ };
+
soc {
topckgen: topckgen@10000000 {
compatible = "mediatek,mt8167-topckgen", "syscon";
@@ -114,6 +127,13 @@ vdecsys: syscon@16000000 {
#clock-cells = <1>;
};
+ mutex: mutex@14015000 {
+ compatible = "mediatek,mt8167-disp-mutex";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ };
+
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8167-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
@@ -126,6 +146,135 @@ pio: pinctrl@1000b000 {
interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
};
+ rdma1: rdma1@1400a000 {
+ compatible = "mediatek,mt8167-disp-rdma",
+ "mediatek,mt2701-disp-rdma";
+ reg = <0 0x1400a000 0 0x1000>;
+ interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb0>;
+ };
+
+ disp_pwm: disp_pwm@1100f000 {
+ compatible = "mediatek,mt8167-disp-pwm",
+ "mediatek,mt8173-disp-pwn";
+ reg = <0 0x1100f000 0 0x1000>;
+ #pwm-cells = <2>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&topckgen CLK_TOP_PWM_SEL>,
+ <&topckgen CLK_TOP_PWM_MM>,
+ <&mmsys CLK_MM_DISP_PWM_26M>,
+ <&mmsys CLK_MM_DISP_PWM_MM>;
+ clock-names = "pwm_sel",
+ "pwm_mm",
+ "main",
+ "mm";
+ status = "disabled";
+ };
+
+ dsi: dsi@14012000 {
+ compatible = "mediatek,mt8167-dsi",
+ "mediatek,mt2701-dsi";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DSI_ENGINE>,
+ <&mmsys CLK_MM_DSI_DIGITAL>,
+ <&mipi_tx>;
+ clock-names = "engine", "digital", "hs";
+ phys = <&mipi_tx>;
+ phy-names = "dphy";
+ status = "disabled";
+ };
+
+ mipi_tx: mipi_dphy@14018000 {
+ compatible = "mediatek,mt8167-mipi-tx",
+ "mediatek,mt2701-mipi-tx";
+ reg = <0 0x14018000 0 0x90>;
+ clocks = <&topckgen CLK_TOP_MIPI_26M_DBG>;
+ clock-output-names = "mipi_tx0_pll";
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ ovl0: ovl0@14007000 {
+ compatible = "mediatek,mt8167-disp-ovl",
+ "mediatek,mt8173-disp-ovl";
+ reg = <0 0x14007000 0 0x1000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ rdma0: rdma0@14009000 {
+ compatible = "mediatek,mt8167-disp-rdma",
+ "mediatek,mt2701-disp-rdma";
+ reg = <0 0x14009000 0 0x1000>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
+ color: color@1400c000 {
+ compatible = "mediatek,mt8167-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR>;
+ };
+
+ ccorr: ccorr@1400d000 {
+ compatible = "mediatek,mt8167-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_CCORR>;
+ };
+
+ aal: aal@1400e000 {
+ compatible = "mediatek,mt8167-disp-aal";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ };
+
+ gamma: gamma@1400f000 {
+ compatible = "mediatek,mt8167-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ };
+
+ dither: dither@14010000 {
+ compatible = "mediatek,mt8167-disp-dither";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_DITHER>;
+ };
+
+ wdma: wdma0@1400b000 {
+ compatible = "mediatek,mt8167-disp-wdma";
+ reg = <0 0x1400b000 0 0x1000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ };
+
mmsys: mmsys@14000000 {
compatible = "mediatek,mt8167-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
--
2.31.0
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^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3 1/3] arm64: dts: mediatek: mt8167: add larb nodes
2021-04-06 11:36 [PATCH v3 1/3] arm64: dts: mediatek: mt8167: add larb nodes Fabien Parent
2021-04-06 11:36 ` [PATCH v3 2/3] arm64: dts: mediatek: mt8167: add iommu node Fabien Parent
2021-04-06 11:36 ` [PATCH v3 3/3] arm64: dts: mediatek: mt8167: add some DRM nodes Fabien Parent
@ 2021-04-06 13:13 ` Matthias Brugger
2 siblings, 0 replies; 5+ messages in thread
From: Matthias Brugger @ 2021-04-06 13:13 UTC (permalink / raw)
To: Fabien Parent, Rob Herring
Cc: mkorpershoek, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel
On 06/04/2021 13:36, Fabien Parent wrote:
> Add larb nodes for MT8167:
> * larb0 is used for display (dsi and hdmi)
> * larb1 is used for camera (csi)
> * larb2 is used for the video hardware decoder
>
> Signed-off-by: Fabien Parent <fparent@baylibre.com>
Whole series applied to v5.12-next/dts64-2
Thanks!
> ---
>
> Note: This series is based on https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git/log/?h=v5.12-next/dts64-2
>
> V3:
> * Removed unicode character in commit summary
> V2:
> * Removed unneeded mediatek,larb-id property
>
> arch/arm64/boot/dts/mediatek/mt8167.dtsi | 30 ++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> index 4b951f81db9e..bbddd4b22d3e 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
> @@ -140,5 +140,35 @@ smi_common: smi@14017000 {
> clock-names = "apb", "smi";
> power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
> };
> +
> + larb0: larb@14016000 {
> + compatible = "mediatek,mt8167-smi-larb";
> + reg = <0 0x14016000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&mmsys CLK_MM_SMI_LARB0>,
> + <&mmsys CLK_MM_SMI_LARB0>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8167_POWER_DOMAIN_MM>;
> + };
> +
> + larb1: larb@15001000 {
> + compatible = "mediatek,mt8167-smi-larb";
> + reg = <0 0x15001000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&imgsys CLK_IMG_LARB1_SMI>,
> + <&imgsys CLK_IMG_LARB1_SMI>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8167_POWER_DOMAIN_ISP>;
> + };
> +
> + larb2: larb@16010000 {
> + compatible = "mediatek,mt8167-smi-larb";
> + reg = <0 0x16010000 0 0x1000>;
> + mediatek,smi = <&smi_common>;
> + clocks = <&vdecsys CLK_VDEC_CKEN>,
> + <&vdecsys CLK_VDEC_LARB1_CKEN>;
> + clock-names = "apb", "smi";
> + power-domains = <&spm MT8167_POWER_DOMAIN_VDEC>;
> + };
> };
> };
>
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^ permalink raw reply [flat|nested] 5+ messages in thread