* [PATCH v3 01/12] dt-bindings: mediatek: display: change txt to yaml file
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-16 17:47 ` Rob Herring
2021-07-15 17:37 ` [PATCH v3 02/12] dt-bindings: mediatek: display: add definition for mt8195 jason-jh.lin
` (10 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Change mediatek,dislpay.txt to mediatek,display.yaml.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.txt | 219 ---------
.../display/mediatek/mediatek,disp.yaml | 434 ++++++++++++++++++
2 files changed, 434 insertions(+), 219 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
deleted file mode 100644
index fbb59c9ddda6..000000000000
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
+++ /dev/null
@@ -1,219 +0,0 @@
-Mediatek display subsystem
-==========================
-
-The Mediatek display subsystem consists of various DISP function blocks in the
-MMSYS register space. The connections between them can be configured by output
-and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
-of frame signal are distributed to the other function blocks by a DISP_MUTEX
-function block.
-
-All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
-For a description of the MMSYS_CONFIG binding, see
-Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt.
-
-DISP function blocks
-====================
-
-A display stream starts at a source function block that reads pixel data from
-memory and ends with a sink function block that drives pixels on a display
-interface, or writes pixels back to memory. All DISP function blocks have
-their own register space, interrupt, and clock gate. The blocks that can
-access memory additionally have to list the IOMMU and local arbiter they are
-connected to.
-
-For a description of the display interface sink function blocks, see
-Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt and
-Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml.
-
-Required properties (all function blocks):
-- compatible: "mediatek,<chip>-disp-<function>", one of
- "mediatek,<chip>-disp-ovl" - overlay (4 layers, blending, csc)
- "mediatek,<chip>-disp-ovl-2l" - overlay (2 layers, blending, csc)
- "mediatek,<chip>-disp-rdma" - read DMA / line buffer
- "mediatek,<chip>-disp-wdma" - write DMA
- "mediatek,<chip>-disp-ccorr" - color correction
- "mediatek,<chip>-disp-color" - color processor
- "mediatek,<chip>-disp-dither" - dither
- "mediatek,<chip>-disp-aal" - adaptive ambient light controller
- "mediatek,<chip>-disp-gamma" - gamma correction
- "mediatek,<chip>-disp-merge" - merge streams from two RDMA sources
- "mediatek,<chip>-disp-postmask" - control round corner for display frame
- "mediatek,<chip>-disp-split" - split stream to two encoders
- "mediatek,<chip>-disp-ufoe" - data compression engine
- "mediatek,<chip>-dsi" - DSI controller, see mediatek,dsi.txt
- "mediatek,<chip>-dpi" - DPI controller, see mediatek,dpi.txt
- "mediatek,<chip>-disp-mutex" - display mutex
- "mediatek,<chip>-disp-od" - overdrive
- the supported chips are mt2701, mt7623, mt2712, mt8167, mt8173, mt8183 and mt8192.
-- reg: Physical base address and length of the function block register space
-- interrupts: The interrupt signal from the function block (required, except for
- merge and split function blocks).
-- clocks: device clocks
- See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
- For most function blocks this is just a single clock input. Only the DSI and
- DPI controller nodes have multiple clock inputs. These are documented in
- mediatek,dsi.txt and mediatek,dpi.txt, respectively.
- An exception is that the mt8183 mutex is always free running with no clocks property.
-
-Required properties (DMA function blocks):
-- compatible: Should be one of
- "mediatek,<chip>-disp-ovl"
- "mediatek,<chip>-disp-rdma"
- "mediatek,<chip>-disp-wdma"
- the supported chips are mt2701, mt8167 and mt8173.
-- larb: Should contain a phandle pointing to the local arbiter device as defined
- in Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
-- iommus: Should point to the respective IOMMU block with master port as
- argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
- for details.
-
-Optional properties (RDMA function blocks):
-- mediatek,rdma-fifo-size: rdma fifo size may be different even in same SOC, add this
- property to the corresponding rdma
- the value is the Max value which defined in hardware data sheet.
- mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
- mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
- mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
-
-Examples:
-
-mmsys: clock-controller@14000000 {
- compatible = "mediatek,mt8173-mmsys", "syscon";
- reg = <0 0x14000000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- #clock-cells = <1>;
-};
-
-ovl0: ovl@1400c000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400c000 0 0x1000>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL0>;
- iommus = <&iommu M4U_PORT_DISP_OVL0>;
- mediatek,larb = <&larb0>;
-};
-
-ovl1: ovl@1400d000 {
- compatible = "mediatek,mt8173-disp-ovl";
- reg = <0 0x1400d000 0 0x1000>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OVL1>;
- iommus = <&iommu M4U_PORT_DISP_OVL1>;
- mediatek,larb = <&larb4>;
-};
-
-rdma0: rdma@1400e000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400e000 0 0x1000>;
- interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA0>;
- iommus = <&iommu M4U_PORT_DISP_RDMA0>;
- mediatek,larb = <&larb0>;
- mediatek,rdma-fifosize = <8192>;
-};
-
-rdma1: rdma@1400f000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x1400f000 0 0x1000>;
- interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA1>;
- iommus = <&iommu M4U_PORT_DISP_RDMA1>;
- mediatek,larb = <&larb4>;
-};
-
-rdma2: rdma@14010000 {
- compatible = "mediatek,mt8173-disp-rdma";
- reg = <0 0x14010000 0 0x1000>;
- interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_RDMA2>;
- iommus = <&iommu M4U_PORT_DISP_RDMA2>;
- mediatek,larb = <&larb4>;
-};
-
-wdma0: wdma@14011000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14011000 0 0x1000>;
- interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA0>;
- iommus = <&iommu M4U_PORT_DISP_WDMA0>;
- mediatek,larb = <&larb0>;
-};
-
-wdma1: wdma@14012000 {
- compatible = "mediatek,mt8173-disp-wdma";
- reg = <0 0x14012000 0 0x1000>;
- interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_WDMA1>;
- iommus = <&iommu M4U_PORT_DISP_WDMA1>;
- mediatek,larb = <&larb4>;
-};
-
-color0: color@14013000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14013000 0 0x1000>;
- interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR0>;
-};
-
-color1: color@14014000 {
- compatible = "mediatek,mt8173-disp-color";
- reg = <0 0x14014000 0 0x1000>;
- interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_COLOR1>;
-};
-
-aal@14015000 {
- compatible = "mediatek,mt8173-disp-aal";
- reg = <0 0x14015000 0 0x1000>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_AAL>;
-};
-
-gamma@14016000 {
- compatible = "mediatek,mt8173-disp-gamma";
- reg = <0 0x14016000 0 0x1000>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_GAMMA>;
-};
-
-ufoe@1401a000 {
- compatible = "mediatek,mt8173-disp-ufoe";
- reg = <0 0x1401a000 0 0x1000>;
- interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_UFOE>;
-};
-
-dsi0: dsi@1401b000 {
- /* See mediatek,dsi.txt for details */
-};
-
-dpi0: dpi@1401d000 {
- /* See mediatek,dpi.txt for details */
-};
-
-mutex: mutex@14020000 {
- compatible = "mediatek,mt8173-disp-mutex";
- reg = <0 0x14020000 0 0x1000>;
- interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_MUTEX_32K>;
-};
-
-od@14023000 {
- compatible = "mediatek,mt8173-disp-od";
- reg = <0 0x14023000 0 0x1000>;
- power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
- clocks = <&mmsys CLK_MM_DISP_OD>;
-};
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
new file mode 100644
index 000000000000..63a6bc975b29
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -0,0 +1,434 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,disp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek Display Subsystem Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jason-JH Lin <jason-jh.lin@mediatek.com>
+
+description: |
+ The Mediatek display subsystem consists of various DISP function blocks in the
+ MMSYS register space. The connections between them can be configured by output
+ and input selectors in the MMSYS_CONFIG register space. Pixel clock and start
+ of frame signal are distributed to the other function blocks by a DISP_MUTEX
+ function block.
+ All DISP device tree nodes must be siblings to the central MMSYS_CONFIG node.
+ For a description of the MMSYS_CONFIG binding, see
+ Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details.
+
+ DISP function blocks
+ ====================
+ A display stream starts at a source function block that reads pixel data from
+ memory and ends with a sink function block that drives pixels on a display
+ interface, or writes pixels back to memory. All DISP function blocks have
+ their own register space, interrupt, and clock gate. The blocks that can
+ access memory additionally have to list the IOMMU and local arbiter they are
+ connected to.
+
+properties:
+ compatible:
+ description: |
+ If the display function block of different soc have the same function,
+ you can use the same compatible name after it.
+ For example, if mt8183 COLOR function is the same as mt8173, then the
+ compatible of mt8183 cholud be set as:
+ compatible = "mediatek,mt8183-disp-color", "mediatek,mt8173-disp-color";
+ oneOf:
+ # OVL: overlay (4 layers, blending, csc)
+ - items:
+ - const: mediatek,mt2701-disp-ovl
+ - items:
+ - const: mediatek,mt8173-disp-ovl
+ - items:
+ - const: mediatek,mt8183-disp-ovl
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-ovl
+ - mediatek,mt2712-disp-ovl
+ - enum:
+ - mediatek,mt2701-disp-ovl
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-ovl
+ - enum:
+ - mediatek,mt8183-disp-ovl
+
+ # OVL2L: overlay (2 layers, blending, csc)
+ - items:
+ - const: mediatek,mt8183-disp-ovl-2l
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-ovl-2l
+ - enum:
+ - mediatek,mt8183-disp-ovl-2l
+
+ # RDMA: read DMA / line buffer
+ - items:
+ - const: mediatek,mt2701-disp-rdma
+ - items:
+ - const: mediatek,mt8173-disp-rdma
+ - items:
+ - const: mediatek,mt8183-disp-rdma
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-rdma
+ - mediatek,mt2712-disp-rdma
+ - enum:
+ - mediatek,mt2701-disp-rdma
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-rdma
+ - enum:
+ - mediatek,mt8183-disp-rdma
+
+ # WDMA: write DMA
+ - items:
+ - const: mediatek,mt8173-disp-wdma
+
+ # CCORR: color correction
+ - items:
+ - const: mediatek,mt8183-disp-ccorr
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-ccorr
+ - enum:
+ - mediatek,mt8183-disp-ccorr
+
+ # COLOR: color processor
+ - items:
+ - const: mediatek,mt2701-disp-color
+ - items:
+ - const: mediatek,mt8167-disp-color
+ - items:
+ - const: mediatek,mt8173-disp-color
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-color
+ - mediatek,mt2712-disp-color
+ - enum:
+ - mediatek,mt2701-disp-color
+ - items:
+ - enum:
+ - mediatek,mt8183-disp-color
+ - mediatek,mt8192-disp-color
+ - enum:
+ - mediatek,mt8173-disp-color
+
+ # DITHER
+ - items:
+ - const: mediatek,mt8183-disp-dither
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-dither
+ - enum:
+ - mediatek,mt8183-disp-dither
+
+ # AAL: adaptive ambient light controller
+ - items:
+ - const: mediatek,mt8173-disp-aal
+ - items:
+ - enum:
+ - mediatek,mt2712-disp-aal
+ - mediatek,mt8183-disp-aal
+ - mediatek,mt8192-disp-aal
+ - enum:
+ - mediatek,mt8173-disp-aal
+
+ # GAMMA: gamma correction
+ - items:
+ - const: mediatek,mt8173-disp-gamma
+ - items:
+ - const: mediatek,mt8183-disp-gamma
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-gamma
+ - enum:
+ - mediatek,mt8183-disp-gamma
+
+ # MERGE: merge streams from two RDMA sources
+
+ # POSTMASK: control round corner for display frame
+ - items:
+ - const: mediatek,mt8192-disp-postmask
+
+ # SPLIT: split stream to two encoders
+
+ # UFOE: data compression engine
+ - items:
+ - const: mediatek,mt8173-disp-ufoe
+
+ # DSI: see Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt for details.
+ - items:
+ - const: mediatek,mt2701-disp-dsi
+ - items:
+ - const: mediatek,mt8173-disp-dsi
+ - items:
+ - const: mediatek,mt8183-disp-dsi
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-dsi
+ - mediatek,mt2712-disp-dsi
+ - enum:
+ - mediatek,mt2701-disp-dsi
+ - items:
+ - enum:
+ - mediatek,mt8192-disp-dsi
+ - enum:
+ - mediatek,mt8183-disp-dsi
+
+ # DPI: see Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml for details.
+ - items:
+ - const: mediatek,mt2701-disp-dpi
+ - items:
+ - const: mediatek,mt8173-disp-dpi
+ - items:
+ - const: mediatek,mt8183-disp-dpi
+ - items:
+ - const: mediatek,mt8192-disp-dpi
+ - items:
+ - enum:
+ - mediatek,mt7623-disp-dpi
+ - mediatek,mt2712-disp-dpi
+ - enum:
+ - mediatek,mt2701-disp-dpi
+
+ # MUTEX: display mutex
+ - items:
+ - const: mediatek,mt2701-disp-mutex
+ - items:
+ - const: mediatek,mt2712-disp-mutex
+ - items:
+ - const: mediatek,mt8167-disp-mutex
+ - items:
+ - const: mediatek,mt8173-disp-mutex
+ - items:
+ - const: mediatek,mt8183-disp-mutex
+ - items:
+ - const: mediatek,mt8192-disp-mutex
+
+ # OD: overdrive
+ - items:
+ - const: mediatek,mt2712-disp-od
+ - items:
+ - const: mediatek,mt8173-disp-od
+
+ reg:
+ description: Physical base address and length of the function block register space.
+
+ interrupts:
+ description: The interrupt signal from the function block required,
+ except for merge and split function blocks.
+
+ clocks:
+ description: clock drivers
+ See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
+ For most function blocks this is just a single clock input.
+ Only the DSI and DPI controller nodes have multiple clock inputs. These are documented
+ in mediatek,dsi.txt and mediatek,dpi.yaml, respectively.
+ An exception is that the mt8183 mutex is always free running with no clocks property.
+
+ mediatek,larb:
+ description: The compatible property should be one of DMA function blocks,
+ such as "mediatek,<chip>-disp-ovl", "mediatek,<chip>-disp-rdma" or
+ "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167 and mt8173.
+ Should contain a phandle pointing to the local arbiter device as defined in
+ Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
+ It must sort according to the local arbiter index, like larb0, larb1, larb2...
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 32
+
+ iommus:
+ description: The compatible property should be one of DMA function blocks,
+ such as "mediatek,<chip>-disp-ovl", "mediatek,<chip>-disp-rdma" or
+ "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167 and mt8173.
+ Should point to the respective IOMMU block with master port as argument, see
+ Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
+
+ mediatek,rdma-fifo-size:
+ description: RDMA function blocks
+ rdma fifo size may be different even in same SOC, add this property to the
+ corresponding rdma.
+ The value below is the Max value which defined in hardware data sheet
+ mediatek,rdma-fifo-size of mt8173-rdma0 is 8K
+ mediatek,rdma-fifo-size of mt8183-rdma0 is 5K
+ mediatek,rdma-fifo-size of mt8183-rdma1 is 2K
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [8*1024, 5*1024, 2*1024]
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mediatek,gce-client-reg:
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, such as gce node, subsys id, offset
+ and register size. The subsys id that is mapping to the register of display
+ function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ For example, The mediatek,gce-client-reg property of OVL in mt8173 is
+ <&gce SUBSYS_1400XXXX 0xc000 0x1000>.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+
+ ovl0: ovl@1400c000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400c000 0 0x1000>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL0>;
+ iommus = <&iommu M4U_PORT_DISP_OVL0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
+ };
+
+ ovl1: ovl@1400d000 {
+ compatible = "mediatek,mt8173-disp-ovl";
+ reg = <0 0x1400d000 0 0x1000>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OVL1>;
+ iommus = <&iommu M4U_PORT_DISP_OVL1>;
+ mediatek,larb = <&larb4>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
+ };
+
+ rdma0: rdma@1400e000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400e000 0 0x1000>;
+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,rdma-fifosize = <8192>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
+ };
+
+ rdma1: rdma@1400f000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x1400f000 0 0x1000>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA1>;
+ mediatek,larb = <&larb4>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
+ };
+
+ rdma2: rdma@14010000 {
+ compatible = "mediatek,mt8173-disp-rdma";
+ reg = <0 0x14010000 0 0x1000>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_RDMA2>;
+ iommus = <&iommu M4U_PORT_DISP_RDMA2>;
+ mediatek,larb = <&larb4>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0 0x1000>;
+ };
+
+ wdma0: wdma@14011000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14011000 0 0x1000>;
+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA0>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA0>;
+ mediatek,larb = <&larb0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
+ };
+
+ wdma1: wdma@14012000 {
+ compatible = "mediatek,mt8173-disp-wdma";
+ reg = <0 0x14012000 0 0x1000>;
+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_WDMA1>;
+ iommus = <&iommu M4U_PORT_DISP_WDMA1>;
+ mediatek,larb = <&larb4>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x2000 0x1000>;
+ };
+
+ color0: color@14013000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14013000 0 0x1000>;
+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x3000 0x1000>;
+ };
+
+ color1: color@14014000 {
+ compatible = "mediatek,mt8173-disp-color";
+ reg = <0 0x14014000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_COLOR1>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x4000 0x1000>;
+ };
+
+ aal@14015000 {
+ compatible = "mediatek,mt8173-disp-aal";
+ reg = <0 0x14015000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_AAL>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x5000 0x1000>;
+ };
+
+ gamma@14016000 {
+ compatible = "mediatek,mt8173-disp-gamma";
+ reg = <0 0x14016000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_GAMMA>;
+ mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x6000 0x1000>;
+ };
+
+ ufoe@1401a000 {
+ compatible = "mediatek,mt8173-disp-ufoe";
+ reg = <0 0x1401a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_UFOE>;
+ };
+
+ dsi0: dsi@1401b000 {
+ /* See mediatek,dsi.txt for details */
+ };
+
+ dpi0: dpi@1401d000 {
+ /* See mediatek,dpi.yaml for details */
+ };
+
+ mutex: mutex@14020000 {
+ compatible = "mediatek,mt8173-disp-mutex";
+ reg = <0 0x14020000 0 0x1000>;
+ interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_MUTEX_32K>;
+ };
+
+ od@14023000 {
+ compatible = "mediatek,mt8173-disp-od";
+ reg = <0 0x14023000 0 0x1000>;
+ power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
+ clocks = <&mmsys CLK_MM_DISP_OD>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 01/12] dt-bindings: mediatek: display: change txt to yaml file
2021-07-15 17:37 ` [PATCH v3 01/12] dt-bindings: mediatek: display: change txt to yaml file jason-jh.lin
@ 2021-07-16 17:47 ` Rob Herring
0 siblings, 0 replies; 22+ messages in thread
From: Rob Herring @ 2021-07-16 17:47 UTC (permalink / raw)
To: jason-jh.lin
Cc: Chun-Kuang Hu, Matthias Brugger, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, nancy.lin,
singo.chang
On Thu, Jul 15, 2021 at 11:43 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Change mediatek,dislpay.txt to mediatek,display.yaml.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../display/mediatek/mediatek,disp.txt | 219 ---------
> .../display/mediatek/mediatek,disp.yaml | 434 ++++++++++++++++++
> 2 files changed, 434 insertions(+), 219 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.txt
> create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
Please resend to DT list so that automated checks run and it's in my
review queue.
This is going to need to be split into a schema per block.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 02/12] dt-bindings: mediatek: display: add definition for mt8195
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 01/12] dt-bindings: mediatek: display: change txt to yaml file jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-16 6:14 ` Fei Shao
2021-07-15 17:37 ` [PATCH v3 03/12] dt-bindings: mediatek: display: add MERGE additional description jason-jh.lin
` (9 subsequent siblings)
11 siblings, 1 reply; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Add definition for mt8195 display.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../bindings/display/mediatek/mediatek,disp.yaml | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index 63a6bc975b29..910bb9ce61d6 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -54,6 +54,7 @@ properties:
- items:
- enum:
- mediatek,mt8192-disp-ovl
+ - mediatek,mt8195-disp-ovl
- enum:
- mediatek,mt8183-disp-ovl
@@ -82,6 +83,7 @@ properties:
- items:
- enum:
- mediatek,mt8192-disp-rdma
+ - mediatek,mt8195-disp-rdma
- enum:
- mediatek,mt8183-disp-rdma
@@ -95,6 +97,7 @@ properties:
- items:
- enum:
- mediatek,mt8192-disp-ccorr
+ - mediatek,mt8195-disp-ccorr
- enum:
- mediatek,mt8183-disp-ccorr
@@ -115,6 +118,7 @@ properties:
- enum:
- mediatek,mt8183-disp-color
- mediatek,mt8192-disp-color
+ - mediatek,mt8195-disp-color
- enum:
- mediatek,mt8173-disp-color
@@ -124,6 +128,7 @@ properties:
- items:
- enum:
- mediatek,mt8192-disp-dither
+ - mediatek,mt8195-disp-dither
- enum:
- mediatek,mt8183-disp-dither
@@ -135,6 +140,7 @@ properties:
- mediatek,mt2712-disp-aal
- mediatek,mt8183-disp-aal
- mediatek,mt8192-disp-aal
+ - mediatek,mt8195-disp-aal
- enum:
- mediatek,mt8173-disp-aal
@@ -146,10 +152,13 @@ properties:
- items:
- enum:
- mediatek,mt8192-disp-gamma
+ - mediatek,mt8195-disp-gamma
- enum:
- mediatek,mt8183-disp-gamma
# MERGE: merge streams from two RDMA sources
+ - items:
+ - const: mediatek,mt8195-disp-merge
# POSTMASK: control round corner for display frame
- items:
@@ -209,6 +218,7 @@ properties:
- const: mediatek,mt8183-disp-mutex
- items:
- const: mediatek,mt8192-disp-mutex
+ - const: mediatek,mt8195-disp-mutex
# OD: overdrive
- items:
@@ -234,7 +244,7 @@ properties:
mediatek,larb:
description: The compatible property should be one of DMA function blocks,
such as "mediatek,<chip>-disp-ovl", "mediatek,<chip>-disp-rdma" or
- "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167 and mt8173.
+ "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167, mt8173 and mt8195.
Should contain a phandle pointing to the local arbiter device as defined in
Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
It must sort according to the local arbiter index, like larb0, larb1, larb2...
@@ -245,7 +255,7 @@ properties:
iommus:
description: The compatible property should be one of DMA function blocks,
such as "mediatek,<chip>-disp-ovl", "mediatek,<chip>-disp-rdma" or
- "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167 and mt8173.
+ "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167, mt8173 and mt8195.
Should point to the respective IOMMU block with master port as argument, see
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 02/12] dt-bindings: mediatek: display: add definition for mt8195
2021-07-15 17:37 ` [PATCH v3 02/12] dt-bindings: mediatek: display: add definition for mt8195 jason-jh.lin
@ 2021-07-16 6:14 ` Fei Shao
0 siblings, 0 replies; 22+ messages in thread
From: Fei Shao @ 2021-07-16 6:14 UTC (permalink / raw)
To: jason-jh.lin
Cc: chunkuang.hu, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group, nancy.lin,
singo.chang
On Fri, Jul 16, 2021 at 1:38 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Add definition for mt8195 display.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../bindings/display/mediatek/mediatek,disp.yaml | 14 ++++++++++++--
> 1 file changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> index 63a6bc975b29..910bb9ce61d6 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
> @@ -54,6 +54,7 @@ properties:
> - items:
> - enum:
> - mediatek,mt8192-disp-ovl
> + - mediatek,mt8195-disp-ovl
> - enum:
> - mediatek,mt8183-disp-ovl
>
> @@ -82,6 +83,7 @@ properties:
> - items:
> - enum:
> - mediatek,mt8192-disp-rdma
> + - mediatek,mt8195-disp-rdma
Make mediatek,mt8195-disp-rdma an individual item to align with the dts change.
> - enum:
> - mediatek,mt8183-disp-rdma
>
> @@ -95,6 +97,7 @@ properties:
> - items:
> - enum:
> - mediatek,mt8192-disp-ccorr
> + - mediatek,mt8195-disp-ccorr
> - enum:
> - mediatek,mt8183-disp-ccorr
>
> @@ -115,6 +118,7 @@ properties:
> - enum:
> - mediatek,mt8183-disp-color
> - mediatek,mt8192-disp-color
> + - mediatek,mt8195-disp-color
> - enum:
> - mediatek,mt8173-disp-color
>
> @@ -124,6 +128,7 @@ properties:
> - items:
> - enum:
> - mediatek,mt8192-disp-dither
> + - mediatek,mt8195-disp-dither
> - enum:
> - mediatek,mt8183-disp-dither
>
> @@ -135,6 +140,7 @@ properties:
> - mediatek,mt2712-disp-aal
> - mediatek,mt8183-disp-aal
> - mediatek,mt8192-disp-aal
> + - mediatek,mt8195-disp-aal
> - enum:
> - mediatek,mt8173-disp-aal
>
> @@ -146,10 +152,13 @@ properties:
> - items:
> - enum:
> - mediatek,mt8192-disp-gamma
> + - mediatek,mt8195-disp-gamma
> - enum:
> - mediatek,mt8183-disp-gamma
>
> # MERGE: merge streams from two RDMA sources
> + - items:
> + - const: mediatek,mt8195-disp-merge
>
> # POSTMASK: control round corner for display frame
> - items:
> @@ -209,6 +218,7 @@ properties:
> - const: mediatek,mt8183-disp-mutex
> - items:
> - const: mediatek,mt8192-disp-mutex
> + - const: mediatek,mt8195-disp-mutex
>
> # OD: overdrive
> - items:
> @@ -234,7 +244,7 @@ properties:
> mediatek,larb:
> description: The compatible property should be one of DMA function blocks,
> such as "mediatek,<chip>-disp-ovl", "mediatek,<chip>-disp-rdma" or
> - "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167 and mt8173.
> + "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167, mt8173 and mt8195.
> Should contain a phandle pointing to the local arbiter device as defined in
> Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml.
> It must sort according to the local arbiter index, like larb0, larb1, larb2...
> @@ -245,7 +255,7 @@ properties:
> iommus:
> description: The compatible property should be one of DMA function blocks,
> such as "mediatek,<chip>-disp-ovl", "mediatek,<chip>-disp-rdma" or
> - "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167 and mt8173.
> + "mediatek,<chip>-disp-wdma". The supported chips are mt2701, mt8167, mt8173 and mt8195.
> Should point to the respective IOMMU block with master port as argument, see
> Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
>
> --
> 2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 03/12] dt-bindings: mediatek: display: add MERGE additional description
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 01/12] dt-bindings: mediatek: display: change txt to yaml file jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 02/12] dt-bindings: mediatek: display: add definition for mt8195 jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 04/12] dt-bindings: mediatek: add DSC definition for mt8195 jason-jh.lin
` (8 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
1. clock drivers of MERGE
The MERGE controller may have 2 clock inputs.
The second clock of MERGE is async clock which is controlling
the async buffer between MERGE and other display function blocks.
2. MERGE fifo settings enable
The setting of merge fifo is mainly provided for the display
latency buffer. To ensure that the back-end panel display data
will not be underrun, a little more data is needed in the fifo.
According to the merge fifo settings, when the water level is
detected to be insufficient, it will trigger RDMA sending
ultra and preulra command to SMI to speed up the data rate.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../bindings/display/mediatek/mediatek,disp.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index 910bb9ce61d6..8beeb9c3c057 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -237,6 +237,9 @@ properties:
description: clock drivers
See Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
For most function blocks this is just a single clock input.
+ The MERGE controller may have 2 clock inputs. The second clock of MERGE is async clock,
+ which is controlling the synchronous process between MERGE and other display function
+ blocks cross clock domain.
Only the DSI and DPI controller nodes have multiple clock inputs. These are documented
in mediatek,dsi.txt and mediatek,dpi.yaml, respectively.
An exception is that the mt8183 mutex is always free running with no clocks property.
@@ -270,6 +273,15 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8*1024, 5*1024, 2*1024]
+ mediatek,merge-fifo-en:
+ description: MERGE fifo settings enable
+ The setting of merge fifo is mainly provided for the display latency buffer.
+ To ensure that the back-end panel display data will not be underrun,
+ a little more data is needed in the fifo. According to the merge fifo settings,
+ when the water level is detected to be insufficient, it will trigger RDMA sending
+ ultra and preulra command to SMI to speed up the data rate.
+ type: boolean
+
power-domains:
description: A phandle and PM domain specifier as defined by bindings of
the power controller specified by phandle. See
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 04/12] dt-bindings: mediatek: add DSC definition for mt8195
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (2 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 03/12] dt-bindings: mediatek: display: add MERGE additional description jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file jason-jh.lin
` (7 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
1. Add DSC definition file for mt8195 display.
2. Add mediatek,dsc.yaml to decribe DSC module in details.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../display/mediatek/mediatek,disp.yaml | 8 ++
.../display/mediatek/mediatek,dsc.yaml | 73 +++++++++++++++++++
2 files changed, 81 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
index 8beeb9c3c057..aac1796e3f6b 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,disp.yaml
@@ -156,6 +156,10 @@ properties:
- enum:
- mediatek,mt8183-disp-gamma
+ # DSC: see Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml for details.
+ - items:
+ - const: mediatek,mt8195-disp-dsc
+
# MERGE: merge streams from two RDMA sources
- items:
- const: mediatek,mt8195-disp-merge
@@ -453,4 +457,8 @@ examples:
clocks = <&mmsys CLK_MM_DISP_OD>;
};
+ dsc0: disp_dsc_wrap@1c009000 {
+ /* See mediatek,dsc.yaml for details */
+ };
+
...
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
new file mode 100644
index 000000000000..f575532bfb21
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsc.yaml
@@ -0,0 +1,73 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,dsc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek DSC Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jitao shi <jitao.shi@mediatek.com>
+ - Jason-JH Lin <jason-jh.lin@mediatek.com>
+
+description: |
+ The DSC standard is a specification of the algorithms used for
+ compressing and decompressing image display streams, including
+ the specification of the syntax and semantics of the compressed
+ video bit stream. DSC is designed for real-time systems with
+ real-time compression, transmission, decompression and Display.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: mediatek,mt8195-disp-dsc
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: DSC Wrapper Clock
+
+ power-domains:
+ description: A phandle and PM domain specifier as defined by bindings of
+ the power controller specified by phandle. See
+ Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+ mediatek,gce-client-reg:
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, such as gce node, subsys id, offset
+ and register size. The subsys id that is mapping to the register of display
+ function blocks is defined in the gce header
+ include/include/dt-bindings/gce/<chip>-gce.h of each chips.
+ For example, The mediatek,gce-client-reg property of OVL in mt8173 is
+ <&gce SUBSYS_1400XXXX 0xc000 0x1000>.
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (3 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 04/12] dt-bindings: mediatek: add DSC definition for mt8195 jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-16 7:46 ` Fei Shao
2021-07-16 17:42 ` Rob Herring
2021-07-15 17:37 ` [PATCH v3 06/12] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
` (6 subsequent siblings)
11 siblings, 2 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Change mediatek,mmsys.txt to mediatek,mmsys.yaml
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,mmsys.txt | 32 ------
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 102 ++++++++++++++++++
2 files changed, 102 insertions(+), 32 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
deleted file mode 100644
index 9712a6831fab..000000000000
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Mediatek mmsys controller
-============================
-
-The Mediatek mmsys system controller provides clock control, routing control,
-and miscellaneous control in mmsys partition.
-
-Required Properties:
-
-- compatible: Should be one of:
- - "mediatek,mt2701-mmsys", "syscon"
- - "mediatek,mt2712-mmsys", "syscon"
- - "mediatek,mt6765-mmsys", "syscon"
- - "mediatek,mt6779-mmsys", "syscon"
- - "mediatek,mt6797-mmsys", "syscon"
- - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
- - "mediatek,mt8167-mmsys", "syscon"
- - "mediatek,mt8173-mmsys", "syscon"
- - "mediatek,mt8183-mmsys", "syscon"
- - "mediatek,mt8192-mmsys", "syscon"
-- #clock-cells: Must be 1
-
-For the clock control, the mmsys controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-mmsys: syscon@14000000 {
- compatible = "mediatek,mt8173-mmsys", "syscon";
- reg = <0 0x14000000 0 0x1000>;
- #clock-cells = <1>;
-};
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
new file mode 100644
index 000000000000..ea31c7c2792c
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: mediatek mmsys Controller Device Tree Bindings
+
+maintainers:
+ - CK Hu <ck.hu@mediatek.com>
+ - Jason-JH Lin <jason-jh.lin@mediatek.com>
+
+description: |
+ The Mediatek mmsys system controller provides clock control, routing control,
+ and miscellaneous control in mmsys partition.
+
+properties:
+ compatible:
+ description: |
+ If the mmsys controller of different soc have the same function,
+ you can use the same compatible name after it.
+ For example, if the function of mt2701 mmsys controller is the same as syscon,
+ then the compatible property could be set as:
+ compatible = "mediatek,mt2701-mmsys", "syscon";
+ oneOf:
+ - items:
+ - const: syscon
+ - items:
+ - enum:
+ - mediatek,mt2701-mmsys
+ - mediatek,mt7623-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt2712-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt6779-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt6797-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt8167-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt8173-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt8183-mmsys
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt8192-mmsys
+ - enum:
+ - syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ description: |
+ For the clock control, the mmsys controller uses the common clk binding from
+ Documentation/devicetree/bindings/clock/clock-bindings.txt
+ The available clocks are defined in dt-bindings/clock/mt*-clk.h
+ const: 1
+
+ mboxes:
+ description: |
+ Client use mailbox to communicate with GCE, it should have this
+ property and list of phandle with mailbox specifiers as defined in
+ Documentation/devicetree/bindings/mailbox/mtk-gce.txt
+
+required:
+ - compatible
+ - reg
+ - '#clocks-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt8173-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file
2021-07-15 17:37 ` [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file jason-jh.lin
@ 2021-07-16 7:46 ` Fei Shao
2021-07-16 17:42 ` Rob Herring
1 sibling, 0 replies; 22+ messages in thread
From: Fei Shao @ 2021-07-16 7:46 UTC (permalink / raw)
To: jason-jh.lin
Cc: chunkuang.hu, Matthias Brugger, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group, nancy.lin,
singo.chang
On Fri, Jul 16, 2021 at 1:48 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Change mediatek,mmsys.txt to mediatek,mmsys.yaml
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../bindings/arm/mediatek/mediatek,mmsys.txt | 32 ------
> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 102 ++++++++++++++++++
> 2 files changed, 102 insertions(+), 32 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> deleted file mode 100644
> index 9712a6831fab..000000000000
> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> +++ /dev/null
> @@ -1,32 +0,0 @@
> -Mediatek mmsys controller
> -============================
> -
> -The Mediatek mmsys system controller provides clock control, routing control,
> -and miscellaneous control in mmsys partition.
> -
> -Required Properties:
> -
> -- compatible: Should be one of:
> - - "mediatek,mt2701-mmsys", "syscon"
> - - "mediatek,mt2712-mmsys", "syscon"
> - - "mediatek,mt6765-mmsys", "syscon"
> - - "mediatek,mt6779-mmsys", "syscon"
> - - "mediatek,mt6797-mmsys", "syscon"
> - - "mediatek,mt7623-mmsys", "mediatek,mt2701-mmsys", "syscon"
> - - "mediatek,mt8167-mmsys", "syscon"
> - - "mediatek,mt8173-mmsys", "syscon"
> - - "mediatek,mt8183-mmsys", "syscon"
> - - "mediatek,mt8192-mmsys", "syscon"
> -- #clock-cells: Must be 1
> -
> -For the clock control, the mmsys controller uses the common clk binding from
> -Documentation/devicetree/bindings/clock/clock-bindings.txt
> -The available clocks are defined in dt-bindings/clock/mt*-clk.h.
> -
> -Example:
> -
> -mmsys: syscon@14000000 {
> - compatible = "mediatek,mt8173-mmsys", "syscon";
> - reg = <0 0x14000000 0 0x1000>;
> - #clock-cells = <1>;
> -};
> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> new file mode 100644
> index 000000000000..ea31c7c2792c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
> @@ -0,0 +1,102 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: mediatek mmsys Controller Device Tree Bindings
> +
> +maintainers:
> + - CK Hu <ck.hu@mediatek.com>
> + - Jason-JH Lin <jason-jh.lin@mediatek.com>
> +
> +description: |
> + The Mediatek mmsys system controller provides clock control, routing control,
> + and miscellaneous control in mmsys partition.
> +
> +properties:
> + compatible:
> + description: |
> + If the mmsys controller of different soc have the same function,
> + you can use the same compatible name after it.
> + For example, if the function of mt2701 mmsys controller is the same as syscon,
> + then the compatible property could be set as:
> + compatible = "mediatek,mt2701-mmsys", "syscon";
> + oneOf:
> + - items:
> + - const: syscon
> + - items:
> + - enum:
> + - mediatek,mt2701-mmsys
> + - mediatek,mt7623-mmsys
> + - enum:
> + - syscon
Not a yaml expert but I think it's:
- items:
- enum:
- mediatek,mt7623-mmsys
- enum:
- mediatek,mt2701-mmsys
- enum:
- syscon
> + - items:
> + - enum:
> + - mediatek,mt2712-mmsys
> + - enum:
> + - syscon
> + - items:
> + - enum:
> + - mediatek,mt6779-mmsys
> + - enum:
> + - syscon
> + - items:
> + - enum:
> + - mediatek,mt6797-mmsys
> + - enum:
> + - syscon
> + - items:
> + - enum:
> + - mediatek,mt8167-mmsys
> + - enum:
> + - syscon
> + - items:
> + - enum:
> + - mediatek,mt8173-mmsys
> + - enum:
> + - syscon
> + - items:
> + - enum:
> + - mediatek,mt8183-mmsys
> + - enum:
> + - syscon
> + - items:
> + - enum:
> + - mediatek,mt8192-mmsys
> + - enum:
> + - syscon
Just
- enum:
- mediatek,mt2712-mmsys
...
- mediatek,mt8192-mmsys
- enum:
- syscon
Fei
> +
> + reg:
> + maxItems: 1
> +
> + '#clock-cells':
> + description: |
> + For the clock control, the mmsys controller uses the common clk binding from
> + Documentation/devicetree/bindings/clock/clock-bindings.txt
> + The available clocks are defined in dt-bindings/clock/mt*-clk.h
> + const: 1
> +
> + mboxes:
> + description: |
> + Client use mailbox to communicate with GCE, it should have this
> + property and list of phandle with mailbox specifiers as defined in
> + Documentation/devicetree/bindings/mailbox/mtk-gce.txt
> +
> +required:
> + - compatible
> + - reg
> + - '#clocks-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> +
> + mmsys: syscon@14000000 {
> + compatible = "mediatek,mt8173-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> +...
> --
> 2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file
2021-07-15 17:37 ` [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file jason-jh.lin
2021-07-16 7:46 ` Fei Shao
@ 2021-07-16 17:42 ` Rob Herring
1 sibling, 0 replies; 22+ messages in thread
From: Rob Herring @ 2021-07-16 17:42 UTC (permalink / raw)
To: jason-jh.lin, Matthias Brugger
Cc: Chun-Kuang Hu, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, nancy.lin,
singo.chang
On Thu, Jul 15, 2021 at 11:55 AM jason-jh.lin <jason-jh.lin@mediatek.com> wrote:
>
> Change mediatek,mmsys.txt to mediatek,mmsys.yaml
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> .../bindings/arm/mediatek/mediatek,mmsys.txt | 32 ------
> .../bindings/arm/mediatek/mediatek,mmsys.yaml | 102 ++++++++++++++++++
> 2 files changed, 102 insertions(+), 32 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt
> create mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
There's already a reviewed patch for this[1]. Not sure why it isn't applied?
Rob
[1] https://lore.kernel.org/lkml/20210519161847.3747352-1-fparent@baylibre.com/
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 06/12] dt-bindings: arm: mediatek: add definition for mt8195 mmsys
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (4 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 05/12] dt-bindings: arm: mediatek: change mmsys txt to yaml file jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 07/12] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
` (5 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
There are 2 display hardware path in mt8195, namely vdosys0 and
vdosys1, so add their definition in mtk-mmsys documentation.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
.../bindings/arm/mediatek/mediatek,mmsys.yaml | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index ea31c7c2792c..e6cd6e2173d4 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -66,6 +66,16 @@ properties:
- mediatek,mt8192-mmsys
- enum:
- syscon
+ - items:
+ - enum:
+ - mediatek,mt8195-vdosys0
+ - enum:
+ - syscon
+ - items:
+ - enum:
+ - mediatek,mt8195-vdosys1
+ - enum:
+ - syscon
reg:
maxItems: 1
@@ -99,4 +109,18 @@ examples:
#clock-cells = <1>;
};
+ vdosys0: syscon@1c01a000 {
+ compatible = "mediatek,mt8195-vdosys0", "syscon";
+ reg = <0 0x1c01a000 0 0x1000>;
+ #clock-cells = <1>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
+ };
+
+ vdosys1: syscon@1c100000 {
+ compatible = "mediatek,mt8195-vdosys1", "syscon";
+ reg = <0 0x1c100000 0 0x1000>;
+ #clock-cells = <1>;
+ mboxes = <&gce1 1 CMDQ_THR_PRIO_4>;
+ };
+
...
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 07/12] arm64: dts: mt8195: add display node for vdosys0
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (5 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 06/12] dt-bindings: arm: mediatek: add definition for mt8195 mmsys jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
` (4 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Add display node for vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
This patch is based on [1][2][3]
[1]arm64: dts: Add Mediatek SoC MT8195 and evaluation board dts and Makefile
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210601075350.31515-2-seiya.wang@mediatek.com/
[2]arm64: dts: mt8195: add IOMMU and smi nodes
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210615173233.26682-15-tinghan.shen@mediatek.com/
[3]arm64: dts: mt8195: add gce node
- https://patchwork.kernel.org/project/linux-mediatek/patch/20210705053429.4380-4-jason-jh.lin@mediatek.com/
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++
1 file changed, 111 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 04d3e95175fa..aa2a7849b822 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1155,9 +1155,120 @@
#clock-cells = <1>;
};
+ ovl0: disp_ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl",
+ "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: disp_rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: disp_color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color",
+ "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: disp_ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr",
+ "mediatek,mt8183-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: disp_aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal",
+ "mediatek,mt8173-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: disp_gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma",
+ "mediatek,mt8173-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: disp_dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither",
+ "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: disp_dsc_wrap@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: disp_vpp_merge0@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg =
+ <&gce1 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: disp_mutex0@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ reg-names = "vdo0_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ clock-names = "vdo0_mutex";
+ mediatek,gce-events =
+ <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-vdosys0", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce1 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (6 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 07/12] arm64: dts: mt8195: add display node for vdosys0 jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 09/12] soc: mediatek: add mtk-mutex " jason-jh.lin
` (3 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Add mt8195 vdosys0 clock driver name and routing table to
the driver data of mtk-mmsys.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/soc/mediatek/mt8195-mmsys.h | 191 +++++++++++++++++++++++++
drivers/soc/mediatek/mtk-mmsys.c | 11 ++
include/linux/soc/mediatek/mtk-mmsys.h | 10 ++
3 files changed, 212 insertions(+)
create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..73e9e8286d50
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN 0xf14
+#define MOUT_DISP_OVL0_TO_DISP_RDMA0 BIT(0)
+#define MOUT_DISP_OVL0_TO_DISP_WDMA0 BIT(1)
+#define MOUT_DISP_OVL0_TO_DISP_OVL1 BIT(2)
+#define MOUT_DISP_OVL1_TO_DISP_RDMA1 BIT(4)
+#define MOUT_DISP_OVL1_TO_DISP_WDMA1 BIT(5)
+#define MOUT_DISP_OVL1_TO_DISP_OVL0 BIT(6)
+
+#define MT8195_VDO0_SEL_IN 0xf34
+#define SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT (0 << 0)
+#define SEL_IN_VPP_MERGE_FROM_DISP_DITHER1 (1 << 0)
+#define SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0 (2 << 0)
+#define SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0 (0 << 4)
+#define SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE (1 << 4)
+#define SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1 (0 << 5)
+#define SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE (1 << 5)
+#define SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE (0 << 8)
+#define SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT (1 << 8)
+#define SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT (0 << 9)
+#define SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT (0 << 12)
+#define SEL_IN_DP_INTF0_FROM_VPP_MERGE (1 << 12)
+#define SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0 (2 << 12)
+#define SEL_IN_DSI0_FROM_DSC_WRAP0_OUT (0 << 16)
+#define SEL_IN_DSI0_FROM_DISP_DITHER0 (1 << 16)
+#define SEL_IN_DSI1_FROM_DSC_WRAP1_OUT (0 << 17)
+#define SEL_IN_DSI1_FROM_VPP_MERGE (1 << 17)
+#define SEL_IN_DISP_WDMA1_FROM_DISP_OVL1 (0 << 20)
+#define SEL_IN_DISP_WDMA1_FROM_VPP_MERGE (1 << 20)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN (0 << 21)
+#define SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1 (1 << 21)
+#define SEL_IN_DISP_WDMA0_FROM_DISP_OVL0 (0 << 22)
+#define SEL_IN_DISP_WDMA0_FROM_VPP_MERGE (1 << 22)
+
+#define MT8195_VDO0_SEL_OUT 0xf38
+#define SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN (0 << 0)
+#define SOUT_DISP_DITHER0_TO_DSI0 (1 << 0)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN (0 << 1)
+#define SOUT_DISP_DITHER1_TO_VPP_MERGE (1 << 1)
+#define SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT (2 << 1)
+#define SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE (0 << 4)
+#define SOUT_VDO1_VIRTUAL0_TO_DP_INTF0 (1 << 4)
+#define SOUT_VPP_MERGE_TO_DSI1 (0 << 8)
+#define SOUT_VPP_MERGE_TO_DP_INTF0 (1 << 8)
+#define SOUT_VPP_MERGE_TO_SINA_VIRTUAL0 (2 << 8)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA1 (3 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP0_IN (4 << 8)
+#define SOUT_VPP_MERGE_TO_DSC_WRAP1_IN (0 << 11)
+#define SOUT_VPP_MERGE_TO_DISP_WDMA0 (1 << 11)
+#define SOUT_DSC_WRAP0_OUT_TO_DSI0 (0 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0 (1 << 12)
+#define SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE (2 << 12)
+#define SOUT_DSC_WRAP1_OUT_TO_DSI1 (0 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_DP_INTF0 (1 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
+#define SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
+
+#define MT8195_VDO1_VPP3_ASYNC_SOUT 0xf54
+#define SOUT_TO_VPP_MERGE0_P0_SEL (0 << 0)
+#define SOUT_TO_VPP_MERGE0_P1_SEL (1 << 0)
+
+#define MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL 0xf40
+#define SOUT_TO_HDR_VDO_FE0 (0 << 0)
+
+#define MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL 0xf44
+#define SOUT_TO_HDR_VDO_FE1 (0 << 0)
+
+#define MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL 0xf48
+#define SOUT_TO_HDR_GFX_FE0 (0 << 0)
+
+#define MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL 0xf4c
+#define SOUT_TO_HDR_GFX_FE1 (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SOUT_SEL 0xf58
+#define MIXER_IN1_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SOUT_SEL 0xf5c
+#define MIXER_IN2_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SOUT_SEL 0xf60
+#define MIXER_IN3_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SOUT_SEL 0xf64
+#define MIXER_IN4_SOUT_TO_DISP_MIXER (0 << 0)
+
+#define MT8195_VDO1_MIXER_OUT_SOUT_SEL 0xf34
+#define MIXER_SOUT_TO_HDR_VDO_BE0 (0 << 0)
+
+#define MT8195_VDO1_MERGE4_SOUT_SEL 0xf18
+#define MERGE4_SOUT_TO_VDOSYS0 (0 << 0)
+#define MERGE4_SOUT_TO_DPI0_SEL (1 << 0)
+#define MERGE4_SOUT_TO_DPI1_SEL (2 << 0)
+#define MERGE4_SOUT_TO_DP_INTF0_SEL (3 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
+#define VPP_MERGE0_P0_SEL_IN_FROM_SVPP2 (0 << 0)
+#define VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE0_P1_SEL_IN 0xf08
+#define VPP_MERGE0_P1_SEL_IN_FROM_SVPP3 (0 << 0)
+#define VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1 (1 << 0)
+
+#define MT8195_VDO1_VPP_MERGE1_P0_SEL_IN 0xf3c
+#define VPP_MERGE1_P0_SEL_IN_FROM_VPP3_ASYNC_SOUT (0 << 0)
+#define VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2 (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN1_SEL_IN 0xf24
+#define MIXER_IN1_SEL_IN_FROM_HDR_VDO_FE0 (0 << 0)
+#define MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN2_SEL_IN 0xf28
+#define MIXER_IN2_SEL_IN_FROM_HDR_VDO_FE1 (0 << 0)
+#define MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN3_SEL_IN 0xf2c
+#define MIXER_IN3_SEL_IN_FROM_HDR_GFX_FE0 (0 << 0)
+#define MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_IN4_SEL_IN 0xf30
+#define MIXER_IN4_SEL_IN_FROM_HDR_GFX_FE1 (0 << 0)
+#define MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT (1 << 0)
+
+#define MT8195_VDO1_MIXER_SOUT_SEL_IN 0xf68
+#define MIXER_SOUT_SEL_IN_FROM_DISP_MIXER (0 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN1_SOUT (1 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN2_SOUT (2 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN3_SOUTR (3 << 0)
+#define MIXER_SOUT_SEL_IN_FROM_MIXER_IN4_SOUTR (4 << 0)
+
+#define MT8195_VDO1_MERGE4_ASYNC_SEL_IN 0xf50
+#define MERGE4_ASYNC_SEL_IN_FROM_HDR_VDO_BE0 (0 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT (1 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE0_ASYNC_SOUT (2 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE1_ASYNC_SOUT (3 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE2_ASYNC_SOUT (4 << 0)
+#define MERGE4_ASYNC_SEL_IN_FROM_MERGE3_ASYNC_SOUT (5 << 0)
+
+#define MT8195_VDO1_DISP_DPI0_SEL_IN 0xf0c
+#define DISP_DPI0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
+#define DISP_DPI0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+
+#define MT8195_VDO1_DISP_DPI1_SEL_IN 0xf10
+#define DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
+#define DISP_DPI1_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+
+#define MT8195_VDO1_DISP_DP_INTF0_SEL_IN 0xf14
+#define DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT (0 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_MERGE_DL_ASYNC_MOUT (1 << 0)
+#define DISP_DP_INTF0_SEL_IN_FROM_VDO0_DSC_DL_ASYNC_MOUT (2 << 0)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+ {
+ DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+ MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL0_TO_DISP_RDMA0
+ }, {
+ DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+ MT8195_VDO0_OVL_MOUT_EN, MOUT_DISP_OVL1_TO_DISP_RDMA1
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_IN, SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_IN, SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_IN, SEL_IN_DSI0_FROM_DISP_DITHER0
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+ MT8195_VDO0_SEL_OUT, SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+ }, {
+ DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, DDP_COMPONENT_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+ MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_DSI0
+ }, {
+ DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+ MT8195_VDO0_SEL_OUT, SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+ }
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 080660ef11bf..1fb241750897 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -13,6 +13,7 @@
#include "mtk-mmsys.h"
#include "mt8167-mmsys.h"
#include "mt8183-mmsys.h"
+#include "mt8195-mmsys.h"
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.clk_driver = "clk-mt2701-mm",
@@ -52,6 +53,12 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.num_routes = ARRAY_SIZE(mmsys_mt8183_routing_table),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .clk_driver = "clk-mt8195-vdo0",
+ .routes = mmsys_mt8195_routing_table,
+ .num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
struct mtk_mmsys {
void __iomem *regs;
const struct mtk_mmsys_driver_data *data;
@@ -157,6 +164,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = {
.compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data,
},
+ {
+ .compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data,
+ },
{ }
};
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 2228bf6133da..34cb605e5df9 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -39,6 +39,16 @@ enum mtk_ddp_comp_id {
DDP_COMPONENT_UFOE,
DDP_COMPONENT_WDMA0,
DDP_COMPONENT_WDMA1,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_MERGE1,
+ DDP_COMPONENT_MERGE2,
+ DDP_COMPONENT_MERGE3,
+ DDP_COMPONENT_MERGE4,
+ DDP_COMPONENT_MERGE5,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_DSC1,
+ DDP_COMPONENT_DSC1_VIRTUAL0,
+ DDP_COMPONENT_DP_INTF0,
DDP_COMPONENT_ID_MAX,
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 09/12] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (7 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 08/12] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 10/12] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
` (2 subsequent siblings)
11 siblings, 0 replies; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Add mtk-mutex support for mt8195 vdosys0.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/soc/mediatek/mtk-mutex.c | 93 ++++++++++++++++++++++++++++++--
1 file changed, 90 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 2e4bcc300576..cb8bbf7f3fd8 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
#define MT8183_MUTEX0_MOD0 0x30
#define MT8183_MUTEX0_SOF0 0x2c
+#define MT8195_DISP_MUTEX0_MOD0 0x30
+#define MT8195_DISP_MUTEX0_SOF 0x2c
+
#define DISP_REG_MUTEX_EN(n) (0x20 + 0x20 * (n))
#define DISP_REG_MUTEX(n) (0x24 + 0x20 * (n))
#define DISP_REG_MUTEX_RST(n) (0x28 + 0x20 * (n))
@@ -67,6 +70,36 @@
#define MT8173_MUTEX_MOD_DISP_PWM1 24
#define MT8173_MUTEX_MOD_DISP_OD 25
+#define MT8195_MUTEX_MOD_DISP_OVL0 0
+#define MT8195_MUTEX_MOD_DISP_WDMA0 1
+#define MT8195_MUTEX_MOD_DISP_RDMA0 2
+#define MT8195_MUTEX_MOD_DISP_COLOR0 3
+#define MT8195_MUTEX_MOD_DISP_CCORR0 4
+#define MT8195_MUTEX_MOD_DISP_AAL0 5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0 6
+#define MT8195_MUTEX_MOD_DISP_DITHER0 7
+#define MT8195_MUTEX_MOD_DISP_DSI0 8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0 9
+#define MT8195_MUTEX_MOD_DISP_OVL1 10
+#define MT8195_MUTEX_MOD_DISP_WDMA1 11
+#define MT8195_MUTEX_MOD_DISP_RDMA1 12
+#define MT8195_MUTEX_MOD_DISP_COLOR1 13
+#define MT8195_MUTEX_MOD_DISP_CCORR1 14
+#define MT8195_MUTEX_MOD_DISP_AAL1 15
+#define MT8195_MUTEX_MOD_DISP_GAMMA1 16
+#define MT8195_MUTEX_MOD_DISP_DITHER1 17
+#define MT8195_MUTEX_MOD_DISP_DSI1 18
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE1 19
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE 20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0 21
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY0 22
+#define MT8195_MUTEX_MOD_DISP_VPP1_DL_RELAY1 23
+#define MT8195_MUTEX_MOD_DISP_VDO1_DL_RELAY2 24
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY3 25
+#define MT8195_MUTEX_MOD_DISP_VDO0_DL_RELAY4 26
+#define MT8195_MUTEX_MOD_DISP_PWM0 27
+#define MT8195_MUTEX_MOD_DISP_PWM1 28
+
#define MT2712_MUTEX_MOD_DISP_PWM2 10
#define MT2712_MUTEX_MOD_DISP_OVL0 11
#define MT2712_MUTEX_MOD_DISP_OVL1 12
@@ -101,12 +134,27 @@
#define MT2712_MUTEX_SOF_DSI3 6
#define MT8167_MUTEX_SOF_DPI0 2
#define MT8167_MUTEX_SOF_DPI1 3
+
#define MT8183_MUTEX_SOF_DSI0 1
#define MT8183_MUTEX_SOF_DPI0 2
#define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6)
#define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_SOF_DSI0 1
+#define MT8195_MUTEX_SOF_DSI1 2
+#define MT8195_MUTEX_SOF_DP_INTF0 3
+#define MT8195_MUTEX_SOF_DP_INTF1 4
+#define MT8195_MUTEX_SOF_DPI0 6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1 5 /* for digital video out */
+
+#define MT8195_MUTEX_EOF_DSI0 (MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1 (MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0 (MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1 (MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0 (MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1 (MT8195_MUTEX_SOF_DPI1 << 7)
+
struct mtk_mutex {
int id;
bool claimed;
@@ -120,6 +168,9 @@ enum mtk_mutex_sof_id {
MUTEX_SOF_DPI1,
MUTEX_SOF_DSI2,
MUTEX_SOF_DSI3,
+ MUTEX_SOF_DP_INTF0,
+ MUTEX_SOF_DP_INTF1,
+ DDP_MUTEX_SOF_MAX,
};
struct mtk_mutex_data {
@@ -214,7 +265,22 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_WDMA0] = MT8183_MUTEX_MOD_DISP_WDMA0,
};
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+ [DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+ [DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+ [DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+ [DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+ [DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+ [DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+ [DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+ [DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+ [DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+ [DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+ [DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+ [DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -224,7 +290,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
};
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -232,12 +298,24 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
};
/* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
};
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+ [MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+ [MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+ [MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+ [MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+ [MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+ [MUTEX_SOF_DP_INTF0] =
+ MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+ [MUTEX_SOF_DP_INTF1] =
+ MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
static const struct mtk_mutex_data mt2701_mutex_driver_data = {
.mutex_mod = mt2701_mutex_mod,
.mutex_sof = mt2712_mutex_sof,
@@ -275,6 +353,13 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = {
.no_clk = true,
};
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+ .mutex_mod = mt8195_mutex_mod,
+ .mutex_sof = mt8195_mutex_sof,
+ .mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+ .mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
struct mtk_mutex *mtk_mutex_get(struct device *dev)
{
struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -507,6 +592,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
.data = &mt8173_mutex_driver_data},
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = &mt8183_mutex_driver_data},
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = &mt8195_mutex_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply related [flat|nested] 22+ messages in thread* [PATCH v3 10/12] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (8 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 09/12] soc: mediatek: add mtk-mutex " jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-16 4:35 ` CK Hu
2021-07-15 17:37 ` [PATCH v3 11/12] drm/mediatek: add DSC " jason-jh.lin
2021-07-15 17:37 ` [PATCH v3 12/12] drm/mediatek: add MERGE " jason-jh.lin
11 siblings, 1 reply; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24 ++++++++++++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 728aaadfea8c..00e9827acefe 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
.fifo_size = 5 * SZ_1K,
};
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+ .fifo_size = 1920,
+};
+
static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
{ .compatible = "mediatek,mt2701-disp-rdma",
.data = &mt2701_rdma_driver_data},
@@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
.data = &mt8173_rdma_driver_data},
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = &mt8183_rdma_driver_data},
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = &mt8195_rdma_driver_data},
{},
};
MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index b46bdb8985da..d6f6d1bdad85 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
DDP_COMPONENT_DPI0,
};
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+ DDP_COMPONENT_OVL0,
+ DDP_COMPONENT_RDMA0,
+ DDP_COMPONENT_COLOR0,
+ DDP_COMPONENT_CCORR,
+ DDP_COMPONENT_AAL0,
+ DDP_COMPONENT_GAMMA,
+ DDP_COMPONENT_DITHER,
+ DDP_COMPONENT_DSC0,
+ DDP_COMPONENT_MERGE0,
+ DDP_COMPONENT_DP_INTF0,
+};
+
static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
.main_path = mt2701_mtk_ddp_main,
.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
};
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+ .main_path = mt8195_mtk_ddp_main,
+ .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
static int mtk_drm_kms_init(struct drm_device *drm)
{
struct mtk_drm_private *private = drm->dev_private;
@@ -410,6 +428,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8183-disp-rdma",
.data = (void *)MTK_DISP_RDMA },
+ { .compatible = "mediatek,mt8195-disp-rdma",
+ .data = (void *)MTK_DISP_RDMA },
{ .compatible = "mediatek,mt8173-disp-wdma",
.data = (void *)MTK_DISP_WDMA },
{ .compatible = "mediatek,mt8183-disp-ccorr",
@@ -448,6 +468,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt8183-disp-mutex",
.data = (void *)MTK_DISP_MUTEX },
+ { .compatible = "mediatek,mt8195-disp-mutex",
+ .data = (void *)MTK_DISP_MUTEX },
{ .compatible = "mediatek,mt2701-disp-pwm",
.data = (void *)MTK_DISP_BLS },
{ .compatible = "mediatek,mt8173-disp-pwm",
@@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
.data = &mt8173_mmsys_driver_data},
{ .compatible = "mediatek,mt8183-mmsys",
.data = &mt8183_mmsys_driver_data},
+ {.compatible = "mediatek,mt8195-vdosys0",
+ .data = &mt8195_vdosys0_driver_data},
{ }
};
MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
--
2.18.0
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 10/12] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195
2021-07-15 17:37 ` [PATCH v3 10/12] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
@ 2021-07-16 4:35 ` CK Hu
0 siblings, 0 replies; 22+ messages in thread
From: CK Hu @ 2021-07-16 4:35 UTC (permalink / raw)
To: jason-jh.lin
Cc: chunkuang.hu, matthias.bgg, linux-arm-kernel, linux-mediatek,
linux-kernel, Project_Global_Chrome_Upstream_Group, fshao,
nancy.lin, singo.chang
Hi, Jason:
On Fri, 2021-07-16 at 01:37 +0800, jason-jh.lin wrote:
> Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 ++++++
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 24 ++++++++++++++++++++++++
> 2 files changed, 30 insertions(+)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> index 728aaadfea8c..00e9827acefe 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
> @@ -355,6 +355,10 @@ static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
> .fifo_size = 5 * SZ_1K,
> };
>
> +static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
> + .fifo_size = 1920,
> +};
> +
> static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> { .compatible = "mediatek,mt2701-disp-rdma",
> .data = &mt2701_rdma_driver_data},
> @@ -362,6 +366,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
> .data = &mt8173_rdma_driver_data},
> { .compatible = "mediatek,mt8183-disp-rdma",
> .data = &mt8183_rdma_driver_data},
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = &mt8195_rdma_driver_data},
> {},
> };
> MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index b46bdb8985da..d6f6d1bdad85 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -147,6 +147,19 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_ext[] = {
> DDP_COMPONENT_DPI0,
> };
>
> +static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
> + DDP_COMPONENT_OVL0,
> + DDP_COMPONENT_RDMA0,
> + DDP_COMPONENT_COLOR0,
> + DDP_COMPONENT_CCORR,
> + DDP_COMPONENT_AAL0,
> + DDP_COMPONENT_GAMMA,
> + DDP_COMPONENT_DITHER,
> + DDP_COMPONENT_DSC0,
> + DDP_COMPONENT_MERGE0,
> + DDP_COMPONENT_DP_INTF0,
Where is the dp_intf sub driver in this series?
Regards,
CK
> +};
> +
> static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
> .main_path = mt2701_mtk_ddp_main,
> .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
> @@ -186,6 +199,11 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
> .ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
> };
>
> +static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
> + .main_path = mt8195_mtk_ddp_main,
> + .main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
> +};
> +
> static int mtk_drm_kms_init(struct drm_device *drm)
> {
> struct mtk_drm_private *private = drm->dev_private;
> @@ -410,6 +428,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8183-disp-rdma",
> .data = (void *)MTK_DISP_RDMA },
> + { .compatible = "mediatek,mt8195-disp-rdma",
> + .data = (void *)MTK_DISP_RDMA },
> { .compatible = "mediatek,mt8173-disp-wdma",
> .data = (void *)MTK_DISP_WDMA },
> { .compatible = "mediatek,mt8183-disp-ccorr",
> @@ -448,6 +468,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt8183-disp-mutex",
> .data = (void *)MTK_DISP_MUTEX },
> + { .compatible = "mediatek,mt8195-disp-mutex",
> + .data = (void *)MTK_DISP_MUTEX },
> { .compatible = "mediatek,mt2701-disp-pwm",
> .data = (void *)MTK_DISP_BLS },
> { .compatible = "mediatek,mt8173-disp-pwm",
> @@ -468,6 +490,8 @@ static const struct of_device_id mtk_drm_of_ids[] = {
> .data = &mt8173_mmsys_driver_data},
> { .compatible = "mediatek,mt8183-mmsys",
> .data = &mt8183_mmsys_driver_data},
> + {.compatible = "mediatek,mt8195-vdosys0",
> + .data = &mt8195_vdosys0_driver_data},
> { }
> };
> MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
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^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 11/12] drm/mediatek: add DSC support for MT8195
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (9 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 10/12] drm/mediatek: add mediatek-drm of vdosys0 support for MT8195 jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 23:21 ` Chun-Kuang Hu
2021-07-15 17:37 ` [PATCH v3 12/12] drm/mediatek: add MERGE " jason-jh.lin
11 siblings, 1 reply; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
Add DSC module file:
DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_dsc.c | 161 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 19 ++-
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
7 files changed, 194 insertions(+), 5 deletions(-)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index dc54a7a69005..44948e221fd3 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -2,6 +2,7 @@
mediatek-drm-y := mtk_disp_ccorr.o \
mtk_disp_color.o \
+ mtk_disp_dsc.o \
mtk_disp_gamma.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index cafd9df2d63b..c7e9bd370acd 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -33,6 +33,14 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
void mtk_dpi_start(struct device *dev);
void mtk_dpi_stop(struct device *dev);
+int mtk_dsc_clk_enable(struct device *dev);
+void mtk_dsc_clk_disable(struct device *dev);
+void mtk_dsc_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_dsc_start(struct device *dev);
+void mtk_dsc_stop(struct device *dev);
+
void mtk_dsi_ddp_start(struct device *dev);
void mtk_dsi_ddp_stop(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
new file mode 100644
index 000000000000..6a196220c532
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_gem.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_DSC_CON 0x0000
+#define DSC_EN BIT(0)
+#define DSC_DUAL_INOUT BIT(2)
+#define DSC_BYPASS BIT(4)
+#define DSC_UFOE_SEL BIT(16)
+
+/**
+ * struct mtk_disp_dsc - DISP_DSC driver structure
+ * @clk - clk of dsc hardware
+ * @regs - hardware register address of dsc
+ * @cmdq_reg - structure containing cmdq hardware resource
+ */
+struct mtk_disp_dsc {
+ struct clk *clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+};
+
+void mtk_dsc_start(struct device *dev)
+{
+ struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+ void __iomem *baddr = dsc->regs;
+
+ mtk_ddp_write_mask(NULL, DSC_EN, &dsc->cmdq_reg, baddr,
+ DISP_REG_DSC_CON, DSC_EN);
+}
+
+void mtk_dsc_stop(struct device *dev)
+{
+ struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+ void __iomem *baddr = dsc->regs;
+
+ mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
+ DISP_REG_DSC_CON, DSC_EN);
+}
+
+int mtk_dsc_clk_enable(struct device *dev)
+{
+ struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+ return clk_prepare_enable(dsc->clk);
+}
+
+void mtk_dsc_clk_disable(struct device *dev)
+{
+ struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+ clk_disable_unprepare(dsc->clk);
+}
+
+void mtk_dsc_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *handle)
+{
+ struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
+
+ /* dsc bypass mode */
+ mtk_ddp_write_mask(handle, DSC_BYPASS, &dsc->cmdq_reg, dsc->regs,
+ DISP_REG_DSC_CON, DSC_BYPASS);
+ mtk_ddp_write_mask(handle, DSC_UFOE_SEL, &dsc->cmdq_reg, dsc->regs,
+ DISP_REG_DSC_CON, DSC_UFOE_SEL);
+ mtk_ddp_write_mask(handle, DSC_DUAL_INOUT, &dsc->cmdq_reg, dsc->regs,
+ DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_dsc_component_ops = {
+ .bind = mtk_disp_dsc_bind,
+ .unbind = mtk_disp_dsc_unbind,
+};
+
+static int mtk_disp_dsc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_dsc *priv;
+ int irq;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get dsc clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap dsc\n");
+ return PTR_ERR(priv->regs);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_dsc_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_dsc_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-dsc", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
+
+struct platform_driver mtk_disp_dsc_driver = {
+ .probe = mtk_disp_dsc_probe,
+ .remove = mtk_disp_dsc_remove,
+ .driver = {
+ .name = "mediatek-disp-dsc",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_dsc_driver_dt_match,
+ },
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 75bc00e17fc4..ba3d7a1ce7ab 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
.layer_config = mtk_rdma_layer_config,
};
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+ .config = mtk_dsc_config,
+ .start = mtk_dsc_start,
+ .stop = mtk_dsc_stop,
+ .clk_enable = mtk_dsc_clk_enable,
+ .clk_disable = mtk_dsc_clk_disable,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -356,6 +364,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_MUTEX] = "mutex",
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
+ [MTK_DISP_DSC] = "dsc",
};
struct mtk_ddp_comp_match {
@@ -374,6 +383,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
[DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
[DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
+ [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
+ [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
+ [DDP_COMPONENT_DSC1_VIRTUAL0] = { MTK_DISP_DSC, -1, &ddp_dsc },
[DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
[DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
@@ -508,13 +520,14 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
if (type == MTK_DISP_BLS ||
type == MTK_DISP_CCORR ||
type == MTK_DISP_COLOR ||
+ type == MTK_DISP_DSC ||
type == MTK_DISP_GAMMA ||
- type == MTK_DPI ||
- type == MTK_DSI ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
- type == MTK_DISP_RDMA)
+ type == MTK_DISP_RDMA ||
+ type == MTK_DPI ||
+ type == MTK_DSI)
return 0;
priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index bb914d976cf5..661fb620e266 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_MUTEX,
MTK_DISP_OD,
MTK_DISP_BLS,
+ MTK_DISP_DSC,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index d6f6d1bdad85..990a54049a7d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -446,6 +446,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_GAMMA, },
{ .compatible = "mediatek,mt8183-disp-dither",
.data = (void *)MTK_DISP_DITHER },
+ { .compatible = "mediatek,mt8195-disp-dsc",
+ .data = (void *)MTK_DISP_DSC },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
@@ -562,12 +564,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
*/
if (comp_type == MTK_DISP_CCORR ||
comp_type == MTK_DISP_COLOR ||
+ comp_type == MTK_DISP_DSC ||
comp_type == MTK_DISP_GAMMA ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
- comp_type == MTK_DSI ||
- comp_type == MTK_DPI) {
+ comp_type == MTK_DPI ||
+ comp_type == MTK_DSI) {
dev_info(dev, "Adding component match for %pOF\n",
node);
drm_of_component_match_add(dev, &match, compare_of,
@@ -662,6 +665,7 @@ static struct platform_driver mtk_drm_platform_driver = {
static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_ccorr_driver,
&mtk_disp_color_driver,
+ &mtk_disp_dsc_driver,
&mtk_disp_gamma_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 637f5669e895..8b722330ef7d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
+extern struct platform_driver mtk_disp_dsc_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 11/12] drm/mediatek: add DSC support for MT8195
2021-07-15 17:37 ` [PATCH v3 11/12] drm/mediatek: add DSC " jason-jh.lin
@ 2021-07-15 23:21 ` Chun-Kuang Hu
2021-07-23 2:45 ` Jason-JH Lin
0 siblings, 1 reply; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-07-15 23:21 UTC (permalink / raw)
To: jason-jh.lin
Cc: Chun-Kuang Hu, Matthias Brugger, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, Nancy Lin,
singo.chang
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月16日 週五 上午1:38寫道：
>
> Add DSC module file:
> DSC is designed for real-time systems with real-time compression,
> transmission, decompression and display.
> The DSC standard is a specification of the algorithms used for
> compressing and decompressing image display streams, including
> the specification of the syntax and semantics of the compressed
> video bit stream.
>
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_dsc.c | 161 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 19 ++-
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 7 files changed, 194 insertions(+), 5 deletions(-)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index dc54a7a69005..44948e221fd3 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -2,6 +2,7 @@
>
> mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_disp_color.o \
> + mtk_disp_dsc.o \
> mtk_disp_gamma.o \
> mtk_disp_ovl.o \
> mtk_disp_rdma.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index cafd9df2d63b..c7e9bd370acd 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -33,6 +33,14 @@ void mtk_dither_set_common(void __iomem *regs, struct cmdq_client_reg *cmdq_reg,
> void mtk_dpi_start(struct device *dev);
> void mtk_dpi_stop(struct device *dev);
>
> +int mtk_dsc_clk_enable(struct device *dev);
> +void mtk_dsc_clk_disable(struct device *dev);
> +void mtk_dsc_config(struct device *dev, unsigned int width,
> + unsigned int height, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_dsc_start(struct device *dev);
> +void mtk_dsc_stop(struct device *dev);
> +
> void mtk_dsi_ddp_start(struct device *dev);
> void mtk_dsi_ddp_stop(struct device *dev);
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> new file mode 100644
> index 000000000000..6a196220c532
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> @@ -0,0 +1,161 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_gem.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_DSC_CON 0x0000
> +#define DSC_EN BIT(0)
> +#define DSC_DUAL_INOUT BIT(2)
> +#define DSC_BYPASS BIT(4)
> +#define DSC_UFOE_SEL BIT(16)
> +
> +/**
> + * struct mtk_disp_dsc - DISP_DSC driver structure
> + * @clk - clk of dsc hardware
> + * @regs - hardware register address of dsc
> + * @cmdq_reg - structure containing cmdq hardware resource
> + */
> +struct mtk_disp_dsc {
> + struct clk *clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> +};
Squash mtk_disp_dsc.c into mtk_drm_ddp_comp.c and this patch would be
much simpler.
> +
> +void mtk_dsc_start(struct device *dev)
> +{
> + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> + void __iomem *baddr = dsc->regs;
baddr is used only once, so use dsc->regs directly.
> +
> + mtk_ddp_write_mask(NULL, DSC_EN, &dsc->cmdq_reg, baddr,
> + DISP_REG_DSC_CON, DSC_EN);
> +}
> +
> +void mtk_dsc_stop(struct device *dev)
> +{
> + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> + void __iomem *baddr = dsc->regs;
Ditto.
> +
> + mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> + DISP_REG_DSC_CON, DSC_EN);
> +}
> +
> +int mtk_dsc_clk_enable(struct device *dev)
> +{
> + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> + return clk_prepare_enable(dsc->clk);
> +}
> +
> +void mtk_dsc_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> + clk_disable_unprepare(dsc->clk);
> +}
> +
> +void mtk_dsc_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *handle)
> +{
> + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> +
> + /* dsc bypass mode */
> + mtk_ddp_write_mask(handle, DSC_BYPASS, &dsc->cmdq_reg, dsc->regs,
> + DISP_REG_DSC_CON, DSC_BYPASS);
> + mtk_ddp_write_mask(handle, DSC_UFOE_SEL, &dsc->cmdq_reg, dsc->regs,
> + DISP_REG_DSC_CON, DSC_UFOE_SEL);
> + mtk_ddp_write_mask(handle, DSC_DUAL_INOUT, &dsc->cmdq_reg, dsc->regs,
> + DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> +}
> +
> +static int mtk_disp_dsc_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_dsc_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_dsc_component_ops = {
> + .bind = mtk_disp_dsc_bind,
> + .unbind = mtk_disp_dsc_unbind,
> +};
> +
> +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + struct mtk_disp_dsc *priv;
> + int irq;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get dsc clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap dsc\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = component_add(dev, &mtk_disp_dsc_component_ops);
> + if (ret != 0)
> + dev_err(dev, "Failed to add component: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-dsc", },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> +
> +struct platform_driver mtk_disp_dsc_driver = {
> + .probe = mtk_disp_dsc_probe,
> + .remove = mtk_disp_dsc_remove,
> + .driver = {
> + .name = "mediatek-disp-dsc",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_dsc_driver_dt_match,
> + },
> +};
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index 75bc00e17fc4..ba3d7a1ce7ab 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs ddp_rdma = {
> .layer_config = mtk_rdma_layer_config,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> + .config = mtk_dsc_config,
> + .start = mtk_dsc_start,
> + .stop = mtk_dsc_stop,
> + .clk_enable = mtk_dsc_clk_enable,
> + .clk_disable = mtk_dsc_clk_disable,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .clk_enable = mtk_ddp_clk_enable,
> .clk_disable = mtk_ddp_clk_disable,
> @@ -356,6 +364,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_MUTEX] = "mutex",
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> + [MTK_DISP_DSC] = "dsc",
> };
>
> struct mtk_ddp_comp_match {
> @@ -374,6 +383,9 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0, &ddp_dither },
> [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi },
> [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi },
> + [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc },
> + [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc },
> + [DDP_COMPONENT_DSC1_VIRTUAL0] = { MTK_DISP_DSC, -1, &ddp_dsc },
What is DDP_COMPONENT_DSC1_VIRTUAL0? If use less, remove it.
> [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi },
> [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi },
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> @@ -508,13 +520,14 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> if (type == MTK_DISP_BLS ||
> type == MTK_DISP_CCORR ||
> type == MTK_DISP_COLOR ||
> + type == MTK_DISP_DSC ||
> type == MTK_DISP_GAMMA ||
> - type == MTK_DPI ||
> - type == MTK_DSI ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> type == MTK_DISP_PWM ||
> - type == MTK_DISP_RDMA)
> + type == MTK_DISP_RDMA ||
> + type == MTK_DPI ||
> + type == MTK_DSI)
Moving MTK_DPI and MTK_DSI is not related to DSC, so move this
modification to another patch.
> return 0;
>
> priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index bb914d976cf5..661fb620e266 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_MUTEX,
> MTK_DISP_OD,
> MTK_DISP_BLS,
> + MTK_DISP_DSC,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index d6f6d1bdad85..990a54049a7d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -446,6 +446,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_GAMMA, },
> { .compatible = "mediatek,mt8183-disp-dither",
> .data = (void *)MTK_DISP_DITHER },
> + { .compatible = "mediatek,mt8195-disp-dsc",
> + .data = (void *)MTK_DISP_DSC },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt2701-dsi",
> @@ -562,12 +564,13 @@ static int mtk_drm_probe(struct platform_device *pdev)
> */
> if (comp_type == MTK_DISP_CCORR ||
> comp_type == MTK_DISP_COLOR ||
> + comp_type == MTK_DISP_DSC ||
> comp_type == MTK_DISP_GAMMA ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> comp_type == MTK_DISP_RDMA ||
> - comp_type == MTK_DSI ||
> - comp_type == MTK_DPI) {
> + comp_type == MTK_DPI ||
> + comp_type == MTK_DSI) {
> dev_info(dev, "Adding component match for %pOF\n",
> node);
> drm_of_component_match_add(dev, &match, compare_of,
> @@ -662,6 +665,7 @@ static struct platform_driver mtk_drm_platform_driver = {
> static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_disp_ccorr_driver,
> &mtk_disp_color_driver,
> + &mtk_disp_dsc_driver,
> &mtk_disp_gamma_driver,
> &mtk_disp_ovl_driver,
> &mtk_disp_rdma_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 637f5669e895..8b722330ef7d 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -51,6 +51,7 @@ extern struct platform_driver mtk_disp_color_driver;
> extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> +extern struct platform_driver mtk_disp_dsc_driver;
Alphabetic order.
Regards,
Chun-Kuang.
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
>
> --
> 2.18.0
>
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linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 11/12] drm/mediatek: add DSC support for MT8195
2021-07-15 23:21 ` Chun-Kuang Hu
@ 2021-07-23 2:45 ` Jason-JH Lin
0 siblings, 0 replies; 22+ messages in thread
From: Jason-JH Lin @ 2021-07-23 2:45 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Matthias Brugger, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, Nancy Lin,
singo.chang
Hi CK,
On Fri, 2021-07-16 at 07:21 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月16日 週五 上午1:38寫道：
> >
> > Add DSC module file:
> > DSC is designed for real-time systems with real-time compression,
> > transmission, decompression and display.
> > The DSC standard is a specification of the algorithms used for
> > compressing and decompressing image display streams, including
> > the specification of the syntax and semantics of the compressed
> > video bit stream.
> >
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > drivers/gpu/drm/mediatek/mtk_disp_dsc.c | 161
> > ++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 19 ++-
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 8 +-
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 7 files changed, 194 insertions(+), 5 deletions(-)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index dc54a7a69005..44948e221fd3 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -2,6 +2,7 @@
> >
> > mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_disp_color.o \
> > + mtk_disp_dsc.o \
> > mtk_disp_gamma.o \
> > mtk_disp_ovl.o \
> > mtk_disp_rdma.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index cafd9df2d63b..c7e9bd370acd 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -33,6 +33,14 @@ void mtk_dither_set_common(void __iomem *regs,
> > struct cmdq_client_reg *cmdq_reg,
> > void mtk_dpi_start(struct device *dev);
> > void mtk_dpi_stop(struct device *dev);
> >
> > +int mtk_dsc_clk_enable(struct device *dev);
> > +void mtk_dsc_clk_disable(struct device *dev);
> > +void mtk_dsc_config(struct device *dev, unsigned int width,
> > + unsigned int height, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_dsc_start(struct device *dev);
> > +void mtk_dsc_stop(struct device *dev);
> > +
> > void mtk_dsi_ddp_start(struct device *dev);
> > void mtk_dsi_ddp_stop(struct device *dev);
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > new file mode 100644
> > index 000000000000..6a196220c532
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_dsc.c
> > @@ -0,0 +1,161 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_gem.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_DSC_CON 0x0000
> > +#define DSC_EN BIT(0)
> > +#define DSC_DUAL_INOUT BIT(2)
> > +#define DSC_BYPASS BIT(4)
> > +#define DSC_UFOE_SEL BIT(16)
> > +
> > +/**
> > + * struct mtk_disp_dsc - DISP_DSC driver structure
> > + * @clk - clk of dsc hardware
> > + * @regs - hardware register address of dsc
> > + * @cmdq_reg - structure containing cmdq hardware resource
> > + */
> > +struct mtk_disp_dsc {
> > + struct clk *clk;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_reg;
> > +};
>
> Squash mtk_disp_dsc.c into mtk_drm_ddp_comp.c and this patch would be
> much simpler.
>
OK, I'll squash it into mtk_drm_ddp_comp.c at next version.
> > +
> > +void mtk_dsc_start(struct device *dev)
> > +{
> > + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > + void __iomem *baddr = dsc->regs;
>
> baddr is used only once, so use dsc->regs directly.
OK, I'll fix this.
>
> > +
> > + mtk_ddp_write_mask(NULL, DSC_EN, &dsc->cmdq_reg, baddr,
> > + DISP_REG_DSC_CON, DSC_EN);
> > +}
> > +
> > +void mtk_dsc_stop(struct device *dev)
> > +{
> > + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > + void __iomem *baddr = dsc->regs;
>
> Ditto.
>
OK, I'll fix this.
> > +
> > + mtk_ddp_write_mask(NULL, 0x0, &dsc->cmdq_reg, baddr,
> > + DISP_REG_DSC_CON, DSC_EN);
> > +}
> > +
> > +int mtk_dsc_clk_enable(struct device *dev)
> > +{
> > + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > + return clk_prepare_enable(dsc->clk);
> > +}
> > +
> > +void mtk_dsc_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > + clk_disable_unprepare(dsc->clk);
> > +}
> > +
> > +void mtk_dsc_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > + struct mtk_disp_dsc *dsc = dev_get_drvdata(dev);
> > +
> > + /* dsc bypass mode */
> > + mtk_ddp_write_mask(handle, DSC_BYPASS, &dsc->cmdq_reg, dsc-
> > >regs,
> > + DISP_REG_DSC_CON, DSC_BYPASS);
> > + mtk_ddp_write_mask(handle, DSC_UFOE_SEL, &dsc->cmdq_reg,
> > dsc->regs,
> > + DISP_REG_DSC_CON, DSC_UFOE_SEL);
> > + mtk_ddp_write_mask(handle, DSC_DUAL_INOUT, &dsc->cmdq_reg,
> > dsc->regs,
> > + DISP_REG_DSC_CON, DSC_DUAL_INOUT);
> > +}
> > +
> > +static int mtk_disp_dsc_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_dsc_unbind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_dsc_component_ops = {
> > + .bind = mtk_disp_dsc_bind,
> > + .unbind = mtk_disp_dsc_unbind,
> > +};
> > +
> > +static int mtk_disp_dsc_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + struct mtk_disp_dsc *priv;
> > + int irq;
> > + int ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + priv->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(priv->clk)) {
> > + dev_err(dev, "failed to get dsc clk\n");
> > + return PTR_ERR(priv->clk);
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + priv->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(priv->regs)) {
> > + dev_err(dev, "failed to ioremap dsc\n");
> > + return PTR_ERR(priv->regs);
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = component_add(dev, &mtk_disp_dsc_component_ops);
> > + if (ret != 0)
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_dsc_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_dsc_component_ops);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_dsc_driver_dt_match[] =
> > {
> > + { .compatible = "mediatek,mt8195-disp-dsc", },
> > + {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_dsc_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_dsc_driver = {
> > + .probe = mtk_disp_dsc_probe,
> > + .remove = mtk_disp_dsc_remove,
> > + .driver = {
> > + .name = "mediatek-disp-dsc",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_disp_dsc_driver_dt_match,
> > + },
> > +};
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index 75bc00e17fc4..ba3d7a1ce7ab 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -333,6 +333,14 @@ static const struct mtk_ddp_comp_funcs
> > ddp_rdma = {
> > .layer_config = mtk_rdma_layer_config,
> > };
> >
> > +static const struct mtk_ddp_comp_funcs ddp_dsc = {
> > + .config = mtk_dsc_config,
> > + .start = mtk_dsc_start,
> > + .stop = mtk_dsc_stop,
> > + .clk_enable = mtk_dsc_clk_enable,
> > + .clk_disable = mtk_dsc_clk_disable,
> > +};
> > +
> > static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> > .clk_enable = mtk_ddp_clk_enable,
> > .clk_disable = mtk_ddp_clk_disable,
> > @@ -356,6 +364,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > [MTK_DISP_MUTEX] = "mutex",
> > [MTK_DISP_OD] = "od",
> > [MTK_DISP_BLS] = "bls",
> > + [MTK_DISP_DSC] = "dsc",
> > };
> >
> > struct mtk_ddp_comp_match {
> > @@ -374,6 +383,9 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_DITHER] = { MTK_DISP_DITHER, 0,
> > &ddp_dither },
> > [DDP_COMPONENT_DPI0] = { MTK_DPI, 0, &ddp_dpi
> > },
> > [DDP_COMPONENT_DPI1] = { MTK_DPI, 1, &ddp_dpi
> > },
> > + [DDP_COMPONENT_DSC0] = { MTK_DISP_DSC, 0, &ddp_dsc
> > },
> > + [DDP_COMPONENT_DSC1] = { MTK_DISP_DSC, 1, &ddp_dsc
> > },
> > + [DDP_COMPONENT_DSC1_VIRTUAL0] = { MTK_DISP_DSC, -1,
> > &ddp_dsc },
>
> What is DDP_COMPONENT_DSC1_VIRTUAL0? If use less, remove it.
DDP_COMPONENT_DSC1_VIRTUAL0 is the MUX without a physical module.
It will be used as the sel_in for DITHER1 and DSC1 and the sel_out for
DSI1, DP_INTF0, SINA_VIRTUAL0 and MERGE0.
So I think we sholud keep this component enum to supoort DITHER1 or
DSC1 sel_in and DSI1 or DP_INTF0 sel_out for dual pipe in the future.
>
> > [DDP_COMPONENT_DSI0] = { MTK_DSI, 0, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI1] = { MTK_DSI, 1, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi
> > },
> > @@ -508,13 +520,14 @@ int mtk_ddp_comp_init(struct device_node
> > *node, struct mtk_ddp_comp *comp,
> > if (type == MTK_DISP_BLS ||
> > type == MTK_DISP_CCORR ||
> > type == MTK_DISP_COLOR ||
> > + type == MTK_DISP_DSC ||
> > type == MTK_DISP_GAMMA ||
> > - type == MTK_DPI ||
> > - type == MTK_DSI ||
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > - type == MTK_DISP_RDMA)
> > + type == MTK_DISP_RDMA ||
> > + type == MTK_DPI ||
> > + type == MTK_DSI)
>
> Moving MTK_DPI and MTK_DSI is not related to DSC, so move this
> modification to another patch.
>
OK, I will rollback this modification.
> > return 0;
> >
> > priv = devm_kzalloc(comp->dev, sizeof(*priv), GFP_KERNEL);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index bb914d976cf5..661fb620e266 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -34,6 +34,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_MUTEX,
> > MTK_DISP_OD,
> > MTK_DISP_BLS,
> > + MTK_DISP_DSC,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index d6f6d1bdad85..990a54049a7d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -446,6 +446,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_GAMMA, },
> > { .compatible = "mediatek,mt8183-disp-dither",
> > .data = (void *)MTK_DISP_DITHER },
> > + { .compatible = "mediatek,mt8195-disp-dsc",
> > + .data = (void *)MTK_DISP_DSC },
> > { .compatible = "mediatek,mt8173-disp-ufoe",
> > .data = (void *)MTK_DISP_UFOE },
> > { .compatible = "mediatek,mt2701-dsi",
> > @@ -562,12 +564,13 @@ static int mtk_drm_probe(struct
> > platform_device *pdev)
> > */
> > if (comp_type == MTK_DISP_CCORR ||
> > comp_type == MTK_DISP_COLOR ||
> > + comp_type == MTK_DISP_DSC ||
> > comp_type == MTK_DISP_GAMMA ||
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > - comp_type == MTK_DSI ||
> > - comp_type == MTK_DPI) {
> > + comp_type == MTK_DPI ||
> > + comp_type == MTK_DSI) {
> > dev_info(dev, "Adding component match for
> > %pOF\n",
> > node);
> > drm_of_component_match_add(dev, &match,
> > compare_of,
> > @@ -662,6 +665,7 @@ static struct platform_driver
> > mtk_drm_platform_driver = {
> > static struct platform_driver * const mtk_drm_drivers[] = {
> > &mtk_disp_ccorr_driver,
> > &mtk_disp_color_driver,
> > + &mtk_disp_dsc_driver,
> > &mtk_disp_gamma_driver,
> > &mtk_disp_ovl_driver,
> > &mtk_disp_rdma_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 637f5669e895..8b722330ef7d 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -51,6 +51,7 @@ extern struct platform_driver
> > mtk_disp_color_driver;
> > extern struct platform_driver mtk_disp_gamma_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > +extern struct platform_driver mtk_disp_dsc_driver;
>
> Alphabetic order.
OK, I'll fix this.
>
> Regards,
> Chun-Kuang.
>
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> >
> > --
> > 2.18.0
> >
Regards,
Jason-JH Lin
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 22+ messages in thread
* [PATCH v3 12/12] drm/mediatek: add MERGE support for MT8195
2021-07-15 17:37 [PATCH v3 00/12] Add MediaTek SoC DRM (vdosys0) support for mt8195 jason-jh.lin
` (10 preceding siblings ...)
2021-07-15 17:37 ` [PATCH v3 11/12] drm/mediatek: add DSC " jason-jh.lin
@ 2021-07-15 17:37 ` jason-jh.lin
2021-07-15 23:50 ` Chun-Kuang Hu
11 siblings, 1 reply; 22+ messages in thread
From: jason-jh.lin @ 2021-07-15 17:37 UTC (permalink / raw)
To: chunkuang.hu, matthias.bgg
Cc: linux-arm-kernel, linux-mediatek, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, jason-jh.lin,
nancy.lin, singo.chang
1. Add MERGE module file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.
2. Add REG_FLD macro in mtk_dem_crtc header to support
bitwise register settings.
Change-Id: Ie196aa61661eaf7d0959482d3700f3242de32e5e
Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
drivers/gpu/drm/mediatek/Makefile | 1 +
drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
drivers/gpu/drm/mediatek/mtk_disp_merge.c | 372 ++++++++++++++++++++
drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 14 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 +
drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
8 files changed, 417 insertions(+)
create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 44948e221fd3..27c89847d43b 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
mtk_disp_color.o \
mtk_disp_dsc.o \
mtk_disp_gamma.o \
+ mtk_disp_merge.o \
mtk_disp_ovl.o \
mtk_disp_rdma.o \
mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index c7e9bd370acd..3e27ce7fef57 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -54,6 +54,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
void mtk_gamma_start(struct device *dev);
void mtk_gamma_stop(struct device *dev);
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+ unsigned int height, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
void mtk_ovl_bgclr_in_on(struct device *dev);
void mtk_ovl_bgclr_in_off(struct device *dev);
void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..768c282d2d63
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,372 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_crtc.h"
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL (0x000)
+#define FLD_MERGE_EN BIT(0)
+#define FLD_MERGE_RST BIT(4)
+#define FLD_MERGE_LR_SWAP BIT(8)
+#define FLD_MERGE_DCM_DIS BIT(12)
+#define DISP_MERGE_CFG_0 0x010
+#define DISP_MERGE_CFG_4 0x020
+#define DISP_MERGE_CFG_10 0x038
+#define DISP_MERGE_CFG_12 0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE 6
+#define CFG_10_10_2PI_2PO_BUF_MODE 8
+#define DISP_MERGE_CFG_24 0x070
+#define DISP_MERGE_CFG_25 0x074
+#define DISP_MERGE_CFG_36 0x0a0
+#define DISP_MERGE_CFG_36_FLD_ULTRA_EN REG_FLD(1, 0)
+#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN REG_FLD(1, 4)
+#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN REG_FLD(1, 8)
+#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
+#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
+#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
+#define DISP_MERGE_CFG_37 0x0a4
+#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE REG_FLD(2, 0)
+#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
+#define DISP_MERGE_CFG_38 0x0a8
+#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA REG_FLD(1, 0)
+#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA REG_FLD(1, 4)
+#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH REG_FLD(16, 16)
+#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
+#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
+#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
+#define DISP_MERGE_CFG_39 0x0ac
+#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA REG_FLD(1, 8)
+#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA REG_FLD(1, 12)
+#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH REG_FLD(16, 16)
+#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
+#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
+#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
+#define DISP_MERGE_CFG_40 0x0b0
+#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW REG_FLD(16, 0)
+#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH REG_FLD(16, 16)
+#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
+#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
+#define DISP_MERGE_CFG_41 0x0b4
+#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW REG_FLD(16, 0)
+#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH REG_FLD(16, 16)
+#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
+#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
+ REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
+
+struct mtk_merge_config_struct {
+ unsigned short width_right;
+ unsigned short width_left;
+ unsigned int height;
+ unsigned int mode;
+};
+
+struct mtk_disp_merge {
+ enum mtk_ddp_comp_id comp_id;
+ struct drm_crtc *crtc;
+ struct clk *clk;
+ struct clk *async_clk;
+ void __iomem *regs;
+ struct cmdq_client_reg cmdq_reg;
+ u32 fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
+}
+
+static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
+{
+ if (!merge_config->height ||
+ !merge_config->width_left || !merge_config->width_right) {
+ pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
+ __func__, merge_config->width_left,
+ merge_config->width_right, merge_config->height);
+ return -EINVAL;
+ }
+ pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
+ __func__, merge_config->width_left,
+ merge_config->width_right, merge_config->height);
+ return 0;
+}
+
+static int mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+ struct cmdq_pkt *handle)
+{
+ int ultra_en = 1;
+ int preultra_en = 1;
+ int halt_for_dvfs_en = 0;
+ int buffer_mode = 3;
+ int vde_block_ultra = 0;
+ int valid_th_block_ultra = 0;
+ int ultra_fifo_valid_th = 0;
+ int nvde_force_preultra = 0;
+ int nvalid_th_force_preultra = 0;
+ int preultra_fifo_valid_th = 0;
+ int ultra_th_low = 0xe10;
+ int ultra_th_high = 0x12c0;
+ int preultra_th_low = 0x12c0;
+ int preultra_th_high = 0x1518;
+
+ mtk_ddp_write_mask(handle,
+ DISP_MERGE_CFG_36_VAL_ULTRA_EN(ultra_en) |
+ DISP_MERGE_CFG_36_VAL_PREULTRA_EN(preultra_en) |
+ DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(halt_for_dvfs_en),
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_36,
+ REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
+ REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
+ REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
+
+ mtk_ddp_write_mask(handle,
+ DISP_MERGE_CFG_37_VAL_BUFFER_MODE(buffer_mode),
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_37,
+ REG_FLD_MASK(DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
+
+ mtk_ddp_write_mask(handle,
+ DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(vde_block_ultra) |
+ DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(valid_th_block_ultra) |
+ DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(ultra_fifo_valid_th),
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_38,
+ REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
+ REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
+ REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
+
+ mtk_ddp_write_mask(handle,
+ DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(nvde_force_preultra) |
+ DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
+ (nvalid_th_force_preultra) |
+ DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(preultra_fifo_valid_th),
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_39,
+ REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
+ REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
+ REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
+
+ mtk_ddp_write_mask(handle,
+ DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(ultra_th_low) |
+ DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(ultra_th_high),
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_40,
+ REG_FLD_MASK(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
+ REG_FLD_MASK(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
+
+ mtk_ddp_write_mask(handle,
+ DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(preultra_th_low) |
+ DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(preultra_th_high),
+ &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_41,
+ REG_FLD_MASK(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
+ REG_FLD_MASK(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
+
+ return 0;
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+ unsigned int h, unsigned int vrefresh,
+ unsigned int bpc, struct cmdq_pkt *handle)
+{
+ struct mtk_merge_config_struct merge_config;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->fifo_en)
+ mtk_merge_fifo_setting(priv, handle);
+
+ switch (priv->comp_id) {
+ case DDP_COMPONENT_MERGE0:
+ merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
+ merge_config.width_left = w;
+ merge_config.width_right = w;
+ merge_config.height = h;
+ break;
+ case DDP_COMPONENT_MERGE5:
+ merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
+ merge_config.width_left = w;
+ merge_config.width_right = w;
+ merge_config.height = h;
+ break;
+ default:
+ pr_err("No find component merge %d\n", priv->comp_id);
+ return;
+ }
+
+ mtk_merge_check_params(&merge_config);
+
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_0);
+
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_4);
+
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_24);
+
+ mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_25);
+
+ /* no swap */
+ mtk_ddp_write_mask(handle, 0, &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_10, 0x1f);
+
+ mtk_ddp_write_mask(handle, merge_config.mode, &priv->cmdq_reg, priv->regs,
+ DISP_MERGE_CFG_12, 0x1f);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+ int ret = 0;
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->clk) {
+ ret = clk_prepare_enable(priv->clk);
+ if (ret)
+ pr_err("merge clk prepare enable failed\n");
+ }
+
+ if (priv->async_clk) {
+ ret = clk_prepare_enable(priv->async_clk);
+ if (ret)
+ pr_err("async clk prepare enable failed\n");
+ }
+
+ return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+ struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+ if (priv->async_clk)
+ clk_disable_unprepare(priv->async_clk);
+
+ if (priv->clk)
+ clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+ .bind = mtk_disp_merge_bind,
+ .unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct mtk_disp_merge *priv;
+ enum mtk_ddp_comp_id comp_id;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
+ if ((int)comp_id < 0) {
+ dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
+ return comp_id;
+ }
+
+ priv->comp_id = comp_id;
+
+ priv->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(priv->clk)) {
+ dev_err(dev, "failed to get merge clk\n");
+ return PTR_ERR(priv->clk);
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ priv->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(priv->regs)) {
+ dev_err(dev, "failed to ioremap merge\n");
+ return PTR_ERR(priv->regs);
+ }
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+ ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+ if (ret)
+ dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+ priv->async_clk = of_clk_get(dev->of_node, 1);
+ if (IS_ERR(priv->async_clk)) {
+ ret = PTR_ERR(priv->async_clk);
+ dev_dbg(dev, "No merge async clock: %d\n", ret);
+ priv->async_clk = NULL;
+ }
+
+ priv->fifo_en = of_property_read_bool(dev->of_node,
+ "mediatek,merge-fifo-en");
+
+ platform_set_drvdata(pdev, priv);
+
+ ret = component_add(dev, &mtk_disp_merge_component_ops);
+ if (ret != 0)
+ dev_err(dev, "Failed to add component: %d\n", ret);
+
+ return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+ return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+ { .compatible = "mediatek,mt8195-disp-merge", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+ .probe = mtk_disp_merge_probe,
+ .remove = mtk_disp_merge_remove,
+ .driver = {
+ .name = "mediatek-disp-merge",
+ .owner = THIS_MODULE,
+ .of_match_table = mtk_disp_merge_driver_dt_match,
+ },
+};
+
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
index cb9a36c48d4f..66d1cf03dfe8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
@@ -14,6 +14,20 @@
#define MTK_MAX_BPC 10
#define MTK_MIN_BPC 3
+#define REG_FLD(width, shift) \
+ ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
+
+#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
+
+#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
+
+#define REG_FLD_MASK(field) \
+ ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
+ << REG_FLD_SHIFT(field))
+
+#define REG_FLD_VAL(field, val) \
+ (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
+
void mtk_drm_crtc_commit(struct drm_crtc *crtc);
int mtk_drm_crtc_create(struct drm_device *drm_dev,
const enum mtk_ddp_comp_id *path,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index ba3d7a1ce7ab..9125d0f6352f 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc = {
.clk_disable = mtk_dsc_clk_disable,
};
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+ .clk_enable = mtk_merge_clk_enable,
+ .clk_disable = mtk_merge_clk_disable,
+ .start = mtk_merge_start,
+ .stop = mtk_merge_stop,
+ .config = mtk_merge_config,
+};
+
static const struct mtk_ddp_comp_funcs ddp_ufoe = {
.clk_enable = mtk_ddp_clk_enable,
.clk_disable = mtk_ddp_clk_disable,
@@ -365,6 +373,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
[MTK_DISP_OD] = "od",
[MTK_DISP_BLS] = "bls",
[MTK_DISP_DSC] = "dsc",
+ [MTK_DISP_MERGE] = "merge",
};
struct mtk_ddp_comp_match {
@@ -391,6 +400,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
[DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
[DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
[DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
+ [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
+ [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
+ [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
+ [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
+ [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
+ [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
[DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
[DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
[DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
@@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
type == MTK_DISP_COLOR ||
type == MTK_DISP_DSC ||
type == MTK_DISP_GAMMA ||
+ type == MTK_DISP_MERGE ||
type == MTK_DISP_OVL ||
type == MTK_DISP_OVL_2L ||
type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 661fb620e266..0afd78c0bc92 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
MTK_DISP_OD,
MTK_DISP_BLS,
MTK_DISP_DSC,
+ MTK_DISP_MERGE,
MTK_DDP_COMP_TYPE_MAX,
};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 990a54049a7d..11c25daf05d8 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -448,6 +448,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
.data = (void *)MTK_DISP_DITHER },
{ .compatible = "mediatek,mt8195-disp-dsc",
.data = (void *)MTK_DISP_DSC },
+ { .compatible = "mediatek,mt8195-disp-merge",
+ .data = (void *)MTK_DISP_MERGE },
{ .compatible = "mediatek,mt8173-disp-ufoe",
.data = (void *)MTK_DISP_UFOE },
{ .compatible = "mediatek,mt2701-dsi",
@@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
comp_type == MTK_DISP_COLOR ||
comp_type == MTK_DISP_DSC ||
comp_type == MTK_DISP_GAMMA ||
+ comp_type == MTK_DISP_MERGE ||
comp_type == MTK_DISP_OVL ||
comp_type == MTK_DISP_OVL_2L ||
comp_type == MTK_DISP_RDMA ||
@@ -667,6 +670,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
&mtk_disp_color_driver,
&mtk_disp_dsc_driver,
&mtk_disp_gamma_driver,
+ &mtk_disp_merge_driver,
&mtk_disp_ovl_driver,
&mtk_disp_rdma_driver,
&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 8b722330ef7d..c4d802a43531 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
extern struct platform_driver mtk_disp_ovl_driver;
extern struct platform_driver mtk_disp_rdma_driver;
extern struct platform_driver mtk_disp_dsc_driver;
+extern struct platform_driver mtk_disp_merge_driver;
extern struct platform_driver mtk_dpi_driver;
extern struct platform_driver mtk_dsi_driver;
--
2.18.0
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^ permalink raw reply related [flat|nested] 22+ messages in thread* Re: [PATCH v3 12/12] drm/mediatek: add MERGE support for MT8195
2021-07-15 17:37 ` [PATCH v3 12/12] drm/mediatek: add MERGE " jason-jh.lin
@ 2021-07-15 23:50 ` Chun-Kuang Hu
2021-07-23 2:41 ` Jason-JH Lin
0 siblings, 1 reply; 22+ messages in thread
From: Chun-Kuang Hu @ 2021-07-15 23:50 UTC (permalink / raw)
To: jason-jh.lin
Cc: Chun-Kuang Hu, Matthias Brugger, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, Nancy Lin,
singo.chang
Hi, Jason:
jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月16日 週五 上午1:38寫道：
>
> 1. Add MERGE module file:
> MERGE module is used to merge two slice-per-line inputs
> into one side-by-side output.
>
> 2. Add REG_FLD macro in mtk_dem_crtc header to support
> bitwise register settings.
>
> Change-Id: Ie196aa61661eaf7d0959482d3700f3242de32e5e
> Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/Makefile | 1 +
> drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> drivers/gpu/drm/mediatek/mtk_disp_merge.c | 372 ++++++++++++++++++++
> drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 14 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 +
> drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> 8 files changed, 417 insertions(+)
> create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
>
> diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
> index 44948e221fd3..27c89847d43b 100644
> --- a/drivers/gpu/drm/mediatek/Makefile
> +++ b/drivers/gpu/drm/mediatek/Makefile
> @@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> mtk_disp_color.o \
> mtk_disp_dsc.o \
> mtk_disp_gamma.o \
> + mtk_disp_merge.o \
> mtk_disp_ovl.o \
> mtk_disp_rdma.o \
> mtk_drm_crtc.o \
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> index c7e9bd370acd..3e27ce7fef57 100644
> --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> @@ -54,6 +54,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
> void mtk_gamma_start(struct device *dev);
> void mtk_gamma_stop(struct device *dev);
>
> +int mtk_merge_clk_enable(struct device *dev);
> +void mtk_merge_clk_disable(struct device *dev);
> +void mtk_merge_config(struct device *dev, unsigned int width,
> + unsigned int height, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> +void mtk_merge_start(struct device *dev);
> +void mtk_merge_stop(struct device *dev);
> +
> void mtk_ovl_bgclr_in_on(struct device *dev);
> void mtk_ovl_bgclr_in_off(struct device *dev);
> void mtk_ovl_bypass_shadow(struct device *dev);
> diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> new file mode 100644
> index 000000000000..768c282d2d63
> --- /dev/null
> +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> @@ -0,0 +1,372 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2021 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/component.h>
> +#include <linux/of_device.h>
> +#include <linux/of_irq.h>
> +#include <linux/platform_device.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> +#include "mtk_drm_crtc.h"
> +#include "mtk_drm_ddp_comp.h"
> +#include "mtk_drm_drv.h"
> +#include "mtk_disp_drv.h"
> +
> +#define DISP_REG_MERGE_CTRL (0x000)
> +#define FLD_MERGE_EN BIT(0)
> +#define FLD_MERGE_RST BIT(4)
> +#define FLD_MERGE_LR_SWAP BIT(8)
> +#define FLD_MERGE_DCM_DIS BIT(12)
> +#define DISP_MERGE_CFG_0 0x010
> +#define DISP_MERGE_CFG_4 0x020
> +#define DISP_MERGE_CFG_10 0x038
> +#define DISP_MERGE_CFG_12 0x040
> +#define CFG_10_10_1PI_2PO_BUF_MODE 6
> +#define CFG_10_10_2PI_2PO_BUF_MODE 8
> +#define DISP_MERGE_CFG_24 0x070
> +#define DISP_MERGE_CFG_25 0x074
> +#define DISP_MERGE_CFG_36 0x0a0
> +#define DISP_MERGE_CFG_36_FLD_ULTRA_EN REG_FLD(1, 0)
#define DISP_MERGE_CFG_36_FLD_ULTRA_EN GENMASK(1, 0)
> +#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN REG_FLD(1, 4)
> +#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN REG_FLD(1, 8)
> +#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> +#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> +#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> +#define DISP_MERGE_CFG_37 0x0a4
> +#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE REG_FLD(2, 0)
> +#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> +#define DISP_MERGE_CFG_38 0x0a8
> +#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA REG_FLD(1, 0)
> +#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA REG_FLD(1, 4)
> +#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> +#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA, val)
> +#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
> +#define DISP_MERGE_CFG_39 0x0ac
> +#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA REG_FLD(1, 8)
> +#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA REG_FLD(1, 12)
> +#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
> +#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA, val)
> +#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH, val)
> +#define DISP_MERGE_CFG_40 0x0b0
> +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW REG_FLD(16, 0)
> +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> +#define DISP_MERGE_CFG_41 0x0b4
> +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW REG_FLD(16, 0)
> +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH REG_FLD(16, 16)
> +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> + REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> +
> +struct mtk_merge_config_struct {
> + unsigned short width_right;
> + unsigned short width_left;
> + unsigned int height;
> + unsigned int mode;
> +};
> +
> +struct mtk_disp_merge {
> + enum mtk_ddp_comp_id comp_id;
> + struct drm_crtc *crtc;
> + struct clk *clk;
> + struct clk *async_clk;
> + void __iomem *regs;
> + struct cmdq_client_reg cmdq_reg;
> + u32 fifo_en;
> +};
> +
> +void mtk_merge_start(struct device *dev)
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
> +}
> +
> +void mtk_merge_stop(struct device *dev)
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CTRL);
> +}
> +
> +static int mtk_merge_check_params(struct mtk_merge_config_struct *merge_config)
> +{
> + if (!merge_config->height ||
> + !merge_config->width_left || !merge_config->width_right) {
> + pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> + __func__, merge_config->width_left,
> + merge_config->width_right, merge_config->height);
> + return -EINVAL;
> + }
> + pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> + __func__, merge_config->width_left,
> + merge_config->width_right, merge_config->height);
> + return 0;
> +}
> +
> +static int mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> + struct cmdq_pkt *handle)
> +{
> + int ultra_en = 1;
> + int preultra_en = 1;
> + int halt_for_dvfs_en = 0;
> + int buffer_mode = 3;
Explain what is buffer_mode 3.
> + int vde_block_ultra = 0;
> + int valid_th_block_ultra = 0;
> + int ultra_fifo_valid_th = 0;
> + int nvde_force_preultra = 0;
> + int nvalid_th_force_preultra = 0;
> + int preultra_fifo_valid_th = 0;
> + int ultra_th_low = 0xe10;
> + int ultra_th_high = 0x12c0;
> + int preultra_th_low = 0x12c0;
> + int preultra_th_high = 0x1518;
For the threshold, I would like some formula like RDMA threshold,
/*
* Enable FIFO underflow since DSI and DPI can't be blocked.
* Keep the FIFO pseudo size reset default of 8 KiB. Set the
* output threshold to 6 microseconds with 7/6 overhead to
* account for blanking, and with a pixel depth of 4 bytes:
*/
threshold = width * height * vrefresh * 4 * 7 / 1000000;
> +
> + mtk_ddp_write_mask(handle,
> + DISP_MERGE_CFG_36_VAL_ULTRA_EN(ultra_en) |
> + DISP_MERGE_CFG_36_VAL_PREULTRA_EN(preultra_en) |
> + DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(halt_for_dvfs_en),
Align to the coding style of other sub driver,
halt_for_dvfs_en << 8 | preultra_en << 4 | ultra_en << 0,
> + &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_36,
> + REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_ULTRA_EN) |
> + REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_PREULTRA_EN) |
> + REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN));
Align to the coding style of other sub driver,
DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN |
DISP_MERGE_CFG_36_FLD_PREULTRA_EN | DISP_MERGE_CFG_36_FLD_ULTRA_EN
> +
> + mtk_ddp_write_mask(handle,
> + DISP_MERGE_CFG_37_VAL_BUFFER_MODE(buffer_mode),
> + &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_37,
> + REG_FLD_MASK(DISP_MERGE_CFG_37_FLD_BUFFER_MODE));
> +
> + mtk_ddp_write_mask(handle,
> + DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(vde_block_ultra) |
> + DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(valid_th_block_ultra) |
> + DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(ultra_fifo_valid_th),
> + &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_38,
> + REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA) |
> + REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA) |
> + REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH));
> +
> + mtk_ddp_write_mask(handle,
> + DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(nvde_force_preultra) |
> + DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA
> + (nvalid_th_force_preultra) |
> + DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(preultra_fifo_valid_th),
> + &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_39,
> + REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA) |
> + REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA) |
> + REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH));
> +
> + mtk_ddp_write_mask(handle,
> + DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(ultra_th_low) |
> + DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(ultra_th_high),
> + &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_40,
> + REG_FLD_MASK(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW) |
> + REG_FLD_MASK(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH));
> +
> + mtk_ddp_write_mask(handle,
> + DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(preultra_th_low) |
> + DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(preultra_th_high),
> + &priv->cmdq_reg, priv->regs, DISP_MERGE_CFG_41,
> + REG_FLD_MASK(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW) |
> + REG_FLD_MASK(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH));
> +
> + return 0;
This function always return 0, so change to void.
> +}
> +
> +void mtk_merge_config(struct device *dev, unsigned int w,
> + unsigned int h, unsigned int vrefresh,
> + unsigned int bpc, struct cmdq_pkt *handle)
> +{
> + struct mtk_merge_config_struct merge_config;
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->fifo_en)
> + mtk_merge_fifo_setting(priv, handle);
> +
> + switch (priv->comp_id) {
I think you should use priv->fifo_en instead of priv->comp_id.
> + case DDP_COMPONENT_MERGE0:
> + merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
> + merge_config.width_left = w;
> + merge_config.width_right = w;
> + merge_config.height = h;
> + break;
> + case DDP_COMPONENT_MERGE5:
> + merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> + merge_config.width_left = w;
> + merge_config.width_right = w;
> + merge_config.height = h;
> + break;
> + default:
> + pr_err("No find component merge %d\n", priv->comp_id);
> + return;
> + }
> +
> + mtk_merge_check_params(&merge_config);
I think you should remove mtk_merge_check_params() and directly check
w and h, and remove whole switch case.
> +
> + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
> + DISP_MERGE_CFG_0);
> +
> + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
> + DISP_MERGE_CFG_4);
> +
> + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
> + DISP_MERGE_CFG_24);
> +
> + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv->regs,
> + DISP_MERGE_CFG_25);
> +
> + /* no swap */
> + mtk_ddp_write_mask(handle, 0, &priv->cmdq_reg, priv->regs,
> + DISP_MERGE_CFG_10, 0x1f);
> +
> + mtk_ddp_write_mask(handle, merge_config.mode, &priv->cmdq_reg, priv->regs,
> + DISP_MERGE_CFG_12, 0x1f);
> +}
> +
> +int mtk_merge_clk_enable(struct device *dev)
> +{
> + int ret = 0;
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->clk) {
clk_prepare_enable() would check this, so remove this check.
> + ret = clk_prepare_enable(priv->clk);
> + if (ret)
> + pr_err("merge clk prepare enable failed\n");
> + }
> +
> + if (priv->async_clk) {
> + ret = clk_prepare_enable(priv->async_clk);
> + if (ret)
> + pr_err("async clk prepare enable failed\n");
> + }
> +
> + return ret;
> +}
> +
> +void mtk_merge_clk_disable(struct device *dev)
> +{
> + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> +
> + if (priv->async_clk)
> + clk_disable_unprepare(priv->async_clk);
> +
> + if (priv->clk)
> + clk_disable_unprepare(priv->clk);
> +}
> +
> +static int mtk_disp_merge_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + return 0;
> +}
> +
> +static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> +}
> +
> +static const struct component_ops mtk_disp_merge_component_ops = {
> + .bind = mtk_disp_merge_bind,
> + .unbind = mtk_disp_merge_unbind,
> +};
> +
> +static int mtk_disp_merge_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + struct mtk_disp_merge *priv;
> + enum mtk_ddp_comp_id comp_id;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + comp_id = mtk_ddp_comp_get_id(dev->of_node, MTK_DISP_MERGE);
> + if ((int)comp_id < 0) {
> + dev_err(dev, "Failed to identify by alias: %d\n", comp_id);
> + return comp_id;
> + }
> +
> + priv->comp_id = comp_id;
> +
> + priv->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "failed to get merge clk\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->regs = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->regs)) {
> + dev_err(dev, "failed to ioremap merge\n");
> + return PTR_ERR(priv->regs);
> + }
> +
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> + if (ret)
> + dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
> +#endif
> +
> + priv->async_clk = of_clk_get(dev->of_node, 1);
> + if (IS_ERR(priv->async_clk)) {
> + ret = PTR_ERR(priv->async_clk);
> + dev_dbg(dev, "No merge async clock: %d\n", ret);
> + priv->async_clk = NULL;
> + }
> +
> + priv->fifo_en = of_property_read_bool(dev->of_node,
> + "mediatek,merge-fifo-en");
> +
> + platform_set_drvdata(pdev, priv);
> +
> + ret = component_add(dev, &mtk_disp_merge_component_ops);
> + if (ret != 0)
> + dev_err(dev, "Failed to add component: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int mtk_disp_merge_remove(struct platform_device *pdev)
> +{
> + component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
> + { .compatible = "mediatek,mt8195-disp-merge", },
> + {},
> +};
> +
> +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> +
> +struct platform_driver mtk_disp_merge_driver = {
> + .probe = mtk_disp_merge_probe,
> + .remove = mtk_disp_merge_remove,
> + .driver = {
> + .name = "mediatek-disp-merge",
> + .owner = THIS_MODULE,
> + .of_match_table = mtk_disp_merge_driver_dt_match,
> + },
> +};
> +
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> index cb9a36c48d4f..66d1cf03dfe8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> @@ -14,6 +14,20 @@
> #define MTK_MAX_BPC 10
> #define MTK_MIN_BPC 3
>
> +#define REG_FLD(width, shift) \
> + ((unsigned int)((((width) & 0xff) << 16) | ((shift) & 0xff)))
> +
> +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) & 0xff))
> +
> +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> +
> +#define REG_FLD_MASK(field) \
> + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> + << REG_FLD_SHIFT(field))
> +
> +#define REG_FLD_VAL(field, val) \
> + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> +
> void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> int mtk_drm_crtc_create(struct drm_device *drm_dev,
> const enum mtk_ddp_comp_id *path,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> index ba3d7a1ce7ab..9125d0f6352f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> @@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc = {
> .clk_disable = mtk_dsc_clk_disable,
> };
>
> +static const struct mtk_ddp_comp_funcs ddp_merge = {
> + .clk_enable = mtk_merge_clk_enable,
> + .clk_disable = mtk_merge_clk_disable,
> + .start = mtk_merge_start,
> + .stop = mtk_merge_stop,
> + .config = mtk_merge_config,
> +};
> +
> static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> .clk_enable = mtk_ddp_clk_enable,
> .clk_disable = mtk_ddp_clk_disable,
> @@ -365,6 +373,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> [MTK_DISP_OD] = "od",
> [MTK_DISP_BLS] = "bls",
> [MTK_DISP_DSC] = "dsc",
> + [MTK_DISP_MERGE] = "merge",
> };
>
> struct mtk_ddp_comp_match {
> @@ -391,6 +400,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi },
> [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi },
> [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0, &ddp_gamma },
> + [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0, &ddp_merge },
> + [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1, &ddp_merge },
> + [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2, &ddp_merge },
> + [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3, &ddp_merge },
> + [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4, &ddp_merge },
> + [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5, &ddp_merge },
> [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od },
> [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od },
> [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl },
> @@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
> type == MTK_DISP_COLOR ||
> type == MTK_DISP_DSC ||
> type == MTK_DISP_GAMMA ||
> + type == MTK_DISP_MERGE ||
> type == MTK_DISP_OVL ||
> type == MTK_DISP_OVL_2L ||
> type == MTK_DISP_PWM ||
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> index 661fb620e266..0afd78c0bc92 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
> MTK_DISP_OD,
> MTK_DISP_BLS,
> MTK_DISP_DSC,
> + MTK_DISP_MERGE,
> MTK_DDP_COMP_TYPE_MAX,
> };
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> index 990a54049a7d..11c25daf05d8 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> @@ -448,6 +448,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
> .data = (void *)MTK_DISP_DITHER },
> { .compatible = "mediatek,mt8195-disp-dsc",
> .data = (void *)MTK_DISP_DSC },
> + { .compatible = "mediatek,mt8195-disp-merge",
> + .data = (void *)MTK_DISP_MERGE },
> { .compatible = "mediatek,mt8173-disp-ufoe",
> .data = (void *)MTK_DISP_UFOE },
> { .compatible = "mediatek,mt2701-dsi",
> @@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
> comp_type == MTK_DISP_COLOR ||
> comp_type == MTK_DISP_DSC ||
> comp_type == MTK_DISP_GAMMA ||
> + comp_type == MTK_DISP_MERGE ||
> comp_type == MTK_DISP_OVL ||
> comp_type == MTK_DISP_OVL_2L ||
> comp_type == MTK_DISP_RDMA ||
> @@ -667,6 +670,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
> &mtk_disp_color_driver,
> &mtk_disp_dsc_driver,
> &mtk_disp_gamma_driver,
> + &mtk_disp_merge_driver,
> &mtk_disp_ovl_driver,
> &mtk_disp_rdma_driver,
> &mtk_dpi_driver,
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> index 8b722330ef7d..c4d802a43531 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> @@ -52,6 +52,7 @@ extern struct platform_driver mtk_disp_gamma_driver;
> extern struct platform_driver mtk_disp_ovl_driver;
> extern struct platform_driver mtk_disp_rdma_driver;
> extern struct platform_driver mtk_disp_dsc_driver;
> +extern struct platform_driver mtk_disp_merge_driver;
Alphabetic order.
Regards,
Chun-Kuang.
> extern struct platform_driver mtk_dpi_driver;
> extern struct platform_driver mtk_dsi_driver;
>
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 22+ messages in thread* Re: [PATCH v3 12/12] drm/mediatek: add MERGE support for MT8195
2021-07-15 23:50 ` Chun-Kuang Hu
@ 2021-07-23 2:41 ` Jason-JH Lin
0 siblings, 0 replies; 22+ messages in thread
From: Jason-JH Lin @ 2021-07-23 2:41 UTC (permalink / raw)
To: Chun-Kuang Hu
Cc: Matthias Brugger, Linux ARM,
moderated list:ARM/Mediatek SoC support, linux-kernel,
Project_Global_Chrome_Upstream_Group, fshao, Nancy Lin,
singo.chang
Hi CK,
On Fri, 2021-07-16 at 07:50 +0800, Chun-Kuang Hu wrote:
> Hi, Jason:
>
> jason-jh.lin <jason-jh.lin@mediatek.com> 於 2021年7月16日 週五 上午1:38寫道：
> >
> > 1. Add MERGE module file:
> > MERGE module is used to merge two slice-per-line inputs
> > into one side-by-side output.
> >
> > 2. Add REG_FLD macro in mtk_dem_crtc header to support
> > bitwise register settings.
> >
> > Change-Id: Ie196aa61661eaf7d0959482d3700f3242de32e5e
> > Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
> > ---
> > drivers/gpu/drm/mediatek/Makefile | 1 +
> > drivers/gpu/drm/mediatek/mtk_disp_drv.h | 8 +
> > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 372
> > ++++++++++++++++++++
> > drivers/gpu/drm/mediatek/mtk_drm_crtc.h | 14 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 16 +
> > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.c | 4 +
> > drivers/gpu/drm/mediatek/mtk_drm_drv.h | 1 +
> > 8 files changed, 417 insertions(+)
> > create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
> >
> > diff --git a/drivers/gpu/drm/mediatek/Makefile
> > b/drivers/gpu/drm/mediatek/Makefile
> > index 44948e221fd3..27c89847d43b 100644
> > --- a/drivers/gpu/drm/mediatek/Makefile
> > +++ b/drivers/gpu/drm/mediatek/Makefile
> > @@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_ccorr.o \
> > mtk_disp_color.o \
> > mtk_disp_dsc.o \
> > mtk_disp_gamma.o \
> > + mtk_disp_merge.o \
> > mtk_disp_ovl.o \
> > mtk_disp_rdma.o \
> > mtk_drm_crtc.o \
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > index c7e9bd370acd..3e27ce7fef57 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
> > @@ -54,6 +54,14 @@ void mtk_gamma_set_common(void __iomem *regs,
> > struct drm_crtc_state *state);
> > void mtk_gamma_start(struct device *dev);
> > void mtk_gamma_stop(struct device *dev);
> >
> > +int mtk_merge_clk_enable(struct device *dev);
> > +void mtk_merge_clk_disable(struct device *dev);
> > +void mtk_merge_config(struct device *dev, unsigned int width,
> > + unsigned int height, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
> > +void mtk_merge_start(struct device *dev);
> > +void mtk_merge_stop(struct device *dev);
> > +
> > void mtk_ovl_bgclr_in_on(struct device *dev);
> > void mtk_ovl_bgclr_in_off(struct device *dev);
> > void mtk_ovl_bypass_shadow(struct device *dev);
> > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > new file mode 100644
> > index 000000000000..768c282d2d63
> > --- /dev/null
> > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
> > @@ -0,0 +1,372 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (c) 2021 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/component.h>
> > +#include <linux/of_device.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/soc/mediatek/mtk-cmdq.h>
> > +
> > +#include "mtk_drm_crtc.h"
> > +#include "mtk_drm_ddp_comp.h"
> > +#include "mtk_drm_drv.h"
> > +#include "mtk_disp_drv.h"
> > +
> > +#define DISP_REG_MERGE_CTRL (0x000)
> > +#define FLD_MERGE_EN BIT(0)
> > +#define FLD_MERGE_RST BIT(4)
> > +#define FLD_MERGE_LR_SWAP BIT(8)
> > +#define FLD_MERGE_DCM_DIS BIT(12)
> > +#define DISP_MERGE_CFG_0 0x010
> > +#define DISP_MERGE_CFG_4 0x020
> > +#define DISP_MERGE_CFG_10 0x038
> > +#define DISP_MERGE_CFG_12 0x040
> > +#define CFG_10_10_1PI_2PO_BUF_MODE 6
> > +#define CFG_10_10_2PI_2PO_BUF_MODE 8
> > +#define DISP_MERGE_CFG_24 0x070
> > +#define DISP_MERGE_CFG_25 0x074
> > +#define DISP_MERGE_CFG_36 0x0a0
> > +#define DISP_MERGE_CFG_36_FLD_ULTRA_EN REG_FLD(1, 0)
>
> #define DISP_MERGE_CFG_36_FLD_ULTRA_EN GENMASK(1, 0)
OK, I'll fefine these macro.
>
> > +#define DISP_MERGE_CFG_36_FLD_PREULTRA_EN REG_FLD(1, 4)
> > +#define DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN REG_FLD(1, 8)
> > +#define DISP_MERGE_CFG_36_VAL_ULTRA_EN(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_ULTRA_EN, val)
> > +#define DISP_MERGE_CFG_36_VAL_PREULTRA_EN(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_PREULTRA_EN, val)
> > +#define DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN, val)
> > +#define DISP_MERGE_CFG_37 0x0a4
> > +#define DISP_MERGE_CFG_37_FLD_BUFFER_MODE REG_FLD(2, 0)
> > +#define DISP_MERGE_CFG_37_VAL_BUFFER_MODE(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_37_FLD_BUFFER_MODE, val)
> > +#define DISP_MERGE_CFG_38 0x0a8
> > +#define DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA REG_FLD(1, 0)
> > +#define DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA REG_FLD(1, 4)
> > +#define DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VDE_BLOCK_ULTRA, val)
> > +#define DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULTRA(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_VALID_TH_BLOCK_ULTRA,
> > val)
> > +#define DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_TH(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_38_FLD_ULTRA_FIFO_VALID_TH, val)
> > +#define DISP_MERGE_CFG_39 0x0ac
> > +#define DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA REG_FLD(1, 8)
> > +#define DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA REG_FLD(1,
> > 12)
> > +#define DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH REG_FLD(16,
> > 16)
> > +#define DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTRA(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVDE_FORCE_PREULTRA, val)
> > +#define DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PREULTRA(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_NVALID_TH_FORCE_PREULTRA,
> > val)
> > +#define DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALID_TH(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_39_FLD_PREULTRA_FIFO_VALID_TH,
> > val)
> > +#define DISP_MERGE_CFG_40 0x0b0
> > +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW REG_FLD(16, 0)
> > +#define DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_LOW, (val))
> > +#define DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_40_FLD_ULTRA_TH_HIGH, val)
> > +#define DISP_MERGE_CFG_41 0x0b4
> > +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW REG_FLD(16, 0)
> > +#define DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH REG_FLD(16, 16)
> > +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_LOW, val)
> > +#define DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(val) \
> > + REG_FLD_VAL(DISP_MERGE_CFG_41_FLD_PREULTRA_TH_HIGH, val)
> > +
> > +struct mtk_merge_config_struct {
> > + unsigned short width_right;
> > + unsigned short width_left;
> > + unsigned int height;
> > + unsigned int mode;
> > +};
> > +
> > +struct mtk_disp_merge {
> > + enum mtk_ddp_comp_id comp_id;
> > + struct drm_crtc *crtc;
> > + struct clk *clk;
> > + struct clk *async_clk;
> > + void __iomem *regs;
> > + struct cmdq_client_reg cmdq_reg;
> > + u32 fifo_en;
> > +};
> > +
> > +void mtk_merge_start(struct device *dev)
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(NULL, 0x1, &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +void mtk_merge_stop(struct device *dev)
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + mtk_ddp_write(NULL, 0x0, &priv->cmdq_reg, priv->regs,
> > DISP_REG_MERGE_CTRL);
> > +}
> > +
> > +static int mtk_merge_check_params(struct mtk_merge_config_struct
> > *merge_config)
> > +{
> > + if (!merge_config->height ||
> > + !merge_config->width_left || !merge_config-
> > >width_right) {
> > + pr_err("%s:merge input width l(%u) w(%u) h(%u)\n",
> > + __func__, merge_config->width_left,
> > + merge_config->width_right, merge_config-
> > >height);
> > + return -EINVAL;
> > + }
> > + pr_debug("%s:merge input width l(%u) r(%u) height(%u)\n",
> > + __func__, merge_config->width_left,
> > + merge_config->width_right, merge_config->height);
> > + return 0;
> > +}
> > +
> > +static int mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
> > + struct cmdq_pkt *handle)
> > +{
> > + int ultra_en = 1;
> > + int preultra_en = 1;
> > + int halt_for_dvfs_en = 0;
> > + int buffer_mode = 3;
>
> Explain what is buffer_mode 3.
I'll add the comment at the next version.
/*
* 0 : Off
* 1 : SRAM 0
* 2 : SRAM 1
* 3 : SRAM 0 + SRAM 1
*/
>
> > + int vde_block_ultra = 0;
> > + int valid_th_block_ultra = 0;
> > + int ultra_fifo_valid_th = 0;
> > + int nvde_force_preultra = 0;
> > + int nvalid_th_force_preultra = 0;
> > + int preultra_fifo_valid_th = 0;
> > + int ultra_th_low = 0xe10;
> > + int ultra_th_high = 0x12c0;
> > + int preultra_th_low = 0x12c0;
> > + int preultra_th_high = 0x1518;
>
> For the threshold, I would like some formula like RDMA threshold,
>
> /*
> * Enable FIFO underflow since DSI and DPI can't be blocked.
> * Keep the FIFO pseudo size reset default of 8 KiB. Set the
> * output threshold to 6 microseconds with 7/6 overhead to
> * account for blanking, and with a pixel depth of 4 bytes:
> */
> threshold = width * height * vrefresh * 4 * 7 / 1000000;
>
>
OK, I'll change it to
/* 6us, 600M pixel/sec */
unsigned int ultra_th_low = 6 * 600;
/* 8us, 600M pixel/sec */
unsigned int ultra_th_high = 8 * 600;
/* 8us, 600M pixel/sec */
unsigned int preultra_th_low = 8 * 600;
/* 9us, 600M pixel/sec */
unsigned int preultra_th_high = 9 * 600;
at the next version.
> > +
> > + mtk_ddp_write_mask(handle,
> > + DISP_MERGE_CFG_36_VAL_ULTRA_EN(ultra_en)
> > |
> > + DISP_MERGE_CFG_36_VAL_PREULTRA_EN(preult
> > ra_en) |
> > + DISP_MERGE_CFG_36_VAL_HALT_FOR_DVFS_EN(h
> > alt_for_dvfs_en),
>
> Align to the coding style of other sub driver,
>
> halt_for_dvfs_en << 8 | preultra_en << 4 | ultra_en << 0,
>
OK, I'll fix it.
>
> > + &priv->cmdq_reg, priv->regs,
> > DISP_MERGE_CFG_36,
> > + REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_ULTRA
> > _EN) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_PREUL
> > TRA_EN) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_36_FLD_HALT_
> > FOR_DVFS_EN));
>
> Align to the coding style of other sub driver,
>
> DISP_MERGE_CFG_36_FLD_HALT_FOR_DVFS_EN |
> DISP_MERGE_CFG_36_FLD_PREULTRA_EN | DISP_MERGE_CFG_36_FLD_ULTRA_EN
>
OK, I'll fix it.
> > +
> > + mtk_ddp_write_mask(handle,
> > + DISP_MERGE_CFG_37_VAL_BUFFER_MODE(buffer
> > _mode),
> > + &priv->cmdq_reg, priv->regs,
> > DISP_MERGE_CFG_37,
> > + REG_FLD_MASK(DISP_MERGE_CFG_37_FLD_BUFFE
> > R_MODE));
> > +
> > + mtk_ddp_write_mask(handle,
> > + DISP_MERGE_CFG_38_VAL_VDE_BLOCK_ULTRA(vd
> > e_block_ultra) |
> > + DISP_MERGE_CFG_38_VAL_VALID_TH_BLOCK_ULT
> > RA(valid_th_block_ultra) |
> > + DISP_MERGE_CFG_38_VAL_ULTRA_FIFO_VALID_T
> > H(ultra_fifo_valid_th),
> > + &priv->cmdq_reg, priv->regs,
> > DISP_MERGE_CFG_38,
> > + REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_VDE_B
> > LOCK_ULTRA) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_VALID
> > _TH_BLOCK_ULTRA) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_38_FLD_ULTRA
> > _FIFO_VALID_TH));
> > +
> > + mtk_ddp_write_mask(handle,
> > + DISP_MERGE_CFG_39_VAL_NVDE_FORCE_PREULTR
> > A(nvde_force_preultra) |
> > + DISP_MERGE_CFG_39_VAL_NVALID_TH_FORCE_PR
> > EULTRA
> > + (nvalid_th_force_preultra) |
> > + DISP_MERGE_CFG_39_VAL_PREULTRA_FIFO_VALI
> > D_TH(preultra_fifo_valid_th),
> > + &priv->cmdq_reg, priv->regs,
> > DISP_MERGE_CFG_39,
> > + REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_NVDE_
> > FORCE_PREULTRA) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_NVALI
> > D_TH_FORCE_PREULTRA) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_39_FLD_PREUL
> > TRA_FIFO_VALID_TH));
> > +
> > + mtk_ddp_write_mask(handle,
> > + DISP_MERGE_CFG_40_VAL_ULTRA_TH_LOW(ultra
> > _th_low) |
> > + DISP_MERGE_CFG_40_VAL_ULTRA_TH_HIGH(ultr
> > a_th_high),
> > + &priv->cmdq_reg, priv->regs,
> > DISP_MERGE_CFG_40,
> > + REG_FLD_MASK(DISP_MERGE_CFG_40_FLD_ULTRA
> > _TH_LOW) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_40_FLD_ULTRA
> > _TH_HIGH));
> > +
> > + mtk_ddp_write_mask(handle,
> > + DISP_MERGE_CFG_41_VAL_PREULTRA_TH_LOW(pr
> > eultra_th_low) |
> > + DISP_MERGE_CFG_41_VAL_PREULTRA_TH_HIGH(p
> > reultra_th_high),
> > + &priv->cmdq_reg, priv->regs,
> > DISP_MERGE_CFG_41,
> > + REG_FLD_MASK(DISP_MERGE_CFG_41_FLD_PREUL
> > TRA_TH_LOW) |
> > + REG_FLD_MASK(DISP_MERGE_CFG_41_FLD_PREUL
> > TRA_TH_HIGH));
> > +
> > + return 0;
>
> This function always return 0, so change to void.
>
OK, I'll fix it.
> > +}
> > +
> > +void mtk_merge_config(struct device *dev, unsigned int w,
> > + unsigned int h, unsigned int vrefresh,
> > + unsigned int bpc, struct cmdq_pkt *handle)
> > +{
> > + struct mtk_merge_config_struct merge_config;
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->fifo_en)
> > + mtk_merge_fifo_setting(priv, handle);
> > +
> > + switch (priv->comp_id) {
>
> I think you should use priv->fifo_en instead of priv->comp_id.
OK, I'll fix it.
>
> > + case DDP_COMPONENT_MERGE0:
> > + merge_config.mode = CFG_10_10_1PI_2PO_BUF_MODE;
> > + merge_config.width_left = w;
> > + merge_config.width_right = w;
> > + merge_config.height = h;
> > + break;
> > + case DDP_COMPONENT_MERGE5:
> > + merge_config.mode = CFG_10_10_2PI_2PO_BUF_MODE;
> > + merge_config.width_left = w;
> > + merge_config.width_right = w;
> > + merge_config.height = h;
> > + break;
> > + default:
> > + pr_err("No find component merge %d\n", priv-
> > >comp_id);
> > + return;
> > + }
> > +
> > + mtk_merge_check_params(&merge_config);
>
> I think you should remove mtk_merge_check_params() and directly check
> w and h, and remove whole switch case.
>
OK, I'll remove it.
> > +
> > + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_MERGE_CFG_0);
> > +
> > + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_MERGE_CFG_4);
> > +
> > + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_MERGE_CFG_24);
> > +
> > + mtk_ddp_write(handle, (h << 16 | w), &priv->cmdq_reg, priv-
> > >regs,
> > + DISP_MERGE_CFG_25);
> > +
> > + /* no swap */
> > + mtk_ddp_write_mask(handle, 0, &priv->cmdq_reg, priv->regs,
> > + DISP_MERGE_CFG_10, 0x1f);
> > +
> > + mtk_ddp_write_mask(handle, merge_config.mode, &priv-
> > >cmdq_reg, priv->regs,
> > + DISP_MERGE_CFG_12, 0x1f);
> > +}
> > +
> > +int mtk_merge_clk_enable(struct device *dev)
> > +{
> > + int ret = 0;
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->clk) {
>
> clk_prepare_enable() would check this, so remove this check.
>
OK, I'll remove it.
> > + ret = clk_prepare_enable(priv->clk);
> > + if (ret)
> > + pr_err("merge clk prepare enable
> > failed\n");
> > + }
> > +
> > + if (priv->async_clk) {
> > + ret = clk_prepare_enable(priv->async_clk);
> > + if (ret)
> > + pr_err("async clk prepare enable
> > failed\n");
> > + }
> > +
> > + return ret;
> > +}
> > +
> > +void mtk_merge_clk_disable(struct device *dev)
> > +{
> > + struct mtk_disp_merge *priv = dev_get_drvdata(dev);
> > +
> > + if (priv->async_clk)
> > + clk_disable_unprepare(priv->async_clk);
> > +
> > + if (priv->clk)
> > + clk_disable_unprepare(priv->clk);
> > +}
> > +
> > +static int mtk_disp_merge_bind(struct device *dev, struct device
> > *master,
> > + void *data)
> > +{
> > + return 0;
> > +}
> > +
> > +static void mtk_disp_merge_unbind(struct device *dev, struct
> > device *master,
> > + void *data)
> > +{
> > +}
> > +
> > +static const struct component_ops mtk_disp_merge_component_ops = {
> > + .bind = mtk_disp_merge_bind,
> > + .unbind = mtk_disp_merge_unbind,
> > +};
> > +
> > +static int mtk_disp_merge_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + struct mtk_disp_merge *priv;
> > + enum mtk_ddp_comp_id comp_id;
> > + int ret;
> > +
> > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> > + if (!priv)
> > + return -ENOMEM;
> > +
> > + comp_id = mtk_ddp_comp_get_id(dev->of_node,
> > MTK_DISP_MERGE);
> > + if ((int)comp_id < 0) {
> > + dev_err(dev, "Failed to identify by alias: %d\n",
> > comp_id);
> > + return comp_id;
> > + }
> > +
> > + priv->comp_id = comp_id;
> > +
> > + priv->clk = devm_clk_get(dev, NULL);
> > + if (IS_ERR(priv->clk)) {
> > + dev_err(dev, "failed to get merge clk\n");
> > + return PTR_ERR(priv->clk);
> > + }
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + priv->regs = devm_ioremap_resource(dev, res);
> > + if (IS_ERR(priv->regs)) {
> > + dev_err(dev, "failed to ioremap merge\n");
> > + return PTR_ERR(priv->regs);
> > + }
> > +
> > +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> > + ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
> > + if (ret)
> > + dev_dbg(dev, "get mediatek,gce-client-reg
> > fail!\n");
> > +#endif
> > +
> > + priv->async_clk = of_clk_get(dev->of_node, 1);
> > + if (IS_ERR(priv->async_clk)) {
> > + ret = PTR_ERR(priv->async_clk);
> > + dev_dbg(dev, "No merge async clock: %d\n", ret);
> > + priv->async_clk = NULL;
> > + }
> > +
> > + priv->fifo_en = of_property_read_bool(dev->of_node,
> > + "mediatek,merge-fifo-en");
> > +
> > + platform_set_drvdata(pdev, priv);
> > +
> > + ret = component_add(dev, &mtk_disp_merge_component_ops);
> > + if (ret != 0)
> > + dev_err(dev, "Failed to add component: %d\n", ret);
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_disp_merge_remove(struct platform_device *pdev)
> > +{
> > + component_del(&pdev->dev, &mtk_disp_merge_component_ops);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id mtk_disp_merge_driver_dt_match[]
> > = {
> > + { .compatible = "mediatek,mt8195-disp-merge", },
> > + {},
> > +};
> > +
> > +MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
> > +
> > +struct platform_driver mtk_disp_merge_driver = {
> > + .probe = mtk_disp_merge_probe,
> > + .remove = mtk_disp_merge_remove,
> > + .driver = {
> > + .name = "mediatek-disp-merge",
> > + .owner = THIS_MODULE,
> > + .of_match_table = mtk_disp_merge_driver_dt_match,
> > + },
> > +};
> > +
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > index cb9a36c48d4f..66d1cf03dfe8 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.h
> > @@ -14,6 +14,20 @@
> > #define MTK_MAX_BPC 10
> > #define MTK_MIN_BPC 3
> >
> > +#define REG_FLD(width, shift) \
> > + ((unsigned int)((((width) & 0xff) << 16) | ((shift) &
> > 0xff)))
> > +
> > +#define REG_FLD_WIDTH(field) ((unsigned int)(((field) >> 16) &
> > 0xff))
> > +
> > +#define REG_FLD_SHIFT(field) ((unsigned int)((field) & 0xff))
> > +
> > +#define REG_FLD_MASK(field) \
> > + ((unsigned int)((1ULL << REG_FLD_WIDTH(field)) - 1) \
> > + << REG_FLD_SHIFT(field))
> > +
> > +#define REG_FLD_VAL(field, val) \
> > + (((val) << REG_FLD_SHIFT(field)) & REG_FLD_MASK(field))
> > +
I'll remove these marco.
> > void mtk_drm_crtc_commit(struct drm_crtc *crtc);
> > int mtk_drm_crtc_create(struct drm_device *drm_dev,
> > const enum mtk_ddp_comp_id *path,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > index ba3d7a1ce7ab..9125d0f6352f 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
> > @@ -341,6 +341,14 @@ static const struct mtk_ddp_comp_funcs ddp_dsc
> > = {
> > .clk_disable = mtk_dsc_clk_disable,
> > };
> >
> > +static const struct mtk_ddp_comp_funcs ddp_merge = {
> > + .clk_enable = mtk_merge_clk_enable,
> > + .clk_disable = mtk_merge_clk_disable,
> > + .start = mtk_merge_start,
> > + .stop = mtk_merge_stop,
> > + .config = mtk_merge_config,
> > +};
> > +
> > static const struct mtk_ddp_comp_funcs ddp_ufoe = {
> > .clk_enable = mtk_ddp_clk_enable,
> > .clk_disable = mtk_ddp_clk_disable,
> > @@ -365,6 +373,7 @@ static const char * const
> > mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
> > [MTK_DISP_OD] = "od",
> > [MTK_DISP_BLS] = "bls",
> > [MTK_DISP_DSC] = "dsc",
> > + [MTK_DISP_MERGE] = "merge",
> > };
> >
> > struct mtk_ddp_comp_match {
> > @@ -391,6 +400,12 @@ static const struct mtk_ddp_comp_match
> > mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
> > [DDP_COMPONENT_DSI2] = { MTK_DSI, 2, &ddp_dsi
> > },
> > [DDP_COMPONENT_DSI3] = { MTK_DSI, 3, &ddp_dsi
> > },
> > [DDP_COMPONENT_GAMMA] = { MTK_DISP_GAMMA, 0,
> > &ddp_gamma },
> > + [DDP_COMPONENT_MERGE0] = { MTK_DISP_MERGE, 0,
> > &ddp_merge },
> > + [DDP_COMPONENT_MERGE1] = { MTK_DISP_MERGE, 1,
> > &ddp_merge },
> > + [DDP_COMPONENT_MERGE2] = { MTK_DISP_MERGE, 2,
> > &ddp_merge },
> > + [DDP_COMPONENT_MERGE3] = { MTK_DISP_MERGE, 3,
> > &ddp_merge },
> > + [DDP_COMPONENT_MERGE4] = { MTK_DISP_MERGE, 4,
> > &ddp_merge },
> > + [DDP_COMPONENT_MERGE5] = { MTK_DISP_MERGE, 5,
> > &ddp_merge },
> > [DDP_COMPONENT_OD0] = { MTK_DISP_OD, 0, &ddp_od
> > },
> > [DDP_COMPONENT_OD1] = { MTK_DISP_OD, 1, &ddp_od
> > },
> > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, &ddp_ovl
> > },
> > @@ -522,6 +537,7 @@ int mtk_ddp_comp_init(struct device_node *node,
> > struct mtk_ddp_comp *comp,
> > type == MTK_DISP_COLOR ||
> > type == MTK_DISP_DSC ||
> > type == MTK_DISP_GAMMA ||
> > + type == MTK_DISP_MERGE ||
> > type == MTK_DISP_OVL ||
> > type == MTK_DISP_OVL_2L ||
> > type == MTK_DISP_PWM ||
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > index 661fb620e266..0afd78c0bc92 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
> > @@ -35,6 +35,7 @@ enum mtk_ddp_comp_type {
> > MTK_DISP_OD,
> > MTK_DISP_BLS,
> > MTK_DISP_DSC,
> > + MTK_DISP_MERGE,
> > MTK_DDP_COMP_TYPE_MAX,
> > };
> >
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > index 990a54049a7d..11c25daf05d8 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
> > @@ -448,6 +448,8 @@ static const struct of_device_id
> > mtk_ddp_comp_dt_ids[] = {
> > .data = (void *)MTK_DISP_DITHER },
> > { .compatible = "mediatek,mt8195-disp-dsc",
> > .data = (void *)MTK_DISP_DSC },
> > + { .compatible = "mediatek,mt8195-disp-merge",
> > + .data = (void *)MTK_DISP_MERGE },
> > { .compatible = "mediatek,mt8173-disp-ufoe",
> > .data = (void *)MTK_DISP_UFOE },
> > { .compatible = "mediatek,mt2701-dsi",
> > @@ -566,6 +568,7 @@ static int mtk_drm_probe(struct platform_device
> > *pdev)
> > comp_type == MTK_DISP_COLOR ||
> > comp_type == MTK_DISP_DSC ||
> > comp_type == MTK_DISP_GAMMA ||
> > + comp_type == MTK_DISP_MERGE ||
> > comp_type == MTK_DISP_OVL ||
> > comp_type == MTK_DISP_OVL_2L ||
> > comp_type == MTK_DISP_RDMA ||
> > @@ -667,6 +670,7 @@ static struct platform_driver * const
> > mtk_drm_drivers[] = {
> > &mtk_disp_color_driver,
> > &mtk_disp_dsc_driver,
> > &mtk_disp_gamma_driver,
> > + &mtk_disp_merge_driver,
> > &mtk_disp_ovl_driver,
> > &mtk_disp_rdma_driver,
> > &mtk_dpi_driver,
> > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > index 8b722330ef7d..c4d802a43531 100644
> > --- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > +++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
> > @@ -52,6 +52,7 @@ extern struct platform_driver
> > mtk_disp_gamma_driver;
> > extern struct platform_driver mtk_disp_ovl_driver;
> > extern struct platform_driver mtk_disp_rdma_driver;
> > extern struct platform_driver mtk_disp_dsc_driver;
> > +extern struct platform_driver mtk_disp_merge_driver;
>
> Alphabetic order.
OK, I'll fix it.
>
> Regards,
> Chun-Kuang.
>
> > extern struct platform_driver mtk_dpi_driver;
> > extern struct platform_driver mtk_dsi_driver;
> >
> > --
> > 2.18.0
> >
Regards,
Jason-JH Lin
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