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* [PATCHv2 0/2] coresight: Do not default to CPU0 for missing CPU phandle
@ 2019-06-20 18:31 Sai Prakash Ranjan
  2019-06-20 18:31 ` [PATCHv2 1/2] " Sai Prakash Ranjan
  2019-06-20 18:31 ` [PATCHv2 2/2] coresight: Abort probe if cpus are not available Sai Prakash Ranjan
  0 siblings, 2 replies; 7+ messages in thread
From: Sai Prakash Ranjan @ 2019-06-20 18:31 UTC (permalink / raw)
  To: Mathieu Poirier, Suzuki K Poulose, Leo Yan, Rob Herring,
	devicetree, Alexander Shishkin, Andy Gross, David Brown,
	Mark Rutland
  Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
	linux-kernel, linux-arm-msm, Sai Prakash Ranjan

In case of missing CPU phandle, the affinity is set default to
CPU0 which is not a correct assumption. Fix this in coresight
platform to set affinity to invalid and abort the probe in drivers.
Also update the dt-bindings accordingly.

Patch 2 allows the probe of coresight etm and cpu-debug to abort
earlier in case cpus are not available.

v2:
 * Addressed review comments from Suzuki and Mathieu.
 * Allows the probe of etm and cpu-debug to abort earlier
   in case of unavailability of respective cpus.

Sai Prakash Ranjan (2):
  coresight: Do not default to CPU0 for missing CPU phandle
  coresight: Abort probe if cpus are not available

 Documentation/devicetree/bindings/arm/coresight.txt |  2 +-
 drivers/hwtracing/coresight/coresight-cpu-debug.c   |  3 +++
 drivers/hwtracing/coresight/coresight-etm3x.c       |  3 +++
 drivers/hwtracing/coresight/coresight-etm4x.c       |  3 +++
 drivers/hwtracing/coresight/coresight-platform.c    | 13 ++++++++-----
 5 files changed, 18 insertions(+), 6 deletions(-)

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCHv2 1/2] coresight: Do not default to CPU0 for missing CPU phandle
  2019-06-20 18:31 [PATCHv2 0/2] coresight: Do not default to CPU0 for missing CPU phandle Sai Prakash Ranjan
@ 2019-06-20 18:31 ` " Sai Prakash Ranjan
  2019-06-21  9:48   ` Suzuki K Poulose
  2019-06-20 18:31 ` [PATCHv2 2/2] coresight: Abort probe if cpus are not available Sai Prakash Ranjan
  1 sibling, 1 reply; 7+ messages in thread
From: Sai Prakash Ranjan @ 2019-06-20 18:31 UTC (permalink / raw)
  To: Mathieu Poirier, Suzuki K Poulose, Leo Yan, Rob Herring,
	devicetree, Alexander Shishkin, Andy Gross, David Brown,
	Mark Rutland
  Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
	linux-kernel, linux-arm-msm, Sai Prakash Ranjan

Coresight platform support assumes that a missing "cpu" phandle
defaults to CPU0. This could be problematic and unnecessarily binds
components to CPU0, where they may not be. Let us make the DT binding
rules a bit stricter by not defaulting to CPU0 for missing "cpu"
affinity information.

Also in coresight etm and cpu-debug drivers, abort the probe
for such cases.

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 Documentation/devicetree/bindings/arm/coresight.txt |  2 +-
 drivers/hwtracing/coresight/coresight-cpu-debug.c   |  3 +++
 drivers/hwtracing/coresight/coresight-etm3x.c       |  3 +++
 drivers/hwtracing/coresight/coresight-etm4x.c       |  3 +++
 drivers/hwtracing/coresight/coresight-platform.c    | 10 +++++-----
 5 files changed, 15 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 8a88ddebc1a2..c4659ba9457d 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -88,7 +88,7 @@ its hardware characteristcs.
 	  registers via co-processor 14.
 
 	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
-	  source is considered to belong to CPU0.
+	  affinity is set to invalid.
 
 * Optional property for TMC:
 
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
index 07a1367c733f..58bfd6319f65 100644
--- a/drivers/hwtracing/coresight/coresight-cpu-debug.c
+++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
@@ -579,6 +579,9 @@ static int debug_probe(struct amba_device *adev, const struct amba_id *id)
 		return -ENOMEM;
 
 	drvdata->cpu = coresight_get_cpu(dev);
+	if (drvdata->cpu < 0)
+		return drvdata->cpu;
+
 	if (per_cpu(debug_drvdata, drvdata->cpu)) {
 		dev_err(dev, "CPU%d drvdata has already been initialized\n",
 			drvdata->cpu);
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index 225c2982e4fe..e2cb6873c3f2 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -816,6 +816,9 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
 	}
 
 	drvdata->cpu = coresight_get_cpu(dev);
+	if (drvdata->cpu < 0)
+		return drvdata->cpu;
+
 	desc.name  = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
 	if (!desc.name)
 		return -ENOMEM;
diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c
index 7fe266194ab5..7bcac8896fc1 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x.c
@@ -1101,6 +1101,9 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 	spin_lock_init(&drvdata->spinlock);
 
 	drvdata->cpu = coresight_get_cpu(dev);
+	if (drvdata->cpu < 0)
+		return drvdata->cpu;
+
 	desc.name = devm_kasprintf(dev, GFP_KERNEL, "etm%d", drvdata->cpu);
 	if (!desc.name)
 		return -ENOMEM;
diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
index 3c5ceda8db24..8b03fa573684 100644
--- a/drivers/hwtracing/coresight/coresight-platform.c
+++ b/drivers/hwtracing/coresight/coresight-platform.c
@@ -159,16 +159,16 @@ static int of_coresight_get_cpu(struct device *dev)
 	struct device_node *dn;
 
 	if (!dev->of_node)
-		return 0;
+		return -ENODEV;
+
 	dn = of_parse_phandle(dev->of_node, "cpu", 0);
-	/* Affinity defaults to CPU0 */
 	if (!dn)
-		return 0;
+		return -ENODEV;
+
 	cpu = of_cpu_node_to_id(dn);
 	of_node_put(dn);
 
-	/* Affinity to CPU0 if no cpu nodes are found */
-	return (cpu < 0) ? 0 : cpu;
+	return cpu;
 }
 
 /*
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 7+ messages in thread

* [PATCHv2 2/2] coresight: Abort probe if cpus are not available
  2019-06-20 18:31 [PATCHv2 0/2] coresight: Do not default to CPU0 for missing CPU phandle Sai Prakash Ranjan
  2019-06-20 18:31 ` [PATCHv2 1/2] " Sai Prakash Ranjan
@ 2019-06-20 18:31 ` Sai Prakash Ranjan
  2019-06-21  9:40   ` Suzuki K Poulose
  1 sibling, 1 reply; 7+ messages in thread
From: Sai Prakash Ranjan @ 2019-06-20 18:31 UTC (permalink / raw)
  To: Mathieu Poirier, Suzuki K Poulose, Leo Yan, Rob Herring,
	devicetree, Alexander Shishkin, Andy Gross, David Brown,
	Mark Rutland
  Cc: Rajendra Nayak, Vivek Gautam, Sibi Sankar, linux-arm-kernel,
	linux-kernel, linux-arm-msm, Sai Prakash Ranjan

Currently coresight etm and cpu-debug will go ahead with
the probe even when corresponding cpus are not available
and error out later in the probe path. In such cases, it
is better to abort the probe earlier.

Without this, setting *nosmp* will throw below errors:

 [    5.910622] coresight-cpu-debug 850000.debug: Coresight debug-CPU0 initialized
 [    5.914266] coresight-cpu-debug 852000.debug: CPU1 debug arch init failed
 [    5.921474] coresight-cpu-debug 854000.debug: CPU2 debug arch init failed
 [    5.928328] coresight-cpu-debug 856000.debug: CPU3 debug arch init failed
 [    5.935330] coresight etm0: CPU0: ETM v4.0 initialized
 [    5.941875] coresight-etm4x 85d000.etm: ETM arch init failed
 [    5.946794] coresight-etm4x: probe of 85d000.etm failed with error -22
 [    5.952707] coresight-etm4x 85e000.etm: ETM arch init failed
 [    5.958945] coresight-etm4x: probe of 85e000.etm failed with error -22
 [    5.964853] coresight-etm4x 85f000.etm: ETM arch init failed
 [    5.971096] coresight-etm4x: probe of 85f000.etm failed with error -22

Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
---
 drivers/hwtracing/coresight/coresight-platform.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
index 8b03fa573684..3f4559596c6b 100644
--- a/drivers/hwtracing/coresight/coresight-platform.c
+++ b/drivers/hwtracing/coresight/coresight-platform.c
@@ -168,6 +168,9 @@ static int of_coresight_get_cpu(struct device *dev)
 	cpu = of_cpu_node_to_id(dn);
 	of_node_put(dn);
 
+	if (num_online_cpus() <= cpu)
+		return -ENODEV;
+
 	return cpu;
 }
 
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation


^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCHv2 2/2] coresight: Abort probe if cpus are not available
  2019-06-20 18:31 ` [PATCHv2 2/2] coresight: Abort probe if cpus are not available Sai Prakash Ranjan
@ 2019-06-21  9:40   ` Suzuki K Poulose
  2019-06-21 10:31     ` Sai Prakash Ranjan
  0 siblings, 1 reply; 7+ messages in thread
From: Suzuki K Poulose @ 2019-06-21  9:40 UTC (permalink / raw)
  To: saiprakash.ranjan, mathieu.poirier, leo.yan, robh+dt, devicetree,
	alexander.shishkin, david.brown, mark.rutland
  Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
	linux-arm-msm

On 06/20/2019 07:31 PM, Sai Prakash Ranjan wrote:
> Currently coresight etm and cpu-debug will go ahead with
> the probe even when corresponding cpus are not available
> and error out later in the probe path. In such cases, it
> is better to abort the probe earlier.
> 
> Without this, setting *nosmp* will throw below errors:
> 
>   [    5.910622] coresight-cpu-debug 850000.debug: Coresight debug-CPU0 initialized
>   [    5.914266] coresight-cpu-debug 852000.debug: CPU1 debug arch init failed
>   [    5.921474] coresight-cpu-debug 854000.debug: CPU2 debug arch init failed
>   [    5.928328] coresight-cpu-debug 856000.debug: CPU3 debug arch init failed
>   [    5.935330] coresight etm0: CPU0: ETM v4.0 initialized
>   [    5.941875] coresight-etm4x 85d000.etm: ETM arch init failed
>   [    5.946794] coresight-etm4x: probe of 85d000.etm failed with error -22
>   [    5.952707] coresight-etm4x 85e000.etm: ETM arch init failed
>   [    5.958945] coresight-etm4x: probe of 85e000.etm failed with error -22
>   [    5.964853] coresight-etm4x 85f000.etm: ETM arch init failed
>   [    5.971096] coresight-etm4x: probe of 85f000.etm failed with error -22

That is expected. What else do you expect ?

> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> ---
>   drivers/hwtracing/coresight/coresight-platform.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
> index 8b03fa573684..3f4559596c6b 100644
> --- a/drivers/hwtracing/coresight/coresight-platform.c
> +++ b/drivers/hwtracing/coresight/coresight-platform.c
> @@ -168,6 +168,9 @@ static int of_coresight_get_cpu(struct device *dev)
>   	cpu = of_cpu_node_to_id(dn);
>   	of_node_put(dn);
>   
> +	if (num_online_cpus() <= cpu)
> +		return -ENODEV;

That is a pointless and terribly wrong check. What if you have only 2
online CPUs (CPU0 and CPU4) and you were processing the ETM for CPU4 ?

More over you should simply let the driver handle a case where the CPU
is not online. May be the driver could register a hotplug notifier and
bring itself up when the CPU comes online.

So, please drop this patch.

Kind regards
Suzuki

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCHv2 1/2] coresight: Do not default to CPU0 for missing CPU phandle
  2019-06-20 18:31 ` [PATCHv2 1/2] " Sai Prakash Ranjan
@ 2019-06-21  9:48   ` Suzuki K Poulose
  2019-06-21 10:33     ` Sai Prakash Ranjan
  0 siblings, 1 reply; 7+ messages in thread
From: Suzuki K Poulose @ 2019-06-21  9:48 UTC (permalink / raw)
  To: saiprakash.ranjan, mathieu.poirier, leo.yan, robh+dt, devicetree,
	alexander.shishkin, david.brown, mark.rutland
  Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
	linux-arm-msm

Hi Sai,


On 06/20/2019 07:31 PM, Sai Prakash Ranjan wrote:
> Coresight platform support assumes that a missing "cpu" phandle
> defaults to CPU0. This could be problematic and unnecessarily binds
> components to CPU0, where they may not be. Let us make the DT binding
> rules a bit stricter by not defaulting to CPU0 for missing "cpu"
> affinity information.
> 
> Also in coresight etm and cpu-debug drivers, abort the probe
> for such cases.
> 
> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>

Please drop this tag for now.

> ---
>   Documentation/devicetree/bindings/arm/coresight.txt |  2 +-
>   drivers/hwtracing/coresight/coresight-cpu-debug.c   |  3 +++
>   drivers/hwtracing/coresight/coresight-etm3x.c       |  3 +++
>   drivers/hwtracing/coresight/coresight-etm4x.c       |  3 +++
>   drivers/hwtracing/coresight/coresight-platform.c    | 10 +++++-----
>   5 files changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 8a88ddebc1a2..c4659ba9457d 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -88,7 +88,7 @@ its hardware characteristcs.
>   	  registers via co-processor 14.
>   
>   	* cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
> -	  source is considered to belong to CPU0.
> +	  affinity is set to invalid.
>   

Please move this from the "Optional properties". It is not "Optional"
anymore with this change. Please make sure it is evident that this
is mandatory. Also please fix the bindings document for cpu-debug.txt.


>   * Optional property for TMC:
>   

> diff --git a/drivers/hwtracing/coresight/coresight-platform.c b/drivers/hwtracing/coresight/coresight-platform.c
> index 3c5ceda8db24..8b03fa573684 100644
> --- a/drivers/hwtracing/coresight/coresight-platform.c
> +++ b/drivers/hwtracing/coresight/coresight-platform.c
> @@ -159,16 +159,16 @@ static int of_coresight_get_cpu(struct device *dev)
>   	struct device_node *dn;
>   
>   	if (!dev->of_node)
> -		return 0;
> +		return -ENODEV;
> +
>   	dn = of_parse_phandle(dev->of_node, "cpu", 0);
> -	/* Affinity defaults to CPU0 */
>   	if (!dn)
> -		return 0;
> +		return -ENODEV;
> +
>   	cpu = of_cpu_node_to_id(dn);
>   	of_node_put(dn);
>   

Please fix the acpi_coresight_get_cpu() for ACPI.

Rest looks fine to me.

Suzuki

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCHv2 2/2] coresight: Abort probe if cpus are not available
  2019-06-21  9:40   ` Suzuki K Poulose
@ 2019-06-21 10:31     ` Sai Prakash Ranjan
  0 siblings, 0 replies; 7+ messages in thread
From: Sai Prakash Ranjan @ 2019-06-21 10:31 UTC (permalink / raw)
  To: Suzuki K Poulose, mathieu.poirier, leo.yan, robh+dt, devicetree,
	alexander.shishkin, david.brown, mark.rutland
  Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
	linux-arm-msm

Hi Suzuki,

On 6/21/2019 3:10 PM, Suzuki K Poulose wrote:
> On 06/20/2019 07:31 PM, Sai Prakash Ranjan wrote:
>> Currently coresight etm and cpu-debug will go ahead with
>> the probe even when corresponding cpus are not available
>> and error out later in the probe path. In such cases, it
>> is better to abort the probe earlier.
>>
>> Without this, setting *nosmp* will throw below errors:
>>
>>   [    5.910622] coresight-cpu-debug 850000.debug: Coresight 
>> debug-CPU0 initialized
>>   [    5.914266] coresight-cpu-debug 852000.debug: CPU1 debug arch 
>> init failed
>>   [    5.921474] coresight-cpu-debug 854000.debug: CPU2 debug arch 
>> init failed
>>   [    5.928328] coresight-cpu-debug 856000.debug: CPU3 debug arch 
>> init failed
>>   [    5.935330] coresight etm0: CPU0: ETM v4.0 initialized
>>   [    5.941875] coresight-etm4x 85d000.etm: ETM arch init failed
>>   [    5.946794] coresight-etm4x: probe of 85d000.etm failed with 
>> error -22
>>   [    5.952707] coresight-etm4x 85e000.etm: ETM arch init failed
>>   [    5.958945] coresight-etm4x: probe of 85e000.etm failed with 
>> error -22
>>   [    5.964853] coresight-etm4x 85f000.etm: ETM arch init failed
>>   [    5.971096] coresight-etm4x: probe of 85f000.etm failed with 
>> error -22
> 
> That is expected. What else do you expect ?
> 
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> ---
>>   drivers/hwtracing/coresight/coresight-platform.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/hwtracing/coresight/coresight-platform.c 
>> b/drivers/hwtracing/coresight/coresight-platform.c
>> index 8b03fa573684..3f4559596c6b 100644
>> --- a/drivers/hwtracing/coresight/coresight-platform.c
>> +++ b/drivers/hwtracing/coresight/coresight-platform.c
>> @@ -168,6 +168,9 @@ static int of_coresight_get_cpu(struct device *dev)
>>       cpu = of_cpu_node_to_id(dn);
>>       of_node_put(dn);
>> +    if (num_online_cpus() <= cpu)
>> +        return -ENODEV;
> 
> That is a pointless and terribly wrong check. What if you have only 2
> online CPUs (CPU0 and CPU4) and you were processing the ETM for CPU4 ?
>

Sorry, I did not consider such cases.

> More over you should simply let the driver handle a case where the CPU
> is not online. May be the driver could register a hotplug notifier and
> bring itself up when the CPU comes online.
> 
> So, please drop this patch.
> 

Sure I will drop this patch.

Thanks,
Sai

-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

^ permalink raw reply	[flat|nested] 7+ messages in thread

* Re: [PATCHv2 1/2] coresight: Do not default to CPU0 for missing CPU phandle
  2019-06-21  9:48   ` Suzuki K Poulose
@ 2019-06-21 10:33     ` Sai Prakash Ranjan
  0 siblings, 0 replies; 7+ messages in thread
From: Sai Prakash Ranjan @ 2019-06-21 10:33 UTC (permalink / raw)
  To: Suzuki K Poulose, mathieu.poirier, leo.yan, robh+dt, devicetree,
	alexander.shishkin, david.brown, mark.rutland
  Cc: rnayak, vivek.gautam, sibis, linux-arm-kernel, linux-kernel,
	linux-arm-msm

Hello Suzuki,

On 6/21/2019 3:18 PM, Suzuki K Poulose wrote:
> Hi Sai,
> 
> 
> On 06/20/2019 07:31 PM, Sai Prakash Ranjan wrote:
>> Coresight platform support assumes that a missing "cpu" phandle
>> defaults to CPU0. This could be problematic and unnecessarily binds
>> components to CPU0, where they may not be. Let us make the DT binding
>> rules a bit stricter by not defaulting to CPU0 for missing "cpu"
>> affinity information.
>>
>> Also in coresight etm and cpu-debug drivers, abort the probe
>> for such cases.
>>
>> Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
>> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> 
> Please drop this tag for now.
> 

Ok will drop this.

>> ---
>>   Documentation/devicetree/bindings/arm/coresight.txt |  2 +-
>>   drivers/hwtracing/coresight/coresight-cpu-debug.c   |  3 +++
>>   drivers/hwtracing/coresight/coresight-etm3x.c       |  3 +++
>>   drivers/hwtracing/coresight/coresight-etm4x.c       |  3 +++
>>   drivers/hwtracing/coresight/coresight-platform.c    | 10 +++++-----
>>   5 files changed, 15 insertions(+), 6 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt 
>> b/Documentation/devicetree/bindings/arm/coresight.txt
>> index 8a88ddebc1a2..c4659ba9457d 100644
>> --- a/Documentation/devicetree/bindings/arm/coresight.txt
>> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
>> @@ -88,7 +88,7 @@ its hardware characteristcs.
>>         registers via co-processor 14.
>>       * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
>> -      source is considered to belong to CPU0.
>> +      affinity is set to invalid.
> 
> Please move this from the "Optional properties". It is not "Optional"
> anymore with this change. Please make sure it is evident that this
> is mandatory. Also please fix the bindings document for cpu-debug.txt.
> 
> 
>>   * Optional property for TMC:
> 
>> diff --git a/drivers/hwtracing/coresight/coresight-platform.c 
>> b/drivers/hwtracing/coresight/coresight-platform.c
>> index 3c5ceda8db24..8b03fa573684 100644
>> --- a/drivers/hwtracing/coresight/coresight-platform.c
>> +++ b/drivers/hwtracing/coresight/coresight-platform.c
>> @@ -159,16 +159,16 @@ static int of_coresight_get_cpu(struct device *dev)
>>       struct device_node *dn;
>>       if (!dev->of_node)
>> -        return 0;
>> +        return -ENODEV;
>> +
>>       dn = of_parse_phandle(dev->of_node, "cpu", 0);
>> -    /* Affinity defaults to CPU0 */
>>       if (!dn)
>> -        return 0;
>> +        return -ENODEV;
>> +
>>       cpu = of_cpu_node_to_id(dn);
>>       of_node_put(dn);
> 
> Please fix the acpi_coresight_get_cpu() for ACPI.
> 

Ok will do it. Thanks again for the review comments.

-Sai

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^ permalink raw reply	[flat|nested] 7+ messages in thread

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Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-06-20 18:31 [PATCHv2 0/2] coresight: Do not default to CPU0 for missing CPU phandle Sai Prakash Ranjan
2019-06-20 18:31 ` [PATCHv2 1/2] " Sai Prakash Ranjan
2019-06-21  9:48   ` Suzuki K Poulose
2019-06-21 10:33     ` Sai Prakash Ranjan
2019-06-20 18:31 ` [PATCHv2 2/2] coresight: Abort probe if cpus are not available Sai Prakash Ranjan
2019-06-21  9:40   ` Suzuki K Poulose
2019-06-21 10:31     ` Sai Prakash Ranjan

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