* [PATCH v1 0/9] clk: qcom: Introduce parent_map tables
@ 2015-03-18 13:32 Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 1/9] clk: qcom: Fix clk_get_parent function return value Georgi Djakov
` (9 more replies)
0 siblings, 10 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
This patchset introduces the parent_map index tables, which solve the
issue discussed here [1].
While doing this, fix also some of the code around (patches 1 and 2)
[1] https://lkml.org/lkml/2015/3/5/682
Patchset based on clk-next.
Georgi Djakov (9):
clk: qcom: Fix clk_get_parent function return value
clk: qcom: Do some error handling in configure_bank()
clk: qcom: Introduce parent_map tables
clk: qcom: Make RCGs use the parent_map struct
clk: qcom: Convert apq8084 to parent_map tables
clk: qcom: Convert msm8974 to parent_map tables
clk: qcom: Convert msm8960 to parent_map tables
clk: qcom: Convert ipq806x to parent_map tables
clk: qcom: Convert msm8660 to parent_map tables
drivers/clk/qcom/clk-rcg.c | 99 +++++++++++++++-------
drivers/clk/qcom/clk-rcg.h | 15 +++-
drivers/clk/qcom/clk-rcg2.c | 18 ++--
drivers/clk/qcom/common.c | 17 ++++
drivers/clk/qcom/common.h | 2 +
drivers/clk/qcom/gcc-apq8084.c | 70 ++++++++-------
drivers/clk/qcom/gcc-ipq806x.c | 51 ++++++-----
drivers/clk/qcom/gcc-msm8660.c | 24 +++---
drivers/clk/qcom/gcc-msm8960.c | 35 ++++----
drivers/clk/qcom/gcc-msm8974.c | 33 +++++---
drivers/clk/qcom/lcc-ipq806x.c | 13 +--
drivers/clk/qcom/lcc-msm8960.c | 13 +--
drivers/clk/qcom/mmcc-apq8084.c | 178 +++++++++++++++++++++------------------
drivers/clk/qcom/mmcc-msm8960.c | 53 ++++++------
drivers/clk/qcom/mmcc-msm8974.c | 142 ++++++++++++++++---------------
15 files changed, 448 insertions(+), 315 deletions(-)
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v1 1/9] clk: qcom: Fix clk_get_parent function return value
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 2/9] clk: qcom: Do some error handling in configure_bank() Georgi Djakov
` (8 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
According to the common clock framework API, the clk_get_parent() function
should return u8. Currently we are returning negative values on error. Fix
this and use the default parent in case of an error.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/clk-rcg.c | 26 +++++++++++++++++++-------
drivers/clk/qcom/clk-rcg2.c | 7 +++++--
2 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 466f30ca65c2..59a093e56366 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -47,15 +47,20 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
struct clk_rcg *rcg = to_clk_rcg(hw);
int num_parents = __clk_get_num_parents(hw->clk);
u32 ns;
- int i;
+ int i, ret;
- regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+ ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
+ if (ret)
+ goto err;
ns = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++)
if (ns == rcg->s.parent_map[i])
return i;
- return -EINVAL;
+err:
+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
+ __func__, __clk_get_name(hw->clk));
+ return 0;
}
static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank)
@@ -70,21 +75,28 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
int num_parents = __clk_get_num_parents(hw->clk);
u32 ns, reg;
int bank;
- int i;
+ int i, ret;
struct src_sel *s;
- regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
+ ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
+ if (ret)
+ goto err;
bank = reg_to_bank(rcg, reg);
s = &rcg->s[bank];
- regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
+ ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns);
+ if (ret)
+ goto err;
ns = ns_to_src(s, ns);
for (i = 0; i < num_parents; i++)
if (ns == s->parent_map[i])
return i;
- return -EINVAL;
+err:
+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
+ __func__, __clk_get_name(hw->clk));
+ return 0;
}
static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 742acfa18d63..6f27c5c614cc 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -69,7 +69,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg);
if (ret)
- return ret;
+ goto err;
cfg &= CFG_SRC_SEL_MASK;
cfg >>= CFG_SRC_SEL_SHIFT;
@@ -78,7 +78,10 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
if (cfg == rcg->parent_map[i])
return i;
- return -EINVAL;
+err:
+ pr_debug("%s: Clock %s has invalid parent, using default.\n",
+ __func__, __clk_get_name(hw->clk));
+ return 0;
}
static int update_config(struct clk_rcg2 *rcg)
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 2/9] clk: qcom: Do some error handling in configure_bank()
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 1/9] clk: qcom: Fix clk_get_parent function return value Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 3/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (7 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Currently configure_bank() returns void. Add some error
checking on the regmap calls and propagate if there is
any error.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/clk-rcg.c | 62 +++++++++++++++++++++++++++++---------------
1 file changed, 41 insertions(+), 21 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 59a093e56366..64d98c62459d 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -203,10 +203,10 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
return val;
}
-static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
+static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
{
u32 ns, md, reg;
- int bank, new_bank;
+ int bank, new_bank, ret;
struct mn *mn;
struct pre_div *p;
struct src_sel *s;
@@ -218,38 +218,55 @@ static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
enabled = __clk_is_enabled(hw->clk);
- regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
+ ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
+ if (ret)
+ return ret;
bank = reg_to_bank(rcg, reg);
new_bank = enabled ? !bank : bank;
ns_reg = rcg->ns_reg[new_bank];
- regmap_read(rcg->clkr.regmap, ns_reg, &ns);
+ ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns);
+ if (ret)
+ return ret;
if (banked_mn) {
mn = &rcg->mn[new_bank];
md_reg = rcg->md_reg[new_bank];
ns |= BIT(mn->mnctr_reset_bit);
- regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ if (ret)
+ return ret;
- regmap_read(rcg->clkr.regmap, md_reg, &md);
+ ret = regmap_read(rcg->clkr.regmap, md_reg, &md);
+ if (ret)
+ return ret;
md = mn_to_md(mn, f->m, f->n, md);
- regmap_write(rcg->clkr.regmap, md_reg, md);
-
+ ret = regmap_write(rcg->clkr.regmap, md_reg, md);
+ if (ret)
+ return ret;
ns = mn_to_ns(mn, f->m, f->n, ns);
- regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ if (ret)
+ return ret;
/* Two NS registers means mode control is in NS register */
if (rcg->ns_reg[0] != rcg->ns_reg[1]) {
ns = mn_to_reg(mn, f->m, f->n, ns);
- regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ if (ret)
+ return ret;
} else {
reg = mn_to_reg(mn, f->m, f->n, reg);
- regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+ ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+ if (ret)
+ return ret;
}
ns &= ~BIT(mn->mnctr_reset_bit);
- regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ if (ret)
+ return ret;
}
if (banked_p) {
@@ -259,13 +276,20 @@ static void configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
s = &rcg->s[new_bank];
ns = src_to_ns(s, s->parent_map[f->src], ns);
- regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
+ if (ret)
+ return ret;
if (enabled) {
- regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
+ ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®);
+ if (ret)
+ return ret;
reg ^= BIT(rcg->mux_sel_bit);
- regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+ ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg);
+ if (ret)
+ return ret;
}
+ return 0;
}
static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
@@ -292,9 +316,7 @@ static int clk_dyn_rcg_set_parent(struct clk_hw *hw, u8 index)
f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1;
f.src = index;
- configure_bank(rcg, &f);
-
- return 0;
+ return configure_bank(rcg, &f);
}
/*
@@ -567,9 +589,7 @@ static int __clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate)
if (!f)
return -EINVAL;
- configure_bank(rcg, f);
-
- return 0;
+ return configure_bank(rcg, f);
}
static int clk_dyn_rcg_set_rate(struct clk_hw *hw, unsigned long rate,
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 3/9] clk: qcom: Introduce parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 1/9] clk: qcom: Fix clk_get_parent function return value Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 2/9] clk: qcom: Do some error handling in configure_bank() Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 4/9] clk: qcom: Make RCGs use the parent_map struct Georgi Djakov
` (6 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Define a parent_map struct to describe the relations between
PLL source index and register configuration value.
Add a qcom_find_src_index() function for finding the index of
a clock matching the specific PLL configuration
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/clk-rcg.h | 11 +++++++++++
drivers/clk/qcom/common.c | 17 +++++++++++++++++
drivers/clk/qcom/common.h | 2 ++
3 files changed, 30 insertions(+)
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index d09d06ba278e..6d94d5300e9e 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -26,6 +26,17 @@ struct freq_tbl {
};
/**
+ * struct parent_map - map table for PLL source select configuration values
+ *
+ * @src: source PLL
+ * @cfg: configuration value
+ */
+struct parent_map {
+ u8 src;
+ u8 cfg;
+};
+
+/**
* struct mn - M/N:D counter
* @mnctr_en_bit: bit to enable mn counter
* @mnctr_reset_bit: bit to assert mn counter reset
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index e20d947db3e5..a946b48f2d82 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -43,6 +43,23 @@ struct freq_tbl *qcom_find_freq(const struct freq_tbl *f, unsigned long rate)
}
EXPORT_SYMBOL_GPL(qcom_find_freq);
+int qcom_find_src_index(const struct parent_map *map, u8 src)
+{
+ int i = 0;
+
+ if (!map)
+ return -EINVAL;
+
+ do {
+ if (src == map->src)
+ return i;
+ i++;
+ } while (map++);
+
+ return -ENOENT;
+}
+EXPORT_SYMBOL_GPL(qcom_find_src_index);
+
struct regmap *
qcom_cc_map(struct platform_device *pdev, const struct qcom_cc_desc *desc)
{
diff --git a/drivers/clk/qcom/common.h b/drivers/clk/qcom/common.h
index f519322acdf3..b3d7e5716f5e 100644
--- a/drivers/clk/qcom/common.h
+++ b/drivers/clk/qcom/common.h
@@ -19,6 +19,7 @@ struct clk_regmap;
struct qcom_reset_map;
struct regmap;
struct freq_tbl;
+struct parent_map;
struct qcom_cc_desc {
const struct regmap_config *config;
@@ -30,6 +31,7 @@ struct qcom_cc_desc {
extern const struct freq_tbl *qcom_find_freq(const struct freq_tbl *f,
unsigned long rate);
+extern int qcom_find_src_index(const struct parent_map *map, u8 src);
extern struct regmap *qcom_cc_map(struct platform_device *pdev,
const struct qcom_cc_desc *desc);
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 4/9] clk: qcom: Make RCGs use the parent_map struct
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (2 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 3/9] clk: qcom: Introduce parent_map tables Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 5/9] clk: qcom: Convert apq8084 to parent_map tables Georgi Djakov
` (5 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Switch RCG functions to use of the newly introduced
parent_map struct.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/clk-rcg.c | 13 ++++++++-----
drivers/clk/qcom/clk-rcg.h | 4 ++--
drivers/clk/qcom/clk-rcg2.c | 11 +++++++----
3 files changed, 17 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg.c b/drivers/clk/qcom/clk-rcg.c
index 64d98c62459d..6eab85882a43 100644
--- a/drivers/clk/qcom/clk-rcg.c
+++ b/drivers/clk/qcom/clk-rcg.c
@@ -54,7 +54,7 @@ static u8 clk_rcg_get_parent(struct clk_hw *hw)
goto err;
ns = ns_to_src(&rcg->s, ns);
for (i = 0; i < num_parents; i++)
- if (ns == rcg->s.parent_map[i])
+ if (ns == rcg->s.parent_map[i].cfg)
return i;
err:
@@ -90,7 +90,7 @@ static u8 clk_dyn_rcg_get_parent(struct clk_hw *hw)
ns = ns_to_src(s, ns);
for (i = 0; i < num_parents; i++)
- if (ns == s->parent_map[i])
+ if (ns == s->parent_map[i].cfg)
return i;
err:
@@ -105,7 +105,7 @@ static int clk_rcg_set_parent(struct clk_hw *hw, u8 index)
u32 ns;
regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns);
- ns = src_to_ns(&rcg->s, rcg->s.parent_map[index], ns);
+ ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns);
regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns);
return 0;
@@ -206,7 +206,7 @@ static u32 mn_to_reg(struct mn *mn, u32 m, u32 n, u32 val)
static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
{
u32 ns, md, reg;
- int bank, new_bank, ret;
+ int bank, new_bank, ret, index;
struct mn *mn;
struct pre_div *p;
struct src_sel *s;
@@ -275,7 +275,10 @@ static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f)
}
s = &rcg->s[new_bank];
- ns = src_to_ns(s, s->parent_map[f->src], ns);
+ index = qcom_find_src_index(s->parent_map, f->src);
+ if (index < 0)
+ return index;
+ ns = src_to_ns(s, s->parent_map[index].cfg, ns);
ret = regmap_write(rcg->clkr.regmap, ns_reg, ns);
if (ret)
return ret;
diff --git a/drivers/clk/qcom/clk-rcg.h b/drivers/clk/qcom/clk-rcg.h
index 6d94d5300e9e..4a5aa5f125a5 100644
--- a/drivers/clk/qcom/clk-rcg.h
+++ b/drivers/clk/qcom/clk-rcg.h
@@ -76,7 +76,7 @@ struct pre_div {
struct src_sel {
u8 src_sel_shift;
#define SRC_SEL_MASK 0x7
- const u8 *parent_map;
+ const struct parent_map *parent_map;
};
/**
@@ -162,7 +162,7 @@ struct clk_rcg2 {
u32 cmd_rcgr;
u8 mnd_width;
u8 hid_width;
- const u8 *parent_map;
+ const struct parent_map *parent_map;
const struct freq_tbl *freq_tbl;
struct clk_regmap clkr;
};
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index 6f27c5c614cc..15cbba3d41fe 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -75,7 +75,7 @@ static u8 clk_rcg2_get_parent(struct clk_hw *hw)
cfg >>= CFG_SRC_SEL_SHIFT;
for (i = 0; i < num_parents; i++)
- if (cfg == rcg->parent_map[i])
+ if (cfg == rcg->parent_map[i].cfg)
return i;
err:
@@ -117,7 +117,7 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG,
CFG_SRC_SEL_MASK,
- rcg->parent_map[index] << CFG_SRC_SEL_SHIFT);
+ rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT);
if (ret)
return ret;
@@ -222,7 +222,7 @@ static long clk_rcg2_determine_rate(struct clk_hw *hw, unsigned long rate,
static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
{
u32 cfg, mask;
- int ret;
+ int ret, index;
if (rcg->mnd_width && f->n) {
mask = BIT(rcg->mnd_width) - 1;
@@ -245,7 +245,10 @@ static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f)
mask = BIT(rcg->hid_width) - 1;
mask |= CFG_SRC_SEL_MASK | CFG_MODE_MASK;
cfg = f->pre_div << CFG_SRC_DIV_SHIFT;
- cfg |= rcg->parent_map[f->src] << CFG_SRC_SEL_SHIFT;
+ index = qcom_find_src_index(rcg->parent_map, f->src);
+ if (index < 0)
+ return index;
+ cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT;
if (rcg->mnd_width && f->n)
cfg |= CFG_MODE_DUAL_EDGE;
ret = regmap_update_bits(rcg->clkr.regmap,
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 5/9] clk: qcom: Convert apq8084 to parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (3 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 4/9] clk: qcom: Make RCGs use the parent_map struct Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 6/9] clk: qcom: Convert msm8974 " Georgi Djakov
` (4 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/gcc-apq8084.c | 70 ++++++++-------
drivers/clk/qcom/mmcc-apq8084.c | 178 +++++++++++++++++++++------------------
2 files changed, 134 insertions(+), 114 deletions(-)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index e3ef90264214..f75b505a13b8 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -32,18 +32,21 @@
#include "clk-branch.h"
#include "reset.h"
-#define P_XO 0
-#define P_GPLL0 1
-#define P_GPLL1 1
-#define P_GPLL4 2
-#define P_PCIE_0_1_PIPE_CLK 1
-#define P_SATA_ASIC0_CLK 1
-#define P_SATA_RX_CLK 1
-#define P_SLEEP_CLK 1
-
-static const u8 gcc_xo_gpll0_map[] = {
- [P_XO] = 0,
- [P_GPLL0] = 1,
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+ P_PCIE_0_1_PIPE_CLK,
+ P_SATA_ASIC0_CLK,
+ P_SATA_RX_CLK,
+ P_SLEEP_CLK,
+};
+
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { }
};
static const char *gcc_xo_gpll0[] = {
@@ -51,10 +54,11 @@ static const char *gcc_xo_gpll0[] = {
"gpll0_vote",
};
-static const u8 gcc_xo_gpll0_gpll4_map[] = {
- [P_XO] = 0,
- [P_GPLL0] = 1,
- [P_GPLL4] = 5,
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { }
};
static const char *gcc_xo_gpll0_gpll4[] = {
@@ -63,9 +67,10 @@ static const char *gcc_xo_gpll0_gpll4[] = {
"gpll4_vote",
};
-static const u8 gcc_xo_sata_asic0_map[] = {
- [P_XO] = 0,
- [P_SATA_ASIC0_CLK] = 2,
+static const struct parent_map gcc_xo_sata_asic0_map[] = {
+ { P_XO, 0 },
+ { P_SATA_ASIC0_CLK, 2 },
+ { }
};
static const char *gcc_xo_sata_asic0[] = {
@@ -73,9 +78,10 @@ static const char *gcc_xo_sata_asic0[] = {
"sata_asic0_clk",
};
-static const u8 gcc_xo_sata_rx_map[] = {
- [P_XO] = 0,
- [P_SATA_RX_CLK] = 2,
+static const struct parent_map gcc_xo_sata_rx_map[] = {
+ { P_XO, 0 },
+ { P_SATA_RX_CLK, 2},
+ { }
};
static const char *gcc_xo_sata_rx[] = {
@@ -83,9 +89,10 @@ static const char *gcc_xo_sata_rx[] = {
"sata_rx_clk",
};
-static const u8 gcc_xo_pcie_map[] = {
- [P_XO] = 0,
- [P_PCIE_0_1_PIPE_CLK] = 2,
+static const struct parent_map gcc_xo_pcie_map[] = {
+ { P_XO, 0 },
+ { P_PCIE_0_1_PIPE_CLK, 2 },
+ { }
};
static const char *gcc_xo_pcie[] = {
@@ -93,9 +100,10 @@ static const char *gcc_xo_pcie[] = {
"pcie_pipe",
};
-static const u8 gcc_xo_pcie_sleep_map[] = {
- [P_XO] = 0,
- [P_SLEEP_CLK] = 6,
+static const struct parent_map gcc_xo_pcie_sleep_map[] = {
+ { P_XO, 0 },
+ { P_SLEEP_CLK, 6 },
+ { }
};
static const char *gcc_xo_pcie_sleep[] = {
@@ -1263,9 +1271,9 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
{ }
};
-static u8 usb_hsic_clk_src_map[] = {
- [P_XO] = 0,
- [P_GPLL1] = 4,
+static const struct parent_map usb_hsic_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_GPLL1, 4 },
};
static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
index 157139a5c1ca..0fe93fd85a43 100644
--- a/drivers/clk/qcom/mmcc-apq8084.c
+++ b/drivers/clk/qcom/mmcc-apq8084.c
@@ -27,28 +27,31 @@
#include "clk-branch.h"
#include "reset.h"
-#define P_XO 0
-#define P_MMPLL0 1
-#define P_EDPLINK 1
-#define P_MMPLL1 2
-#define P_HDMIPLL 2
-#define P_GPLL0 3
-#define P_EDPVCO 3
-#define P_MMPLL4 4
-#define P_DSI0PLL 4
-#define P_DSI0PLL_BYTE 4
-#define P_MMPLL2 4
-#define P_MMPLL3 4
-#define P_GPLL1 5
-#define P_DSI1PLL 5
-#define P_DSI1PLL_BYTE 5
-#define P_MMSLEEP 6
-
-static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
+enum {
+ P_XO,
+ P_MMPLL0,
+ P_EDPLINK,
+ P_MMPLL1,
+ P_HDMIPLL,
+ P_GPLL0,
+ P_EDPVCO,
+ P_MMPLL4,
+ P_DSI0PLL,
+ P_DSI0PLL_BYTE,
+ P_MMPLL2,
+ P_MMPLL3,
+ P_GPLL1,
+ P_DSI1PLL,
+ P_DSI1PLL_BYTE,
+ P_MMSLEEP,
+};
+
+static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { }
};
static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -58,13 +61,14 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
"mmss_gpll0_vote",
};
-static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_HDMIPLL] = 4,
- [P_GPLL0] = 5,
- [P_DSI0PLL] = 2,
- [P_DSI1PLL] = 3,
+static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_HDMIPLL, 4 },
+ { P_GPLL0, 5 },
+ { P_DSI0PLL, 2 },
+ { P_DSI1PLL, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -76,12 +80,13 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
"dsi1pll",
};
-static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
- [P_MMPLL2] = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { P_MMPLL2, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -92,12 +97,13 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
"mmpll2",
};
-static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
- [P_MMPLL3] = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { P_MMPLL3, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -108,13 +114,14 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
"mmpll3",
};
-static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
- [P_XO] = 0,
- [P_EDPLINK] = 4,
- [P_HDMIPLL] = 3,
- [P_EDPVCO] = 5,
- [P_DSI0PLL] = 1,
- [P_DSI1PLL] = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
+ { P_XO, 0 },
+ { P_EDPLINK, 4 },
+ { P_HDMIPLL, 3 },
+ { P_EDPVCO, 5 },
+ { P_DSI0PLL, 1 },
+ { P_DSI1PLL, 2 },
+ { }
};
static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -126,13 +133,14 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
"dsi1pll",
};
-static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
- [P_XO] = 0,
- [P_EDPLINK] = 4,
- [P_HDMIPLL] = 3,
- [P_GPLL0] = 5,
- [P_DSI0PLL] = 1,
- [P_DSI1PLL] = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_EDPLINK, 4 },
+ { P_HDMIPLL, 3 },
+ { P_GPLL0, 5 },
+ { P_DSI0PLL, 1 },
+ { P_DSI1PLL, 2 },
+ { }
};
static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -144,13 +152,14 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
"dsi1pll",
};
-static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
- [P_XO] = 0,
- [P_EDPLINK] = 4,
- [P_HDMIPLL] = 3,
- [P_GPLL0] = 5,
- [P_DSI0PLL_BYTE] = 1,
- [P_DSI1PLL_BYTE] = 2,
+static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_EDPLINK, 4 },
+ { P_HDMIPLL, 3 },
+ { P_GPLL0, 5 },
+ { P_DSI0PLL_BYTE, 1 },
+ { P_DSI1PLL_BYTE, 2 },
+ { }
};
static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
@@ -162,12 +171,13 @@ static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
"dsi1pllbyte",
};
-static const u8 mmcc_xo_mmpll0_1_4_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
- [P_MMPLL4] = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_4_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { P_MMPLL4, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
@@ -178,13 +188,14 @@ static const char *mmcc_xo_mmpll0_1_4_gpll0[] = {
"gpll0",
};
-static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_MMPLL4] = 3,
- [P_GPLL0] = 5,
- [P_GPLL1] = 4,
+static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_MMPLL4, 3 },
+ { P_GPLL0, 5 },
+ { P_GPLL1, 4 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
@@ -196,14 +207,15 @@ static const char *mmcc_xo_mmpll0_1_4_gpll1_0[] = {
"gpll0",
};
-static const u8 mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_MMPLL4] = 3,
- [P_GPLL0] = 5,
- [P_GPLL1] = 4,
- [P_MMSLEEP] = 6,
+static const struct parent_map mmcc_xo_mmpll0_1_4_gpll1_0_sleep_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_MMPLL4, 3 },
+ { P_GPLL0, 5 },
+ { P_GPLL1, 4 },
+ { P_MMSLEEP, 6 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_4_gpll1_0_sleep[] = {
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 6/9] clk: qcom: Convert msm8974 to parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (4 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 5/9] clk: qcom: Convert apq8084 to parent_map tables Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 7/9] clk: qcom: Convert msm8960 " Georgi Djakov
` (3 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/gcc-msm8974.c | 33 +++++----
drivers/clk/qcom/mmcc-msm8974.c | 142 +++++++++++++++++++++------------------
2 files changed, 95 insertions(+), 80 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8974.c b/drivers/clk/qcom/gcc-msm8974.c
index a6937fe78d8a..a7141145e902 100644
--- a/drivers/clk/qcom/gcc-msm8974.c
+++ b/drivers/clk/qcom/gcc-msm8974.c
@@ -32,14 +32,17 @@
#include "clk-branch.h"
#include "reset.h"
-#define P_XO 0
-#define P_GPLL0 1
-#define P_GPLL1 1
-#define P_GPLL4 2
+enum {
+ P_XO,
+ P_GPLL0,
+ P_GPLL1,
+ P_GPLL4,
+};
-static const u8 gcc_xo_gpll0_map[] = {
- [P_XO] = 0,
- [P_GPLL0] = 1,
+static const struct parent_map gcc_xo_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1},
+ { }
};
static const char *gcc_xo_gpll0[] = {
@@ -47,10 +50,11 @@ static const char *gcc_xo_gpll0[] = {
"gpll0_vote",
};
-static const u8 gcc_xo_gpll0_gpll4_map[] = {
- [P_XO] = 0,
- [P_GPLL0] = 1,
- [P_GPLL4] = 5,
+static const struct parent_map gcc_xo_gpll0_gpll4_map[] = {
+ { P_XO, 0 },
+ { P_GPLL0, 1 },
+ { P_GPLL4, 5 },
+ { }
};
static const char *gcc_xo_gpll0_gpll4[] = {
@@ -984,9 +988,10 @@ static const struct freq_tbl ftbl_gcc_usb_hsic_clk[] = {
{ }
};
-static u8 usb_hsic_clk_src_map[] = {
- [P_XO] = 0,
- [P_GPLL1] = 4,
+static const struct parent_map usb_hsic_clk_src_map[] = {
+ { P_XO, 0 },
+ { P_GPLL1, 4 },
+ { }
};
static struct clk_rcg2 usb_hsic_clk_src = {
diff --git a/drivers/clk/qcom/mmcc-msm8974.c b/drivers/clk/qcom/mmcc-msm8974.c
index be94c54a9a4f..a3b7af3ace43 100644
--- a/drivers/clk/qcom/mmcc-msm8974.c
+++ b/drivers/clk/qcom/mmcc-msm8974.c
@@ -32,26 +32,29 @@
#include "clk-branch.h"
#include "reset.h"
-#define P_XO 0
-#define P_MMPLL0 1
-#define P_EDPLINK 1
-#define P_MMPLL1 2
-#define P_HDMIPLL 2
-#define P_GPLL0 3
-#define P_EDPVCO 3
-#define P_GPLL1 4
-#define P_DSI0PLL 4
-#define P_DSI0PLL_BYTE 4
-#define P_MMPLL2 4
-#define P_MMPLL3 4
-#define P_DSI1PLL 5
-#define P_DSI1PLL_BYTE 5
-
-static const u8 mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
+enum {
+ P_XO,
+ P_MMPLL0,
+ P_EDPLINK,
+ P_MMPLL1,
+ P_HDMIPLL,
+ P_GPLL0,
+ P_EDPVCO,
+ P_GPLL1,
+ P_DSI0PLL,
+ P_DSI0PLL_BYTE,
+ P_MMPLL2,
+ P_MMPLL3,
+ P_DSI1PLL,
+ P_DSI1PLL_BYTE,
+};
+
+static const struct parent_map mmcc_xo_mmpll0_mmpll1_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { }
};
static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
@@ -61,13 +64,14 @@ static const char *mmcc_xo_mmpll0_mmpll1_gpll0[] = {
"mmss_gpll0_vote",
};
-static const u8 mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_HDMIPLL] = 4,
- [P_GPLL0] = 5,
- [P_DSI0PLL] = 2,
- [P_DSI1PLL] = 3,
+static const struct parent_map mmcc_xo_mmpll0_dsi_hdmi_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_HDMIPLL, 4 },
+ { P_GPLL0, 5 },
+ { P_DSI0PLL, 2 },
+ { P_DSI1PLL, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
@@ -79,12 +83,13 @@ static const char *mmcc_xo_mmpll0_dsi_hdmi_gpll0[] = {
"dsi1pll",
};
-static const u8 mmcc_xo_mmpll0_1_2_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
- [P_MMPLL2] = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_2_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { P_MMPLL2, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
@@ -95,12 +100,13 @@ static const char *mmcc_xo_mmpll0_1_2_gpll0[] = {
"mmpll2",
};
-static const u8 mmcc_xo_mmpll0_1_3_gpll0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
- [P_MMPLL3] = 3,
+static const struct parent_map mmcc_xo_mmpll0_1_3_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { P_MMPLL3, 3 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
@@ -111,12 +117,13 @@ static const char *mmcc_xo_mmpll0_1_3_gpll0[] = {
"mmpll3",
};
-static const u8 mmcc_xo_mmpll0_1_gpll1_0_map[] = {
- [P_XO] = 0,
- [P_MMPLL0] = 1,
- [P_MMPLL1] = 2,
- [P_GPLL0] = 5,
- [P_GPLL1] = 4,
+static const struct parent_map mmcc_xo_mmpll0_1_gpll1_0_map[] = {
+ { P_XO, 0 },
+ { P_MMPLL0, 1 },
+ { P_MMPLL1, 2 },
+ { P_GPLL0, 5 },
+ { P_GPLL1, 4 },
+ { }
};
static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
@@ -127,13 +134,14 @@ static const char *mmcc_xo_mmpll0_1_gpll1_0[] = {
"gpll1_vote",
};
-static const u8 mmcc_xo_dsi_hdmi_edp_map[] = {
- [P_XO] = 0,
- [P_EDPLINK] = 4,
- [P_HDMIPLL] = 3,
- [P_EDPVCO] = 5,
- [P_DSI0PLL] = 1,
- [P_DSI1PLL] = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_map[] = {
+ { P_XO, 0 },
+ { P_EDPLINK, 4 },
+ { P_HDMIPLL, 3 },
+ { P_EDPVCO, 5 },
+ { P_DSI0PLL, 1 },
+ { P_DSI1PLL, 2 },
+ { }
};
static const char *mmcc_xo_dsi_hdmi_edp[] = {
@@ -145,13 +153,14 @@ static const char *mmcc_xo_dsi_hdmi_edp[] = {
"dsi1pll",
};
-static const u8 mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
- [P_XO] = 0,
- [P_EDPLINK] = 4,
- [P_HDMIPLL] = 3,
- [P_GPLL0] = 5,
- [P_DSI0PLL] = 1,
- [P_DSI1PLL] = 2,
+static const struct parent_map mmcc_xo_dsi_hdmi_edp_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_EDPLINK, 4 },
+ { P_HDMIPLL, 3 },
+ { P_GPLL0, 5 },
+ { P_DSI0PLL, 1 },
+ { P_DSI1PLL, 2 },
+ { }
};
static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
@@ -163,13 +172,14 @@ static const char *mmcc_xo_dsi_hdmi_edp_gpll0[] = {
"dsi1pll",
};
-static const u8 mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
- [P_XO] = 0,
- [P_EDPLINK] = 4,
- [P_HDMIPLL] = 3,
- [P_GPLL0] = 5,
- [P_DSI0PLL_BYTE] = 1,
- [P_DSI1PLL_BYTE] = 2,
+static const struct parent_map mmcc_xo_dsibyte_hdmi_edp_gpll0_map[] = {
+ { P_XO, 0 },
+ { P_EDPLINK, 4 },
+ { P_HDMIPLL, 3 },
+ { P_GPLL0, 5 },
+ { P_DSI0PLL_BYTE, 1 },
+ { P_DSI1PLL_BYTE, 2 },
+ { }
};
static const char *mmcc_xo_dsibyte_hdmi_edp_gpll0[] = {
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 7/9] clk: qcom: Convert msm8960 to parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (5 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 6/9] clk: qcom: Convert msm8974 " Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 8/9] clk: qcom: Convert ipq806x " Georgi Djakov
` (2 subsequent siblings)
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/gcc-msm8960.c | 35 +++++++++++++++-----------
drivers/clk/qcom/lcc-msm8960.c | 13 ++++++----
drivers/clk/qcom/mmcc-msm8960.c | 53 +++++++++++++++++++++------------------
3 files changed, 57 insertions(+), 44 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
index e60feffc10a1..51956727b0e6 100644
--- a/drivers/clk/qcom/gcc-msm8960.c
+++ b/drivers/clk/qcom/gcc-msm8960.c
@@ -113,14 +113,17 @@ static struct clk_regmap pll14_vote = {
},
};
-#define P_PXO 0
-#define P_PLL8 1
-#define P_PLL3 2
-#define P_CXO 2
+enum {
+ P_PXO,
+ P_PLL8,
+ P_PLL3,
+ P_CXO,
+};
-static const u8 gcc_pxo_pll8_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
+static const struct parent_map gcc_pxo_pll8_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { }
};
static const char *gcc_pxo_pll8[] = {
@@ -128,10 +131,11 @@ static const char *gcc_pxo_pll8[] = {
"pll8_vote",
};
-static const u8 gcc_pxo_pll8_cxo_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
- [P_CXO] = 5,
+static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { P_CXO, 5 },
+ { }
};
static const char *gcc_pxo_pll8_cxo[] = {
@@ -140,10 +144,11 @@ static const char *gcc_pxo_pll8_cxo[] = {
"cxo",
};
-static const u8 gcc_pxo_pll8_pll3_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
- [P_PLL3] = 6,
+static const struct parent_map gcc_pxo_pll8_pll3_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { P_PLL3, 6 },
+ { }
};
static const char *gcc_pxo_pll8_pll3[] = {
diff --git a/drivers/clk/qcom/lcc-msm8960.c b/drivers/clk/qcom/lcc-msm8960.c
index e2c863295f00..b88b8687dbe7 100644
--- a/drivers/clk/qcom/lcc-msm8960.c
+++ b/drivers/clk/qcom/lcc-msm8960.c
@@ -47,12 +47,15 @@ static struct clk_pll pll4 = {
},
};
-#define P_PXO 0
-#define P_PLL4 1
+enum {
+ P_PXO,
+ P_PLL4,
+};
-static const u8 lcc_pxo_pll4_map[] = {
- [P_PXO] = 0,
- [P_PLL4] = 2,
+static const struct parent_map lcc_pxo_pll4_map[] = {
+ { P_PXO, 0 },
+ { P_PLL4, 2 },
+ { }
};
static const char *lcc_pxo_pll4[] = {
diff --git a/drivers/clk/qcom/mmcc-msm8960.c b/drivers/clk/qcom/mmcc-msm8960.c
index e8b33bbc362f..eff872cc2baf 100644
--- a/drivers/clk/qcom/mmcc-msm8960.c
+++ b/drivers/clk/qcom/mmcc-msm8960.c
@@ -33,18 +33,22 @@
#include "clk-branch.h"
#include "reset.h"
-#define P_PXO 0
-#define P_PLL8 1
-#define P_PLL2 2
-#define P_PLL3 3
-#define P_PLL15 3
+enum {
+ P_PXO,
+ P_PLL8,
+ P_PLL2,
+ P_PLL3,
+ P_PLL15,
+ P_HDMI_PLL,
+};
#define F_MN(f, s, _m, _n) { .freq = f, .src = s, .m = _m, .n = _n }
-static u8 mmcc_pxo_pll8_pll2_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 2,
- [P_PLL2] = 1,
+static const struct parent_map mmcc_pxo_pll8_pll2_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 2 },
+ { P_PLL2, 1 },
+ { }
};
static const char *mmcc_pxo_pll8_pll2[] = {
@@ -53,11 +57,12 @@ static const char *mmcc_pxo_pll8_pll2[] = {
"pll2",
};
-static u8 mmcc_pxo_pll8_pll2_pll3_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 2,
- [P_PLL2] = 1,
- [P_PLL3] = 3,
+static const struct parent_map mmcc_pxo_pll8_pll2_pll3_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 2 },
+ { P_PLL2, 1 },
+ { P_PLL3, 3 },
+ { }
};
static const char *mmcc_pxo_pll8_pll2_pll15[] = {
@@ -67,11 +72,12 @@ static const char *mmcc_pxo_pll8_pll2_pll15[] = {
"pll15",
};
-static u8 mmcc_pxo_pll8_pll2_pll15_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 2,
- [P_PLL2] = 1,
- [P_PLL15] = 3,
+static const struct parent_map mmcc_pxo_pll8_pll2_pll15_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 2 },
+ { P_PLL2, 1 },
+ { P_PLL15, 3 },
+ { }
};
static const char *mmcc_pxo_pll8_pll2_pll3[] = {
@@ -1377,11 +1383,10 @@ static struct clk_branch rot_clk = {
},
};
-#define P_HDMI_PLL 1
-
-static u8 mmcc_pxo_hdmi_map[] = {
- [P_PXO] = 0,
- [P_HDMI_PLL] = 3,
+static const struct parent_map mmcc_pxo_hdmi_map[] = {
+ { P_PXO, 0 },
+ { P_HDMI_PLL, 3 },
+ { }
};
static const char *mmcc_pxo_hdmi[] = {
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 8/9] clk: qcom: Convert ipq806x to parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (6 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 7/9] clk: qcom: Convert msm8960 " Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 9/9] clk: qcom: Convert msm8660 " Georgi Djakov
2015-03-18 19:19 ` [PATCH v1 0/9] clk: qcom: Introduce " Stephen Boyd
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/gcc-ipq806x.c | 51 +++++++++++++++++++++++-----------------
drivers/clk/qcom/lcc-ipq806x.c | 13 ++++++----
2 files changed, 37 insertions(+), 27 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index a015bb06c09b..127a151f9bbc 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -140,15 +140,18 @@ static struct clk_regmap pll14_vote = {
},
};
-#define P_PXO 0
-#define P_PLL8 1
-#define P_PLL3 1
-#define P_PLL0 2
-#define P_CXO 2
+enum {
+ P_PXO,
+ P_PLL8,
+ P_PLL3,
+ P_PLL0,
+ P_CXO,
+};
-static const u8 gcc_pxo_pll8_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
+static const struct parent_map gcc_pxo_pll8_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { }
};
static const char *gcc_pxo_pll8[] = {
@@ -156,10 +159,11 @@ static const char *gcc_pxo_pll8[] = {
"pll8_vote",
};
-static const u8 gcc_pxo_pll8_cxo_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
- [P_CXO] = 5,
+static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { P_CXO, 5 },
+ { }
};
static const char *gcc_pxo_pll8_cxo[] = {
@@ -168,14 +172,16 @@ static const char *gcc_pxo_pll8_cxo[] = {
"cxo",
};
-static const u8 gcc_pxo_pll3_map[] = {
- [P_PXO] = 0,
- [P_PLL3] = 1,
+static const struct parent_map gcc_pxo_pll3_map[] = {
+ { P_PXO, 0 },
+ { P_PLL3, 1 },
+ { }
};
-static const u8 gcc_pxo_pll3_sata_map[] = {
- [P_PXO] = 0,
- [P_PLL3] = 6,
+static const struct parent_map gcc_pxo_pll3_sata_map[] = {
+ { P_PXO, 0 },
+ { P_PLL3, 6 },
+ { }
};
static const char *gcc_pxo_pll3[] = {
@@ -183,10 +189,11 @@ static const char *gcc_pxo_pll3[] = {
"pll3",
};
-static const u8 gcc_pxo_pll8_pll0[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
- [P_PLL0] = 2,
+static const struct parent_map gcc_pxo_pll8_pll0[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { P_PLL0, 2 },
+ { }
};
static const char *gcc_pxo_pll8_pll0_map[] = {
diff --git a/drivers/clk/qcom/lcc-ipq806x.c b/drivers/clk/qcom/lcc-ipq806x.c
index 19378b080dd7..5f261e695264 100644
--- a/drivers/clk/qcom/lcc-ipq806x.c
+++ b/drivers/clk/qcom/lcc-ipq806x.c
@@ -61,12 +61,15 @@ static const struct pll_config pll4_config = {
.main_output_mask = BIT(23),
};
-#define P_PXO 0
-#define P_PLL4 1
+enum {
+ P_PXO,
+ P_PLL4,
+};
-static const u8 lcc_pxo_pll4_map[] = {
- [P_PXO] = 0,
- [P_PLL4] = 2,
+static const struct parent_map lcc_pxo_pll4_map[] = {
+ { P_PXO, 0 },
+ { P_PLL4, 2 },
+ { }
};
static const char *lcc_pxo_pll4[] = {
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v1 9/9] clk: qcom: Convert msm8660 to parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (7 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 8/9] clk: qcom: Convert ipq806x " Georgi Djakov
@ 2015-03-18 13:32 ` Georgi Djakov
2015-03-18 19:19 ` [PATCH v1 0/9] clk: qcom: Introduce " Stephen Boyd
9 siblings, 0 replies; 11+ messages in thread
From: Georgi Djakov @ 2015-03-18 13:32 UTC (permalink / raw)
To: sboyd, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
drivers/clk/qcom/gcc-msm8660.c | 24 ++++++++++++++----------
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
index f366e68f7316..e9fc9389f977 100644
--- a/drivers/clk/qcom/gcc-msm8660.c
+++ b/drivers/clk/qcom/gcc-msm8660.c
@@ -59,13 +59,16 @@ static struct clk_regmap pll8_vote = {
},
};
-#define P_PXO 0
-#define P_PLL8 1
-#define P_CXO 2
+enum {
+ P_PXO,
+ P_PLL8,
+ P_CXO,
+};
-static const u8 gcc_pxo_pll8_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
+static const struct parent_map gcc_pxo_pll8_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { }
};
static const char *gcc_pxo_pll8[] = {
@@ -73,10 +76,11 @@ static const char *gcc_pxo_pll8[] = {
"pll8_vote",
};
-static const u8 gcc_pxo_pll8_cxo_map[] = {
- [P_PXO] = 0,
- [P_PLL8] = 3,
- [P_CXO] = 5,
+static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
+ { P_PXO, 0 },
+ { P_PLL8, 3 },
+ { P_CXO, 5 },
+ { }
};
static const char *gcc_pxo_pll8_cxo[] = {
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v1 0/9] clk: qcom: Introduce parent_map tables
2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
` (8 preceding siblings ...)
2015-03-18 13:32 ` [PATCH v1 9/9] clk: qcom: Convert msm8660 " Georgi Djakov
@ 2015-03-18 19:19 ` Stephen Boyd
9 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2015-03-18 19:19 UTC (permalink / raw)
To: Georgi Djakov, mturquette; +Cc: galak, linux-kernel, linux-arm-msm
On 03/18/15 06:32, Georgi Djakov wrote:
> This patchset introduces the parent_map index tables, which solve the
> issue discussed here [1].
> While doing this, fix also some of the code around (patches 1 and 2)
>
> [1] https://lkml.org/lkml/2015/3/5/682
>
> Patchset based on clk-next.
The concept looks fine, but I don't see how the series is bisectable.
Half way through we change the struct definition and that should break
all the drivers, right? Please fix that.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-03-18 19:19 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
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2015-03-18 13:32 [PATCH v1 0/9] clk: qcom: Introduce parent_map tables Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 1/9] clk: qcom: Fix clk_get_parent function return value Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 2/9] clk: qcom: Do some error handling in configure_bank() Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 3/9] clk: qcom: Introduce parent_map tables Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 4/9] clk: qcom: Make RCGs use the parent_map struct Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 5/9] clk: qcom: Convert apq8084 to parent_map tables Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 6/9] clk: qcom: Convert msm8974 " Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 7/9] clk: qcom: Convert msm8960 " Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 8/9] clk: qcom: Convert ipq806x " Georgi Djakov
2015-03-18 13:32 ` [PATCH v1 9/9] clk: qcom: Convert msm8660 " Georgi Djakov
2015-03-18 19:19 ` [PATCH v1 0/9] clk: qcom: Introduce " Stephen Boyd
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