[PATCH RFC 0/7] arm64: qcom: cpuidle support for MSM8916 SoC

[PATCH RFC 0/7] arm64: qcom: cpuidle support for MSM8916 SoC

[Lina Iyer]

Hi,

This patchset adds cpuidle support for the MSM8916 Qualcomm SoC.  This is based
on cpu-ops patches for the QCOM arm-v8 SoCs [1].

MSM8916 SoC is a quad-A53 SoC with an L2 configured as a single cluster. Like
many other QCOM SoC's the power management for the cpu is controlled by a
peripheral hardware block called the Subsystem Power Manager (SPM) [2]. The SPM
is a finite state machine that is triggered when the core executes the ARM WFI
instruction. SPM is configured to execute the desired idle state before
terminating the cpu in SCM. Low power modes supported are WFI and SPC (standalone
power collapse - individual cpu power down state).

The patches do the following -

- Modify ARM32 cpuidle_ops structure to match that of ARM64
- Support ARM32 and AARCH64 initialization using the same platform code
- Add 8916 specific SPM register information
- Add device bindings for 8916 SPM nodes
- Add cpuidle device bindings.

Thanks,
Lina

[1]. https://lkml.org/lkml/2015/4/9/774
[2]. http://www.spinics.net/lists/arm-kernel/msg411542.html

Lina Iyer (7):
  arm: Modify cpuidle_ops structures to match ARM64
  arm64: qcom: Add SPM driver support for ARM and ARM64
  qcom: spm: Use u32 for register offsets
  qcom: spm: Add 8916 SPM register data
  arm64: dts: Add power-controller device bindings for QCOM 8916 SoC
  arm64: dts: Add cpu idle states for 8916
  arm64: defconfig: Enable power management support for QCOM SoCs

 .../devicetree/bindings/arm/msm/qcom,saw2.txt      |  1 +
 arch/arm/include/asm/cpuidle.h                     |  4 +--
 arch/arm/kernel/cpuidle.c                          |  2 +-
 arch/arm64/boot/dts/qcom/msm8916.dtsi              | 38 ++++++++++++++++++++
 arch/arm64/configs/defconfig                       |  1 +
 drivers/soc/qcom/cpu_ops.c                         |  5 +++
 drivers/soc/qcom/spm.c                             | 40 ++++++++++++++++++----
 7 files changed, 82 insertions(+), 9 deletions(-)

-- 
2.1.0

[PATCH RFC 1/7] arm: Modify cpuidle_ops structures to match ARM64

[Lina Iyer]

SoC's tend to reuse the same hardware block for both ARM and ARM64 based
cpus. As such the idle setup and enter functions are generally common.
Using the same arguments as cpu_operations for cpuidle callbacks, allow
reuse of the same driver for many SoCs.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm/include/asm/cpuidle.h | 4 ++--
 arch/arm/kernel/cpuidle.c      | 2 +-
 drivers/soc/qcom/spm.c         | 5 +++--
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
index 0f84249..08768da 100644
--- a/arch/arm/include/asm/cpuidle.h
+++ b/arch/arm/include/asm/cpuidle.h
@@ -30,8 +30,8 @@ static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
 struct device_node;
 
 struct cpuidle_ops {
-	int (*suspend)(int cpu, unsigned long arg);
-	int (*init)(struct device_node *, int cpu);
+	int (*suspend)(unsigned long arg);
+	int (*init)(struct device_node *, unsigned int cpu);
 };
 
 struct of_cpuidle_method {
diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c
index 318da33..703926e 100644
--- a/arch/arm/kernel/cpuidle.c
+++ b/arch/arm/kernel/cpuidle.c
@@ -56,7 +56,7 @@ int arm_cpuidle_suspend(int index)
 	int cpu = smp_processor_id();
 
 	if (cpuidle_ops[cpu].suspend)
-		ret = cpuidle_ops[cpu].suspend(cpu, index);
+		ret = cpuidle_ops[cpu].suspend(index);
 
 	return ret;
 }
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index b562af8..5d0dd8c 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -197,8 +197,9 @@ static int qcom_cpu_spc(int cpu)
 	return ret;
 }
 
-static int qcom_idle_enter(int cpu, unsigned long index)
+static int qcom_idle_enter(unsigned long index)
 {
+	int cpu = smp_processor_id();
 	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
 }
 
@@ -207,7 +208,7 @@ static const struct of_device_id qcom_idle_state_match[] __initconst = {
 	{ },
 };
 
-static int __init qcom_cpuidle_init(struct device_node *cpu_node, int cpu)
+static int __init qcom_cpuidle_init(struct device_node *cpu_node, u32 cpu)
 {
 	const struct of_device_id *match_id;
 	struct device_node *state_node;
-- 
2.1.0

[PATCH RFC 2/7] arm64: qcom: Add SPM driver support for ARM and ARM64

[Lina Iyer]

The SAW power controller can be used with both ARM v7 and v8 cpus. The
driver registers with the cpuidle framework as a provider of idle entry
points for all idle states. Certain aspects of cpuidle callback
registration are different been ARM and ARM64 variants. Use compile time
definitions to use appropriate idle and registration functions.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 drivers/soc/qcom/cpu_ops.c |  5 +++++
 drivers/soc/qcom/spm.c     | 12 +++++++++---
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/qcom/cpu_ops.c b/drivers/soc/qcom/cpu_ops.c
index d831cb0..363147c 100644
--- a/drivers/soc/qcom/cpu_ops.c
+++ b/drivers/soc/qcom/cpu_ops.c
@@ -32,6 +32,9 @@
 #include <asm/cputype.h>
 #include <asm/smp_plat.h>
 
+extern int qcom_idle_enter(unsigned long index);
+extern int qcom_cpuidle_init(struct device_node *cpu_node, u32 cpu);
+
 static DEFINE_RAW_SPINLOCK(boot_lock);
 
 DEFINE_PER_CPU(int, cold_boot_done);
@@ -339,5 +342,7 @@ static const struct cpu_operations msm_cortex_a_ops = {
 	.cpu_prepare	= msm_cpu_prepare,
 	.cpu_boot	= msm_cpu_boot,
 	.cpu_postboot	= msm_cpu_postboot,
+	.cpu_suspend	= qcom_idle_enter,
+	.cpu_init_idle	= qcom_cpuidle_init,
 };
 CPU_METHOD_OF_DECLARE(msm_cortex_a_ops, &msm_cortex_a_ops);
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 5d0dd8c..b66d86c 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -29,6 +29,7 @@
 #include <asm/cpuidle.h>
 #include <asm/proc-fns.h>
 #include <asm/suspend.h>
+#include <asm/cpu_ops.h>
 
 #define MAX_PMIC_DATA		2
 #define MAX_SEQ_DATA		64
@@ -185,7 +186,11 @@ static int qcom_cpu_spc(int cpu)
 	struct spm_driver_data *drv = per_cpu(cpu_spm_drv, cpu);
 
 	spm_set_low_power_mode(drv, PM_SLEEP_MODE_SPC);
+#if defined (CONFIG_ARCH_ARM)
 	ret = cpu_suspend(0, qcom_pm_collapse);
+#else
+	ret = __cpu_suspend(0, qcom_pm_collapse);
+#endif
 	/*
 	 * ARM common code executes WFI without calling into our driver and
 	 * if the SPM mode is not reset, then we may accidently power down the
@@ -197,7 +202,7 @@ static int qcom_cpu_spc(int cpu)
 	return ret;
 }
 
-static int qcom_idle_enter(unsigned long index)
+int qcom_idle_enter(unsigned long index)
 {
 	int cpu = smp_processor_id();
 	return per_cpu(qcom_idle_ops, cpu)[index](cpu);
@@ -208,7 +213,7 @@ static const struct of_device_id qcom_idle_state_match[] __initconst = {
 	{ },
 };
 
-static int __init qcom_cpuidle_init(struct device_node *cpu_node, u32 cpu)
+int __init qcom_cpuidle_init(struct device_node *cpu_node, u32 cpu)
 {
 	const struct of_device_id *match_id;
 	struct device_node *state_node;
@@ -275,13 +280,14 @@ check_spm:
 	return per_cpu(cpu_spm_drv, cpu) ? 0 : -ENXIO;
 }
 
+#if defined (CONFIG_ARCH_ARM)
 static struct cpuidle_ops qcom_cpuidle_ops __initdata = {
 	.suspend = qcom_idle_enter,
 	.init = qcom_cpuidle_init,
 };
-
 CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v1, "qcom,kpss-acc-v1", &qcom_cpuidle_ops);
 CPUIDLE_METHOD_OF_DECLARE(qcom_idle_v2, "qcom,kpss-acc-v2", &qcom_cpuidle_ops);
+#endif
 
 static struct spm_driver_data *spm_get_drv(struct platform_device *pdev,
 		int *spm_cpu)
-- 
2.1.0

[PATCH RFC 3/7] qcom: spm: Use u32 for register offsets

[Lina Iyer]

Newer SoC's allow a bigger memory range for the SPM. The offsets for the
SPM sequences could therefore, be more than the capcacity of u8.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 drivers/soc/qcom/spm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index b66d86c..392a714 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -60,7 +60,7 @@ enum spm_reg {
 };
 
 struct spm_reg_data {
-	const u8 *reg_offset;
+	const u32 *reg_offset;
 	u32 spm_cfg;
 	u32 spm_dly;
 	u32 pmic_dly;
@@ -74,7 +74,7 @@ struct spm_driver_data {
 	const struct spm_reg_data *reg_data;
 };
 
-static const u8 spm_reg_offset_v2_1[SPM_REG_NR] = {
+static const u32 spm_reg_offset_v2_1[SPM_REG_NR] = {
 	[SPM_REG_CFG]		= 0x08,
 	[SPM_REG_SPM_CTL]	= 0x30,
 	[SPM_REG_DLY]		= 0x34,
@@ -93,7 +93,7 @@ static const struct spm_reg_data spm_reg_8974_8084_cpu  = {
 	.start_index[PM_SLEEP_MODE_SPC] = 3,
 };
 
-static const u8 spm_reg_offset_v1_1[SPM_REG_NR] = {
+static const u32 spm_reg_offset_v1_1[SPM_REG_NR] = {
 	[SPM_REG_CFG]		= 0x08,
 	[SPM_REG_SPM_CTL]	= 0x20,
 	[SPM_REG_PMIC_DLY]	= 0x24,
-- 
2.1.0

[PATCH RFC 4/7] qcom: spm: Add 8916 SPM register data

[Lina Iyer]

Add SPM register information and initialization values for QCOM 8916
SoC.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 .../devicetree/bindings/arm/msm/qcom,saw2.txt       |  1 +
 drivers/soc/qcom/spm.c                              | 21 +++++++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
index ae4afc6..986a8ea 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt
@@ -27,6 +27,7 @@ PROPERTIES
 			"qcom,apq8064-saw2-v1.1-cpu"
 			"qcom,msm8974-saw2-v2.1-cpu"
 			"qcom,apq8084-saw2-v2.1-cpu"
+			"qcom,msm8916-saw2-v3.0-cpu"
 
 - reg:
 	Usage: required
diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 392a714..ffb6045 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -115,6 +115,25 @@ static const struct spm_reg_data spm_reg_8064_cpu = {
 	.start_index[PM_SLEEP_MODE_SPC] = 2,
 };
 
+static const u32 spm_reg_offset_v3_0[SPM_REG_NR] = {
+	[SPM_REG_CFG]		= 0x08,
+	[SPM_REG_SPM_CTL]	= 0x30,
+	[SPM_REG_DLY]		= 0x34,
+	[SPM_REG_SEQ_ENTRY]	= 0x400,
+};
+
+/* SPM register data for 8916 */
+static const struct spm_reg_data spm_reg_8916_cpu = {
+	.reg_offset = spm_reg_offset_v3_0,
+	.spm_cfg = 0x1,
+	.spm_dly = 0x3C102800,
+	.seq = { 0x60, 0x03, 0x60, 0x0B, 0x0F, 0x20, 0x10, 0x80, 0x30, 0x90,
+		0x5B, 0x60, 0x03, 0x60, 0x3B, 0x76, 0x76, 0x0B, 0x94, 0x5B,
+		0x80, 0x10, 0x26, 0x30, 0x0F },
+	.start_index[PM_SLEEP_MODE_STBY] = 0,
+	.start_index[PM_SLEEP_MODE_SPC] = 5,
+};
+
 static DEFINE_PER_CPU(struct spm_driver_data *, cpu_spm_drv);
 
 typedef int (*idle_fn)(int);
@@ -325,6 +344,8 @@ static const struct of_device_id spm_match_table[] = {
 	  .data = &spm_reg_8974_8084_cpu },
 	{ .compatible = "qcom,apq8064-saw2-v1.1-cpu",
 	  .data = &spm_reg_8064_cpu },
+	{ .compatible = "qcom,msm8916-saw2-v3.0-cpu",
+	  .data = &spm_reg_8916_cpu },
 	{ },
 };
 
-- 
2.1.0

[PATCH RFC 5/7] arm64: dts: Add power-controller device bindings for QCOM 8916 SoC

[Lina Iyer]

CPUs on the MSM8916 SoC has a power controller for each cpu that aids in
regualting power during active and idle usecase. Add SAW device bindings
for each cpu and L2.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ac4b3e5..a3232be 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -51,6 +51,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc0>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw0>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -65,6 +66,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc1>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw1>;
 		};
 
 		CPU2: cpu@2 {
@@ -74,6 +76,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc2>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw2>;
 		};
 
 		CPU3: cpu@3 {
@@ -83,6 +86,7 @@
 			enable-method = "qcom,arm-cortex-acc";
 			qcom,acc = <&acc3>;
 			next-level-cache = <&L2_0>;
+			qcom,saw = <&saw3>;
 		};
 	};
 
@@ -254,5 +258,25 @@
 			reg = <0x0b0b8000 0x1000>,
 			      <0x0b008000 0x1000>;
 		};
+
+		saw0: power-controller@B089000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB089000 0x1000>, <0xB009000 0x1000>;
+		};
+
+		saw1: power-controller@B099000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB099000 0x1000>, <0xB009000 0x1000>;
+		};
+
+		saw2: power-controller@B0A9000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB0A9000 0x1000>, <0xB009000 0x1000>;
+		};
+
+		saw3: power-controller@B0B9000 {
+			compatible = "qcom,msm8916-saw2-v3.0-cpu";
+			reg = <0xB0B9000 0x1000>, <0xB009000 0x1000>;
+		};
 	};
 };
-- 
2.1.0

[PATCH RFC 6/7] arm64: dts: Add cpu idle states for 8916

[Lina Iyer]

Add ARM common idle states device bindings for cpuidle support for 8916
SOC.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm64/boot/dts/qcom/msm8916.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index a3232be..3c46898 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -52,6 +52,7 @@
 			qcom,acc = <&acc0>;
 			next-level-cache = <&L2_0>;
 			qcom,saw = <&saw0>;
+			cpu-idle-states = <&CPU_SPC>;
 			L2_0: l2-cache {
 			      compatible = "arm,arch-cache";
 			      cache-level = <2>;
@@ -67,6 +68,7 @@
 			qcom,acc = <&acc1>;
 			next-level-cache = <&L2_0>;
 			qcom,saw = <&saw1>;
+			cpu-idle-states = <&CPU_SPC>;
 		};
 
 		CPU2: cpu@2 {
@@ -77,6 +79,7 @@
 			qcom,acc = <&acc2>;
 			next-level-cache = <&L2_0>;
 			qcom,saw = <&saw2>;
+			cpu-idle-states = <&CPU_SPC>;
 		};
 
 		CPU3: cpu@3 {
@@ -87,6 +90,17 @@
 			qcom,acc = <&acc3>;
 			next-level-cache = <&L2_0>;
 			qcom,saw = <&saw3>;
+			cpu-idle-states = <&CPU_SPC>;
+		};
+
+		idle-states {
+			CPU_SPC: spc {
+				compatible = "qcom,idle-state-spc",
+						"arm,idle-state";
+				entry-latency-us = <130>;
+				exit-latency-us = <150>;
+				min-residency-us = <2000>;
+			};
 		};
 	};
 
-- 
2.1.0

[PATCH RFC 7/7] arm64: defconfig: Enable power management support for QCOM SoCs

[Lina Iyer]

Enable QCOM_PM to allow QCOM SoCs to use the platform support to enter
idle states.

Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
---
 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2212d40..901b05e 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -132,6 +132,7 @@ CONFIG_RTC_DRV_XGENE=y
 CONFIG_VIRTIO_BALLOON=y
 CONFIG_VIRTIO_MMIO=y
 CONFIG_COMMON_CLK_QCOM=y
+CONFIG_QCOM_PM=y
 CONFIG_MSM_GCC_8916=y
 # CONFIG_IOMMU_SUPPORT is not set
 CONFIG_PHY_XGENE=y
-- 
2.1.0