From: Taniya Das <tdas@codeaurora.org>
To: "Stephen Boyd" <sboyd@kernel.org>,
"Michael Turquette " <mturquette@baylibre.com>
Cc: David Brown <david.brown@linaro.org>,
Rajendra Nayak <rnayak@codeaurora.org>,
linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
Andy Gross <agross@kernel.org>,
devicetree@vger.kernel.org, robh@kernel.org, robh+dt@kernel.org,
Taniya Das <tdas@codeaurora.org>
Subject: [PATCH v1 1/4] clk: qcom: gdsc: Add support to enable retention of GSDCR
Date: Sat, 28 Mar 2020 01:18:02 +0530 [thread overview]
Message-ID: <1585338485-31820-2-git-send-email-tdas@codeaurora.org> (raw)
In-Reply-To: <1585338485-31820-1-git-send-email-tdas@codeaurora.org>
Add support for the RETAIN_FF_ENABLE feature which enables the
usage of retention registers. These registers maintain their
state after disabling and re-enabling a GDSC.
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
drivers/clk/qcom/gdsc.c | 12 ++++++++++++
drivers/clk/qcom/gdsc.h | 1 +
2 files changed, 13 insertions(+)
diff --git a/drivers/clk/qcom/gdsc.c b/drivers/clk/qcom/gdsc.c
index a250f59..cfe908f 100644
--- a/drivers/clk/qcom/gdsc.c
+++ b/drivers/clk/qcom/gdsc.c
@@ -28,6 +28,7 @@
/* CFG_GDSCR */
#define GDSC_POWER_UP_COMPLETE BIT(16)
#define GDSC_POWER_DOWN_COMPLETE BIT(15)
+#define GDSC_RETAIN_FF_ENABLE BIT(11)
#define CFG_GDSCR_OFFSET 0x4
/* Wait 2^n CXO cycles between all states. Here, n=2 (4 cycles). */
@@ -202,6 +203,14 @@ static inline void gdsc_assert_reset_aon(struct gdsc *sc)
regmap_update_bits(sc->regmap, sc->clamp_io_ctrl,
GMEM_RESET_MASK, 0);
}
+
+static inline void gdsc_retain_ff_on(struct gdsc *sc)
+{
+ u32 mask = RETAIN_FF_ENABLE;
+
+ regmap_update_bits(sc->regmap, sc->gdscr, mask, mask);
+}
+
static int gdsc_enable(struct generic_pm_domain *domain)
{
struct gdsc *sc = domain_to_gdsc(domain);
@@ -254,6 +263,9 @@ static int gdsc_enable(struct generic_pm_domain *domain)
udelay(1);
}
+ if (sc->flags & RETAIN_FF_ENABLE)
+ gdsc_retain_ff_on(sc);
+
return 0;
}
diff --git a/drivers/clk/qcom/gdsc.h b/drivers/clk/qcom/gdsc.h
index 64cdc8c..8604d44 100644
--- a/drivers/clk/qcom/gdsc.h
+++ b/drivers/clk/qcom/gdsc.h
@@ -49,6 +49,7 @@ struct gdsc {
#define AON_RESET BIT(4)
#define POLL_CFG_GDSCR BIT(5)
#define ALWAYS_ON BIT(6)
+#define RETAIN_FF_ENABLE BIT(7)
struct reset_controller_dev *rcdev;
unsigned int *resets;
unsigned int reset_count;
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the Linux Foundation.
next prev parent reply other threads:[~2020-03-27 19:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-03-27 19:48 [PATCH v1 0/4] clk: qcom: Support for Low Power Audio Clocks on SC7180 Taniya Das
2020-03-27 19:48 ` Taniya Das [this message]
2020-04-09 20:06 ` [PATCH v1 1/4] clk: qcom: gdsc: Add support to enable retention of GSDCR Stephen Boyd
2020-05-17 9:17 ` Taniya Das
2020-03-27 19:48 ` [PATCH v1 2/4] dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180 Taniya Das
2020-04-05 2:09 ` Rob Herring
2020-05-17 9:20 ` Taniya Das
2020-03-27 19:48 ` [PATCH v1 3/4] clk: qcom: gcc: Add support for GCC LPASS clock for SC7180 Taniya Das
2020-04-09 20:08 ` Stephen Boyd
2020-03-27 19:48 ` [PATCH v1 4/4] clk: qcom: lpass: Add support for LPASS clock controller " Taniya Das
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