* [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings
@ 2021-02-12 10:49 Krishna Manikandan
2021-02-12 10:49 ` [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings Krishna Manikandan
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Krishna Manikandan @ 2021-02-12 10:49 UTC (permalink / raw)
To: linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
swboyd, bjorn.andersson, vinod.koul, rnayak, dianders, sibis,
khsieh
MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks
like DPU display controller, DSI etc. Add YAML schema
for DPU device tree bindings.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Changes in v2:
- Changed dpu to DPU (Sam Ravnborg)
- Fixed indentation issues (Sam Ravnborg)
- Added empty line between different properties (Sam Ravnborg)
- Replaced reference txt files with their corresponding
yaml files (Sam Ravnborg)
- Modified the file to use "|" only when it is
necessary (Sam Ravnborg)
Changes in v3:
- Corrected the license used (Rob Herring)
- Added maxItems for properties (Rob Herring)
- Dropped generic descriptions (Rob Herring)
- Added ranges property (Rob Herring)
- Corrected the indendation (Rob Herring)
- Added additionalProperties (Rob Herring)
- Split dsi file into two, one for dsi controller
and another one for dsi phy per target (Rob Herring)
- Corrected description for pinctrl-names (Rob Herring)
- Corrected the examples used in yaml file (Rob Herring)
- Delete dsi.txt and dpu.txt (Rob Herring)
Changes in v4:
- Move schema up by one level (Rob Herring)
- Add patternProperties for mdp node (Rob Herring)
- Corrected description of some properties (Rob Herring)
Changes in v5:
- Correct the indentation (Rob Herring)
- Remove unnecessary description from properties (Rob Herring)
- Correct the number of interconnect entries (Rob Herring)
- Add interconnect names for sc7180 (Rob Herring)
- Add description for ports (Rob Herring)
- Remove common properties (Rob Herring)
- Add unevalutatedProperties (Rob Herring)
- Reference existing dsi controller yaml in the common
dsi controller file (Rob Herring)
- Correct the description of clock names to include only the
clocks that are required (Rob Herring)
- Remove properties which are already covered under the common
binding (Rob Herring)
- Add dsi phy supply nodes which are required for sc7180 and
sdm845 targets (Rob Herring)
- Add type ref for syscon-sfpb (Rob Herring)
Changes in v6:
- Fixed errors during dt_binding_check (Rob Herring)
- Add maxItems for phys and phys-names (Rob Herring)
- Use unevaluatedProperties wherever required (Rob Herring)
- Removed interrupt controller from required properties for
dsi controller (Rob Herring)
- Add constraints for dsi-phy reg-names based on the compatible
phy version (Rob Herring)
- Add constraints for dsi-phy supply nodes based on the
compatible phy version (Rob Herring)
Changes in v7:
- Add default value for qcom,mdss-mdp-transfer-time-us (Rob Herring)
- Modify the schema for data-lanes (Rob Herring)
- Split the phy schema into separate schemas based on
the phy version (Rob Herring)
Changes in v8:
- Resolve merge conflicts with latest dsi.txt file
- Include dp yaml change also in the same series
Changes in v9:
- Combine target specific dsi controller yaml files
to a single yaml file (Rob Herring)
- Combine target specific dsi phy yaml files into a
single yaml file (Rob Herring)
- Use unevaluatedProperties and additionalProperties
wherever required
- Remove duplicate properties from common yaml files
Changes in v10:
- Split the patch into separate patches for DPU, DSI and
PHY (Stephen Boyd)
- Drop unnecessary fullstop (Stephen Boyd)
- Add newline whereever required (Stephen Boyd)
- Add description for clock used (Stephen Boyd)
- Modify the description for interconnect entries (Stephen Boyd)
- Drop assigned clock entries as it a generic property (Stephen Boyd)
- Correct the definition for interrupts (Stephen Boyd)
- Drop clock names from required properties (Stephen Boyd)
- Drop labels for display nodes from example (Stephen Boyd)
- Drop flags from interrupts entries (Stephen Boyd)
Changes in v11:
- Drop maxItems for clocks (Stephen Boyd)
Changes in v12:
- Add description for register property (Stephen Boyd)
- Add maxItems for interrupts (Stephen Boyd)
- Add description for iommus property (Stephen Boyd)
- Add description for interconnects (Stephen Boyd)
- Change display node name to display_controller (Stephen Boyd)
---
.../bindings/display/msm/dpu-sc7180.yaml | 212 +++++++++++++++++++++
.../bindings/display/msm/dpu-sdm845.yaml | 202 ++++++++++++++++++++
.../devicetree/bindings/display/msm/dpu.txt | 141 --------------
3 files changed, 414 insertions(+), 141 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
delete mode 100644 Documentation/devicetree/bindings/display/msm/dpu.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
new file mode 100644
index 0000000..df88146
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
@@ -0,0 +1,212 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DPU dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for SC7180 target.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sc7180-mdss
+
+ reg:
+ items:
+ - description: Address offset and size for mdss register set
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock from dispcc
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with sid mask for hf0
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+ interconnects:
+ items:
+ - description: Interconnect path specifying the port ids for data bus
+
+ interconnect-names:
+ const: mdp0-mem
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ description: Node containing the properties of DPU.
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,sc7180-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display hf axi clock
+ - description: Display ahb clock
+ - description: Display rotator clock
+ - description: Display lut clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: bus
+ - const: iface
+ - const: rot
+ - const: lut
+ - const: core
+ - const: vsync
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ type: object
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface. These
+ are described by the standard properties documented in files
+ mentioned below.
+
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ properties:
+ port@0:
+ type: object
+ description: DPU_INTF1 (DSI1)
+
+ port@1:
+ type: object
+ description: DPU_INTF2 (DSI2)
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+ #include <dt-bindings/clock/qcom,gcc-sc7180.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mdss@ae00000 {
+ compatible = "qcom,sc7180-mdss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0 0xae00000 0 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
+ interconnect-names = "mdp0-mem";
+
+ iommus = <&apps_smmu 0x800 0x2>;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sc7180-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "bus", "iface", "rot", "lut", "core",
+ "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
new file mode 100644
index 0000000..71f8658
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
@@ -0,0 +1,202 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DPU dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
+ sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
+ bindings of MDSS and DPU are mentioned for SDM845 target.
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sdm845-mdss
+
+ reg:
+ items:
+ - description: Address offset and size for mdss register set
+
+ reg-names:
+ const: mdss
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AXI clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ iommus:
+ items:
+ - description: Phandle to apps_smmu node with sid mask for hf0
+ - description: Phandle to apps_smmu node with sid mask for hf1
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ description: Node containing the properties of DPU.
+
+ properties:
+ compatible:
+ items:
+ - const: qcom,sdm845-dpu
+
+ reg:
+ items:
+ - description: Address offset and size for mdp register set
+ - description: Address offset and size for vbif register set
+
+ reg-names:
+ items:
+ - const: mdp
+ - const: vbif
+
+ clocks:
+ items:
+ - description: Display ahb clock
+ - description: Display axi clock
+ - description: Display core clock
+ - description: Display vsync clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+ - const: vsync
+
+ interrupts:
+ maxItems: 1
+
+ ports:
+ type: object
+ description: |
+ Contains the list of output ports from DPU device. These ports
+ connect to interfaces that are external to the DPU hardware,
+ such as DSI, DP etc. Each output port contains an endpoint that
+ describes how it is connected to an external interface. These
+ are described by the standard properties documented in files
+ mentioned below.
+
+ Documentation/devicetree/bindings/graph.txt
+ Documentation/devicetree/bindings/media/video-interfaces.txt
+
+ properties:
+ port@0:
+ type: object
+ description: DPU_INTF1 (DSI1)
+
+ port@1:
+ type: object
+ description: DPU_INTF2 (DSI2)
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - power-domains
+ - clocks
+ - interrupts
+ - interrupt-controller
+ - iommus
+
+additionalProperties: false
+
+examples:
+- |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ mdss@ae00000 {
+ compatible = "qcom,sdm845-mdss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&gcc GCC_DISP_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "bus", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x880 0x8>,
+ <&apps_smmu 0xc80 0x8>;
+
+ display-controller@ae01000 {
+ compatible = "qcom,sdm845-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "iface", "bus", "core", "vsync";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt b/Documentation/devicetree/bindings/display/msm/dpu.txt
deleted file mode 100644
index 551ae26..0000000
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ /dev/null
@@ -1,141 +0,0 @@
-Qualcomm Technologies, Inc. DPU KMS
-
-Description:
-
-Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
-sub-blocks like DPU display controller, DSI and DP interfaces etc.
-The DPU display controller is found in SDM845 SoC.
-
-MDSS:
-Required properties:
-- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
-- reg: physical base address and length of contoller's registers.
-- reg-names: register region names. The following region is required:
- * "mdss"
-- power-domains: a power domain consumer specifier according to
- Documentation/devicetree/bindings/power/power_domain.txt
-- clocks: list of clock specifiers for clocks needed by the device.
-- clock-names: device clock names, must be in same order as clocks property.
- The following clocks are required:
- * "iface"
- * "bus"
- * "core"
-- interrupts: interrupt signal from MDSS.
-- interrupt-controller: identifies the node as an interrupt controller.
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- iommus: phandle of iommu device node.
-- #address-cells: number of address cells for the MDSS children. Should be 1.
-- #size-cells: Should be 1.
-- ranges: parent bus address space is the same as the child bus address space.
-- interconnects : interconnect path specifier for MDSS according to
- Documentation/devicetree/bindings/interconnect/interconnect.txt. Should be
- 2 paths corresponding to 2 AXI ports.
-- interconnect-names : MDSS will have 2 port names to differentiate between the
- 2 interconnect paths defined with interconnect specifier.
-
-Optional properties:
-- assigned-clocks: list of clock specifiers for clocks needing rate assignment
-- assigned-clock-rates: list of clock frequencies sorted in the same order as
- the assigned-clocks property.
-
-MDP:
-Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
-- reg: physical base address and length of controller's registers.
-- reg-names : register region names. The following region is required:
- * "mdp"
- * "vbif"
-- clocks: list of clock specifiers for clocks needed by the device.
-- clock-names: device clock names, must be in same order as clocks property.
- The following clocks are required.
- * "bus"
- * "iface"
- * "core"
- * "vsync"
-- interrupts: interrupt line from DPU to MDSS.
-- ports: contains the list of output ports from DPU device. These ports connect
- to interfaces that are external to the DPU hardware, such as DSI, DP etc.
-
- Each output port contains an endpoint that describes how it is connected to an
- external interface. These are described by the standard properties documented
- here:
- Documentation/devicetree/bindings/graph.txt
- Documentation/devicetree/bindings/media/video-interfaces.txt
-
- Port 0 -> DPU_INTF1 (DSI1)
- Port 1 -> DPU_INTF2 (DSI2)
-
-Optional properties:
-- assigned-clocks: list of clock specifiers for clocks needing rate assignment
-- assigned-clock-rates: list of clock frequencies sorted in the same order as
- the assigned-clocks property.
-
-Example:
-
- mdss: mdss@ae00000 {
- compatible = "qcom,sdm845-mdss";
- reg = <0xae00000 0x1000>;
- reg-names = "mdss";
-
- power-domains = <&clock_dispcc 0>;
-
- clocks = <&gcc GCC_DISP_AHB_CLK>, <&gcc GCC_DISP_AXI_CLK>,
- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
- clock-names = "iface", "bus", "core";
-
- assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
- assigned-clock-rates = <300000000>;
-
- interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interconnects = <&rsc_hlos MASTER_MDP0 &rsc_hlos SLAVE_EBI1>,
- <&rsc_hlos MASTER_MDP1 &rsc_hlos SLAVE_EBI1>;
-
- interconnect-names = "mdp0-mem", "mdp1-mem";
-
- iommus = <&apps_iommu 0>;
-
- #address-cells = <2>;
- #size-cells = <1>;
- ranges = <0 0 0xae00000 0xb2008>;
-
- mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
- reg = <0 0x1000 0x8f000>, <0 0xb0000 0x2008>;
- reg-names = "mdp", "vbif";
-
- clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,
- <&clock_dispcc DISP_CC_MDSS_AXI_CLK>,
- <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
- <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
- clock-names = "iface", "bus", "core", "vsync";
-
- assigned-clocks = <&clock_dispcc DISP_CC_MDSS_MDP_CLK>,
- <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>;
- assigned-clock-rates = <0 0 300000000 19200000>;
-
- interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dpu_intf1_out: endpoint {
- remote-endpoint = <&dsi0_in>;
- };
- };
-
- port@1 {
- reg = <1>;
- dpu_intf2_out: endpoint {
- remote-endpoint = <&dsi1_in>;
- };
- };
- };
- };
- };
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings
2021-02-12 10:49 [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Krishna Manikandan
@ 2021-02-12 10:49 ` Krishna Manikandan
2021-02-26 19:48 ` Stephen Boyd
2021-02-12 10:49 ` [PATCH v12 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings Krishna Manikandan
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Krishna Manikandan @ 2021-02-12 10:49 UTC (permalink / raw)
To: linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
swboyd, bjorn.andersson, vinod.koul, rnayak, dianders, sibis,
khsieh
Add YAML schema for the device tree bindings for DSI
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Changes in v1:
- Separate dsi controller bindings to a separate patch (Stephen Boyd)
- Merge dsi-common-controller.yaml and dsi-controller-main.yaml to
a single file (Stephen Boyd)
- Drop supply entries and definitions from properties (Stephen Boyd)
- Modify phy-names property for dsi controller (Stephen Boyd)
- Remove boolean from description (Stephen Boyd)
- Drop pinctrl properties as they are standard entries (Stephen Boyd)
- Modify the description for ports property and keep the reference
to the generic binding where this is defined (Stephen Boyd)
- Add description to clock names (Stephen Boyd)
- Correct the indendation (Stephen Boyd)
- Drop the label for display dt nodes and correct the node
name (Stephen Boyd)
Changes in v2:
- Drop maxItems for clock (Stephen Boyd)
- Drop qcom,mdss-mdp-transfer-time-us as it is not used in upstream
dt file (Stephen Boyd)
- Keep child node directly under soc node (Stephen Boyd)
- Drop qcom,sync-dual-dsi as it is not used in upstream dt
Changes in v3:
- Add description for register property (Stephen Boyd)
---
.../bindings/display/msm/dsi-controller-main.yaml | 201 +++++++++++++++++
.../devicetree/bindings/display/msm/dsi.txt | 249 ---------------------
2 files changed, 201 insertions(+), 249 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
new file mode 100644
index 0000000..2e9269d
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
@@ -0,0 +1,201 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DSI controller dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Common Device tree bindings for DSI controller.
+
+allOf:
+ - $ref: "../dsi-controller.yaml#"
+
+properties:
+ compatible:
+ items:
+ - const: qcom,mdss-dsi-ctrl
+
+ reg:
+ items:
+ - description: Address offset and size for dsi register set
+
+ reg-names:
+ const: dsi_ctrl
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display byte clock
+ - description: Display byte interface clock
+ - description: Display pixel clock
+ - description: Display escape clock
+ - description: Display AHB clock
+ - description: Display AXI clock
+
+ clock-names:
+ items:
+ - const: byte
+ - const: byte_intf
+ - const: pixel
+ - const: core
+ - const: iface
+ - const: bus
+
+ phys:
+ minItems: 1
+
+ phy-names:
+ const: dsi
+
+ syscon-sfpb:
+ description: A phandle to mmss_sfpb syscon node (only for DSIv2).
+ $ref: "/schemas/types.yaml#/definitions/phandle"
+
+ qcom,dual-dsi-mode:
+ type: boolean
+ description: |
+ Indicates if the DSI controller is driving a panel which needs
+ 2 DSI links.
+
+ qcom,master-dsi:
+ type: boolean
+ description: |
+ Indicates if the DSI controller is driving the master link of
+ the 2-DSI panel.
+
+ ports:
+ type: object
+ description: |
+ Contains DSI controller input and output ports as children, each
+ containing one endpoint subnode as defined in
+ Documentation/devicetree/bindings/graph.txt and
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+
+ properties:
+ port@0:
+ type: object
+ description: |
+ Input endpoints of the controller.
+
+ properties:
+ reg:
+ const: 0
+
+ endpoint:
+ type: object
+ properties:
+ remote-endpoint:
+ description: |
+ For port@0, set to phandle of the connected panel/bridge's
+ input endpoint. For port@1, set to the MDP interface output.
+ See Documentation/devicetree/bindings/graph.txt for
+ device graph info.
+
+ data-lanes:
+ description: |
+ This describes how the physical DSI data lanes are mapped
+ to the logical lanes on the given platform. The value contained in
+ index n describes what physical lane is mapped to the logical lane n
+ (DATAn, where n lies between 0 and 3). The clock lane position is fixed
+ and can't be changed. Hence, they aren't a part of the DT bindings. See
+ Documentation/devicetree/bindings/media/video-interfaces.txt for
+ more info on the data-lanes property.
+
+ items:
+ - const: 0
+ - const: 1
+ - const: 2
+ - const: 3
+ port@1:
+ type: object
+ description: |
+ Output endpoints of the controller.
+ properties:
+ reg:
+ const: 1
+
+ endpoint:
+ type: object
+ properties:
+ remote-endpoint: true
+ data-lanes:
+ items:
+ - const: 0
+ - const: 1
+ - const: 2
+ - const: 3
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi@ae94000 {
+ compatible = "qcom,mdss-dsi-ctrl";
+ reg = <0 0x0ae94000 0 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ phys = <&dsi0_phy>;
+ phy-names = "dsi";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt
deleted file mode 100644
index b9a64d3..0000000
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ /dev/null
@@ -1,249 +0,0 @@
-Qualcomm Technologies Inc. adreno/snapdragon DSI output
-
-DSI Controller:
-Required properties:
-- compatible:
- * "qcom,mdss-dsi-ctrl"
-- reg: Physical base address and length of the registers of controller
-- reg-names: The names of register regions. The following regions are required:
- * "dsi_ctrl"
-- interrupts: The interrupt signal from the DSI block.
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks.
-- clock-names: the following clocks are required:
- * "mdp_core"
- * "iface"
- * "bus"
- * "core_mmss"
- * "byte"
- * "pixel"
- * "core"
- For DSIv2, we need an additional clock:
- * "src"
- For DSI6G v2.0 onwards, we need also need the clock:
- * "byte_intf"
-- assigned-clocks: Parents of "byte" and "pixel" for the given platform.
-- assigned-clock-parents: The Byte clock and Pixel clock PLL outputs provided
- by a DSI PHY block. See [1] for details on clock bindings.
-- vdd-supply: phandle to vdd regulator device node
-- vddio-supply: phandle to vdd-io regulator device node
-- vdda-supply: phandle to vdda regulator device node
-- phys: phandle to DSI PHY device node
-- phy-names: the name of the corresponding PHY device
-- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
-- ports: Contains 2 DSI controller ports as child nodes. Each port contains
- an endpoint subnode as defined in [2] and [3].
-
-Optional properties:
-- panel@0: Node of panel connected to this DSI controller.
- See files in [4] for each supported panel.
-- qcom,dual-dsi-mode: Boolean value indicating if the DSI controller is
- driving a panel which needs 2 DSI links.
-- qcom,master-dsi: Boolean value indicating if the DSI controller is driving
- the master link of the 2-DSI panel.
-- qcom,sync-dual-dsi: Boolean value indicating if the DSI controller is
- driving a 2-DSI panel whose 2 links need receive command simultaneously.
-- pinctrl-names: the pin control state names; should contain "default"
-- pinctrl-0: the default pinctrl state (active)
-- pinctrl-n: the "sleep" pinctrl state
-- ports: contains DSI controller input and output ports as children, each
- containing one endpoint subnode.
-
- DSI Endpoint properties:
- - remote-endpoint: For port@0, set to phandle of the connected panel/bridge's
- input endpoint. For port@1, set to the MDP interface output. See [2] for
- device graph info.
-
- - data-lanes: this describes how the physical DSI data lanes are mapped
- to the logical lanes on the given platform. The value contained in
- index n describes what physical lane is mapped to the logical lane n
- (DATAn, where n lies between 0 and 3). The clock lane position is fixed
- and can't be changed. Hence, they aren't a part of the DT bindings. See
- [3] for more info on the data-lanes property.
-
- For example:
-
- data-lanes = <3 0 1 2>;
-
- The above mapping describes that the logical data lane DATA0 is mapped to
- the physical data lane DATA3, logical DATA1 to physical DATA0, logic DATA2
- to phys DATA1 and logic DATA3 to phys DATA2.
-
- There are only a limited number of physical to logical mappings possible:
- <0 1 2 3>
- <1 2 3 0>
- <2 3 0 1>
- <3 0 1 2>
- <0 3 2 1>
- <1 0 3 2>
- <2 1 0 3>
- <3 2 1 0>
-
-DSI PHY:
-Required properties:
-- compatible: Could be the following
- * "qcom,dsi-phy-28nm-hpm"
- * "qcom,dsi-phy-28nm-lp"
- * "qcom,dsi-phy-20nm"
- * "qcom,dsi-phy-28nm-8960"
- * "qcom,dsi-phy-14nm"
- * "qcom,dsi-phy-14nm-660"
- * "qcom,dsi-phy-10nm"
- * "qcom,dsi-phy-10nm-8998"
- * "qcom,dsi-phy-7nm"
- * "qcom,dsi-phy-7nm-8150"
-- reg: Physical base address and length of the registers of PLL, PHY. Some
- revisions require the PHY regulator base address, whereas others require the
- PHY lane base address. See below for each PHY revision.
-- reg-names: The names of register regions. The following regions are required:
- For DSI 28nm HPM/LP/8960 PHYs and 20nm PHY:
- * "dsi_pll"
- * "dsi_phy"
- * "dsi_phy_regulator"
- For DSI 14nm, 10nm and 7nm PHYs:
- * "dsi_pll"
- * "dsi_phy"
- * "dsi_phy_lane"
-- clock-cells: Must be 1. The DSI PHY block acts as a clock provider, creating
- 2 clocks: A byte clock (index 0), and a pixel clock (index 1).
-- power-domains: Should be <&mmcc MDSS_GDSC>.
-- clocks: Phandles to device clocks. See [1] for details on clock bindings.
-- clock-names: the following clocks are required:
- * "iface"
- * "ref" (only required for new DTS files/entries)
- For 28nm HPM/LP, 28nm 8960 PHYs:
-- vddio-supply: phandle to vdd-io regulator device node
- For 20nm PHY:
-- vddio-supply: phandle to vdd-io regulator device node
-- vcca-supply: phandle to vcca regulator device node
- For 14nm PHY:
-- vcca-supply: phandle to vcca regulator device node
- For 10nm and 7nm PHY:
-- vdds-supply: phandle to vdds regulator device node
-
-Optional properties:
-- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
- regulator is wanted.
-- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for command mode
- panels in microseconds. Driver uses this number to adjust
- the clock rate according to the expected transfer time.
- Increasing this value would slow down the mdp processing
- and can result in slower performance.
- Decreasing this value can speed up the mdp processing,
- but this can also impact power consumption.
- As a rule this time should not be higher than the time
- that would be expected with the processing at the
- dsi link rate since anyways this would be the maximum
- transfer time that could be achieved.
- If ping pong split is enabled, this time should not be higher
- than two times the dsi link rate time.
- If the property is not specified, then the default value is 14000 us.
-
-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
-[2] Documentation/devicetree/bindings/graph.txt
-[3] Documentation/devicetree/bindings/media/video-interfaces.txt
-[4] Documentation/devicetree/bindings/display/panel/
-
-Example:
- dsi0: dsi@fd922800 {
- compatible = "qcom,mdss-dsi-ctrl";
- qcom,dsi-host-index = <0>;
- interrupt-parent = <&mdp>;
- interrupts = <4 0>;
- reg-names = "dsi_ctrl";
- reg = <0xfd922800 0x200>;
- power-domains = <&mmcc MDSS_GDSC>;
- clock-names =
- "bus",
- "byte",
- "core",
- "core_mmss",
- "iface",
- "mdp_core",
- "pixel";
- clocks =
- <&mmcc MDSS_AXI_CLK>,
- <&mmcc MDSS_BYTE0_CLK>,
- <&mmcc MDSS_ESC0_CLK>,
- <&mmcc MMSS_MISC_AHB_CLK>,
- <&mmcc MDSS_AHB_CLK>,
- <&mmcc MDSS_MDP_CLK>,
- <&mmcc MDSS_PCLK0_CLK>;
-
- assigned-clocks =
- <&mmcc BYTE0_CLK_SRC>,
- <&mmcc PCLK0_CLK_SRC>;
- assigned-clock-parents =
- <&dsi_phy0 0>,
- <&dsi_phy0 1>;
-
- vdda-supply = <&pma8084_l2>;
- vdd-supply = <&pma8084_l22>;
- vddio-supply = <&pma8084_l12>;
-
- phys = <&dsi_phy0>;
- phy-names ="dsi-phy";
-
- qcom,dual-dsi-mode;
- qcom,master-dsi;
- qcom,sync-dual-dsi;
-
- qcom,mdss-mdp-transfer-time-us = <12000>;
-
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&dsi_active>;
- pinctrl-1 = <&dsi_suspend>;
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- dsi0_in: endpoint {
- remote-endpoint = <&mdp_intf1_out>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi0_out: endpoint {
- remote-endpoint = <&panel_in>;
- data-lanes = <0 1 2 3>;
- };
- };
- };
-
- panel: panel@0 {
- compatible = "sharp,lq101r1sx01";
- reg = <0>;
- link2 = <&secondary>;
-
- power-supply = <...>;
- backlight = <...>;
-
- port {
- panel_in: endpoint {
- remote-endpoint = <&dsi0_out>;
- };
- };
- };
- };
-
- dsi_phy0: dsi-phy@fd922a00 {
- compatible = "qcom,dsi-phy-28nm-hpm";
- qcom,dsi-phy-index = <0>;
- reg-names =
- "dsi_pll",
- "dsi_phy",
- "dsi_phy_regulator";
- reg = <0xfd922a00 0xd4>,
- <0xfd922b00 0x2b0>,
- <0xfd922d80 0x7b>;
- clock-names = "iface";
- clocks = <&mmcc MDSS_AHB_CLK>;
- #clock-cells = <1>;
- vddio-supply = <&pma8084_l12>;
-
- qcom,dsi-phy-regulator-ldo-mode;
- };
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v12 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings
2021-02-12 10:49 [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Krishna Manikandan
2021-02-12 10:49 ` [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings Krishna Manikandan
@ 2021-02-12 10:49 ` Krishna Manikandan
2021-02-26 19:52 ` Stephen Boyd
2021-02-12 10:50 ` [PATCH v12 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller Krishna Manikandan
2021-02-26 19:45 ` [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Stephen Boyd
3 siblings, 1 reply; 11+ messages in thread
From: Krishna Manikandan @ 2021-02-12 10:49 UTC (permalink / raw)
To: linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
swboyd, bjorn.andersson, vinod.koul, rnayak, dianders, sibis,
khsieh
Add YAML schema for the device tree bindings for DSI PHY.
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Changes in v1:
- Merge dsi-phy.yaml and dsi-phy-10nm.yaml (Stephen Boyd)
- Remove qcom,dsi-phy-regulator-ldo-mode (Stephen Boyd)
- Add clock cells properly (Stephen Boyd)
- Remove unnecessary decription from clock names (Stephen Boyd)
- Add pin names for the supply entries for 10nm phy which is
used in sc7180 and sdm845 (Stephen Boyd)
- Remove unused header files from examples (Stephen Boyd)
- Drop labels for display nodes and correct node name (Stephen Boyd)
Changes in v2:
- Drop maxItems for clock (Stephen Boyd)
- Add vdds supply pin information for sdm845 (Stephen Boyd)
- Add examples for 14nm, 20nm and 28nm phy yaml files (Stephen Boyd)
- Keep child nodes directly under soc node (Stephen Boyd)
---
.../bindings/display/msm/dsi-phy-10nm.yaml | 85 +++++++++++++++++++++
.../bindings/display/msm/dsi-phy-14nm.yaml | 83 ++++++++++++++++++++
.../bindings/display/msm/dsi-phy-20nm.yaml | 88 ++++++++++++++++++++++
.../bindings/display/msm/dsi-phy-28nm.yaml | 84 +++++++++++++++++++++
4 files changed, 340 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
new file mode 100644
index 0000000..627de6f
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-10nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DSI 10nm PHY dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Common Device tree bindings for DSI 10nm PHY.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-10nm
+ - const: qcom,dsi-phy-10nm-8998
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ "#clock-cells":
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ref
+
+ vdds-supply:
+ description: |
+ Connected to DSI0_MIPI_DSI_PLL_VDDA0P9 pin for sc7180 target and
+ connected to VDDA_MIPI_DSI_0_PLL_0P9 pin for sdm845 target
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - vdds-supply
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-10nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94a00 0 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vdds-supply = <&vdda_mipi_dsi0_pll>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
new file mode 100644
index 0000000..d1fa6ed
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DSI 14nm PHY dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Common Device tree bindings for DSI 14nm PHY.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-14nm
+ - const: qcom,dsi-phy-14nm-660
+
+ reg-names:
+ items:
+ - const: dsi_phy
+ - const: dsi_phy_lane
+ - const: dsi_pll
+
+ "#clock-cells":
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ref
+
+ vcca-supply:
+ description: Phandle to vcca regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - vcca-supply
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi-phy@ae94400 {
+ compatible = "qcom,dsi-phy-14nm";
+ reg = <0 0x0ae94400 0 0x200>,
+ <0 0x0ae94600 0 0x280>,
+ <0 0x0ae94a00 0 0x1e0>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vcca-supply = <&vcca_reg>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
new file mode 100644
index 0000000..ea13a32
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-20nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DSI 20nm PHY dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Common Device tree bindings for DSI 20nm PHY.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-20nm
+
+ reg-names:
+ items:
+ - const: dsi_pll
+ - const: dsi_phy
+ - const: dsi_phy_regulator
+
+ "#clock-cells":
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ref
+
+ vcca-supply:
+ description: Phandle to vcca regulator device node.
+
+ vddio-supply:
+ description: Phandle to vdd-io regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - vddio-supply
+ - vcca-supply
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-20nm";
+ reg = <0 0xfd922a00 0 0xd4>,
+ <0 0xfd922b00 0 0x2b0>,
+ <0 0xfd922d80 0 0x7b>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vcca-supply = <&vcca_reg>;
+ vddio-supply = <&vddio_reg>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
new file mode 100644
index 0000000..07c8294
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
@@ -0,0 +1,84 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dsi-phy-28nm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Description of Qualcomm Display DSI 28nm PHY dt properties
+
+maintainers:
+ - Krishna Manikandan <mkrishn@codeaurora.org>
+
+description: |
+ Common Device tree bindings for DSI 28nm PHY.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,dsi-phy-28nm-hpm
+ - const: qcom,dsi-phy-28nm-lp
+ - const: qcom,dsi-phy-28nm-8960
+
+ reg-names:
+ items:
+ - const: dsi_pll
+ - const: dsi_phy
+ - const: dsi_phy_regulator
+
+ "#clock-cells":
+ const: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: Display AHB clock
+ - description: Board XO source
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ref
+
+ vddio-supply:
+ description: Phandle to vdd-io regulator device node.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - vddio-supply
+
+additionalProperties: true
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dsi-phy@fd922a00 {
+ compatible = "qcom,dsi-phy-28nm";
+ reg = <0 0xfd922a00 0 0xd4>,
+ <0 0xfd922b00 0 0x2b0>,
+ <0 0xfd922d80 0 0x7b>;
+ reg-names = "dsi_pll",
+ "dsi_phy",
+ "dsi_phy_regulator";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ vddio-supply = <&vddio_reg>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v12 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller
2021-02-12 10:49 [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Krishna Manikandan
2021-02-12 10:49 ` [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings Krishna Manikandan
2021-02-12 10:49 ` [PATCH v12 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings Krishna Manikandan
@ 2021-02-12 10:50 ` Krishna Manikandan
2021-02-26 19:54 ` Stephen Boyd
2021-02-26 19:45 ` [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Stephen Boyd
3 siblings, 1 reply; 11+ messages in thread
From: Krishna Manikandan @ 2021-02-12 10:50 UTC (permalink / raw)
To: linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
swboyd, bjorn.andersson, vinod.koul, rnayak, dianders, sibis,
khsieh, Chandan Uddaraju, Vara Reddy
Add bindings for Snapdragon DisplayPort controller driver.
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Vara Reddy <varar@codeaurora.org>
Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Changes in V2:
-Provide details about sel-gpio
Changes in V4:
-Provide details about max dp lanes
-Change the commit text
Changes in V5:
-moved dp.txt to yaml file
Changes in v6:
- Squash all AUX LUT properties into one pattern Property
- Make aux-cfg[0-9]-settings properties optional
- Remove PLL/PHY bindings from DP controller dts
- Add DP clocks description
- Remove _clk suffix from clock names
- Rename pixel clock to stream_pixel
- Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
- Fix indentation
- Add Display Port as interface of DPU in DPU bindings
and add port mapping accordingly.
Chages in v7:
- Add dp-controller.yaml file common between multiple SOC
- Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
- change compatible string and add SOC name to it.
- Remove Root clock generator for pixel clock
- Add assigned-clocks and assigned-clock-parents bindings
- Remove redundant properties, descriptions and blank lines
- Add DP port in DPU bindings
- Update depends-on tag in commit message and rebase change accordingly
Changes in v8:
- Add MDSS AHB clock in bindings
Changes in v9:
- Remove redundant reg-name property
- Change assigned-clocks and assigned-clocks-parents counts to 2
- Use IRQ flags in example dts
Changes in v10:
- Change title of this patch as it does not contain PLL bindings anymore
- Remove redundant properties
- Remove use of IRQ flag
- Fix ports property
Changes in v11:
- add ports required of both #address-cells and #size-cells
- add required operating-points-v2
- add required #sound-dai-cells
- add required power-domains
- update maintainer list
---
.../bindings/display/msm/dp-controller.yaml | 152 +++++++++++++++++++++
.../bindings/display/msm/dpu-sc7180.yaml | 10 ++
2 files changed, 162 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
new file mode 100644
index 0000000..22fc03a
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -0,0 +1,152 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/dp-controller.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MSM Display Port Controller
+
+maintainers:
+ - Kuogee Hsieh <khsieh@codeaurora.org>
+
+description: |
+ Device tree bindings for DisplayPort host controller for MSM targets
+ that are compatible with VESA DisplayPort interface specification.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc7180-dp
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: AHB clock to enable register access
+ - description: Display Port AUX clock
+ - description: Display Port Link clock
+ - description: Link interface clock between DP and PHY
+ - description: Display Port Pixel clock
+
+ clock-names:
+ items:
+ - const: core_iface
+ - const: core_aux
+ - const: ctrl_link
+ - const: ctrl_link_iface
+ - const: stream_pixel
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ items:
+ - const: dp
+
+ operating-points-v2:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ "#sound-dai-cells":
+ const: 0
+
+ ports:
+ type: object
+ description: |
+ A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ properties:
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ port@0:
+ type: object
+ description: Input endpoint of the controller
+
+ port@1:
+ type: object
+ description: Output endpoint of the controller
+
+ required:
+ - "#address-cells"
+ - "#size-cells"
+
+ additionalProperties: false
+
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - phys
+ - phy-names
+ - "#sound-dai-cells"
+ - power-domains
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
+ #include <dt-bindings/power/qcom-aoss-qmp.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc: soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ displayport-controller@ae90000 {
+ compatible = "qcom,sc7180-dp";
+ reg = <0 0xae90000 0 0x1400>;
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface", "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface", "stream_pixel";
+
+ phys = <&dp_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ power-domains = <&rpmhpd SC7180_CX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ endpoint {
+ remote-endpoint = <&typec>;
+ };
+ };
+ };
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
index df88146..5fb40c0 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
@@ -130,6 +130,9 @@ patternProperties:
port@1:
type: object
description: DPU_INTF2 (DSI2)
+ port@2:
+ type: object
+ description: DPU_INTF0 (DP)
required:
- compatible
@@ -205,6 +208,13 @@ examples:
remote-endpoint = <&dsi0_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&dp_in>;
+ };
+ };
};
};
};
--
2.7.4
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings
2021-02-12 10:49 [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Krishna Manikandan
` (2 preceding siblings ...)
2021-02-12 10:50 ` [PATCH v12 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller Krishna Manikandan
@ 2021-02-26 19:45 ` Stephen Boyd
2021-03-04 12:36 ` mkrishn
3 siblings, 1 reply; 11+ messages in thread
From: Stephen Boyd @ 2021-02-26 19:45 UTC (permalink / raw)
To: Krishna Manikandan, linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh
Quoting Krishna Manikandan (2021-02-12 02:49:57)
> MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks
> like DPU display controller, DSI etc. Add YAML schema
> for DPU device tree bindings.
>
> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
>
> Changes in v2:
> - Changed dpu to DPU (Sam Ravnborg)
> - Fixed indentation issues (Sam Ravnborg)
> - Added empty line between different properties (Sam Ravnborg)
> - Replaced reference txt files with their corresponding
> yaml files (Sam Ravnborg)
> - Modified the file to use "|" only when it is
> necessary (Sam Ravnborg)
>
> Changes in v3:
> - Corrected the license used (Rob Herring)
> - Added maxItems for properties (Rob Herring)
> - Dropped generic descriptions (Rob Herring)
> - Added ranges property (Rob Herring)
> - Corrected the indendation (Rob Herring)
> - Added additionalProperties (Rob Herring)
> - Split dsi file into two, one for dsi controller
> and another one for dsi phy per target (Rob Herring)
> - Corrected description for pinctrl-names (Rob Herring)
> - Corrected the examples used in yaml file (Rob Herring)
> - Delete dsi.txt and dpu.txt (Rob Herring)
>
> Changes in v4:
> - Move schema up by one level (Rob Herring)
> - Add patternProperties for mdp node (Rob Herring)
> - Corrected description of some properties (Rob Herring)
>
> Changes in v5:
> - Correct the indentation (Rob Herring)
> - Remove unnecessary description from properties (Rob Herring)
> - Correct the number of interconnect entries (Rob Herring)
> - Add interconnect names for sc7180 (Rob Herring)
> - Add description for ports (Rob Herring)
> - Remove common properties (Rob Herring)
> - Add unevalutatedProperties (Rob Herring)
> - Reference existing dsi controller yaml in the common
> dsi controller file (Rob Herring)
> - Correct the description of clock names to include only the
> clocks that are required (Rob Herring)
> - Remove properties which are already covered under the common
> binding (Rob Herring)
> - Add dsi phy supply nodes which are required for sc7180 and
> sdm845 targets (Rob Herring)
> - Add type ref for syscon-sfpb (Rob Herring)
>
> Changes in v6:
> - Fixed errors during dt_binding_check (Rob Herring)
> - Add maxItems for phys and phys-names (Rob Herring)
> - Use unevaluatedProperties wherever required (Rob Herring)
> - Removed interrupt controller from required properties for
> dsi controller (Rob Herring)
> - Add constraints for dsi-phy reg-names based on the compatible
> phy version (Rob Herring)
> - Add constraints for dsi-phy supply nodes based on the
> compatible phy version (Rob Herring)
>
> Changes in v7:
> - Add default value for qcom,mdss-mdp-transfer-time-us (Rob Herring)
> - Modify the schema for data-lanes (Rob Herring)
> - Split the phy schema into separate schemas based on
> the phy version (Rob Herring)
>
> Changes in v8:
> - Resolve merge conflicts with latest dsi.txt file
> - Include dp yaml change also in the same series
>
> Changes in v9:
> - Combine target specific dsi controller yaml files
> to a single yaml file (Rob Herring)
> - Combine target specific dsi phy yaml files into a
> single yaml file (Rob Herring)
> - Use unevaluatedProperties and additionalProperties
> wherever required
> - Remove duplicate properties from common yaml files
>
> Changes in v10:
> - Split the patch into separate patches for DPU, DSI and
> PHY (Stephen Boyd)
> - Drop unnecessary fullstop (Stephen Boyd)
> - Add newline whereever required (Stephen Boyd)
> - Add description for clock used (Stephen Boyd)
> - Modify the description for interconnect entries (Stephen Boyd)
> - Drop assigned clock entries as it a generic property (Stephen Boyd)
> - Correct the definition for interrupts (Stephen Boyd)
> - Drop clock names from required properties (Stephen Boyd)
> - Drop labels for display nodes from example (Stephen Boyd)
> - Drop flags from interrupts entries (Stephen Boyd)
>
> Changes in v11:
> - Drop maxItems for clocks (Stephen Boyd)
>
> Changes in v12:
> - Add description for register property (Stephen Boyd)
> - Add maxItems for interrupts (Stephen Boyd)
> - Add description for iommus property (Stephen Boyd)
> - Add description for interconnects (Stephen Boyd)
> - Change display node name to display_controller (Stephen Boyd)
> ---
Looks mostly good to me. Some minor comments but otherwise seems OK.
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> new file mode 100644
> index 0000000..df88146
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
> @@ -0,0 +1,212 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DPU dt properties
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> + bindings of MDSS and DPU are mentioned for SC7180 target.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sc7180-mdss
> +
> + reg:
> + items:
> + - description: Address offset and size for mdss register set
I think the "rule" is if there's only one reg property then it is
maxItems: 1, sorry about that confusion.
> +
> + reg-names:
> + const: mdss
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Display AHB clock from gcc
> + - description: Display AHB clock from dispcc
> + - description: Display core clock
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: ahb
> + - const: core
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + iommus:
> + items:
> + - description: Phandle to apps_smmu node with sid mask for hf0
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
Why isn't this part of the example?
> +
> + interconnects:
> + items:
> + - description: Interconnect path specifying the port ids for data bus
> +
> + interconnect-names:
> + const: mdp0-mem
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + description: Node containing the properties of DPU.
> +
> + properties:
> + compatible:
> + items:
> + - const: qcom,sc7180-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display hf axi clock
> + - description: Display ahb clock
> + - description: Display rotator clock
> + - description: Display lut clock
> + - description: Display core clock
> + - description: Display vsync clock
> +
> + clock-names:
> + items:
> + - const: bus
> + - const: iface
> + - const: rot
> + - const: lut
> + - const: core
> + - const: vsync
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + type: object
> + description: |
> + Contains the list of output ports from DPU device. These ports
> + connect to interfaces that are external to the DPU hardware,
> + such as DSI, DP etc. Each output port contains an endpoint that
> + describes how it is connected to an external interface. These
> + are described by the standard properties documented in files
> + mentioned below.
> +
> + Documentation/devicetree/bindings/graph.txt
> + Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> + properties:
> + port@0:
> + type: object
> + description: DPU_INTF1 (DSI1)
> +
> + port@1:
> + type: object
> + description: DPU_INTF2 (DSI2)
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> + - clocks
> + - interrupts
> + - interrupt-controller
> + - iommus
Shouldn't ranges be required?
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/interconnect/qcom,sdm845.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + mdss@ae00000 {
> + compatible = "qcom,sc7180-mdss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0 0xae00000 0 0x1000>;
> + reg-names = "mdss";
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "ahb", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
> + interconnect-names = "mdp0-mem";
> +
> + iommus = <&apps_smmu 0x800 0x2>;
> +
> + display-controller@ae01000 {
> + compatible = "qcom,sc7180-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> +
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "bus", "iface", "rot", "lut", "core",
> + "vsync";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> + };
> + };
> + };
> + };
> +...
> diff --git a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
> new file mode 100644
> index 0000000..71f8658
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
> @@ -0,0 +1,202 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DPU dt properties
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that encapsulates
> + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
> + bindings of MDSS and DPU are mentioned for SDM845 target.
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sdm845-mdss
> +
> + reg:
> + items:
> + - description: Address offset and size for mdss register set
> +
> + reg-names:
> + const: mdss
> +
> + power-domains:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Display AHB clock from gcc
> + - description: Display AXI clock
> + - description: Display core clock
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: bus
> + - const: core
> +
> + interrupts:
> + maxItems: 1
> +
> + interrupt-controller: true
> +
> + "#interrupt-cells":
> + const: 1
> +
> + iommus:
> + items:
> + - description: Phandle to apps_smmu node with sid mask for hf0
> + - description: Phandle to apps_smmu node with sid mask for hf1
What does 'hf' mean here? Can you spell it out? And capitalize SID for
Stream ID?
> +
> + "#address-cells":
> + const: 2
> +
> + "#size-cells":
> + const: 2
> +
> + ranges: true
> +
> +patternProperties:
> + "^display-controller@[0-9a-f]+$":
> + type: object
> + description: Node containing the properties of DPU.
> +
> + properties:
> + compatible:
> + items:
> + - const: qcom,sdm845-dpu
> +
> + reg:
> + items:
> + - description: Address offset and size for mdp register set
> + - description: Address offset and size for vbif register set
> +
> + reg-names:
> + items:
> + - const: mdp
> + - const: vbif
> +
> + clocks:
> + items:
> + - description: Display ahb clock
> + - description: Display axi clock
> + - description: Display core clock
> + - description: Display vsync clock
> +
> + clock-names:
> + items:
> + - const: iface
> + - const: bus
> + - const: core
> + - const: vsync
> +
> + interrupts:
> + maxItems: 1
> +
> + ports:
> + type: object
> + description: |
> + Contains the list of output ports from DPU device. These ports
> + connect to interfaces that are external to the DPU hardware,
> + such as DSI, DP etc. Each output port contains an endpoint that
> + describes how it is connected to an external interface. These
> + are described by the standard properties documented in files
> + mentioned below.
> +
> + Documentation/devicetree/bindings/graph.txt
> + Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> + properties:
> + port@0:
> + type: object
> + description: DPU_INTF1 (DSI1)
> +
> + port@1:
> + type: object
> + description: DPU_INTF2 (DSI2)
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - power-domains
> + - clocks
> + - interrupts
> + - interrupt-controller
> + - iommus
> +
> +additionalProperties: false
> +
> +examples:
> +- |
> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
I think we can drop the soc node from the examples.
> +
> + mdss@ae00000 {
> + compatible = "qcom,sdm845-mdss";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + reg = <0 0x0ae00000 0 0x1000>;
> + reg-names = "mdss";
> + power-domains = <&dispcc MDSS_GDSC>;
> +
> + clocks = <&gcc GCC_DISP_AHB_CLK>,
> + <&gcc GCC_DISP_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
> + clock-names = "iface", "bus", "core";
> +
> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <1>;
> +
> + iommus = <&apps_smmu 0x880 0x8>,
> + <&apps_smmu 0xc80 0x8>;
> +
> + display-controller@ae01000 {
> + compatible = "qcom,sdm845-dpu";
> + reg = <0 0x0ae01000 0 0x8f000>,
> + <0 0x0aeb0000 0 0x2008>;
> + reg-names = "mdp", "vbif";
> +
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>,
> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
> + clock-names = "iface", "bus", "core", "vsync";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dpu_intf1_out: endpoint {
> + remote-endpoint = <&dsi0_in>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dpu_intf2_out: endpoint {
> + remote-endpoint = <&dsi1_in>;
> + };
> + };
> + };
> + };
> + };
> + };
> +...
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings
2021-02-12 10:49 ` [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings Krishna Manikandan
@ 2021-02-26 19:48 ` Stephen Boyd
0 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2021-02-26 19:48 UTC (permalink / raw)
To: Krishna Manikandan, linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh
Quoting Krishna Manikandan (2021-02-12 02:49:58)
> Add YAML schema for the device tree bindings for DSI
>
> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
>
> Changes in v1:
> - Separate dsi controller bindings to a separate patch (Stephen Boyd)
> - Merge dsi-common-controller.yaml and dsi-controller-main.yaml to
> a single file (Stephen Boyd)
> - Drop supply entries and definitions from properties (Stephen Boyd)
> - Modify phy-names property for dsi controller (Stephen Boyd)
> - Remove boolean from description (Stephen Boyd)
> - Drop pinctrl properties as they are standard entries (Stephen Boyd)
> - Modify the description for ports property and keep the reference
> to the generic binding where this is defined (Stephen Boyd)
> - Add description to clock names (Stephen Boyd)
> - Correct the indendation (Stephen Boyd)
> - Drop the label for display dt nodes and correct the node
> name (Stephen Boyd)
>
> Changes in v2:
> - Drop maxItems for clock (Stephen Boyd)
> - Drop qcom,mdss-mdp-transfer-time-us as it is not used in upstream
> dt file (Stephen Boyd)
> - Keep child node directly under soc node (Stephen Boyd)
> - Drop qcom,sync-dual-dsi as it is not used in upstream dt
>
> Changes in v3:
> - Add description for register property (Stephen Boyd)
> ---
> .../bindings/display/msm/dsi-controller-main.yaml | 201 +++++++++++++++++
> .../devicetree/bindings/display/msm/dsi.txt | 249 ---------------------
> 2 files changed, 201 insertions(+), 249 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> delete mode 100644 Documentation/devicetree/bindings/display/msm/dsi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> new file mode 100644
> index 0000000..2e9269d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml
> @@ -0,0 +1,201 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Description of Qualcomm Display DSI controller dt properties
> +
> +maintainers:
> + - Krishna Manikandan <mkrishn@codeaurora.org>
> +
> +description: |
> + Common Device tree bindings for DSI controller.
> +
> +allOf:
> + - $ref: "../dsi-controller.yaml#"
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,mdss-dsi-ctrl
> +
> + reg:
> + items:
> + - description: Address offset and size for dsi register set
> +
> + reg-names:
> + const: dsi_ctrl
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: Display byte clock
> + - description: Display byte interface clock
> + - description: Display pixel clock
> + - description: Display escape clock
> + - description: Display AHB clock
> + - description: Display AXI clock
> +
> + clock-names:
> + items:
> + - const: byte
> + - const: byte_intf
> + - const: pixel
> + - const: core
> + - const: iface
> + - const: bus
> +
> + phys:
> + minItems: 1
maxItems:1 ?
> + phy-names:
> + const: dsi
> +
> + syscon-sfpb:
> + description: A phandle to mmss_sfpb syscon node (only for DSIv2).
> + $ref: "/schemas/types.yaml#/definitions/phandle"
> +
> + qcom,dual-dsi-mode:
> + type: boolean
> + description: |
> + Indicates if the DSI controller is driving a panel which needs
> + 2 DSI links.
> +
> + qcom,master-dsi:
> + type: boolean
> + description: |
> + Indicates if the DSI controller is driving the master link of
> + the 2-DSI panel.
> +
> + ports:
> + type: object
> + description: |
> + Contains DSI controller input and output ports as children, each
> + containing one endpoint subnode as defined in
> + Documentation/devicetree/bindings/graph.txt and
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> +
> + properties:
> + port@0:
> + type: object
> + description: |
> + Input endpoints of the controller.
> +
> + properties:
> + reg:
> + const: 0
> +
> + endpoint:
> + type: object
> + properties:
> + remote-endpoint:
> + description: |
> + For port@0, set to phandle of the connected panel/bridge's
> + input endpoint. For port@1, set to the MDP interface output.
> + See Documentation/devicetree/bindings/graph.txt for
> + device graph info.
> +
> + data-lanes:
> + description: |
> + This describes how the physical DSI data lanes are mapped
> + to the logical lanes on the given platform. The value contained in
> + index n describes what physical lane is mapped to the logical lane n
> + (DATAn, where n lies between 0 and 3). The clock lane position is fixed
> + and can't be changed. Hence, they aren't a part of the DT bindings. See
> + Documentation/devicetree/bindings/media/video-interfaces.txt for
> + more info on the data-lanes property.
> +
> + items:
> + - const: 0
> + - const: 1
> + - const: 2
> + - const: 3
Is data-lanes not already covered by some more generic binding?
> + port@1:
> + type: object
> + description: |
> + Output endpoints of the controller.
> + properties:
> + reg:
> + const: 1
> +
> + endpoint:
> + type: object
> + properties:
> + remote-endpoint: true
> + data-lanes:
> + items:
> + - const: 0
> + - const: 1
> + - const: 2
> + - const: 3
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - interrupts
> + - clocks
> + - clock-names
> + - phys
> + - phy-names
> + - ports
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> +
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
Please remove soc from the example
> +
> + dsi@ae94000 {
> + compatible = "qcom,mdss-dsi-ctrl";
> + reg = <0 0x0ae94000 0 0x400>;
> + reg-names = "dsi_ctrl";
> +
> + interrupt-parent = <&mdss>;
> + interrupts = <4>;
> +
> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
> + <&dispcc DISP_CC_MDSS_ESC0_CLK>,
> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_AXI_CLK>;
> + clock-names = "byte",
> + "byte_intf",
> + "pixel",
> + "core",
> + "iface",
> + "bus";
> +
> + phys = <&dsi0_phy>;
> + phy-names = "dsi";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi0_in: endpoint {
> + remote-endpoint = <&dpu_intf1_out>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + dsi0_out: endpoint {
> + };
> + };
> + };
> + };
> + };
> +...
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v12 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings
2021-02-12 10:49 ` [PATCH v12 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings Krishna Manikandan
@ 2021-02-26 19:52 ` Stephen Boyd
0 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2021-02-26 19:52 UTC (permalink / raw)
To: Krishna Manikandan, linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh
Quoting Krishna Manikandan (2021-02-12 02:49:59)
> Add YAML schema for the device tree bindings for DSI PHY.
>
> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
>
> Changes in v1:
> - Merge dsi-phy.yaml and dsi-phy-10nm.yaml (Stephen Boyd)
> - Remove qcom,dsi-phy-regulator-ldo-mode (Stephen Boyd)
> - Add clock cells properly (Stephen Boyd)
> - Remove unnecessary decription from clock names (Stephen Boyd)
> - Add pin names for the supply entries for 10nm phy which is
> used in sc7180 and sdm845 (Stephen Boyd)
> - Remove unused header files from examples (Stephen Boyd)
> - Drop labels for display nodes and correct node name (Stephen Boyd)
>
> Changes in v2:
> - Drop maxItems for clock (Stephen Boyd)
> - Add vdds supply pin information for sdm845 (Stephen Boyd)
> - Add examples for 14nm, 20nm and 28nm phy yaml files (Stephen Boyd)
> - Keep child nodes directly under soc node (Stephen Boyd)
> ---
> .../bindings/display/msm/dsi-phy-10nm.yaml | 85 +++++++++++++++++++++
> .../bindings/display/msm/dsi-phy-14nm.yaml | 83 ++++++++++++++++++++
> .../bindings/display/msm/dsi-phy-20nm.yaml | 88 ++++++++++++++++++++++
> .../bindings/display/msm/dsi-phy-28nm.yaml | 84 +++++++++++++++++++++
Aren't these bindings largely the same modulo the compatible string? Can
we either combine them into one document or use a common binding base
that is imported into the different nanometer phy binding docs? Look at
Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml for how
this was done for the qcom pinctrl binding.
From a quick glance, the compatible string and the supply name is
different. Otherwise it's the same? Please combine them together.
> 4 files changed, 340 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-20nm.yaml
> create mode 100644 Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v12 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller
2021-02-12 10:50 ` [PATCH v12 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller Krishna Manikandan
@ 2021-02-26 19:54 ` Stephen Boyd
0 siblings, 0 replies; 11+ messages in thread
From: Stephen Boyd @ 2021-02-26 19:54 UTC (permalink / raw)
To: Krishna Manikandan, linux-arm-msm
Cc: Krishna Manikandan, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh,
Chandan Uddaraju, Vara Reddy
Quoting Krishna Manikandan (2021-02-12 02:50:00)
> Add bindings for Snapdragon DisplayPort controller driver.
>
> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
> Signed-off-by: Vara Reddy <varar@codeaurora.org>
> Signed-off-by: Tanmay Shah <tanmay@codeaurora.org>
> Signed-off-by: Kuogee Hsieh <khsieh@codeaurora.org>
> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
>
> Changes in V2:
> -Provide details about sel-gpio
>
> Changes in V4:
> -Provide details about max dp lanes
> -Change the commit text
>
> Changes in V5:
> -moved dp.txt to yaml file
>
> Changes in v6:
> - Squash all AUX LUT properties into one pattern Property
> - Make aux-cfg[0-9]-settings properties optional
> - Remove PLL/PHY bindings from DP controller dts
> - Add DP clocks description
> - Remove _clk suffix from clock names
> - Rename pixel clock to stream_pixel
> - Remove redundant bindings (GPIO, PHY, HDCP clock, etc..)
> - Fix indentation
> - Add Display Port as interface of DPU in DPU bindings
> and add port mapping accordingly.
>
> Chages in v7:
> - Add dp-controller.yaml file common between multiple SOC
> - Rename dp-sc7180.yaml to dp-controller-sc7180.yaml
> - change compatible string and add SOC name to it.
> - Remove Root clock generator for pixel clock
> - Add assigned-clocks and assigned-clock-parents bindings
> - Remove redundant properties, descriptions and blank lines
> - Add DP port in DPU bindings
> - Update depends-on tag in commit message and rebase change accordingly
>
> Changes in v8:
> - Add MDSS AHB clock in bindings
>
> Changes in v9:
> - Remove redundant reg-name property
> - Change assigned-clocks and assigned-clocks-parents counts to 2
> - Use IRQ flags in example dts
>
> Changes in v10:
> - Change title of this patch as it does not contain PLL bindings anymore
> - Remove redundant properties
> - Remove use of IRQ flag
> - Fix ports property
>
> Changes in v11:
> - add ports required of both #address-cells and #size-cells
> - add required operating-points-v2
> - add required #sound-dai-cells
> - add required power-domains
> - update maintainer list
> ---
> .../bindings/display/msm/dp-controller.yaml | 152 +++++++++++++++++++++
> .../bindings/display/msm/dpu-sc7180.yaml | 10 ++
Can this dpu-sc7180.yaml update be split away from this patch and put
into the patch that introduces that yaml file?
> 2 files changed, 162 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/msm/dp-controller.yaml
>
Otherwise
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings
2021-02-26 19:45 ` [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Stephen Boyd
@ 2021-03-04 12:36 ` mkrishn
2021-03-05 6:53 ` Stephen Boyd
0 siblings, 1 reply; 11+ messages in thread
From: mkrishn @ 2021-03-04 12:36 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh
On 2021-02-27 01:15, Stephen Boyd wrote:
> Quoting Krishna Manikandan (2021-02-12 02:49:57)
>> MSM Mobile Display Subsytem (MDSS) encapsulates sub-blocks
>> like DPU display controller, DSI etc. Add YAML schema
>> for DPU device tree bindings.
>>
>> Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
>>
>> Changes in v2:
>> - Changed dpu to DPU (Sam Ravnborg)
>> - Fixed indentation issues (Sam Ravnborg)
>> - Added empty line between different properties (Sam Ravnborg)
>> - Replaced reference txt files with their corresponding
>> yaml files (Sam Ravnborg)
>> - Modified the file to use "|" only when it is
>> necessary (Sam Ravnborg)
>>
>> Changes in v3:
>> - Corrected the license used (Rob Herring)
>> - Added maxItems for properties (Rob Herring)
>> - Dropped generic descriptions (Rob Herring)
>> - Added ranges property (Rob Herring)
>> - Corrected the indendation (Rob Herring)
>> - Added additionalProperties (Rob Herring)
>> - Split dsi file into two, one for dsi controller
>> and another one for dsi phy per target (Rob Herring)
>> - Corrected description for pinctrl-names (Rob Herring)
>> - Corrected the examples used in yaml file (Rob Herring)
>> - Delete dsi.txt and dpu.txt (Rob Herring)
>>
>> Changes in v4:
>> - Move schema up by one level (Rob Herring)
>> - Add patternProperties for mdp node (Rob Herring)
>> - Corrected description of some properties (Rob Herring)
>>
>> Changes in v5:
>> - Correct the indentation (Rob Herring)
>> - Remove unnecessary description from properties (Rob Herring)
>> - Correct the number of interconnect entries (Rob Herring)
>> - Add interconnect names for sc7180 (Rob Herring)
>> - Add description for ports (Rob Herring)
>> - Remove common properties (Rob Herring)
>> - Add unevalutatedProperties (Rob Herring)
>> - Reference existing dsi controller yaml in the common
>> dsi controller file (Rob Herring)
>> - Correct the description of clock names to include only the
>> clocks that are required (Rob Herring)
>> - Remove properties which are already covered under the common
>> binding (Rob Herring)
>> - Add dsi phy supply nodes which are required for sc7180 and
>> sdm845 targets (Rob Herring)
>> - Add type ref for syscon-sfpb (Rob Herring)
>>
>> Changes in v6:
>> - Fixed errors during dt_binding_check (Rob Herring)
>> - Add maxItems for phys and phys-names (Rob Herring)
>> - Use unevaluatedProperties wherever required (Rob Herring)
>> - Removed interrupt controller from required properties for
>> dsi controller (Rob Herring)
>> - Add constraints for dsi-phy reg-names based on the compatible
>> phy version (Rob Herring)
>> - Add constraints for dsi-phy supply nodes based on the
>> compatible phy version (Rob Herring)
>>
>> Changes in v7:
>> - Add default value for qcom,mdss-mdp-transfer-time-us (Rob
>> Herring)
>> - Modify the schema for data-lanes (Rob Herring)
>> - Split the phy schema into separate schemas based on
>> the phy version (Rob Herring)
>>
>> Changes in v8:
>> - Resolve merge conflicts with latest dsi.txt file
>> - Include dp yaml change also in the same series
>>
>> Changes in v9:
>> - Combine target specific dsi controller yaml files
>> to a single yaml file (Rob Herring)
>> - Combine target specific dsi phy yaml files into a
>> single yaml file (Rob Herring)
>> - Use unevaluatedProperties and additionalProperties
>> wherever required
>> - Remove duplicate properties from common yaml files
>>
>> Changes in v10:
>> - Split the patch into separate patches for DPU, DSI and
>> PHY (Stephen Boyd)
>> - Drop unnecessary fullstop (Stephen Boyd)
>> - Add newline whereever required (Stephen Boyd)
>> - Add description for clock used (Stephen Boyd)
>> - Modify the description for interconnect entries (Stephen Boyd)
>> - Drop assigned clock entries as it a generic property (Stephen
>> Boyd)
>> - Correct the definition for interrupts (Stephen Boyd)
>> - Drop clock names from required properties (Stephen Boyd)
>> - Drop labels for display nodes from example (Stephen Boyd)
>> - Drop flags from interrupts entries (Stephen Boyd)
>>
>> Changes in v11:
>> - Drop maxItems for clocks (Stephen Boyd)
>>
>> Changes in v12:
>> - Add description for register property (Stephen Boyd)
>> - Add maxItems for interrupts (Stephen Boyd)
>> - Add description for iommus property (Stephen Boyd)
>> - Add description for interconnects (Stephen Boyd)
>> - Change display node name to display_controller (Stephen Boyd)
>> ---
>
> Looks mostly good to me. Some minor comments but otherwise seems OK.
>
>> diff --git
>> a/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
>> b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
>> new file mode 100644
>> index 0000000..df88146
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sc7180.yaml
>> @@ -0,0 +1,212 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/dpu-sc7180.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Description of Qualcomm Display DPU dt properties
>> +
>> +maintainers:
>> + - Krishna Manikandan <mkrishn@codeaurora.org>
>> +
>> +description: |
>> + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that
>> encapsulates
>> + sub-blocks like DPU display controller, DSI and DP interfaces etc.
>> Device tree
>> + bindings of MDSS and DPU are mentioned for SC7180 target.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,sc7180-mdss
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdss register set
>
> I think the "rule" is if there's only one reg property then it is
> maxItems: 1, sorry about that confusion.
>
>> +
>> + reg-names:
>> + const: mdss
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: Display AHB clock from gcc
>> + - description: Display AHB clock from dispcc
>> + - description: Display core clock
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: ahb
>> + - const: core
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupt-controller: true
>> +
>> + "#interrupt-cells":
>> + const: 1
>> +
>> + iommus:
>> + items:
>> + - description: Phandle to apps_smmu node with sid mask for hf0
>> +
>> + "#address-cells":
>> + const: 2
>> +
>> + "#size-cells":
>> + const: 2
>> +
>> + ranges: true
>
> Why isn't this part of the example?
>
>> +
>> + interconnects:
>> + items:
>> + - description: Interconnect path specifying the port ids for
>> data bus
>> +
>> + interconnect-names:
>> + const: mdp0-mem
>> +
>> +patternProperties:
>> + "^display-controller@[0-9a-f]+$":
>> + type: object
>> + description: Node containing the properties of DPU.
>> +
>> + properties:
>> + compatible:
>> + items:
>> + - const: qcom,sc7180-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register
>> set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display hf axi clock
>> + - description: Display ahb clock
>> + - description: Display rotator clock
>> + - description: Display lut clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: bus
>> + - const: iface
>> + - const: rot
>> + - const: lut
>> + - const: core
>> + - const: vsync
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + ports:
>> + type: object
>> + description: |
>> + Contains the list of output ports from DPU device. These
>> ports
>> + connect to interfaces that are external to the DPU
>> hardware,
>> + such as DSI, DP etc. Each output port contains an endpoint
>> that
>> + describes how it is connected to an external interface.
>> These
>> + are described by the standard properties documented in
>> files
>> + mentioned below.
>> +
>> + Documentation/devicetree/bindings/graph.txt
>> +
>> Documentation/devicetree/bindings/media/video-interfaces.txt
>> +
>> + properties:
>> + port@0:
>> + type: object
>> + description: DPU_INTF1 (DSI1)
>> +
>> + port@1:
>> + type: object
>> + description: DPU_INTF2 (DSI2)
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - power-domains
>> + - clocks
>> + - interrupts
>> + - interrupt-controller
>> + - iommus
>
> Shouldn't ranges be required?
>
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
>> + #include <dt-bindings/clock/qcom,gcc-sc7180.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> + #include <dt-bindings/interconnect/qcom,sdm845.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + mdss@ae00000 {
>> + compatible = "qcom,sc7180-mdss";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + reg = <0 0xae00000 0 0x1000>;
>> + reg-names = "mdss";
>> + power-domains = <&dispcc MDSS_GDSC>;
>> +
>> + clocks = <&gcc GCC_DISP_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> + clock-names = "iface", "ahb", "core";
>> +
>> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + interconnects = <&mmss_noc MASTER_MDP0 &mc_virt SLAVE_EBI1>;
>> + interconnect-names = "mdp0-mem";
>> +
>> + iommus = <&apps_smmu 0x800 0x2>;
>> +
>> + display-controller@ae01000 {
>> + compatible = "qcom,sc7180-dpu";
>> + reg = <0 0x0ae01000 0 0x8f000>,
>> + <0 0x0aeb0000 0 0x2008>;
>> +
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_ROT_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "bus", "iface", "rot", "lut",
>> "core",
>> + "vsync";
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint =
>> <&dsi0_in>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> + };
>> +...
>> diff --git
>> a/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
>> b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
>> new file mode 100644
>> index 0000000..71f8658
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/dpu-sdm845.yaml
>> @@ -0,0 +1,202 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/dpu-sdm845.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Description of Qualcomm Display DPU dt properties
>> +
>> +maintainers:
>> + - Krishna Manikandan <mkrishn@codeaurora.org>
>> +
>> +description: |
>> + Device tree bindings for MSM Mobile Display Subsytem(MDSS) that
>> encapsulates
>> + sub-blocks like DPU display controller, DSI and DP interfaces etc.
>> Device tree
>> + bindings of MDSS and DPU are mentioned for SDM845 target.
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,sdm845-mdss
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdss register set
>> +
>> + reg-names:
>> + const: mdss
>> +
>> + power-domains:
>> + maxItems: 1
>> +
>> + clocks:
>> + items:
>> + - description: Display AHB clock from gcc
>> + - description: Display AXI clock
>> + - description: Display core clock
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: bus
>> + - const: core
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + interrupt-controller: true
>> +
>> + "#interrupt-cells":
>> + const: 1
>> +
>> + iommus:
>> + items:
>> + - description: Phandle to apps_smmu node with sid mask for hf0
>> + - description: Phandle to apps_smmu node with sid mask for hf1
>
> What does 'hf' mean here? Can you spell it out? And capitalize SID for
> Stream ID?
>
>> +
>> + "#address-cells":
>> + const: 2
>> +
>> + "#size-cells":
>> + const: 2
>> +
>> + ranges: true
>> +
>> +patternProperties:
>> + "^display-controller@[0-9a-f]+$":
>> + type: object
>> + description: Node containing the properties of DPU.
>> +
>> + properties:
>> + compatible:
>> + items:
>> + - const: qcom,sdm845-dpu
>> +
>> + reg:
>> + items:
>> + - description: Address offset and size for mdp register set
>> + - description: Address offset and size for vbif register
>> set
>> +
>> + reg-names:
>> + items:
>> + - const: mdp
>> + - const: vbif
>> +
>> + clocks:
>> + items:
>> + - description: Display ahb clock
>> + - description: Display axi clock
>> + - description: Display core clock
>> + - description: Display vsync clock
>> +
>> + clock-names:
>> + items:
>> + - const: iface
>> + - const: bus
>> + - const: core
>> + - const: vsync
>> +
>> + interrupts:
>> + maxItems: 1
>> +
>> + ports:
>> + type: object
>> + description: |
>> + Contains the list of output ports from DPU device. These
>> ports
>> + connect to interfaces that are external to the DPU
>> hardware,
>> + such as DSI, DP etc. Each output port contains an endpoint
>> that
>> + describes how it is connected to an external interface.
>> These
>> + are described by the standard properties documented in
>> files
>> + mentioned below.
>> +
>> + Documentation/devicetree/bindings/graph.txt
>> +
>> Documentation/devicetree/bindings/media/video-interfaces.txt
>> +
>> + properties:
>> + port@0:
>> + type: object
>> + description: DPU_INTF1 (DSI1)
>> +
>> + port@1:
>> + type: object
>> + description: DPU_INTF2 (DSI2)
>> +
>> +required:
>> + - compatible
>> + - reg
>> + - reg-names
>> + - power-domains
>> + - clocks
>> + - interrupts
>> + - interrupt-controller
>> + - iommus
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +- |
>> + #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
>> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
>> + #include <dt-bindings/interrupt-controller/arm-gic.h>
>> +
>> + soc {
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>
> I think we can drop the soc node from the examples.
Hi Stephen,
In latest dt schema, there is a rule that we have to specify the address
and size cells or else it will take default value of 1 for both. If we
use these default values, dt binding check will throw error as display
uses 2 address cells and 2 size cells. That's why soc node was added to
specify the values for mdss node.
Thanks,
Krishna
>
>> +
>> + mdss@ae00000 {
>> + compatible = "qcom,sdm845-mdss";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + reg = <0 0x0ae00000 0 0x1000>;
>> + reg-names = "mdss";
>> + power-domains = <&dispcc MDSS_GDSC>;
>> +
>> + clocks = <&gcc GCC_DISP_AHB_CLK>,
>> + <&gcc GCC_DISP_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>;
>> + clock-names = "iface", "bus", "core";
>> +
>> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> +
>> + iommus = <&apps_smmu 0x880 0x8>,
>> + <&apps_smmu 0xc80 0x8>;
>> +
>> + display-controller@ae01000 {
>> + compatible = "qcom,sdm845-dpu";
>> + reg = <0 0x0ae01000 0 0x8f000>,
>> + <0 0x0aeb0000 0 0x2008>;
>> + reg-names = "mdp", "vbif";
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_AXI_CLK>,
>> + <&dispcc DISP_CC_MDSS_MDP_CLK>,
>> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
>> + clock-names = "iface", "bus", "core", "vsync";
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <0>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + dpu_intf1_out: endpoint {
>> + remote-endpoint =
>> <&dsi0_in>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + dpu_intf2_out: endpoint {
>> + remote-endpoint =
>> <&dsi1_in>;
>> + };
>> + };
>> + };
>> + };
>> + };
>> + };
>> +...
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings
2021-03-04 12:36 ` mkrishn
@ 2021-03-05 6:53 ` Stephen Boyd
2021-03-05 13:30 ` mkrishn
0 siblings, 1 reply; 11+ messages in thread
From: Stephen Boyd @ 2021-03-05 6:53 UTC (permalink / raw)
To: mkrishn
Cc: linux-arm-msm, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh
Quoting mkrishn@codeaurora.org (2021-03-04 04:36:05)
> On 2021-02-27 01:15, Stephen Boyd wrote:
> > Quoting Krishna Manikandan (2021-02-12 02:49:57)
> >> +
> >> + soc {
> >> + #address-cells = <2>;
> >> + #size-cells = <2>;
> >
> > I think we can drop the soc node from the examples.
> Hi Stephen,
>
> In latest dt schema, there is a rule that we have to specify the address
> and size cells or else it will take default value of 1 for both. If we
> use these default values, dt binding check will throw error as display
> uses 2 address cells and 2 size cells. That's why soc node was added to
> specify the values for mdss node.
>
Do you need to use both cells in the example? Presumably the second cell
is all zero, so it's useless. The example doesn't have to have both
cells in the reg property, that can be fixed up when writing the DT for
a particular SoC.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings
2021-03-05 6:53 ` Stephen Boyd
@ 2021-03-05 13:30 ` mkrishn
0 siblings, 0 replies; 11+ messages in thread
From: mkrishn @ 2021-03-05 13:30 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-arm-msm, kalyan_t, tanmay, abhinavk, robdclark,
bjorn.andersson, vinod.koul, rnayak, dianders, sibis, khsieh
On 2021-03-05 12:23, Stephen Boyd wrote:
> Quoting mkrishn@codeaurora.org (2021-03-04 04:36:05)
>> On 2021-02-27 01:15, Stephen Boyd wrote:
>> > Quoting Krishna Manikandan (2021-02-12 02:49:57)
>> >> +
>> >> + soc {
>> >> + #address-cells = <2>;
>> >> + #size-cells = <2>;
>> >
>> > I think we can drop the soc node from the examples.
>> Hi Stephen,
>>
>> In latest dt schema, there is a rule that we have to specify the
>> address
>> and size cells or else it will take default value of 1 for both. If we
>> use these default values, dt binding check will throw error as display
>> uses 2 address cells and 2 size cells. That's why soc node was added
>> to
>> specify the values for mdss node.
>>
>
> Do you need to use both cells in the example? Presumably the second
> cell
> is all zero, so it's useless. The example doesn't have to have both
> cells in the reg property, that can be fixed up when writing the DT for
> a particular SoC.
Sure Stephen. I will make the changes in the next patchset.
Thanks,
Krishna
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2021-03-05 13:31 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-02-12 10:49 [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Krishna Manikandan
2021-02-12 10:49 ` [PATCH v12 2/4] dt-bindings: msm: dsi: add yaml schemas for DSI bindings Krishna Manikandan
2021-02-26 19:48 ` Stephen Boyd
2021-02-12 10:49 ` [PATCH v12 3/4] dt-bindings: msm: dsi: add yaml schemas for DSI PHY bindings Krishna Manikandan
2021-02-26 19:52 ` Stephen Boyd
2021-02-12 10:50 ` [PATCH v12 4/4] dt-bindings: msm/dp: Add bindings of MSM DisplayPort controller Krishna Manikandan
2021-02-26 19:54 ` Stephen Boyd
2021-02-26 19:45 ` [PATCH v12 1/4] dt-bindings: msm: disp: add yaml schemas for DPU bindings Stephen Boyd
2021-03-04 12:36 ` mkrishn
2021-03-05 6:53 ` Stephen Boyd
2021-03-05 13:30 ` mkrishn
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