* [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 22:37 ` Rob Herring
` (2 more replies)
2021-09-23 12:16 ` [PATCH V10 2/8] arm64: dts: sc7280: Add QSPI node Rajesh Patil
` (8 subsequent siblings)
9 siblings, 3 replies; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Rajesh Patil
Add compatible for sc7280 SoC.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Change in V10:
- As per Stephen's comments,
sorted compatible names in alphabet order
Changes in V9:
- No changes
Changes in V8:
- As per Doug's comments, added "qcom,sc7280-qspi" compatible
Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
index ef5698f..09aa955 100644
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
@@ -21,7 +21,10 @@ allOf:
properties:
compatible:
items:
- - const: qcom,sdm845-qspi
+ - enum:
+ - qcom,sc7280-qspi
+ - qcom,sdm845-qspi
+
- const: qcom,qspi-v1
reg:
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-23 12:16 ` [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support Rajesh Patil
@ 2021-09-23 22:37 ` Rob Herring
2021-09-23 22:45 ` Doug Anderson
2021-09-24 1:00 ` Rob Herring
2021-09-24 22:47 ` Bjorn Andersson
2 siblings, 1 reply; 23+ messages in thread
From: Rob Herring @ 2021-09-23 22:37 UTC (permalink / raw)
To: Rajesh Patil
Cc: Rob Herring, linux-arm-msm, Andy Gross, msavaliy,
Bjorn Andersson, rnayak, linux-kernel, devicetree,
saiprakash.ranjan, sboyd, dianders, skakit, mka
On Thu, 23 Sep 2021 17:46:11 +0530, Rajesh Patil wrote:
> Add compatible for sc7280 SoC.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
> Change in V10:
> - As per Stephen's comments,
> sorted compatible names in alphabet order
>
> Changes in V9:
> - No changes
>
> Changes in V8:
> - As per Doug's comments, added "qcom,sc7280-qspi" compatible
>
> Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1531702
spi@88dc000: compatible:0: 'qcom,qspi-v1' is not one of ['qcom,sc7280-qspi', 'qcom,sdm845-qspi']
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dt.yaml
spi@88dc000: compatible: ['qcom,qspi-v1'] is too short
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dt.yaml
spi@88dc000: interconnect-names: ['qspi-config'] is too short
arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dt.yaml
arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dt.yaml
>From nobody Thu Sep 23 17:37:11 2021
From: Rob Herring <robh@kernel.org>
To: Konrad Dybcio <konrad.dybcio@somainline.org>
Cc: Taniya Das <tdas@codeaurora.org>, marijn.suijten@somainline.org, Rob Herring <robh+dt@kernel.org>, Stephen Boyd <sboyd@kernel.org>, martin.botka@somainline.org, Andy Gross <agross@kernel.org>, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, angelogioacchino.delregno@somainline.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, jamipkettunen@somainline.org, Bjorn Andersson <bjorn.andersson@linaro.org>, Michael Turquette <mturquette@baylibre.com>, ~postmarketos/upstreaming@lists.sr.ht
In-Reply-To: <20210923162645.23257-1-konrad.dybcio@somainline.org>
References: <20210923162645.23257-1-konrad.dybcio@somainline.org>
Subject: Re: [PATCH v4 1/9] dt-bindings: clk: qcom: Add bindings for MSM8994 GCC driver
Status: RO
Content-Length: 4225
Lines: 83
On Thu, 23 Sep 2021 18:26:34 +0200, Konrad Dybcio wrote:
> Add documentation for the MSM8994 GCC driver. While at it, retire its
> compatible from the old, everyone-get-in-here file.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org>
> ---
> Changes since v3:
> - Don't document the compatible twice
>
> .../bindings/clock/qcom,gcc-msm8994.yaml | 70 +++++++++++++++++++
> .../devicetree/bindings/clock/qcom,gcc.yaml | 2 -
> 2 files changed, 70 insertions(+), 2 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-msm8994.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1531778
clock-controller@100000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-ganges-kirin.dt.yaml
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-discovery.dt.yaml
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-pioneer.dt.yaml
arch/arm64/boot/dts/qcom/sdm630-sony-xperia-nile-voyager.dt.yaml
arch/arm64/boot/dts/qcom/sdm636-sony-xperia-ganges-mermaid.dt.yaml
arch/arm64/boot/dts/qcom/sdm660-xiaomi-lavender.dt.yaml
clock-controller@1800000: '#power-domain-cells' is a required property
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac-bit.dt.yaml
arch/arm/boot/dts/qcom-ipq4018-ap120c-ac.dt.yaml
arch/arm/boot/dts/qcom-ipq4018-jalapeno.dt.yaml
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1-c1.dt.yaml
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dt.yaml
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dt.yaml
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dt.yaml
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dt.yaml
clock-controller@900000: '#power-domain-cells' is a required property
arch/arm/boot/dts/qcom-apq8060-dragonboard.dt.yaml
arch/arm/boot/dts/qcom-mdm9615-wp8548-mangoh-green.dt.yaml
arch/arm/boot/dts/qcom-msm8660-surf.dt.yaml
arch/arm/boot/dts/qcom-msm8960-cdp.dt.yaml
clock-controller@900000: 'thermal-sensor@900000' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm/boot/dts/qcom-ipq8064-ap148.dt.yaml
arch/arm/boot/dts/qcom-ipq8064-rb3011.dt.yaml
clock-controller@fc400000: 'clock-names' is a required property
arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml
arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dt.yaml
arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dt.yaml
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dt.yaml
clock-controller@fc400000: 'clocks' is a required property
arch/arm64/boot/dts/qcom/apq8094-sony-xperia-kitakami-karin_windy.dt.yaml
arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dt.yaml
arch/arm64/boot/dts/qcom/msm8992-msft-lumia-octagon-talkman.dt.yaml
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-msft-lumia-octagon-cityman.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-ivy.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-karin.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-satsuki.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-sumire.dt.yaml
arch/arm64/boot/dts/qcom/msm8994-sony-xperia-kitakami-suzuran.dt.yaml
gcc@1800000: 'clock-names', 'clocks' do not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
gcc@1800000: '#power-domain-cells' is a required property
arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dt.yaml
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-23 22:37 ` Rob Herring
@ 2021-09-23 22:45 ` Doug Anderson
2021-09-24 0:40 ` Rob Herring
0 siblings, 1 reply; 23+ messages in thread
From: Doug Anderson @ 2021-09-23 22:45 UTC (permalink / raw)
To: Rob Herring
Cc: Rajesh Patil, Rob Herring, linux-arm-msm, Andy Gross, msavaliy,
Bjorn Andersson, Rajendra Nayak, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Sai Prakash Ranjan, Stephen Boyd, satya priya, Matthias Kaehlcke
Hi,
On Thu, Sep 23, 2021 at 3:37 PM Rob Herring <robh@kernel.org> wrote:
>
> On Thu, 23 Sep 2021 17:46:11 +0530, Rajesh Patil wrote:
> > Add compatible for sc7280 SoC.
> >
> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > Reviewed-by: Doug Anderson <dianders@chromium.org>
> > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> > ---
> > Change in V10:
> > - As per Stephen's comments,
> > sorted compatible names in alphabet order
> >
> > Changes in V9:
> > - No changes
> >
> > Changes in V8:
> > - As per Doug's comments, added "qcom,sc7280-qspi" compatible
> >
> > Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5 ++++-
> > 1 file changed, 4 insertions(+), 1 deletion(-)
> >
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1531702
>
>
> spi@88dc000: compatible:0: 'qcom,qspi-v1' is not one of ['qcom,sc7280-qspi', 'qcom,sdm845-qspi']
> arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dt.yaml
>
> spi@88dc000: compatible: ['qcom,qspi-v1'] is too short
> arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
> arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
Right. I mentioned this in earlier review feedback and Rajesh said
he'd do a follow-up patch to add sc7180 to the list here and also add
the proper compatible in the sc7180.dtsi file. That's not a new error
and (IMO) shouldn't block this patch from moving forward, though it
should be nearly trivial to do.
-Doug
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-23 22:45 ` Doug Anderson
@ 2021-09-24 0:40 ` Rob Herring
0 siblings, 0 replies; 23+ messages in thread
From: Rob Herring @ 2021-09-24 0:40 UTC (permalink / raw)
To: Doug Anderson
Cc: Rajesh Patil, linux-arm-msm, Andy Gross, msavaliy,
Bjorn Andersson, Rajendra Nayak, LKML,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Sai Prakash Ranjan, Stephen Boyd, satya priya, Matthias Kaehlcke
On Thu, Sep 23, 2021 at 5:45 PM Doug Anderson <dianders@chromium.org> wrote:
>
> Hi,
>
> On Thu, Sep 23, 2021 at 3:37 PM Rob Herring <robh@kernel.org> wrote:
> >
> > On Thu, 23 Sep 2021 17:46:11 +0530, Rajesh Patil wrote:
> > > Add compatible for sc7280 SoC.
> > >
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > Reviewed-by: Doug Anderson <dianders@chromium.org>
> > > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> > > ---
> > > Change in V10:
> > > - As per Stephen's comments,
> > > sorted compatible names in alphabet order
> > >
> > > Changes in V9:
> > > - No changes
> > >
> > > Changes in V8:
> > > - As per Doug's comments, added "qcom,sc7280-qspi" compatible
> > >
> > > Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5 ++++-
> > > 1 file changed, 4 insertions(+), 1 deletion(-)
> > >
> >
> > Running 'make dtbs_check' with the schema in this patch gives the
> > following warnings. Consider if they are expected or the schema is
> > incorrect. These may not be new warnings.
> >
> > Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> > This will change in the future.
> >
> > Full log is available here: https://patchwork.ozlabs.org/patch/1531702
> >
> >
> > spi@88dc000: compatible:0: 'qcom,qspi-v1' is not one of ['qcom,sc7280-qspi', 'qcom,sdm845-qspi']
> > arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r3-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-limozeen-nots-r4.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r0.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-kb.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r1-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-kb.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor-r3-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r1-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r2-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-pompom-r3-lte.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-r1.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-r1-lte.dt.yaml
> >
> > spi@88dc000: compatible: ['qcom,qspi-v1'] is too short
> > arch/arm64/boot/dts/qcom/sc7180-idp.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1.dt.yaml
> > arch/arm64/boot/dts/qcom/sc7180-trogdor-coachz-r1-lte.dt.yaml
>
> Right. I mentioned this in earlier review feedback and Rajesh said
> he'd do a follow-up patch to add sc7180 to the list here and also add
> the proper compatible in the sc7180.dtsi file. That's not a new error
> and (IMO) shouldn't block this patch from moving forward, though it
> should be nearly trivial to do.
To repeat:
> > Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> > This will change in the future.
But I think it is useful information to make an informed decision
whether the schema is missing something or not, so I'm adding these to
my semi-automated emails.
Rob
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-23 12:16 ` [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support Rajesh Patil
2021-09-23 22:37 ` Rob Herring
@ 2021-09-24 1:00 ` Rob Herring
2021-09-24 22:47 ` Bjorn Andersson
2 siblings, 0 replies; 23+ messages in thread
From: Rob Herring @ 2021-09-24 1:00 UTC (permalink / raw)
To: Rajesh Patil
Cc: devicetree, rnayak, skakit, Bjorn Andersson, linux-arm-msm,
Andy Gross, mka, saiprakash.ranjan, Rob Herring, linux-kernel,
sboyd, msavaliy, dianders
On Thu, 23 Sep 2021 17:46:11 +0530, Rajesh Patil wrote:
> Add compatible for sc7280 SoC.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> ---
> Change in V10:
> - As per Stephen's comments,
> sorted compatible names in alphabet order
>
> Changes in V9:
> - No changes
>
> Changes in V8:
> - As per Doug's comments, added "qcom,sc7280-qspi" compatible
>
> Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-23 12:16 ` [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support Rajesh Patil
2021-09-23 22:37 ` Rob Herring
2021-09-24 1:00 ` Rob Herring
@ 2021-09-24 22:47 ` Bjorn Andersson
2021-09-27 6:47 ` rajpat
2 siblings, 1 reply; 23+ messages in thread
From: Bjorn Andersson @ 2021-09-24 22:47 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Rob Herring, linux-arm-msm, linux-kernel, devicetree,
rnayak, saiprakash.ranjan, msavaliy, skakit, sboyd, mka,
dianders
On Thu 23 Sep 07:16 CDT 2021, Rajesh Patil wrote:
> Add compatible for sc7280 SoC.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> Reviewed-by: Doug Anderson <dianders@chromium.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Can you please pick up Rob's review tag and send this patch out again,
this time including the SPI maintainer (Mark Brown <broonie@kernel.org>)
among the recipients.
Thanks,
Bjorn
> ---
> Change in V10:
> - As per Stephen's comments,
> sorted compatible names in alphabet order
>
> Changes in V9:
> - No changes
>
> Changes in V8:
> - As per Doug's comments, added "qcom,sc7280-qspi" compatible
>
> Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
> index ef5698f..09aa955 100644
> --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
> @@ -21,7 +21,10 @@ allOf:
> properties:
> compatible:
> items:
> - - const: qcom,sdm845-qspi
> + - enum:
> + - qcom,sc7280-qspi
> + - qcom,sdm845-qspi
> +
> - const: qcom,qspi-v1
>
> reg:
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support
2021-09-24 22:47 ` Bjorn Andersson
@ 2021-09-27 6:47 ` rajpat
0 siblings, 0 replies; 23+ messages in thread
From: rajpat @ 2021-09-27 6:47 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Andy Gross, Rob Herring, linux-arm-msm, linux-kernel, devicetree,
rnayak, saiprakash.ranjan, msavaliy, skakit, sboyd, mka,
dianders
On 2021-09-25 04:17, Bjorn Andersson wrote:
> On Thu 23 Sep 07:16 CDT 2021, Rajesh Patil wrote:
>
>> Add compatible for sc7280 SoC.
>>
>> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
>> Reviewed-by: Doug Anderson <dianders@chromium.org>
>> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
>
> Can you please pick up Rob's review tag and send this patch out again,
> this time including the SPI maintainer (Mark Brown
> <broonie@kernel.org>)
> among the recipients.
>
> Thanks,
> Bjorn
Okay.
>
>> ---
>> Change in V10:
>> - As per Stephen's comments,
>> sorted compatible names in alphabet order
>>
>> Changes in V9:
>> - No changes
>>
>> Changes in V8:
>> - As per Doug's comments, added "qcom,sc7280-qspi" compatible
>>
>> Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml | 5
>> ++++-
>> 1 file changed, 4 insertions(+), 1 deletion(-)
>>
>> diff --git
>> a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
>> b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
>> index ef5698f..09aa955 100644
>> --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
>> +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml
>> @@ -21,7 +21,10 @@ allOf:
>> properties:
>> compatible:
>> items:
>> - - const: qcom,sdm845-qspi
>> + - enum:
>> + - qcom,sc7280-qspi
>> + - qcom,sdm845-qspi
>> +
>> - const: qcom,qspi-v1
>>
>> reg:
>> --
>> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a
>> member
>> of Code Aurora Forum, hosted by The Linux Foundation
>>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH V10 2/8] arm64: dts: sc7280: Add QSPI node
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 3/8] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
` (7 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Roja Rani Yarubandi, Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QSPI DT node and qspi_opp_table for SC7280 SoC.
Move qspi_opp_table to / because SPI nodes assume
any child node is a spi device and so we can't put the
table underneath the spi controller.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V10:
- No changes
Changes in V9:
- No changes
Changes in V8:
- As per Doug's comments, Added "qcom,sc7280-qspi" compatible in qspi node
Changes in V6:
- As per Stephen comments, updated commit message regarding qspi_opp_table
moved from /soc to /
Changes in V4:
- As per Stephen's comment updated spi-max-frequency to 37.5MHz, moved
qspi_opp_table from /soc to / (root).
Changes in V3:
- Broken the huge V2 patch into 3 smaller patches.
1. QSPI DT nodes
2. QUP wrapper_0 DT nodes
3. QUP wrapper_1 DT nodes
Changes in V2:
- As per Doug's comments removed pinmux/pinconf subnodes.
- As per Doug's comments split of SPI, UART nodes has been done.
- Moved QSPI node before aps_smmu as per the order.
arch/arm64/boot/dts/qcom/sc7280.dtsi | 61 ++++++++++++++++++++++++++++++++++++
1 file changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index fd78f16..2fbcb0a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -415,6 +415,25 @@
method = "smc";
};
+ qspi_opp_table: qspi-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-150000000 {
+ opp-hz = /bits/ 64 <150000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -1318,6 +1337,23 @@
};
};
+ qspi: spi@88dc000 {
+ compatible = "qcom,sc7280-qspi", "qcom,qspi-v1";
+ reg = <0 0x088dc000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
+ <&gcc GCC_QSPI_CORE_CLK>;
+ clock-names = "iface", "core";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0
+ &cnoc2 SLAVE_QSPI_0 0>;
+ interconnect-names = "qspi-config";
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qspi_opp_table>;
+ status = "disabled";
+ };
+
dc_noc: interconnect@90e0000 {
reg = <0 0x090e0000 0 0x5080>;
compatible = "qcom,sc7280-dc-noc";
@@ -1513,6 +1549,31 @@
gpio-ranges = <&tlmm 0 0 175>;
wakeup-parent = <&pdc>;
+ qspi_clk: qspi-clk {
+ pins = "gpio14";
+ function = "qspi_clk";
+ };
+
+ qspi_cs0: qspi-cs0 {
+ pins = "gpio15";
+ function = "qspi_cs";
+ };
+
+ qspi_cs1: qspi-cs1 {
+ pins = "gpio19";
+ function = "qspi_cs";
+ };
+
+ qspi_data01: qspi-data01 {
+ pins = "gpio12", "gpio13";
+ function = "qspi_data";
+ };
+
+ qspi_data12: qspi-data12 {
+ pins = "gpio16", "gpio17";
+ function = "qspi_data";
+ };
+
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V10 3/8] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 1/8] dt-bindings: spi: Add sc7280 support Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 2/8] arm64: dts: sc7280: Add QSPI node Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
` (6 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Rajesh Patil
Add spi-nor flash node and pinctrl configurations for the SC7280 IDP.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V10:
- No changes
Changes in V9:
- No changes
Changes in V8:
- No changes
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 99f9ee5..37b8444 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -211,6 +211,20 @@
vcc-supply = <&vreg_l1c_1p8>;
};
+&qspi {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <37500000>;
+ spi-tx-bus-width = <2>;
+ spi-rx-bus-width = <2>;
+ };
+};
+
&qupv3_id_0 {
status = "okay";
};
@@ -288,6 +302,19 @@
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
+&qspi_cs0 {
+ bias-disable;
+};
+
+&qspi_clk {
+ bias-disable;
+};
+
+&qspi_data01 {
+ /* High-Z when no transfers; nice to park the lines */
+ bias-pull-up;
+};
+
&qup_uart5_default {
tx {
pins = "gpio46";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V10 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (2 preceding siblings ...)
2021-09-23 12:16 ` [PATCH V10 3/8] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 21:25 ` Stephen Boyd
2021-09-23 12:16 ` [PATCH V10 5/8] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
` (5 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Roja Rani Yarubandi, Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
---
Changes in V10:
- As per Stephen's comments,
Removed "<&qup_spiN_cs_gpio>" in all spi ports
Changes in V9:
- As per Stephen's comments,
1. Moved back qup_opp_table from /soc@0/geniqup@9c0000 to /
2. changed node names to "qup_spi0_cs_gpio: qup-spi0-cs-gpio" beacuse
node names should have dashes instead of underscores.
Changes in V8:
- As per Matthias' comments, Added back qup_spiN_cs_gpio nodes in all spi ports
Changes in V7:
- As per Matthias' comments
Configuring cs pin with gpio (qup_spiN_cs_gpio) definitions are removed.
- As per Stephen's comments
Added qup_opp_table under /soc@0/geniqup@9c0000
Changes in V6:
- As per Matthias' comments,
1. Changed convention "clocks" followed by "clock-names"
2. Moved qup_opp_table from /soc to /
arch/arm64/boot/dts/qcom/sc7280.dtsi | 724 ++++++++++++++++++++++++++++++++++-
1 file changed, 722 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 2fbcb0a..8278fd0 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -434,6 +434,25 @@
};
};
+ qup_opp_table: qup-opp-table {
+ compatible = "operating-points-v2";
+
+ opp-75000000 {
+ opp-hz = /bits/ 64 <75000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-100000000 {
+ opp-hz = /bits/ 64 <100000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-128000000 {
+ opp-hz = /bits/ 64 <128000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+
soc: soc@0 {
#address-cells = <2>;
#size-cells = <2>;
@@ -536,24 +555,425 @@
qupv3_id_0: geniqup@9c0000 {
compatible = "qcom,geni-se-qup";
reg = <0 0x009c0000 0 0x2000>;
- clock-names = "m-ahb", "s-ahb";
clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ iommus = <&apps_smmu 0x123 0x0>;
status = "disabled";
+ i2c0: i2c@980000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi0: spi@980000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart0: serial@980000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00980000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>;
+ interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c1: i2c@984000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi1: spi@984000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart1: serial@984000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00984000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>;
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c2: i2c@988000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi2: spi@988000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart2: serial@988000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00988000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>;
+ interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c3: i2c@98c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi3: spi@98c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart3: serial@98c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0098c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>;
+ interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c4: i2c@990000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi4: spi@990000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart4: serial@990000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00990000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>;
+ interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c5: i2c@994000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00994000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi5: spi@994000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00994000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
uart5: serial@994000 {
compatible = "qcom,geni-debug-uart";
reg = <0 0x00994000 0 0x4000>;
- clock-names = "se";
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
pinctrl-names = "default";
pinctrl-0 = <&qup_uart5_default>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
+
+ i2c6: i2c@998000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi6: spi@998000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart6: serial@998000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00998000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>;
+ interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c7: i2c@99c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>,
+ <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi7: spi@99c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart7: serial@99c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x0099c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>;
+ interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
};
cnoc2: interconnect@1500000 {
@@ -1574,11 +1994,311 @@
function = "qspi_data";
};
+ qup_i2c0_data_clk: qup-i2c0-data-clk {
+ pins = "gpio0", "gpio1";
+ function = "qup00";
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk {
+ pins = "gpio4", "gpio5";
+ function = "qup01";
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk {
+ pins = "gpio8", "gpio9";
+ function = "qup02";
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk {
+ pins = "gpio12", "gpio13";
+ function = "qup03";
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk {
+ pins = "gpio16", "gpio17";
+ function = "qup04";
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk {
+ pins = "gpio20", "gpio21";
+ function = "qup05";
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk {
+ pins = "gpio24", "gpio25";
+ function = "qup06";
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk {
+ pins = "gpio28", "gpio29";
+ function = "qup07";
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk {
+ pins = "gpio0", "gpio1", "gpio2";
+ function = "qup00";
+ };
+
+ qup_spi0_cs: qup-spi0-cs {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_spi0_cs_gpio: qup-spi0-cs-gpio {
+ pins = "gpio3";
+ function = "gpio";
+ };
+
+ qup_spi1_data_clk: qup-spi1-data-clk {
+ pins = "gpio4", "gpio5", "gpio6";
+ function = "qup01";
+ };
+
+ qup_spi1_cs: qup-spi1-cs {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_spi1_cs_gpio: qup-spi1-cs-gpio {
+ pins = "gpio7";
+ function = "gpio";
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk {
+ pins = "gpio8", "gpio9", "gpio10";
+ function = "qup02";
+ };
+
+ qup_spi2_cs: qup-spi2-cs {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_spi2_cs_gpio: qup-spi2-cs-gpio {
+ pins = "gpio11";
+ function = "gpio";
+ };
+
+ qup_spi3_data_clk: qup-spi3-data-clk {
+ pins = "gpio12", "gpio13", "gpio14";
+ function = "qup03";
+ };
+
+ qup_spi3_cs: qup-spi3-cs {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_spi3_cs_gpio: qup-spi3-cs-gpio {
+ pins = "gpio15";
+ function = "gpio";
+ };
+
+ qup_spi4_data_clk: qup-spi4-data-clk {
+ pins = "gpio16", "gpio17", "gpio18";
+ function = "qup04";
+ };
+
+ qup_spi4_cs: qup-spi4-cs {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
+ qup_spi4_cs_gpio: qup-spi4-cs-gpio {
+ pins = "gpio19";
+ function = "gpio";
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk {
+ pins = "gpio20", "gpio21", "gpio22";
+ function = "qup05";
+ };
+
+ qup_spi5_cs: qup-spi5-cs {
+ pins = "gpio23";
+ function = "qup05";
+ };
+
+ qup_spi5_cs_gpio: qup-spi5-cs-gpio {
+ pins = "gpio23";
+ function = "gpio";
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk {
+ pins = "gpio24", "gpio25", "gpio26";
+ function = "qup06";
+ };
+
+ qup_spi6_cs: qup-spi6-cs {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_spi6_cs_gpio: qup-spi6-cs-gpio {
+ pins = "gpio27";
+ function = "gpio";
+ };
+
+ qup_spi7_data_clk: qup-spi7-data-clk {
+ pins = "gpio28", "gpio29", "gpio30";
+ function = "qup07";
+ };
+
+ qup_spi7_cs: qup-spi7-cs {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
+ qup_spi7_cs_gpio: qup-spi7-cs-gpio {
+ pins = "gpio31";
+ function = "gpio";
+ };
+
+ qup_uart0_cts: qup-uart0-cts {
+ pins = "gpio0";
+ function = "qup00";
+ };
+
+ qup_uart0_rts: qup-uart0-rts {
+ pins = "gpio1";
+ function = "qup00";
+ };
+
+ qup_uart0_tx: qup-uart0-tx {
+ pins = "gpio2";
+ function = "qup00";
+ };
+
+ qup_uart0_rx: qup-uart0-rx {
+ pins = "gpio3";
+ function = "qup00";
+ };
+
+ qup_uart1_cts: qup-uart1-cts {
+ pins = "gpio4";
+ function = "qup01";
+ };
+
+ qup_uart1_rts: qup-uart1-rts {
+ pins = "gpio5";
+ function = "qup01";
+ };
+
+ qup_uart1_tx: qup-uart1-tx {
+ pins = "gpio6";
+ function = "qup01";
+ };
+
+ qup_uart1_rx: qup-uart1-rx {
+ pins = "gpio7";
+ function = "qup01";
+ };
+
+ qup_uart2_cts: qup-uart2-cts {
+ pins = "gpio8";
+ function = "qup02";
+ };
+
+ qup_uart2_rts: qup-uart2-rts {
+ pins = "gpio9";
+ function = "qup02";
+ };
+
+ qup_uart2_tx: qup-uart2-tx {
+ pins = "gpio10";
+ function = "qup02";
+ };
+
+ qup_uart2_rx: qup-uart2-rx {
+ pins = "gpio11";
+ function = "qup02";
+ };
+
+ qup_uart3_cts: qup-uart3-cts {
+ pins = "gpio12";
+ function = "qup03";
+ };
+
+ qup_uart3_rts: qup-uart3-rts {
+ pins = "gpio13";
+ function = "qup03";
+ };
+
+ qup_uart3_tx: qup-uart3-tx {
+ pins = "gpio14";
+ function = "qup03";
+ };
+
+ qup_uart3_rx: qup-uart3-rx {
+ pins = "gpio15";
+ function = "qup03";
+ };
+
+ qup_uart4_cts: qup-uart4-cts {
+ pins = "gpio16";
+ function = "qup04";
+ };
+
+ qup_uart4_rts: qup-uart4-rts {
+ pins = "gpio17";
+ function = "qup04";
+ };
+
+ qup_uart4_tx: qup-uart4-tx {
+ pins = "gpio18";
+ function = "qup04";
+ };
+
+ qup_uart4_rx: qup-uart4-rx {
+ pins = "gpio19";
+ function = "qup04";
+ };
+
qup_uart5_default: qup-uart5-default {
pins = "gpio46", "gpio47";
function = "qup13";
};
+ qup_uart6_cts: qup-uart6-cts {
+ pins = "gpio24";
+ function = "qup06";
+ };
+
+ qup_uart6_rts: qup-uart6-rts {
+ pins = "gpio25";
+ function = "qup06";
+ };
+
+ qup_uart6_tx: qup-uart6-tx {
+ pins = "gpio26";
+ function = "qup06";
+ };
+
+ qup_uart6_rx: qup-uart6-rx {
+ pins = "gpio27";
+ function = "qup06";
+ };
+
+ qup_uart7_cts: qup-uart7-cts {
+ pins = "gpio28";
+ function = "qup07";
+ };
+
+ qup_uart7_rts: qup-uart7-rts {
+ pins = "gpio29";
+ function = "qup07";
+ };
+
+ qup_uart7_tx: qup-uart7-tx {
+ pins = "gpio30";
+ function = "qup07";
+ };
+
+ qup_uart7_rx: qup-uart7-rx {
+ pins = "gpio31";
+ function = "qup07";
+ };
+
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V10 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
2021-09-23 12:16 ` [PATCH V10 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
@ 2021-09-23 21:25 ` Stephen Boyd
0 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2021-09-23 21:25 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rajesh Patil, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, mka, dianders,
Roja Rani Yarubandi
Quoting Rajesh Patil (2021-09-23 05:16:14)
> From: Roja Rani Yarubandi <rojay@codeaurora.org>
>
> Add QUPv3 wrapper_0 DT nodes for SC7280 SoC.
>
> Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
> ---
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH V10 5/8] arm64: dts: sc7280: Update QUPv3 UART5 DT node
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (3 preceding siblings ...)
2021-09-23 12:16 ` [PATCH V10 4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 6/8] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
` (4 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Roja Rani Yarubandi, Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Uart5 is treated as dedicated debug uart.Change the
compatible as "qcom,geni-uart" in SoC DT to make it generic
and later update it as "qcom,geni-debug-uart" in sc7280-idp
Add interconnects and power-domains. Split the pinctrl
functions and correct the gpio pins.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V10:
- No changes
Changes in V9:
- No changes
Changes in V8:
- No changes
Changes in V7:
- As per Matthias comments,
update commit message regarding UART5 functionality
Changes in V6:
- As per Matthias' comments,
Squashed "Update QUPv3 UART5 DT node" and "Configure debug uart for sc7280-idp"
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 19 ++++++++-----------
arch/arm64/boot/dts/qcom/sc7280.dtsi | 30 +++++++++++++++++++++++++-----
2 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 37b8444..cf82301 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -258,6 +258,7 @@
};
&uart5 {
+ compatible = "qcom,geni-debug-uart";
status = "okay";
};
@@ -315,18 +316,14 @@
bias-pull-up;
};
-&qup_uart5_default {
- tx {
- pins = "gpio46";
- drive-strength = <2>;
- bias-disable;
- };
+&qup_uart5_tx {
+ drive-strength = <2>;
+ bias-disable;
+};
- rx {
- pins = "gpio47";
- drive-strength = <2>;
- bias-pull-up;
- };
+&qup_uart5_rx {
+ drive-strength = <2>;
+ bias-pull-up;
};
&sdc1_on {
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 8278fd0..3254de65 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -861,13 +861,18 @@
};
uart5: serial@994000 {
- compatible = "qcom,geni-debug-uart";
+ compatible = "qcom,geni-uart";
reg = <0 0x00994000 0 0x4000>;
clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
clock-names = "se";
pinctrl-names = "default";
- pinctrl-0 = <&qup_uart5_default>;
+ pinctrl-0 = <&qup_uart5_cts>, <&qup_uart5_rts>, <&qup_uart5_tx>, <&qup_uart5_rx>;
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core", "qup-config";
status = "disabled";
};
@@ -2254,9 +2259,24 @@
function = "qup04";
};
- qup_uart5_default: qup-uart5-default {
- pins = "gpio46", "gpio47";
- function = "qup13";
+ qup_uart5_cts: qup-uart5-cts {
+ pins = "gpio20";
+ function = "qup05";
+ };
+
+ qup_uart5_rts: qup-uart5-rts {
+ pins = "gpio21";
+ function = "qup05";
+ };
+
+ qup_uart5_tx: qup-uart5-tx {
+ pins = "gpio22";
+ function = "qup05";
+ };
+
+ qup_uart5_rx: qup-uart5-rx {
+ pins = "gpio23";
+ function = "qup05";
};
qup_uart6_cts: qup-uart6-cts {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V10 6/8] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (4 preceding siblings ...)
2021-09-23 12:16 ` [PATCH V10 5/8] arm64: dts: sc7280: Update QUPv3 UART5 DT node Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 7/8] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
` (3 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Rajesh Patil
Add bluetooth uart pin configuration for sc7280-idp.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V10:
- No changes
Changes in V9:
- No changes
Change in V8:
- No changes
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 85 ++++++++++++++++++++++++++++++++
1 file changed, 85 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index cf82301..52638e2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -301,6 +301,16 @@
vdda18-supply = <&vreg_l1c_1p8>;
};
+&uart7 {
+ status = "okay";
+
+ /delete-property/interrupts;
+ interrupts-extended = <&intc GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>,
+ <&tlmm 31 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-names = "default", "sleep";
+ pinctrl-1 = <&qup_uart7_sleep_cts>, <&qup_uart7_sleep_rts>, <&qup_uart7_sleep_tx>, <&qup_uart7_sleep_rx>;
+};
+
/* PINCTRL - additions to nodes defined in sc7280.dtsi */
&qspi_cs0 {
@@ -326,6 +336,81 @@
bias-pull-up;
};
+&qup_uart7_cts {
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+};
+
+&qup_uart7_rts {
+ /* We'll drive RTS, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_tx {
+ /* We'll drive TX, so no pull */
+ drive-strength = <2>;
+ bias-disable;
+};
+
+&qup_uart7_rx {
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module is
+ * in tri-state (module powered off or not driving the
+ * signal yet).
+ */
+ bias-pull-up;
+};
+
+&tlmm {
+ qup_uart7_sleep_cts: qup-uart7-sleep-cts {
+ pins = "gpio28";
+ function = "gpio";
+ /*
+ * Configure a pull-down on CTS to match the pull of
+ * the Bluetooth module.
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_rts: qup-uart7-sleep-rts {
+ pins = "gpio29";
+ function = "gpio";
+ /*
+ * Configure pull-down on RTS. As RTS is active low
+ * signal, pull it low to indicate the BT SoC that it
+ * can wakeup the system anytime from suspend state by
+ * pulling RX low (by sending wakeup bytes).
+ */
+ bias-pull-down;
+ };
+
+ qup_uart7_sleep_tx: qup-uart7-sleep-tx {
+ pins = "gpio30";
+ function = "gpio";
+ /*
+ * Configure pull-up on TX when it isn't actively driven
+ * to prevent BT SoC from receiving garbage during sleep.
+ */
+ bias-pull-up;
+ };
+
+ qup_uart7_sleep_rx: qup-uart7-sleep-rx {
+ pins = "gpio31";
+ function = "gpio";
+ /*
+ * Configure a pull-up on RX. This is needed to avoid
+ * garbage data when the TX pin of the Bluetooth module
+ * is floating which may cause spurious wakeups.
+ */
+ bias-pull-up;
+ };
+};
+
&sdc1_on {
clk {
bias-disable;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V10 7/8] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (5 preceding siblings ...)
2021-09-23 12:16 ` [PATCH V10 6/8] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-09-23 12:16 ` [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI Rajesh Patil
` (2 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Roja Rani Yarubandi, Rajesh Patil
From: Roja Rani Yarubandi <rojay@codeaurora.org>
Add QUPv3 wrapper_1 DT nodes for SC7280 SoC.
Signed-off-by: Roja Rani Yarubandi <rojay@codeaurora.org>
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Changes in V10:
- As per Stephen's comments,Removed "<&qup_spiN_cs_gpio>" in spi all ports
- Added "status=okay" in qupv3_id_1 for sc7280-idp board file because EC and TPM
are using "qupv3_id_1" node.
Changes in V9:
- As per Stephen's comments,
changed node names to "qup_spi8_cs_gpio: qup-spi8-cs-gpio" because
node names should have dashes instead of underscores.
Changes in V8:
- No changes
Changes in V7:
- As per Stephen's comments, Removed "status=okay" in qupv3_id_1 for sc7280-idp board file
Changes in V5:
- As per Matthias' comments, Add QUPv3 wrapper_1 nodes
arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 4 +
arch/arm64/boot/dts/qcom/sc7280.dtsi | 749 +++++++++++++++++++++++++++++++
2 files changed, 753 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
index 52638e2..f2dc9f2 100644
--- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi
@@ -229,6 +229,10 @@
status = "okay";
};
+&qupv3_id_1 {
+ status = "okay";
+};
+
&sdhc_1 {
status = "okay";
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index 3254de65..c26647a 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -981,6 +981,435 @@
};
};
+ qupv3_id_1: geniqup@ac0000 {
+ compatible = "qcom,geni-se-qup";
+ reg = <0 0x00ac0000 0 0x2000>;
+ clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
+ <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
+ clock-names = "m-ahb", "s-ahb";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ iommus = <&apps_smmu 0x43 0x0>;
+ status = "disabled";
+
+ i2c8: i2c@a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi8: spi@a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart8: serial@a80000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a80000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>;
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c9: i2c@a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi9: spi@a84000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart9: serial@a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a84000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>;
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c10: i2c@a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c10_data_clk>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi10: spi@a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart10: serial@a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a88000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>;
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c11: i2c@a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c11_data_clk>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi11: spi@a8c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart11: serial@a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a8c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c12: i2c@a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c12_data_clk>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi12: spi@a90000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart12: serial@a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a90000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>;
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c13: i2c@a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c13_data_clk>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi13: spi@a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart13: serial@a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a94000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c14: i2c@a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c14_data_clk>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi14: spi@a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart14: serial@a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a98000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>;
+ interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ i2c15: i2c@a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_i2c15_data_clk>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>,
+ <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "qup-core", "qup-config",
+ "qup-memory";
+ status = "disabled";
+ };
+
+ spi15: spi@a9c000 {
+ compatible = "qcom,geni-spi";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+
+ uart15: serial@a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0 0x00a9c000 0 0x4000>;
+ clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>;
+ clock-names = "se";
+ pinctrl-names = "default";
+ pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>;
+ interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&rpmhpd SC7280_CX>;
+ operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core", "qup-config";
+ status = "disabled";
+ };
+ };
+
cnoc2: interconnect@1500000 {
reg = <0 0x01500000 0 0x1000>;
compatible = "qcom,sc7280-cnoc2";
@@ -2039,6 +2468,46 @@
function = "qup07";
};
+ qup_i2c8_data_clk: qup-i2c8-data-clk {
+ pins = "gpio32", "gpio33";
+ function = "qup10";
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk {
+ pins = "gpio36", "gpio37";
+ function = "qup11";
+ };
+
+ qup_i2c10_data_clk: qup-i2c10-data-clk {
+ pins = "gpio40", "gpio41";
+ function = "qup12";
+ };
+
+ qup_i2c11_data_clk: qup-i2c11-data-clk {
+ pins = "gpio44", "gpio45";
+ function = "qup13";
+ };
+
+ qup_i2c12_data_clk: qup-i2c12-data-clk {
+ pins = "gpio48", "gpio49";
+ function = "qup14";
+ };
+
+ qup_i2c13_data_clk: qup-i2c13-data-clk {
+ pins = "gpio52", "gpio53";
+ function = "qup15";
+ };
+
+ qup_i2c14_data_clk: qup-i2c14-data-clk {
+ pins = "gpio56", "gpio57";
+ function = "qup16";
+ };
+
+ qup_i2c15_data_clk: qup-i2c15-data-clk {
+ pins = "gpio60", "gpio61";
+ function = "qup17";
+ };
+
qup_spi0_data_clk: qup-spi0-data-clk {
pins = "gpio0", "gpio1", "gpio2";
function = "qup00";
@@ -2159,6 +2628,126 @@
function = "gpio";
};
+ qup_spi8_data_clk: qup-spi8-data-clk {
+ pins = "gpio32", "gpio33", "gpio34";
+ function = "qup10";
+ };
+
+ qup_spi8_cs: qup-spi8-cs {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_spi8_cs_gpio: qup-spi8-cs-gpio {
+ pins = "gpio35";
+ function = "gpio";
+ };
+
+ qup_spi9_data_clk: qup-spi9-data-clk {
+ pins = "gpio36", "gpio37", "gpio38";
+ function = "qup11";
+ };
+
+ qup_spi9_cs: qup-spi9-cs {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_spi9_cs_gpio: qup-spi9-cs-gpio {
+ pins = "gpio39";
+ function = "gpio";
+ };
+
+ qup_spi10_data_clk: qup-spi10-data-clk {
+ pins = "gpio40", "gpio41", "gpio42";
+ function = "qup12";
+ };
+
+ qup_spi10_cs: qup-spi10-cs {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_spi10_cs_gpio: qup-spi10-cs-gpio {
+ pins = "gpio43";
+ function = "gpio";
+ };
+
+ qup_spi11_data_clk: qup-spi11-data-clk {
+ pins = "gpio44", "gpio45", "gpio46";
+ function = "qup13";
+ };
+
+ qup_spi11_cs: qup-spi11-cs {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_spi11_cs_gpio: qup-spi11-cs-gpio {
+ pins = "gpio47";
+ function = "gpio";
+ };
+
+ qup_spi12_data_clk: qup-spi12-data-clk {
+ pins = "gpio48", "gpio49", "gpio50";
+ function = "qup14";
+ };
+
+ qup_spi12_cs: qup-spi12-cs {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_spi12_cs_gpio: qup-spi12-cs-gpio {
+ pins = "gpio51";
+ function = "gpio";
+ };
+
+ qup_spi13_data_clk: qup-spi13-data-clk {
+ pins = "gpio52", "gpio53", "gpio54";
+ function = "qup15";
+ };
+
+ qup_spi13_cs: qup-spi13-cs {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_spi13_cs_gpio: qup-spi13-cs-gpio {
+ pins = "gpio55";
+ function = "gpio";
+ };
+
+ qup_spi14_data_clk: qup-spi14-data-clk {
+ pins = "gpio56", "gpio57", "gpio58";
+ function = "qup16";
+ };
+
+ qup_spi14_cs: qup-spi14-cs {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_spi14_cs_gpio: qup-spi14-cs-gpio {
+ pins = "gpio59";
+ function = "gpio";
+ };
+
+ qup_spi15_data_clk: qup-spi15-data-clk {
+ pins = "gpio60", "gpio61", "gpio62";
+ function = "qup17";
+ };
+
+ qup_spi15_cs: qup-spi15-cs {
+ pins = "gpio63";
+ function = "qup17";
+ };
+
+ qup_spi15_cs_gpio: qup-spi15-cs-gpio {
+ pins = "gpio63";
+ function = "gpio";
+ };
+
qup_uart0_cts: qup-uart0-cts {
pins = "gpio0";
function = "qup00";
@@ -2399,6 +2988,166 @@
bias-bus-hold;
};
};
+
+ qup_uart8_cts: qup-uart8-cts {
+ pins = "gpio32";
+ function = "qup10";
+ };
+
+ qup_uart8_rts: qup-uart8-rts {
+ pins = "gpio33";
+ function = "qup10";
+ };
+
+ qup_uart8_tx: qup-uart8-tx {
+ pins = "gpio34";
+ function = "qup10";
+ };
+
+ qup_uart8_rx: qup-uart8-rx {
+ pins = "gpio35";
+ function = "qup10";
+ };
+
+ qup_uart9_cts: qup-uart9-cts {
+ pins = "gpio36";
+ function = "qup11";
+ };
+
+ qup_uart9_rts: qup-uart9-rts {
+ pins = "gpio37";
+ function = "qup11";
+ };
+
+ qup_uart9_tx: qup-uart9-tx {
+ pins = "gpio38";
+ function = "qup11";
+ };
+
+ qup_uart9_rx: qup-uart9-rx {
+ pins = "gpio39";
+ function = "qup11";
+ };
+
+ qup_uart10_cts: qup-uart10-cts {
+ pins = "gpio40";
+ function = "qup12";
+ };
+
+ qup_uart10_rts: qup-uart10-rts {
+ pins = "gpio41";
+ function = "qup12";
+ };
+
+ qup_uart10_tx: qup-uart10-tx {
+ pins = "gpio42";
+ function = "qup12";
+ };
+
+ qup_uart10_rx: qup-uart10-rx {
+ pins = "gpio43";
+ function = "qup12";
+ };
+
+ qup_uart11_cts: qup-uart11-cts {
+ pins = "gpio44";
+ function = "qup13";
+ };
+
+ qup_uart11_rts: qup-uart11-rts {
+ pins = "gpio45";
+ function = "qup13";
+ };
+
+ qup_uart11_tx: qup-uart11-tx {
+ pins = "gpio46";
+ function = "qup13";
+ };
+
+ qup_uart11_rx: qup-uart11-rx {
+ pins = "gpio47";
+ function = "qup13";
+ };
+
+ qup_uart12_cts: qup-uart12-cts {
+ pins = "gpio48";
+ function = "qup14";
+ };
+
+ qup_uart12_rts: qup-uart12-rts {
+ pins = "gpio49";
+ function = "qup14";
+ };
+
+ qup_uart12_tx: qup-uart12-tx {
+ pins = "gpio50";
+ function = "qup14";
+ };
+
+ qup_uart12_rx: qup-uart12-rx {
+ pins = "gpio51";
+ function = "qup14";
+ };
+
+ qup_uart13_cts: qup-uart13-cts {
+ pins = "gpio52";
+ function = "qup15";
+ };
+
+ qup_uart13_rts: qup-uart13-rts {
+ pins = "gpio53";
+ function = "qup15";
+ };
+
+ qup_uart13_tx: qup-uart13-tx {
+ pins = "gpio54";
+ function = "qup15";
+ };
+
+ qup_uart13_rx: qup-uart13-rx {
+ pins = "gpio55";
+ function = "qup15";
+ };
+
+ qup_uart14_cts: qup-uart14-cts {
+ pins = "gpio56";
+ function = "qup16";
+ };
+
+ qup_uart14_rts: qup-uart14-rts {
+ pins = "gpio57";
+ function = "qup16";
+ };
+
+ qup_uart14_tx: qup-uart14-tx {
+ pins = "gpio58";
+ function = "qup16";
+ };
+
+ qup_uart14_rx: qup-uart14-rx {
+ pins = "gpio59";
+ function = "qup16";
+ };
+
+ qup_uart15_cts: qup-uart15-cts {
+ pins = "gpio60";
+ function = "qup17";
+ };
+
+ qup_uart15_rts: qup-uart15-rts {
+ pins = "gpio61";
+ function = "qup17";
+ };
+
+ qup_uart15_tx: qup-uart15-tx {
+ pins = "gpio62";
+ function = "qup17";
+ };
+
+ qup_uart15_rx: qup-uart15-rx {
+ pins = "gpio63";
+ function = "qup17";
+ };
};
apps_smmu: iommu@15000000 {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (6 preceding siblings ...)
2021-09-23 12:16 ` [PATCH V10 7/8] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes Rajesh Patil
@ 2021-09-23 12:16 ` Rajesh Patil
2021-10-19 20:43 ` Arnd Bergmann
2021-09-23 21:27 ` [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Stephen Boyd
2021-09-24 22:44 ` Bjorn Andersson
9 siblings, 1 reply; 23+ messages in thread
From: Rajesh Patil @ 2021-09-23 12:16 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, sboyd, mka, dianders,
Rajesh Patil
Add aliases for i2c and spi for sc7280 soc.
Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
Change in V10:
- No changes
Changes in V9:
- No changes
Changes in V8:
- No changes
Changes in V7:
- As per Stephen's comments, Sorted alias names for i2c and spi as per alphabet order
Changes in V6:
- As per Doug's comments, added aliases for i2c and spi
arch/arm64/boot/dts/qcom/sc7280.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
index c26647a..e5fefd1 100644
--- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
@@ -26,8 +26,40 @@
chosen { };
aliases {
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c6;
+ i2c7 = &i2c7;
+ i2c8 = &i2c8;
+ i2c9 = &i2c9;
+ i2c10 = &i2c10;
+ i2c11 = &i2c11;
+ i2c12 = &i2c12;
+ i2c13 = &i2c13;
+ i2c14 = &i2c14;
+ i2c15 = &i2c15;
mmc1 = &sdhc_1;
mmc2 = &sdhc_2;
+ spi0 = &spi0;
+ spi1 = &spi1;
+ spi2 = &spi2;
+ spi3 = &spi3;
+ spi4 = &spi4;
+ spi5 = &spi5;
+ spi6 = &spi6;
+ spi7 = &spi7;
+ spi8 = &spi8;
+ spi9 = &spi9;
+ spi10 = &spi10;
+ spi11 = &spi11;
+ spi12 = &spi12;
+ spi13 = &spi13;
+ spi14 = &spi14;
+ spi15 = &spi15;
};
clocks {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
2021-09-23 12:16 ` [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI Rajesh Patil
@ 2021-10-19 20:43 ` Arnd Bergmann
2021-10-19 20:59 ` Bjorn Andersson
0 siblings, 1 reply; 23+ messages in thread
From: Arnd Bergmann @ 2021-10-19 20:43 UTC (permalink / raw)
To: Rajesh Patil
Cc: Andy Gross, Bjorn Andersson, Rob Herring, linux-arm-msm,
Linux Kernel Mailing List, DTML, Rajendra Nayak,
Sai Prakash Ranjan, msavaliy, satya priya, Stephen Boyd,
Matthias Kaehlcke, Doug Anderson
On Thu, Sep 23, 2021 at 2:18 PM Rajesh Patil <rajpat@codeaurora.org> wrote:
>
> Add aliases for i2c and spi for sc7280 soc.
>
> Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
I saw this in the pull request, can this please be reverted?
Putting the aliases into the .dtsi file is really silly, as there are
likely boards that
don't connect every single one of those, and then will have to
override and renumber
them.
Please only list the aliases that are actually connected on a particular
board.
Arnd
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index c26647a..e5fefd1 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -26,8 +26,40 @@
> chosen { };
>
> aliases {
> + i2c0 = &i2c0;
> + i2c1 = &i2c1;
> + i2c2 = &i2c2;
> + i2c3 = &i2c3;
> + i2c4 = &i2c4;
> + i2c5 = &i2c5;
> + i2c6 = &i2c6;
> + i2c7 = &i2c7;
> + i2c8 = &i2c8;
> + i2c9 = &i2c9;
> + i2c10 = &i2c10;
> + i2c11 = &i2c11;
> + i2c12 = &i2c12;
> + i2c13 = &i2c13;
> + i2c14 = &i2c14;
> + i2c15 = &i2c15;
> mmc1 = &sdhc_1;
> mmc2 = &sdhc_2;
The mmc ones should probably go away as well.
> + spi0 = &spi0;
> + spi1 = &spi1;
> + spi2 = &spi2;
> + spi3 = &spi3;
> + spi4 = &spi4;
> + spi5 = &spi5;
> + spi6 = &spi6;
> + spi7 = &spi7;
> + spi8 = &spi8;
> + spi9 = &spi9;
> + spi10 = &spi10;
> + spi11 = &spi11;
> + spi12 = &spi12;
> + spi13 = &spi13;
> + spi14 = &spi14;
> + spi15 = &spi15;
> };
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
2021-10-19 20:43 ` Arnd Bergmann
@ 2021-10-19 20:59 ` Bjorn Andersson
2021-10-19 21:11 ` Doug Anderson
0 siblings, 1 reply; 23+ messages in thread
From: Bjorn Andersson @ 2021-10-19 20:59 UTC (permalink / raw)
To: Arnd Bergmann, Rajesh Patil
Cc: Andy Gross, Rob Herring, linux-arm-msm,
Linux Kernel Mailing List, DTML, Rajendra Nayak,
Sai Prakash Ranjan, msavaliy, satya priya, Stephen Boyd,
Matthias Kaehlcke, Doug Anderson
On Tue 19 Oct 13:43 PDT 2021, Arnd Bergmann wrote:
> On Thu, Sep 23, 2021 at 2:18 PM Rajesh Patil <rajpat@codeaurora.org> wrote:
> >
> > Add aliases for i2c and spi for sc7280 soc.
> >
> > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
>
> I saw this in the pull request, can this please be reverted?
>
Yes, this can certainly be corrected.
> Putting the aliases into the .dtsi file is really silly, as there are
> likely boards that
> don't connect every single one of those, and then will have to
> override and renumber
> them.
>
> Please only list the aliases that are actually connected on a particular
> board.
>
> Arnd
>
> > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > index c26647a..e5fefd1 100644
> > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> > @@ -26,8 +26,40 @@
> > chosen { };
> >
> > aliases {
> > + i2c0 = &i2c0;
> > + i2c1 = &i2c1;
> > + i2c2 = &i2c2;
> > + i2c3 = &i2c3;
> > + i2c4 = &i2c4;
> > + i2c5 = &i2c5;
> > + i2c6 = &i2c6;
> > + i2c7 = &i2c7;
> > + i2c8 = &i2c8;
> > + i2c9 = &i2c9;
> > + i2c10 = &i2c10;
> > + i2c11 = &i2c11;
> > + i2c12 = &i2c12;
> > + i2c13 = &i2c13;
> > + i2c14 = &i2c14;
> > + i2c15 = &i2c15;
> > mmc1 = &sdhc_1;
> > mmc2 = &sdhc_2;
>
> The mmc ones should probably go away as well.
>
I should have paid more attention when applying this patch, because the
commit message should have stated why any of these were introduced.
@Rajesh, can you please help me understand the need for any of these and
prepare a patch that introduce the specific ones needed in the
individual board dts(i) files - with reasoning for the aliases in the
commit message.
Thanks,
Bjorn
> > + spi0 = &spi0;
> > + spi1 = &spi1;
> > + spi2 = &spi2;
> > + spi3 = &spi3;
> > + spi4 = &spi4;
> > + spi5 = &spi5;
> > + spi6 = &spi6;
> > + spi7 = &spi7;
> > + spi8 = &spi8;
> > + spi9 = &spi9;
> > + spi10 = &spi10;
> > + spi11 = &spi11;
> > + spi12 = &spi12;
> > + spi13 = &spi13;
> > + spi14 = &spi14;
> > + spi15 = &spi15;
> > };
> >
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
2021-10-19 20:59 ` Bjorn Andersson
@ 2021-10-19 21:11 ` Doug Anderson
2021-10-19 21:27 ` Arnd Bergmann
0 siblings, 1 reply; 23+ messages in thread
From: Doug Anderson @ 2021-10-19 21:11 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Arnd Bergmann, Rajesh Patil, Andy Gross, Rob Herring,
linux-arm-msm, Linux Kernel Mailing List, DTML, Rajendra Nayak,
Sai Prakash Ranjan, msavaliy, satya priya, Stephen Boyd,
Matthias Kaehlcke
Hi,
On Tue, Oct 19, 2021 at 1:57 PM Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
>
> On Tue 19 Oct 13:43 PDT 2021, Arnd Bergmann wrote:
>
> > On Thu, Sep 23, 2021 at 2:18 PM Rajesh Patil <rajpat@codeaurora.org> wrote:
> > >
> > > Add aliases for i2c and spi for sc7280 soc.
> > >
> > > Signed-off-by: Rajesh Patil <rajpat@codeaurora.org>
> > > Reviewed-by: Stephen Boyd <swboyd@chromium.org>
> >
> > I saw this in the pull request, can this please be reverted?
> >
>
> Yes, this can certainly be corrected.
>
> > Putting the aliases into the .dtsi file is really silly, as there are
> > likely boards that
> > don't connect every single one of those, and then will have to
> > override and renumber
> > them.
> >
> > Please only list the aliases that are actually connected on a particular
> > board.
Hrm. I know this gets into slightly controversial topics, but I'm a
little curious what the downside of having these in the dtsi is. In
the case where these i2c/spi/mmc devices _don't_ have "well defined"
numbers in the hardware manual of the SoC then I can agree that it
doesn't make sense to list these in the dtsi file. However, in the
case of sc7280 these numbers are well defined at the SoC level for i2c
and SPI.
Said another way: if you have a board that's got peripherals connected
on the pins labelled "i2c2" and "i2c6" on the SoC then it's a really
nice thing if these show up on /dev/i2c-2 and /dev/i2c-6.
...so I'm not sure what board exactly would be overriding and
re-numbering? Unless a board really has a strong use case where they
need the device connected to the pins for "i2c2" to show up on
"/dev/i2c-0"?
-Doug
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
2021-10-19 21:11 ` Doug Anderson
@ 2021-10-19 21:27 ` Arnd Bergmann
2021-10-19 22:03 ` Doug Anderson
0 siblings, 1 reply; 23+ messages in thread
From: Arnd Bergmann @ 2021-10-19 21:27 UTC (permalink / raw)
To: Doug Anderson
Cc: Bjorn Andersson, Rajesh Patil, Andy Gross, Rob Herring,
linux-arm-msm, Linux Kernel Mailing List, DTML, Rajendra Nayak,
Sai Prakash Ranjan, msavaliy, satya priya, Stephen Boyd,
Matthias Kaehlcke
On Tue, Oct 19, 2021 at 11:11 PM Doug Anderson <dianders@chromium.org> wrote:
> On Tue, Oct 19, 2021 at 1:57 PM Bjorn Andersson
>
> Hrm. I know this gets into slightly controversial topics, but I'm a
> little curious what the downside of having these in the dtsi is. In
> the case where these i2c/spi/mmc devices _don't_ have "well defined"
> numbers in the hardware manual of the SoC then I can agree that it
> doesn't make sense to list these in the dtsi file. However, in the
> case of sc7280 these numbers are well defined at the SoC level for i2c
> and SPI.
>
> Said another way: if you have a board that's got peripherals connected
> on the pins labelled "i2c2" and "i2c6" on the SoC then it's a really
> nice thing if these show up on /dev/i2c-2 and /dev/i2c-6.
>
> ...so I'm not sure what board exactly would be overriding and
> re-numbering? Unless a board really has a strong use case where they
> need the device connected to the pins for "i2c2" to show up on
> "/dev/i2c-0"?
There are multiple things going on here:
- The aliases are traditionally managed by the bootloader, same way
as the /chosen nodes including the kernel command line, so the
numbers are local policy, and the per-board defaults are just
for convenience.
- IMHO there should not be any aliases for status="disabled"
nodes, and the status is usually set in the board files.
- The labels on the board don't always match what the SoC calls
them, or there might not be any labels at all. This is more
important for things like serial ports that are often bare
connectors rather than already wired up. The aliases should
normally match how the board numbers the connectors, not
how they are attached internally.
- For i2c, it's not uncommon to have i2c devices attached behind
expanders on i2c/spi/gpio/usb/pci devices
Arnd
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
2021-10-19 21:27 ` Arnd Bergmann
@ 2021-10-19 22:03 ` Doug Anderson
0 siblings, 0 replies; 23+ messages in thread
From: Doug Anderson @ 2021-10-19 22:03 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Bjorn Andersson, Rajesh Patil, Andy Gross, Rob Herring,
linux-arm-msm, Linux Kernel Mailing List, DTML, Rajendra Nayak,
Sai Prakash Ranjan, msavaliy, satya priya, Stephen Boyd,
Matthias Kaehlcke
Hi,
On Tue, Oct 19, 2021 at 2:27 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> On Tue, Oct 19, 2021 at 11:11 PM Doug Anderson <dianders@chromium.org> wrote:
> > On Tue, Oct 19, 2021 at 1:57 PM Bjorn Andersson
> >
> > Hrm. I know this gets into slightly controversial topics, but I'm a
> > little curious what the downside of having these in the dtsi is. In
> > the case where these i2c/spi/mmc devices _don't_ have "well defined"
> > numbers in the hardware manual of the SoC then I can agree that it
> > doesn't make sense to list these in the dtsi file. However, in the
> > case of sc7280 these numbers are well defined at the SoC level for i2c
> > and SPI.
> >
> > Said another way: if you have a board that's got peripherals connected
> > on the pins labelled "i2c2" and "i2c6" on the SoC then it's a really
> > nice thing if these show up on /dev/i2c-2 and /dev/i2c-6.
> >
> > ...so I'm not sure what board exactly would be overriding and
> > re-numbering? Unless a board really has a strong use case where they
> > need the device connected to the pins for "i2c2" to show up on
> > "/dev/i2c-0"?
>
> There are multiple things going on here:
>
> - The aliases are traditionally managed by the bootloader, same way
> as the /chosen nodes including the kernel command line, so the
> numbers are local policy, and the per-board defaults are just
> for convenience.
The bootloader creates aliases? I've never seen this for I2C or SPI or
MMC, but I will admit I've been off in Chrome OS land for a really
long time and coreboot/depthcharge don't do this. I guess I could
believe that u-boot or some other bootloader does? Do you happen to
have a pointer to code that does this?
> - IMHO there should not be any aliases for status="disabled"
> nodes, and the status is usually set in the board files.
...but there is no harm in having an alias for status="disabled",
right? Below I have a use case where it's helpful to have aliases even
for status="disabled", and if it doesn't hurt...
> - The labels on the board don't always match what the SoC calls
> them, or there might not be any labels at all.
Are you saying that someone would draw up schematics and write on the
schematics "i2c0" and then connect it up to the pins on the SoC
labeled "i2c2"? I mean, I guess they could. I would really not like
working with the EE who did that, but people can do all sorts of crazy
things.
...or maybe you're saying that someone would take these I2C and SPI
pins and expose them to the end user with a little label over them
that said "i2c-0", "i2c-1", and "i2c-2"? ...and that end user would be
confused because the "/dev/i2c" and "/dev/spi" numbers wouldn't match?
I guess I could see that being a problem, though it feels unlikely to
come up in many cases except maybe in dev boards? This is also a new
SoC not designed onto any existing boards, so I'm not convinced that
someone would actually go and do this...
> This is more
> important for things like serial ports that are often bare
> connectors rather than already wired up. The aliases should
> normally match how the board numbers the connectors, not
> how they are attached internally.
So for UARTs I agree with you and that's one reason why this patch
doesn't include serial aliases. There seems to be a lot of history
around UART and requirements built into userspace / other places that
require UARTs be numbered starting at 0. Also UARTs _are_ historically
exposed to end users and they want sane numbers. Luckily this doesn't
cause _too_ much confusion since usually there is only one or two
UARTs in use and mostly they just hook up to console and bluetooth.
I think of UARTs as really the exception here, not the norm.
> - For i2c, it's not uncommon to have i2c devices attached behind
> expanders on i2c/spi/gpio/usb/pci devices
If there are extra i2c devices, that's OK. The i2c subsystem handles
will pick a number that's above the highest defined alias.
...and, in my mind, that actually gives a really good reason for
including all the aliases, even for status="disabled" nodes. Here's an
example output of `i2cdetect -l` on a sc7180-based device which has
aliases for all i2c adapters:
# i2cdetect -l
i2c-13 i2c dpu_dp_aux I2C adapter
i2c-4 i2c Geni-I2C I2C adapter
i2c-2 i2c Geni-I2C I2C adapter
i2c-9 i2c Geni-I2C I2C adapter
i2c-7 i2c Geni-I2C I2C adapter
i2c-14 i2c ti-sn65dsi86-aux I2C adapter
i2c-12 i2c cros-ec-i2c-tunnel I2C adapter
You can see that we've got peripherals hooked up to i2c ports 2, 4, 7, and 9.
On the sc7180 SoC, there are 12 i2c ports built-in to the SoC with
well-defined numbers. These are i2c-0 through i2c-11. On this system,
there are 3 additional extra i2c adapters. You can see that the i2c
subsystem starts numbering the extra adapters at 12. This is
specifically because i2c-10 and i2c-11 aliases were defined. This is
_good_ IMO.
If I saw a log message about "i2c-10" in the logs or in /dev/, I would
first look in the sc7180 devicetree file and assume that the
peripherals must be connected to the i2c10 pins on the SoC. If I see
"i2c-12" in the logs I would quickly realize that it couldn't be one
of the SoC i2c ports and I'd go look at the dynamically numbered ones.
Yes, yes. I'm smart enough to look things up and deal with any random
/ arbitrary numbers. You could also come up with an arbitrary Chinese
character for each i2c bus and I'm smart enough to look it up and map
it to find the right port. ...but there is no reason to make people go
through this work. This is the primary SoC on the system and it has
well-defined numbers. It just makes everyone's lives a little easier
if the numbers match the reference manual.
-Doug
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (7 preceding siblings ...)
2021-09-23 12:16 ` [PATCH V10 8/8] arm64: dts: sc7280: Add aliases for I2C and SPI Rajesh Patil
@ 2021-09-23 21:27 ` Stephen Boyd
2021-09-24 22:44 ` Bjorn Andersson
9 siblings, 0 replies; 23+ messages in thread
From: Stephen Boyd @ 2021-09-23 21:27 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rajesh Patil, Rob Herring
Cc: linux-arm-msm, linux-kernel, devicetree, rnayak,
saiprakash.ranjan, msavaliy, skakit, mka, dianders
Quoting Rajesh Patil (2021-09-23 05:16:10)
> Changes in V10:
> - As per Stephen's comments, Removed <&qup_spiN_cs_gpio> in all spi ports.
> - Added "&qupv3_id_1" in sc7280-idp.dtsi file because EC and TPM
> are using "qupv3_id_1" node.
Thanks. Looks good now. It would be great if qcom maintainers can pick
this up soon so we can have usable i2c/spi devices on sc7280.
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC
2021-09-23 12:16 [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Rajesh Patil
` (8 preceding siblings ...)
2021-09-23 21:27 ` [PATCH V10 0/8] Add QSPI and QUPv3 DT nodes for SC7280 SoC Stephen Boyd
@ 2021-09-24 22:44 ` Bjorn Andersson
9 siblings, 0 replies; 23+ messages in thread
From: Bjorn Andersson @ 2021-09-24 22:44 UTC (permalink / raw)
To: Rajesh Patil, Andy Gross, Rob Herring
Cc: dianders, skakit, sboyd, devicetree, rnayak, mka, msavaliy,
linux-arm-msm, saiprakash.ranjan, linux-kernel
On Thu, 23 Sep 2021 17:46:10 +0530, Rajesh Patil wrote:
> Changes in V10:
> - As per Stephen's comments, Removed <&qup_spiN_cs_gpio> in all spi ports.
> - Added "&qupv3_id_1" in sc7280-idp.dtsi file because EC and TPM
> are using "qupv3_id_1" node.
>
> Changes in V9:
> - As per Stephen's comments,
> 1. Moved back qup_opp_table from /soc@0/geniqup@9c0000 to /
> 2. changed node names to "qup_spi0_cs_gpio: qup-spi0-cs-gpio" because
> node names should have dashes instead of underscores.
>
> [...]
Applied, thanks!
[2/8] arm64: dts: sc7280: Add QSPI node
commit: 7720ea001b528d88cdb7980cb9c97327f95a815d
[3/8] arm64: dts: sc7280: Configure SPI-NOR FLASH for sc7280-idp
commit: df0174b13d3f6e744a5a3dfdfc1853bb60533fdb
[4/8] arm64: dts: sc7280: Add QUPv3 wrapper_0 nodes
commit: bf6f37a3086bec4c103dc4a478b25c9adf8dd671
[5/8] arm64: dts: sc7280: Update QUPv3 UART5 DT node
commit: 38cd93f413fd946fa39b83d3283a6a2a21ca0789
[6/8] arm64: dts: sc7280: Configure uart7 to support bluetooth on sc7280-idp
commit: e3bc6fec5aaa67b8147a422d8d88a36d46827f0f
[7/8] arm64: dts: sc7280: Add QUPv3 wrapper_1 nodes
commit: 4e8e7648ae645d1113649a7b9a781fdb4b2701f5
[8/8] arm64: dts: sc7280: Add aliases for I2C and SPI
commit: 5f65408d9bfcc418353c8cd4dd17f60ba60d61a0
That said, all but a single commit to arch/arm64/boot/dts/qcom/sc7280* has the
prefix "arm64: dts: qcom: sc7280: ", so I would be happy if you could follow
this and include "qcom" in the future.
Best regards,
--
Bjorn Andersson <bjorn.andersson@linaro.org>
^ permalink raw reply [flat|nested] 23+ messages in thread